LLVM  9.0.0svn
Disassembler.cpp
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1 //===-- lib/MC/Disassembler.cpp - Disassembler Public C Interface ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "Disassembler.h"
10 #include "llvm-c/Disassembler.h"
11 #include "llvm/ADT/ArrayRef.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/Triple.h"
14 #include "llvm/MC/MCAsmInfo.h"
15 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstPrinter.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSchedule.h"
31 #include <cassert>
32 #include <cstddef>
33 #include <cstring>
34 
35 using namespace llvm;
36 
37 // LLVMCreateDisasm() creates a disassembler for the TripleName. Symbolic
38 // disassembly is supported by passing a block of information in the DisInfo
39 // parameter and specifying the TagType and callback functions as described in
40 // the header llvm-c/Disassembler.h . The pointer to the block and the
41 // functions can all be passed as NULL. If successful, this returns a
42 // disassembler context. If not, it returns NULL.
43 //
45 LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU,
46  const char *Features, void *DisInfo, int TagType,
47  LLVMOpInfoCallback GetOpInfo,
48  LLVMSymbolLookupCallback SymbolLookUp) {
49  // Get the target.
50  std::string Error;
51  const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
52  if (!TheTarget)
53  return nullptr;
54 
55  const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(TT);
56  if (!MRI)
57  return nullptr;
58 
59  // Get the assembler info needed to setup the MCContext.
60  const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, TT);
61  if (!MAI)
62  return nullptr;
63 
64  const MCInstrInfo *MII = TheTarget->createMCInstrInfo();
65  if (!MII)
66  return nullptr;
67 
68  const MCSubtargetInfo *STI =
69  TheTarget->createMCSubtargetInfo(TT, CPU, Features);
70  if (!STI)
71  return nullptr;
72 
73  // Set up the MCContext for creating symbols and MCExpr's.
74  MCContext *Ctx = new MCContext(MAI, MRI, nullptr);
75  if (!Ctx)
76  return nullptr;
77 
78  // Set up disassembler.
79  MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI, *Ctx);
80  if (!DisAsm)
81  return nullptr;
82 
83  std::unique_ptr<MCRelocationInfo> RelInfo(
84  TheTarget->createMCRelocationInfo(TT, *Ctx));
85  if (!RelInfo)
86  return nullptr;
87 
88  std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
89  TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx, std::move(RelInfo)));
90  DisAsm->setSymbolizer(std::move(Symbolizer));
91 
92  // Set up the instruction printer.
93  int AsmPrinterVariant = MAI->getAssemblerDialect();
94  MCInstPrinter *IP = TheTarget->createMCInstPrinter(
95  Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI);
96  if (!IP)
97  return nullptr;
98 
100  new LLVMDisasmContext(TT, DisInfo, TagType, GetOpInfo, SymbolLookUp,
101  TheTarget, MAI, MRI, STI, MII, Ctx, DisAsm, IP);
102  if (!DC)
103  return nullptr;
104 
105  DC->setCPU(CPU);
106  return DC;
107 }
108 
110 LLVMCreateDisasmCPU(const char *TT, const char *CPU, void *DisInfo, int TagType,
111  LLVMOpInfoCallback GetOpInfo,
112  LLVMSymbolLookupCallback SymbolLookUp) {
113  return LLVMCreateDisasmCPUFeatures(TT, CPU, "", DisInfo, TagType, GetOpInfo,
114  SymbolLookUp);
115 }
116 
117 LLVMDisasmContextRef LLVMCreateDisasm(const char *TT, void *DisInfo,
118  int TagType, LLVMOpInfoCallback GetOpInfo,
119  LLVMSymbolLookupCallback SymbolLookUp) {
120  return LLVMCreateDisasmCPUFeatures(TT, "", "", DisInfo, TagType, GetOpInfo,
121  SymbolLookUp);
122 }
123 
124 //
125 // LLVMDisasmDispose() disposes of the disassembler specified by the context.
126 //
128  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
129  delete DC;
130 }
131 
132 /// Emits the comments that are stored in \p DC comment stream.
133 /// Each comment in the comment stream must end with a newline.
135  formatted_raw_ostream &FormattedOS) {
136  // Flush the stream before taking its content.
137  StringRef Comments = DC->CommentsToEmit.str();
138  // Get the default information for printing a comment.
139  const MCAsmInfo *MAI = DC->getAsmInfo();
140  StringRef CommentBegin = MAI->getCommentString();
141  unsigned CommentColumn = MAI->getCommentColumn();
142  bool IsFirst = true;
143  while (!Comments.empty()) {
144  if (!IsFirst)
145  FormattedOS << '\n';
146  // Emit a line of comments.
147  FormattedOS.PadToColumn(CommentColumn);
148  size_t Position = Comments.find('\n');
149  FormattedOS << CommentBegin << ' ' << Comments.substr(0, Position);
150  // Move after the newline character.
151  Comments = Comments.substr(Position+1);
152  IsFirst = false;
153  }
154  FormattedOS.flush();
155 
156  // Tell the comment stream that the vector changed underneath it.
157  DC->CommentsToEmit.clear();
158 }
159 
160 /// Gets latency information for \p Inst from the itinerary
161 /// scheduling model, based on \p DC information.
162 /// \return The maximum expected latency over all the operands or -1
163 /// if no information is available.
164 static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
165  const int NoInformationAvailable = -1;
166 
167  // Check if we have a CPU to get the itinerary information.
168  if (DC->getCPU().empty())
169  return NoInformationAvailable;
170 
171  // Get itinerary information.
172  const MCSubtargetInfo *STI = DC->getSubtargetInfo();
174  // Get the scheduling class of the requested instruction.
175  const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
176  unsigned SCClass = Desc.getSchedClass();
177 
178  int Latency = 0;
179  for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd;
180  ++OpIdx)
181  Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
182 
183  return Latency;
184 }
185 
186 /// Gets latency information for \p Inst, based on \p DC information.
187 /// \return The maximum expected latency over all the definitions or -1
188 /// if no information is available.
189 static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
190  // Try to compute scheduling information.
191  const MCSubtargetInfo *STI = DC->getSubtargetInfo();
192  const MCSchedModel SCModel = STI->getSchedModel();
193  const int NoInformationAvailable = -1;
194 
195  // Check if we have a scheduling model for instructions.
196  if (!SCModel.hasInstrSchedModel())
197  // Try to fall back to the itinerary model if the scheduling model doesn't
198  // have a scheduling table. Note the default does not have a table.
199  return getItineraryLatency(DC, Inst);
200 
201  // Get the scheduling class of the requested instruction.
202  const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
203  unsigned SCClass = Desc.getSchedClass();
204  const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass);
205  // Resolving the variant SchedClass requires an MI to pass to
206  // SubTargetInfo::resolveSchedClass.
207  if (!SCDesc || !SCDesc->isValid() || SCDesc->isVariant())
208  return NoInformationAvailable;
209 
210  // Compute output latency.
211  int16_t Latency = 0;
212  for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
213  DefIdx != DefEnd; ++DefIdx) {
214  // Lookup the definition's write latency in SubtargetInfo.
215  const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,
216  DefIdx);
217  Latency = std::max(Latency, WLEntry->Cycles);
218  }
219 
220  return Latency;
221 }
222 
223 /// Emits latency information in DC->CommentStream for \p Inst, based
224 /// on the information available in \p DC.
225 static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
226  int Latency = getLatency(DC, Inst);
227 
228  // Report only interesting latencies.
229  if (Latency < 2)
230  return;
231 
232  DC->CommentStream << "Latency: " << Latency << '\n';
233 }
234 
235 //
236 // LLVMDisasmInstruction() disassembles a single instruction using the
237 // disassembler context specified in the parameter DC. The bytes of the
238 // instruction are specified in the parameter Bytes, and contains at least
239 // BytesSize number of bytes. The instruction is at the address specified by
240 // the PC parameter. If a valid instruction can be disassembled its string is
241 // returned indirectly in OutString which whos size is specified in the
242 // parameter OutStringSize. This function returns the number of bytes in the
243 // instruction or zero if there was no valid instruction. If this function
244 // returns zero the caller will have to pick how many bytes they want to step
245 // over by printing a .byte, .long etc. to continue.
246 //
247 size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes,
248  uint64_t BytesSize, uint64_t PC, char *OutString,
249  size_t OutStringSize){
250  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
251  // Wrap the pointer to the Bytes, BytesSize and PC in a MemoryObject.
252  ArrayRef<uint8_t> Data(Bytes, BytesSize);
253 
254  uint64_t Size;
255  MCInst Inst;
256  const MCDisassembler *DisAsm = DC->getDisAsm();
257  MCInstPrinter *IP = DC->getIP();
259  SmallVector<char, 64> InsnStr;
260  raw_svector_ostream Annotations(InsnStr);
261  S = DisAsm->getInstruction(Inst, Size, Data, PC,
262  /*REMOVE*/ nulls(), Annotations);
263  switch (S) {
266  // FIXME: Do something different for soft failure modes?
267  return 0;
268 
270  StringRef AnnotationsStr = Annotations.str();
271 
272  SmallVector<char, 64> InsnStr;
273  raw_svector_ostream OS(InsnStr);
274  formatted_raw_ostream FormattedOS(OS);
275  IP->printInst(&Inst, FormattedOS, AnnotationsStr, *DC->getSubtargetInfo());
276 
278  emitLatency(DC, Inst);
279 
280  emitComments(DC, FormattedOS);
281 
282  assert(OutStringSize != 0 && "Output buffer cannot be zero size");
283  size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());
284  std::memcpy(OutString, InsnStr.data(), OutputSize);
285  OutString[OutputSize] = '\0'; // Terminate string.
286 
287  return Size;
288  }
289  }
290  llvm_unreachable("Invalid DecodeStatus!");
291 }
292 
293 //
294 // LLVMSetDisasmOptions() sets the disassembler's options. It returns 1 if it
295 // can set all the Options and 0 otherwise.
296 //
297 int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){
298  if (Options & LLVMDisassembler_Option_UseMarkup){
299  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
300  MCInstPrinter *IP = DC->getIP();
301  IP->setUseMarkup(true);
302  DC->addOptions(LLVMDisassembler_Option_UseMarkup);
303  Options &= ~LLVMDisassembler_Option_UseMarkup;
304  }
306  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
307  MCInstPrinter *IP = DC->getIP();
308  IP->setPrintImmHex(true);
309  DC->addOptions(LLVMDisassembler_Option_PrintImmHex);
310  Options &= ~LLVMDisassembler_Option_PrintImmHex;
311  }
313  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
314  // Try to set up the new instruction printer.
315  const MCAsmInfo *MAI = DC->getAsmInfo();
316  const MCInstrInfo *MII = DC->getInstrInfo();
317  const MCRegisterInfo *MRI = DC->getRegisterInfo();
318  int AsmPrinterVariant = MAI->getAssemblerDialect();
319  AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
321  Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
322  if (IP) {
323  DC->setIP(IP);
324  DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
325  Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
326  }
327  }
329  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
330  MCInstPrinter *IP = DC->getIP();
332  DC->addOptions(LLVMDisassembler_Option_SetInstrComments);
333  Options &= ~LLVMDisassembler_Option_SetInstrComments;
334  }
335  if (Options & LLVMDisassembler_Option_PrintLatency) {
336  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
337  DC->addOptions(LLVMDisassembler_Option_PrintLatency);
338  Options &= ~LLVMDisassembler_Option_PrintLatency;
339  }
340  return (Options == 0);
341 }
void setIP(MCInstPrinter *NewIP)
Definition: Disassembler.h:117
#define LLVMDisassembler_Option_SetInstrComments
Definition: Disassembler.h:82
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI)=0
Print the specified MCInst to the specified raw_ostream.
LLVMDisasmContextRef LLVMCreateDisasm(const char *TT, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName.
DecodeStatus
Ternary decode status.
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Superclass for all disassemblers.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
const FeatureBitset Features
static void emitComments(LLVMDisasmContext *DC, formatted_raw_ostream &FormattedOS)
Emits the comments that are stored in DC comment stream.
void setPrintImmHex(bool Value)
Definition: MCInstPrinter.h:89
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:509
MCDisassembler * createMCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) const
void setSymbolizer(std::unique_ptr< MCSymbolizer > Symzer)
Set Symzer as the current symbolizer.
#define LLVMDisassembler_Option_UseMarkup
Definition: Disassembler.h:76
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:345
static const Target * lookupTarget(const std::string &Triple, std::string &Error)
lookupTarget - Lookup a target based on a target triple.
LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *TT, const char *CPU, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName and a specific CPU.
static ManagedStatic< DebugCounter > DC
MCInstPrinter * createMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) const
MCInstPrinter * getIP()
Definition: Disassembler.h:116
static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Emits latency information in DC->CommentStream for Inst, based on the information available in DC...
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
void * LLVMDisasmContextRef
An opaque reference to a disassembler context.
Position
Position to insert a new instruction relative to an existing instruction.
const MCRegisterInfo * getRegisterInfo() const
Definition: Disassembler.h:114
StringRef str() const
Explicit conversion to StringRef.
Definition: SmallString.h:266
Context object for machine code objects.
Definition: MCContext.h:62
raw_svector_ostream CommentStream
Definition: Disassembler.h:83
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:132
Itinerary data supplied by a subtarget to be used by a target.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:597
bool isValid() const
Definition: MCSchedule.h:126
static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst, based on DC information.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:576
unsigned const MachineRegisterInfo * MRI
unsigned getAssemblerDialect() const
Definition: MCAsmInfo.h:508
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:109
void setCommentStream(raw_ostream &OS)
Specify a stream to emit comments to.
Definition: MCInstPrinter.h:68
#define LLVMDisassembler_Option_PrintImmHex
Definition: Disassembler.h:78
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
const MCSubtargetInfo * getSubtargetInfo() const
Definition: Disassembler.h:115
StringRef getCommentString() const
Definition: MCAsmInfo.h:485
MCRegisterInfo * createMCRegInfo(StringRef TT) const
createMCRegInfo - Create a MCRegisterInfo implementation.
unsigned getNumOperands() const
Definition: MCInst.h:181
size_t size() const
Definition: SmallVector.h:52
static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst from the itinerary scheduling model, based on DC information...
const MCInstrInfo * getInstrInfo() const
Definition: Disassembler.h:113
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Definition: MCSchedule.h:319
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:77
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:845
const MCAsmInfo * getAsmInfo() const
Definition: Disassembler.h:112
StringRef str()
Return a StringRef for the vector contents.
Definition: raw_ostream.h:534
const Target * getTarget() const
Definition: Disassembler.h:110
LLVMDisasmContextRef LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU, const char *Features, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName, a specific CPU and specific feature string.
MCAsmInfo * createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TheTriple) const
createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple.
Target - Wrapper for Target specific information.
bool isVariant() const
Definition: MCSchedule.h:129
void setUseMarkup(bool Value)
Definition: MCInstPrinter.h:82
size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes, uint64_t BytesSize, uint64_t PC, char *OutString, size_t OutStringSize)
Disassemble a single instruction using the disassembler context specified in the parameter DC...
int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options)
Set the disassembler&#39;s options.
MCSubtargetInfo * createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, StringRef Features) const
createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
#define LLVMDisassembler_Option_AsmPrinterVariant
Definition: Disassembler.h:80
StringRef getCPU() const
Definition: Disassembler.h:120
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:39
pointer data()
Return a pointer to the vector&#39;s buffer, even if empty().
Definition: SmallVector.h:148
uint64_t getOptions() const
Definition: Disassembler.h:118
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
void LLVMDisasmDispose(LLVMDisasmContextRef DCR)
Dispose of a disassembler context.
Generic base class for all target subtargets.
MCSymbolizer * createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo) const
createMCSymbolizer - Create a target specific MCSymbolizer.
uint32_t Size
Definition: Profile.cpp:46
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getCommentColumn() const
This indicates the column (zero-based) at which asm comments should be printed.
Definition: MCAsmInfo.h:483
MCRelocationInfo * createMCRelocationInfo(StringRef TT, MCContext &Ctx) const
createMCRelocationInfo - Create a target specific MCRelocationInfo.
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
raw_ostream & nulls()
This returns a reference to a raw_ostream which simply discards output.
uint16_t NumWriteLatencyEntries
Definition: MCSchedule.h:122
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
void addOptions(uint64_t Options)
Definition: Disassembler.h:119
void setCPU(const char *CPU)
Definition: Disassembler.h:121
const std::string & getTripleName() const
Definition: Disassembler.h:103
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned getOpcode() const
Definition: MCInst.h:171
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:297
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &VStream, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
const MCDisassembler * getDisAsm() const
Definition: Disassembler.h:111
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
SmallString< 128 > CommentsToEmit
Definition: Disassembler.h:82
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:243
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
#define LLVMDisassembler_Option_PrintLatency
Definition: Disassembler.h:84