LLVM  6.0.0svn
Public Member Functions | Protected Member Functions | List of all members
llvm::DefaultVLIWScheduler Class Reference
Inheritance diagram for llvm::DefaultVLIWScheduler:
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Public Member Functions

 DefaultVLIWScheduler (MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA)
 
void schedule () override
 Orders nodes according to selected style. More...
 
void addMutation (std::unique_ptr< ScheduleDAGMutation > Mutation)
 DefaultVLIWScheduler takes ownership of the Mutation object. More...
 
- Public Member Functions inherited from llvm::ScheduleDAGInstrs
 ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)
 
 ~ScheduleDAGInstrs () override=default
 
const TargetSchedModelgetSchedModel () const
 Gets the machine model for instruction scheduling. More...
 
const MCSchedClassDescgetSchedClass (SUnit *SU) const
 Resolves and cache a resolved scheduling class for an SUnit. More...
 
MachineBasicBlock::iterator begin () const
 Returns an iterator to the top of the current scheduling region. More...
 
MachineBasicBlock::iterator end () const
 Returns an iterator to the bottom of the current scheduling region. More...
 
SUnitnewSUnit (MachineInstr *MI)
 Creates a new SUnit and return a ptr to it. More...
 
SUnitgetSUnit (MachineInstr *MI) const
 Returns an existing SUnit for this MI, or nullptr. More...
 
virtual bool doMBBSchedRegionsTopDown () const
 If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB. More...
 
virtual void startBlock (MachineBasicBlock *BB)
 Prepares to perform scheduling in the given block. More...
 
virtual void finishBlock ()
 Cleans up after scheduling in the given block. More...
 
virtual void enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
 Initialize the DAG and common scheduler state for a new scheduling region. More...
 
virtual void exitRegion ()
 Called when the scheduler has finished scheduling the current region. More...
 
void buildSchedGraph (AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
 Builds SUnits for the current region. More...
 
void addSchedBarrierDeps ()
 Adds dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. More...
 
virtual void finalizeSchedule ()
 Allow targets to perform final scheduling actions at the level of the whole MachineFunction. More...
 
void dumpNode (const SUnit *SU) const override
 
std::string getGraphNodeLabel (const SUnit *SU) const override
 Returns a label for a DAG node that points to an instruction. More...
 
std::string getDAGName () const override
 Returns a label for the region of code covered by the DAG. More...
 
void fixupKills (MachineBasicBlock &MBB)
 Fixes register kill flags that scheduling has made invalid. More...
 
- Public Member Functions inherited from llvm::ScheduleDAG
 ScheduleDAG (MachineFunction &mf)
 
virtual ~ScheduleDAG ()
 
void clearDAG ()
 Clears the DAG state (between regions). More...
 
const MCInstrDescgetInstrDesc (const SUnit *SU) const
 Returns the MCInstrDesc of this SUnit. More...
 
virtual void viewGraph (const Twine &Name, const Twine &Title)
 Pops up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'. More...
 
virtual void viewGraph ()
 Out-of-line implementation with no arguments is handy for gdb. More...
 
virtual void addCustomGraphFeatures (GraphWriter< ScheduleDAG *> &) const
 Adds custom features for a visualization of the ScheduleDAG. More...
 
unsigned VerifyScheduledDAG (bool isBottomUp)
 Verifies that all SUnits were scheduled and that their state is consistent. More...
 

Protected Member Functions

void postprocessDAG ()
 Apply each ScheduleDAGMutation step in order. More...
 
- Protected Member Functions inherited from llvm::ScheduleDAGInstrs
void reduceHugeMemNodeMaps (Value2SUsMap &stores, Value2SUsMap &loads, unsigned N)
 Reduces maps in FIFO order, by N SUs. More...
 
void addChainDependency (SUnit *SUa, SUnit *SUb, unsigned Latency=0)
 Adds a chain edge between SUa and SUb, but only if both AliasAnalysis and Target fail to deny the dependency. More...
 
void addChainDependencies (SUnit *SU, SUList &SUs, unsigned Latency)
 Adds dependencies as needed from all SUs in list to SU. More...
 
void addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap)
 Adds dependencies as needed from all SUs in map, to SU. More...
 
void addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V)
 Adds dependencies as needed to SU, from all SUs mapped to V. More...
 
void addBarrierChain (Value2SUsMap &map)
 Adds barrier chain edges from all SUs in map, and then clear the map. More...
 
void insertBarrierChain (Value2SUsMap &map)
 Inserts a barrier chain in a huge region, far below current SU. More...
 
void initSUnits ()
 Creates an SUnit for each real instruction, numbered in top-down topological order. More...
 
void addPhysRegDataDeps (SUnit *SU, unsigned OperIdx)
 MO is an operand of SU's instruction that defines a physical register. More...
 
void addPhysRegDeps (SUnit *SU, unsigned OperIdx)
 Adds register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx. More...
 
void addVRegDefDeps (SUnit *SU, unsigned OperIdx)
 Adds register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx. More...
 
void addVRegUseDeps (SUnit *SU, unsigned OperIdx)
 Adds a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit. More...
 
void startBlockForKills (MachineBasicBlock *BB)
 Initializes register live-range state for updating kills. More...
 
void toggleKillFlag (MachineInstr &MI, MachineOperand &MO)
 Toggles a register operand kill flag. More...
 
LaneBitmask getLaneMaskForMO (const MachineOperand &MO) const
 Returns a mask for which lanes get read/written by the given (register) machine operand. More...
 

Additional Inherited Members

- Public Types inherited from llvm::ScheduleDAGInstrs
using SUList = std::list< SUnit * >
 A list of SUnits, used in Value2SUsMap, during DAG construction. More...
 
- Public Attributes inherited from llvm::ScheduleDAG
const TargetMachineTM
 Target processor. More...
 
const TargetInstrInfoTII
 Target instruction information. More...
 
const TargetRegisterInfoTRI
 Target processor register info. More...
 
MachineFunctionMF
 Machine function. More...
 
MachineRegisterInfoMRI
 Virtual/real register map. More...
 
std::vector< SUnitSUnits
 The scheduling units. More...
 
SUnit EntrySU
 Special node for the region entry. More...
 
SUnit ExitSU
 Special node for the region exit. More...
 
bool StressSched
 
- Protected Types inherited from llvm::ScheduleDAGInstrs
using DbgValueVector = std::vector< std::pair< MachineInstr *, MachineInstr * > >
 
- Protected Attributes inherited from llvm::ScheduleDAGInstrs
const MachineLoopInfoMLI
 
const MachineFrameInfoMFI
 
TargetSchedModel SchedModel
 TargetSchedModel provides an interface to the machine model. More...
 
bool RemoveKillFlags
 True if the DAG builder should remove kill flags (in preparation for rescheduling). More...
 
bool CanHandleTerminators = false
 The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. More...
 
bool TrackLaneMasks = false
 Whether lane masks should get tracked. More...
 
MachineBasicBlockBB
 The block in which to insert instructions. More...
 
MachineBasicBlock::iterator RegionBegin
 The beginning of the range to be scheduled. More...
 
MachineBasicBlock::iterator RegionEnd
 The end of the range to be scheduled. More...
 
unsigned NumRegionInstrs
 Instructions in this region (distance(RegionBegin, RegionEnd)). More...
 
DenseMap< MachineInstr *, SUnit * > MISUnitMap
 After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit. More...
 
Reg2SUnitsMap Defs
 Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions. More...
 
Reg2SUnitsMap Uses
 
VReg2SUnitMultiMap CurrentVRegDefs
 Tracks the last instruction(s) in this region defining each virtual register. More...
 
VReg2SUnitOperIdxMultiMap CurrentVRegUses
 Tracks the last instructions in this region using each virtual register. More...
 
AliasAnalysisAAForDep = nullptr
 
SUnitBarrierChain = nullptr
 Remember a generic side-effecting instruction as we proceed. More...
 
UndefValueUnknownValue
 For an unanalyzable memory access, this Value is used in maps. More...
 
DbgValueVector DbgValues
 Remember instruction that precedes DBG_VALUE. More...
 
MachineInstrFirstDbgValue = nullptr
 
LivePhysRegs LiveRegs
 Set of live physical registers for updating kill flags. More...
 

Detailed Description

Definition at line 167 of file DFAPacketizer.cpp.

Constructor & Destructor Documentation

◆ DefaultVLIWScheduler()

DefaultVLIWScheduler::DefaultVLIWScheduler ( MachineFunction MF,
MachineLoopInfo MLI,
AliasAnalysis AA 
)

Definition at line 191 of file DFAPacketizer.cpp.

References llvm::ScheduleDAGInstrs::CanHandleTerminators.

Member Function Documentation

◆ addMutation()

void llvm::DefaultVLIWScheduler::addMutation ( std::unique_ptr< ScheduleDAGMutation Mutation)
inline

DefaultVLIWScheduler takes ownership of the Mutation object.

Definition at line 181 of file DFAPacketizer.cpp.

Referenced by llvm::VLIWPacketizerList::addMutation().

◆ postprocessDAG()

void DefaultVLIWScheduler::postprocessDAG ( )
protected

Apply each ScheduleDAGMutation step in order.

Definition at line 199 of file DFAPacketizer.cpp.

Referenced by schedule().

◆ schedule()

void DefaultVLIWScheduler::schedule ( )
overridevirtual

Orders nodes according to selected style.

Typically, a scheduling algorithm will implement schedule() without overriding enterRegion() or exitRegion().

Implements llvm::ScheduleDAGInstrs.

Definition at line 204 of file DFAPacketizer.cpp.

References llvm::ScheduleDAGInstrs::buildSchedGraph(), and postprocessDAG().

Referenced by llvm::VLIWPacketizerList::PacketizeMIs().


The documentation for this class was generated from the following file: