LLVM 23.0.0git
Macros | Functions | Variables
ARMISelDAGToDAG.cpp File Reference
#include "ARM.h"
#include "ARMBaseInstrInfo.h"
#include "ARMTargetMachine.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsARM.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetOptions.h"
#include <optional>
#include "ARMGenDAGISel.inc"

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "arm-isel"
#define PASS_NAME   "ARM Instruction Selection"

Functions

static bool isInt32Immediate (SDNode *N, unsigned &Imm)
 isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.
static bool isInt32Immediate (SDValue N, unsigned &Imm)
static bool isOpcWithIntImmediate (SDNode *N, unsigned Opc, unsigned &Imm)
static bool isScaledConstantInRange (SDValue Node, int Scale, int RangeMin, int RangeMax, int &ScaledConstant)
 Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMin, RangeMax).
static bool shouldUseZeroOffsetLdSt (SDValue N)
static SDValue getAL (SelectionDAG *CurDAG, const SDLoc &dl)
 getAL - Returns a ARMCC::AL immediate node.
static bool isVLDfixed (unsigned Opc)
static bool isVSTfixed (unsigned Opc)
static unsigned getVLDSTRegisterUpdateOpcode (unsigned Opc)
static bool isPerfectIncrement (SDValue Inc, EVT VecTy, unsigned NumVecs)
 Returns true if the given increment is a Constant known to be equal to the access size performed by a NEON load/store.
static bool SDValueToConstBool (SDValue SDVal)
static std::optional< std::pair< unsigned, unsigned > > getContiguousRangeOfSetBits (const APInt &A)
static unsigned getVectorShuffleOpcode (EVT VT, unsigned Opc64[3], unsigned Opc128[3])
static void getIntOperandsFromRegisterString (StringRef RegString, SelectionDAG *CurDAG, const SDLoc &DL, std::vector< SDValue > &Ops)
static int getBankedRegisterMask (StringRef RegString)
static int getMClassFlagsMask (StringRef Flags)
static int getMClassRegisterMask (StringRef Reg, const ARMSubtarget *Subtarget)
static int getARClassRegisterMask (StringRef Reg, StringRef Flags)

Variables

static cl::opt< bool > DisableShifterOp ("disable-shifter-op", cl::Hidden, cl::desc("Disable isel of shifter-op"), cl::init(false))

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "arm-isel"

Definition at line 40 of file ARMISelDAGToDAG.cpp.

◆ PASS_NAME

#define PASS_NAME   "ARM Instruction Selection"

Definition at line 41 of file ARMISelDAGToDAG.cpp.

Function Documentation

◆ getAL()

SDValue getAL ( SelectionDAG * CurDAG,
const SDLoc & dl )
inlinestatic

getAL - Returns a ARMCC::AL immediate node.

Definition at line 1576 of file ARMISelDAGToDAG.cpp.

References llvm::ARMCC::AL, and llvm::SelectionDAG::getTargetConstant().

◆ getARClassRegisterMask()

int getARClassRegisterMask ( StringRef Reg,
StringRef Flags )
static

Definition at line 5429 of file ARMISelDAGToDAG.cpp.

References getMClassFlagsMask(), and Reg.

◆ getBankedRegisterMask()

int getBankedRegisterMask ( StringRef RegString)
inlinestatic

Definition at line 5398 of file ARMISelDAGToDAG.cpp.

References llvm::StringRef::lower().

◆ getContiguousRangeOfSetBits()

std::optional< std::pair< unsigned, unsigned > > getContiguousRangeOfSetBits ( const APInt & A)
static

Definition at line 3583 of file ARMISelDAGToDAG.cpp.

References A().

◆ getIntOperandsFromRegisterString()

void getIntOperandsFromRegisterString ( StringRef RegString,
SelectionDAG * CurDAG,
const SDLoc & DL,
std::vector< SDValue > & Ops )
static

Definition at line 5370 of file ARMISelDAGToDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), DL, llvm::SelectionDAG::getTargetConstant(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::StringRef::split().

◆ getMClassFlagsMask()

int getMClassFlagsMask ( StringRef Flags)
inlinestatic

Definition at line 5408 of file ARMISelDAGToDAG.cpp.

References llvm::StringSwitch< T, R >::Case(), and llvm::StringSwitch< T, R >::Default().

Referenced by getARClassRegisterMask().

◆ getMClassRegisterMask()

int getMClassRegisterMask ( StringRef Reg,
const ARMSubtarget * Subtarget )
static

Definition at line 5421 of file ARMISelDAGToDAG.cpp.

References Reg.

◆ getVectorShuffleOpcode()

unsigned getVectorShuffleOpcode ( EVT VT,
unsigned Opc64[3],
unsigned Opc128[3] )
static

Definition at line 3665 of file ARMISelDAGToDAG.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), and llvm_unreachable.

◆ getVLDSTRegisterUpdateOpcode()

unsigned getVLDSTRegisterUpdateOpcode ( unsigned Opc)
static

Definition at line 2026 of file ARMISelDAGToDAG.cpp.

References assert(), isVLDfixed(), isVSTfixed(), and Opc.

◆ isInt32Immediate() [1/2]

bool isInt32Immediate ( SDNode * N,
unsigned & Imm )
static

isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.

If so Imm will receive the 32-bit value.

Definition at line 369 of file ARMISelDAGToDAG.cpp.

References llvm::ISD::Constant, isInt32Immediate(), and N.

Referenced by isInt32Immediate(), isInt32Immediate(), and isOpcWithIntImmediate().

◆ isInt32Immediate() [2/2]

bool isInt32Immediate ( SDValue N,
unsigned & Imm )
static

Definition at line 379 of file ARMISelDAGToDAG.cpp.

References isInt32Immediate(), and N.

◆ isOpcWithIntImmediate()

bool isOpcWithIntImmediate ( SDNode * N,
unsigned Opc,
unsigned & Imm )
static

Definition at line 386 of file ARMISelDAGToDAG.cpp.

References isInt32Immediate(), N, and Opc.

◆ isPerfectIncrement()

bool isPerfectIncrement ( SDValue Inc,
EVT VecTy,
unsigned NumVecs )
static

Returns true if the given increment is a Constant known to be equal to the access size performed by a NEON load/store.

This means the "[rN]!" form can be used.

Definition at line 2100 of file ARMISelDAGToDAG.cpp.

References llvm::CallingConv::C, llvm::dyn_cast(), and llvm::EVT::getSizeInBits().

◆ isScaledConstantInRange()

bool isScaledConstantInRange ( SDValue Node,
int Scale,
int RangeMin,
int RangeMax,
int & ScaledConstant )
static

Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMin, RangeMax).

Parameters
ScaledConstant[out] - On success, the pre-scaled constant value.

Definition at line 395 of file ARMISelDAGToDAG.cpp.

References assert(), llvm::CallingConv::C, and llvm::dyn_cast().

◆ isVLDfixed()

bool isVLDfixed ( unsigned Opc)
static

Definition at line 1953 of file ARMISelDAGToDAG.cpp.

References Opc.

Referenced by getVLDSTRegisterUpdateOpcode().

◆ isVSTfixed()

bool isVSTfixed ( unsigned Opc)
static

Definition at line 1995 of file ARMISelDAGToDAG.cpp.

References Opc.

Referenced by getVLDSTRegisterUpdateOpcode().

◆ SDValueToConstBool()

bool SDValueToConstBool ( SDValue SDVal)
static

Definition at line 2693 of file ARMISelDAGToDAG.cpp.

References assert(), llvm::dyn_cast(), llvm::ConstantSDNode::getZExtValue(), and llvm::isa().

◆ shouldUseZeroOffsetLdSt()

bool shouldUseZeroOffsetLdSt ( SDValue N)
static

Definition at line 1112 of file ARMISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::CallingConv::C, llvm::dyn_cast(), and N.

Variable Documentation

◆ DisableShifterOp

cl::opt< bool > DisableShifterOp("disable-shifter-op", cl::Hidden, cl::desc("Disable isel of shifter-op"), cl::init(false)) ( "disable-shifter-op" ,
cl::Hidden ,
cl::desc("Disable isel of shifter-op") ,
cl::init(false)  )
static
Generated on for LLVM by doxygen 1.14.0