LLVM 23.0.0git
CriticalAntiDepBreaker.h
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1//===- llvm/CodeGen/CriticalAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the CriticalAntiDepBreaker class, which
10// implements register anti-dependence breaking along a blocks
11// critical path during post-RA scheduler.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
16#define LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
17
18#include "llvm/ADT/BitVector.h"
21#include <map>
22#include <vector>
23
24namespace llvm {
25
27class MachineFunction;
28class MachineInstr;
29class MachineOperand;
32class TargetInstrInfo;
33class MCRegisterClass;
36
40 const TargetInstrInfo *TII;
41 const TargetRegisterInfo *TRI;
42 const RegisterClassInfo &RegClassInfo;
43
44 /// The set of allocatable registers.
45 /// We'll be ignoring anti-dependencies on non-allocatable registers,
46 /// because they may not be safe to break.
47 const BitVector AllocatableSet;
48
49 /// For live regs that are only used in one register class in a
50 /// live range, the register class. If the register is not live, the
51 /// corresponding value is null. If the register is live but used in
52 /// multiple register classes, the corresponding value is -1 casted to a
53 /// pointer.
54 std::vector<const TargetRegisterClass *> Classes;
55
56 /// Map registers to all their references within a live range.
57 std::multimap<MCRegister, MachineOperand *> RegRefs;
58
59 using RegRefIter =
60 std::multimap<MCRegister, MachineOperand *>::const_iterator;
61
62 /// The index of the most recent kill (proceeding bottom-up),
63 /// or ~0u if the register is not live.
64 std::vector<unsigned> KillIndices;
65
66 /// The index of the most recent complete def (proceeding
67 /// bottom up), or ~0u if the register is live.
68 std::vector<unsigned> DefIndices;
69
70 /// A set of registers which are live and cannot be changed to
71 /// break anti-dependencies.
72 BitVector KeepRegs;
73
74 public:
77
78 /// Initialize anti-dep breaking for a new basic block.
79 void StartBlock(MachineBasicBlock *BB) override;
80
81 /// Identifiy anti-dependencies along the critical path
82 /// of the ScheduleDAG and break them by renaming registers.
83 unsigned BreakAntiDependencies(const std::vector<SUnit> &SUnits,
86 unsigned InsertPosIndex,
87 DbgValueVector &DbgValues) override;
88
89 /// Update liveness information to account for the current
90 /// instruction, which will not be scheduled.
91 void Observe(MachineInstr &MI, unsigned Count,
92 unsigned InsertPosIndex) override;
93
94 /// Finish anti-dep breaking for a basic block.
95 void FinishBlock() override;
96
97 private:
98 void PrescanInstruction(MachineInstr &MI);
99 void ScanInstruction(MachineInstr &MI, unsigned Count);
100 bool isNewRegClobberedByRefs(RegRefIter RegRefBegin, RegRefIter RegRefEnd,
101 MCRegister NewReg);
103 findSuitableFreeRegister(RegRefIter RegRefBegin, RegRefIter RegRefEnd,
104 MCRegister AntiDepReg, MCRegister LastNewReg,
105 const TargetRegisterClass *RC,
106 const SmallVectorImpl<Register> &Forbid);
107 };
108
109} // end namespace llvm
110
111#endif // LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
This file implements the BitVector class.
#define LLVM_LIBRARY_VISIBILITY
Definition Compiler.h:137
IRTranslator LLVM IR MI
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
unsigned BreakAntiDependencies(const std::vector< SUnit > &SUnits, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned InsertPosIndex, DbgValueVector &DbgValues) override
Identifiy anti-dependencies along the critical path of the ScheduleDAG and break them by renaming reg...
void FinishBlock() override
Finish anti-dep breaking for a basic block.
void Observe(MachineInstr &MI, unsigned Count, unsigned InsertPosIndex) override
Update liveness information to account for the current instruction, which will not be scheduled.
void StartBlock(MachineBasicBlock *BB) override
Initialize anti-dep breaking for a new basic block.
CriticalAntiDepBreaker(MachineFunction &MFi, const RegisterClassInfo &RCI)
MCRegisterClass - Base class of TargetRegisterClass.
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:41
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
RelativeUniformCounterPtr ValuesPtrExpr VTableAddr Count
Definition InstrProf.h:145
MCRegisterClass TargetRegisterClass
Definition FastISel.h:58