15#ifndef LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
16#define LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
26class MachineBasicBlock;
30class MachineRegisterInfo;
31class RegisterClassInfo;
33class TargetRegisterClass;
34class TargetRegisterInfo;
53 std::vector<const TargetRegisterClass *> Classes;
56 std::multimap<unsigned, MachineOperand *> RegRefs;
59 std::multimap<unsigned, MachineOperand *>::const_iterator;
63 std::vector<unsigned> KillIndices;
67 std::vector<unsigned> DefIndices;
82 unsigned BreakAntiDependencies(
const std::vector<SUnit> &SUnits,
85 unsigned InsertPosIndex,
91 unsigned InsertPosIndex)
override;
94 void FinishBlock()
override;
99 bool isNewRegClobberedByRefs(RegRefIter RegRefBegin,
100 RegRefIter RegRefEnd,
102 unsigned findSuitableFreeRegister(RegRefIter RegRefBegin,
103 RegRefIter RegRefEnd,
unsigned const MachineRegisterInfo * MRI
This file implements the BitVector class.
#define LLVM_LIBRARY_VISIBILITY
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
~CriticalAntiDepBreaker() override
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.