LLVM 22.0.0git
HexagonDisassembler.cpp
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1//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/HexagonBaseInfo.h"
10#include "MCTargetDesc/HexagonMCChecker.h"
11#include "MCTargetDesc/HexagonMCInstrInfo.h"
12#include "MCTargetDesc/HexagonMCTargetDesc.h"
13#include "TargetInfo/HexagonTargetInfo.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDecoder.h"
17#include "llvm/MC/MCDecoderOps.h"
18#include "llvm/MC/MCDisassembler/MCDisassembler.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/Compiler.h"
26#include "llvm/Support/Endian.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstddef>
31#include <cstdint>
32#include <memory>
33
34#define DEBUG_TYPE "hexagon-disassembler"
35
36using namespace llvm;
37using namespace llvm::MCD;
38using namespace Hexagon;
39
40using DecodeStatus = MCDisassembler::DecodeStatus;
41
42namespace {
43
44/// Hexagon disassembler for all Hexagon platforms.
45class HexagonDisassembler : public MCDisassembler {
46public:
47 std::unique_ptr<MCInstrInfo const> const MCII;
48 mutable std::unique_ptr<MCInst> CurrentBundle;
49 mutable MCInst const *CurrentExtender;
50
51 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
52 MCInstrInfo const *MCII)
53 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(nullptr),
54 CurrentExtender(nullptr) {}
55
56 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
57 ArrayRef<uint8_t> Bytes, uint64_t Address,
58 raw_ostream &CStream, bool &Complete) const;
59 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
60 ArrayRef<uint8_t> Bytes, uint64_t Address,
61 raw_ostream &CStream) const override;
62
63 DecodeStatus getInstructionBundle(MCInst &Instr, uint64_t &Size,
64 ArrayRef<uint8_t> Bytes, uint64_t Address,
65 raw_ostream &CStream) const override;
66
67 void remapInstruction(MCInst &Instr) const;
68
69private:
70 bool makeBundle(ArrayRef<uint8_t> Bytes, uint64_t Address,
71 uint64_t &BytesToSkip, raw_ostream &CS) const;
72
73 void resetBundle() const {
74 CurrentBundle.reset();
75 CurrentInstruction = nullptr;
76 }
77
78 mutable MCOperand *CurrentInstruction = nullptr;
79};
80
81static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
82 int64_t Value) {
83 MCInstrInfo MCII = *Disassembler.MCII;
84 if (!Disassembler.CurrentExtender ||
85 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
86 return Value;
87 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
88 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
89 int64_t Bits;
90 bool Success =
91 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
92 Bits);
93 assert(Success);
94 (void)Success;
95 uint64_t Upper26 = static_cast<uint64_t>(Bits);
96 uint64_t Operand = Upper26 | Lower6;
97 return Operand;
98}
99static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) {
100 return *static_cast<HexagonDisassembler const *>(Decoder);
101}
102template <size_t T>
103static void signedDecoder(MCInst &MI, unsigned tmp,
104 const MCDisassembler *Decoder) {
105 HexagonDisassembler const &Disassembler = disassembler(Decoder);
106 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
107 int64_t Extended = SignExtend64<32>(FullValue);
108 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
109}
110}
111
112// Forward declare these because the auto-generated code will reference them.
113// Definitions are further down.
114
115static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
116 uint64_t Address,
117 const MCDisassembler *Decoder);
118static DecodeStatus
119DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
120 uint64_t Address,
121 const MCDisassembler *Decoder);
122static DecodeStatus
123DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
124 const MCDisassembler *Decoder);
125static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
126 uint64_t Address,
127 const MCDisassembler *Decoder);
128static DecodeStatus
129DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
130 const MCDisassembler *Decoder);
131static DecodeStatus
132DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
133 uint64_t Address,
134 const MCDisassembler *Decoder);
135static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
136 uint64_t Address,
137 const MCDisassembler *Decoder);
138static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
139 uint64_t Address,
140 const MCDisassembler *Decoder);
141static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
142 uint64_t Address,
143 const MCDisassembler *Decoder);
144static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
145 uint64_t Address,
146 const MCDisassembler *Decoder);
147static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
148 uint64_t Address,
149 const MCDisassembler *Decoder);
150static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
151 uint64_t Address,
152 const MCDisassembler *Decoder);
153static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address,
155 const MCDisassembler *Decoder);
156static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
157 uint64_t Address,
158 const MCDisassembler *Decoder);
159static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address,
161 const MCDisassembler *Decoder);
162static DecodeStatus
163DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
164 const MCDisassembler *Decoder);
165static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
166 uint64_t Address,
167 const MCDisassembler *Decoder);
168
169static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
170 uint64_t Address,
171 const MCDisassembler *Decoder);
172static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
173 uint64_t /*Address*/,
174 const MCDisassembler *Decoder);
175static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
176 const MCDisassembler *Decoder);
177
178static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder) {
179 MCContext &Ctx = Decoder->getContext();
180 MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(-1, Ctx)));
181 return DecodeStatus::Success;
182}
183
184static DecodeStatus sgp10ConstDecoder(MCInst &MI,
185 const MCDisassembler *Decoder) {
186 MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
187 return DecodeStatus::Success;
188}
189
190#include "HexagonDepDecoders.inc"
191#include "HexagonGenDisassemblerTables.inc"
192
193static MCDisassembler *createHexagonDisassembler(const Target &T,
194 const MCSubtargetInfo &STI,
195 MCContext &Ctx) {
196 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
197}
198
199extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
204
205bool HexagonDisassembler::makeBundle(ArrayRef<uint8_t> Bytes, uint64_t Address,
206 uint64_t &BytesToSkip,
207 raw_ostream &CS) const {
208 bool Complete = false;
209 DecodeStatus Result = DecodeStatus::Success;
210
211 CurrentBundle.reset(new MCInst);
212 CurrentBundle->setOpcode(Hexagon::BUNDLE);
213 CurrentBundle->addOperand(MCOperand::createImm(0));
214 while (Result == Success && !Complete) {
215 if (Bytes.size() < HEXAGON_INSTR_SIZE)
216 return false;
217 MCInst *Inst = getContext().createMCInst();
218 Result = getSingleInstruction(*Inst, *CurrentBundle, Bytes, Address, CS,
219 Complete);
220 CurrentBundle->addOperand(MCOperand::createInst(Inst));
221 BytesToSkip += HEXAGON_INSTR_SIZE;
222 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
223 }
224 if (Result == MCDisassembler::Fail)
225 return false;
226 if (BytesToSkip > HEXAGON_MAX_PACKET_SIZE)
227 return false;
228
229 const auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
230 const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI;
231 HexagonMCChecker Checker(getContext(), *MCII, STI_, *CurrentBundle,
232 *getContext().getRegisterInfo(), false);
233 if (!Checker.check())
234 return false;
235 remapInstruction(*CurrentBundle);
236 return true;
237}
238
239DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
240 ArrayRef<uint8_t> Bytes,
241 uint64_t Address,
242 raw_ostream &CS) const {
243 CommentStream = &CS;
244
245 Size = 0;
246 uint64_t BytesToSkip = 0;
247
248 if (!CurrentBundle) {
249 if (!makeBundle(Bytes, Address, BytesToSkip, CS)) {
250 Size = BytesToSkip;
251 resetBundle();
252 return MCDisassembler::Fail;
253 }
254 CurrentInstruction = (CurrentBundle->begin() + 1);
255 }
256
257 MI = *(CurrentInstruction->getInst());
258 Size = HEXAGON_INSTR_SIZE;
259 if (++CurrentInstruction == CurrentBundle->end())
260 resetBundle();
261 return MCDisassembler::Success;
262}
263
264DecodeStatus HexagonDisassembler::getInstructionBundle(MCInst &MI,
265 uint64_t &Size,
266 ArrayRef<uint8_t> Bytes,
267 uint64_t Address,
268 raw_ostream &CS) const {
269 CommentStream = &CS;
270 Size = 0;
271 uint64_t BytesToSkip = 0;
272 assert(!CurrentBundle);
273
274 if (!makeBundle(Bytes, Address, BytesToSkip, CS)) {
275 Size = BytesToSkip;
276 resetBundle();
277 return MCDisassembler::Fail;
278 }
279
280 MI = *CurrentBundle;
281 Size = HEXAGON_INSTR_SIZE * HexagonMCInstrInfo::bundleSize(MI);
282 resetBundle();
283
284 return Success;
285}
286
287void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
288 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
289 auto &MI = const_cast<MCInst &>(*I.getInst());
290 switch (MI.getOpcode()) {
291 case Hexagon::S2_allocframe:
292 if (MI.getOperand(0).getReg() == Hexagon::R29) {
293 MI.setOpcode(Hexagon::S6_allocframe_to_raw);
294 MI.erase(MI.begin () + 1);
295 MI.erase(MI.begin ());
296 }
297 break;
298 case Hexagon::L2_deallocframe:
299 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
300 MI.getOperand(1).getReg() == Hexagon::R30) {
301 MI.setOpcode(L6_deallocframe_map_to_raw);
302 MI.erase(MI.begin () + 1);
303 MI.erase(MI.begin ());
304 }
305 break;
306 case Hexagon::L4_return:
307 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
308 MI.getOperand(1).getReg() == Hexagon::R30) {
309 MI.setOpcode(L6_return_map_to_raw);
310 MI.erase(MI.begin () + 1);
311 MI.erase(MI.begin ());
312 }
313 break;
314 case Hexagon::L4_return_t:
315 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
316 MI.getOperand(2).getReg() == Hexagon::R30) {
317 MI.setOpcode(L4_return_map_to_raw_t);
318 MI.erase(MI.begin () + 2);
319 MI.erase(MI.begin ());
320 }
321 break;
322 case Hexagon::L4_return_f:
323 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
324 MI.getOperand(2).getReg() == Hexagon::R30) {
325 MI.setOpcode(L4_return_map_to_raw_f);
326 MI.erase(MI.begin () + 2);
327 MI.erase(MI.begin ());
328 }
329 break;
330 case Hexagon::L4_return_tnew_pt:
331 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
332 MI.getOperand(2).getReg() == Hexagon::R30) {
333 MI.setOpcode(L4_return_map_to_raw_tnew_pt);
334 MI.erase(MI.begin () + 2);
335 MI.erase(MI.begin ());
336 }
337 break;
338 case Hexagon::L4_return_fnew_pt:
339 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
340 MI.getOperand(2).getReg() == Hexagon::R30) {
341 MI.setOpcode(L4_return_map_to_raw_fnew_pt);
342 MI.erase(MI.begin () + 2);
343 MI.erase(MI.begin ());
344 }
345 break;
346 case Hexagon::L4_return_tnew_pnt:
347 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
348 MI.getOperand(2).getReg() == Hexagon::R30) {
349 MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
350 MI.erase(MI.begin () + 2);
351 MI.erase(MI.begin ());
352 }
353 break;
354 case Hexagon::L4_return_fnew_pnt:
355 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
356 MI.getOperand(2).getReg() == Hexagon::R30) {
357 MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
358 MI.erase(MI.begin () + 2);
359 MI.erase(MI.begin ());
360 }
361 break;
362 }
363 }
364}
365
366DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
367 ArrayRef<uint8_t> Bytes,
368 uint64_t Address,
369 raw_ostream &cs,
370 bool &Complete) const {
371 assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
372
373 uint32_t Instruction = support::endian::read32le(Bytes.data());
374
375 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
376 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
377 HexagonII::INST_PARSE_LOOP_END) {
378 if (BundleSize == 0)
379 HexagonMCInstrInfo::setInnerLoop(MCB);
380 else if (BundleSize == 1)
381 HexagonMCInstrInfo::setOuterLoop(MCB);
382 else
383 return DecodeStatus::Fail;
384 }
385
386 CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
387 MCB, HexagonMCInstrInfo::bundleSize(MCB));
388
389 DecodeStatus Result = DecodeStatus::Fail;
390 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
391 HexagonII::INST_PARSE_DUPLEX) {
392 unsigned duplexIClass;
393 uint8_t const *DecodeLow, *DecodeHigh;
394 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
395 switch (duplexIClass) {
396 default:
397 return MCDisassembler::Fail;
398 case 0:
399 DecodeLow = DecoderTableSUBINSN_L132;
400 DecodeHigh = DecoderTableSUBINSN_L132;
401 break;
402 case 1:
403 DecodeLow = DecoderTableSUBINSN_L232;
404 DecodeHigh = DecoderTableSUBINSN_L132;
405 break;
406 case 2:
407 DecodeLow = DecoderTableSUBINSN_L232;
408 DecodeHigh = DecoderTableSUBINSN_L232;
409 break;
410 case 3:
411 DecodeLow = DecoderTableSUBINSN_A32;
412 DecodeHigh = DecoderTableSUBINSN_A32;
413 break;
414 case 4:
415 DecodeLow = DecoderTableSUBINSN_L132;
416 DecodeHigh = DecoderTableSUBINSN_A32;
417 break;
418 case 5:
419 DecodeLow = DecoderTableSUBINSN_L232;
420 DecodeHigh = DecoderTableSUBINSN_A32;
421 break;
422 case 6:
423 DecodeLow = DecoderTableSUBINSN_S132;
424 DecodeHigh = DecoderTableSUBINSN_A32;
425 break;
426 case 7:
427 DecodeLow = DecoderTableSUBINSN_S232;
428 DecodeHigh = DecoderTableSUBINSN_A32;
429 break;
430 case 8:
431 DecodeLow = DecoderTableSUBINSN_S132;
432 DecodeHigh = DecoderTableSUBINSN_L132;
433 break;
434 case 9:
435 DecodeLow = DecoderTableSUBINSN_S132;
436 DecodeHigh = DecoderTableSUBINSN_L232;
437 break;
438 case 10:
439 DecodeLow = DecoderTableSUBINSN_S132;
440 DecodeHigh = DecoderTableSUBINSN_S132;
441 break;
442 case 11:
443 DecodeLow = DecoderTableSUBINSN_S232;
444 DecodeHigh = DecoderTableSUBINSN_S132;
445 break;
446 case 12:
447 DecodeLow = DecoderTableSUBINSN_S232;
448 DecodeHigh = DecoderTableSUBINSN_L132;
449 break;
450 case 13:
451 DecodeLow = DecoderTableSUBINSN_S232;
452 DecodeHigh = DecoderTableSUBINSN_L232;
453 break;
454 case 14:
455 DecodeLow = DecoderTableSUBINSN_S232;
456 DecodeHigh = DecoderTableSUBINSN_S232;
457 break;
458 }
459 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
460 MCInst *MILow = getContext().createMCInst();
461 MCInst *MIHigh = getContext().createMCInst();
462 auto TmpExtender = CurrentExtender;
463 CurrentExtender =
464 nullptr; // constant extenders in duplex must always be in slot 1
465 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
466 this, STI);
467 CurrentExtender = TmpExtender;
468 if (Result != DecodeStatus::Success)
469 return DecodeStatus::Fail;
470 Result = decodeInstruction(
471 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
472 if (Result != DecodeStatus::Success)
473 return DecodeStatus::Fail;
474 MCOperand OPLow = MCOperand::createInst(MILow);
475 MCOperand OPHigh = MCOperand::createInst(MIHigh);
476 MI.addOperand(OPLow);
477 MI.addOperand(OPHigh);
478 Complete = true;
479 } else {
480 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
481 HexagonII::INST_PARSE_PACKET_END)
482 Complete = true;
483
484 if (CurrentExtender != nullptr)
485 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
486 Address, this, STI);
487
488 if (Result != MCDisassembler::Success)
489 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
490 STI);
491
492 if (Result != MCDisassembler::Success &&
493 STI.hasFeature(Hexagon::ExtensionHVX))
494 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
495 Address, this, STI);
496
497 }
498
499 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
500 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
501 MCOperand &MCO = MI.getOperand(OpIndex);
502 assert(MCO.isReg() && "New value consumers must be registers");
503 unsigned Register =
504 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
505 if ((Register & 0x6) == 0)
506 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
507 return MCDisassembler::Fail;
508 unsigned Lookback = (Register & 0x6) >> 1;
509 unsigned Offset = 1;
510 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
511 bool PrevVector = false;
512 auto Instructions = HexagonMCInstrInfo::bundleInstructions(*CurrentBundle);
513 auto i = Instructions.end() - 1;
514 for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
515 if (i == n)
516 // Couldn't find producer
517 return MCDisassembler::Fail;
518 bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
519 if (Vector && !CurrentVector)
520 // Skip scalars when calculating distances for vectors
521 ++Lookback;
522 if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
523 ++Lookback;
524 PrevVector = CurrentVector;
525 if (Offset == Lookback)
526 break;
527 }
528 auto const &Inst = *i->getInst();
529 bool SubregBit = (Register & 0x1) != 0;
530 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
531 // If subreg bit is set we're selecting the second produced newvalue
532 MCRegister Producer =
533 SubregBit
534 ? HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg()
535 : HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
536 assert(Producer != Hexagon::NoRegister);
537 MCO.setReg(Producer);
538 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
539 MCRegister Producer =
540 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
541
542 if (HexagonMCInstrInfo::IsVecRegPair(Producer)) {
543 const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
544 const unsigned ProdPairIndex =
545 Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
546 if (Rev)
547 SubregBit = !SubregBit;
548 Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
549 } else if (SubregBit)
550 // Hexagon PRM 10.11 New-value operands
551 // Nt[0] is reserved and should always be encoded as zero.
552 return MCDisassembler::Fail;
553 assert(Producer != Hexagon::NoRegister);
554 MCO.setReg(Producer);
555 } else
556 return MCDisassembler::Fail;
557 }
558
559 if (CurrentExtender != nullptr) {
560 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
561 ? *MI.getOperand(1).getInst()
562 : MI;
563 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
564 !HexagonMCInstrInfo::isExtended(*MCII, Inst))
565 return MCDisassembler::Fail;
566 }
567 return Result;
568}
569
570static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
571 ArrayRef<MCPhysReg> Table) {
572 if (RegNo < Table.size()) {
573 Inst.addOperand(MCOperand::createReg(Table[RegNo]));
574 return MCDisassembler::Success;
575 }
576
577 return MCDisassembler::Fail;
578}
579
580static DecodeStatus
581DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
582 const MCDisassembler *Decoder) {
583 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
584}
585
586static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
587 uint64_t Address,
588 const MCDisassembler *Decoder) {
589 static const MCPhysReg IntRegDecoderTable[] = {
590 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
591 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
592 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
593 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
594 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
595 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
596 Hexagon::R30, Hexagon::R31};
597
598 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
599}
600
601static DecodeStatus
602DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
603 uint64_t Address,
604 const MCDisassembler *Decoder) {
605 static const MCPhysReg GeneralSubRegDecoderTable[] = {
606 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
607 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
608 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
609 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
610 };
611
612 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
613}
614
615static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
616 uint64_t /*Address*/,
617 const MCDisassembler *Decoder) {
618 static const MCPhysReg HvxVRDecoderTable[] = {
619 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
620 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
621 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
622 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
623 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
624 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
625 Hexagon::V30, Hexagon::V31};
626
627 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
628}
629
630static DecodeStatus
631DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
632 uint64_t /*Address*/,
633 const MCDisassembler *Decoder) {
634 static const MCPhysReg DoubleRegDecoderTable[] = {
635 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
636 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
637 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
638 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
639
640 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
641}
642
643static DecodeStatus
644DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
645 uint64_t /*Address*/,
646 const MCDisassembler *Decoder) {
647 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
648 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
649 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
650
651 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
652}
653
654static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
655 uint64_t /*Address*/,
656 const MCDisassembler *Decoder) {
657 static const MCPhysReg HvxWRDecoderTable[] = {
658 Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,
659 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4,
660 Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7,
661 Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9,
662 Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12,
663 Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14,
664 Hexagon::W15, Hexagon::WR15,
665 };
666
667 return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable);
668}
669
670LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily.
671 static DecodeStatus
672 DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
673 uint64_t /*Address*/,
674 const MCDisassembler *Decoder) {
675 static const MCPhysReg HvxVQRDecoderTable[] = {
676 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,
677 Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};
678
679 return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable);
680}
681
682static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
683 uint64_t /*Address*/,
684 const MCDisassembler *Decoder) {
685 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
686 Hexagon::P2, Hexagon::P3};
687
688 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
689}
690
691static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
692 uint64_t /*Address*/,
693 const MCDisassembler *Decoder) {
694 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
695 Hexagon::Q2, Hexagon::Q3};
696
697 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
698}
699
700static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
701 uint64_t /*Address*/,
702 const MCDisassembler *Decoder) {
703 using namespace Hexagon;
704
705 static const MCPhysReg CtrlRegDecoderTable[] = {
706 /* 0 */ SA0, LC0, SA1, LC1,
707 /* 4 */ P3_0, C5, M0, M1,
708 /* 8 */ USR, PC, UGP, GP,
709 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
710 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
711 /* 20 */ 0, 0, 0, 0,
712 /* 24 */ 0, 0, 0, 0,
713 /* 28 */ 0, 0, UTIMERLO, UTIMERHI
714 };
715
716 if (RegNo >= std::size(CtrlRegDecoderTable))
717 return MCDisassembler::Fail;
718
719 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
720 if (CtrlRegDecoderTable[RegNo] == NoRegister)
721 return MCDisassembler::Fail;
722
723 unsigned Register = CtrlRegDecoderTable[RegNo];
724 Inst.addOperand(MCOperand::createReg(Register));
725 return MCDisassembler::Success;
726}
727
728static DecodeStatus
729DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
730 const MCDisassembler *Decoder) {
731 using namespace Hexagon;
732
733 static const MCPhysReg CtrlReg64DecoderTable[] = {
734 /* 0 */ C1_0, 0, C3_2, 0,
735 /* 4 */ C5_4, 0, C7_6, 0,
736 /* 8 */ C9_8, 0, C11_10, 0,
737 /* 12 */ CS, 0, UPCYCLE, 0,
738 /* 16 */ C17_16, 0, PKTCOUNT, 0,
739 /* 20 */ 0, 0, 0, 0,
740 /* 24 */ 0, 0, 0, 0,
741 /* 28 */ 0, 0, UTIMER, 0
742 };
743
744 if (RegNo >= std::size(CtrlReg64DecoderTable))
745 return MCDisassembler::Fail;
746
747 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
748 if (CtrlReg64DecoderTable[RegNo] == NoRegister)
749 return MCDisassembler::Fail;
750
751 unsigned Register = CtrlReg64DecoderTable[RegNo];
752 Inst.addOperand(MCOperand::createReg(Register));
753 return MCDisassembler::Success;
754}
755
756static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
757 uint64_t /*Address*/,
758 const MCDisassembler *Decoder) {
759 unsigned Register = 0;
760 switch (RegNo) {
761 case 0:
762 Register = Hexagon::M0;
763 break;
764 case 1:
765 Register = Hexagon::M1;
766 break;
767 default:
768 return MCDisassembler::Fail;
769 }
770 Inst.addOperand(MCOperand::createReg(Register));
771 return MCDisassembler::Success;
772}
773
774static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
775 uint64_t /*Address*/,
776 const MCDisassembler *Decoder) {
777 HexagonDisassembler const &Disassembler = disassembler(Decoder);
778 int64_t FullValue = fullValue(Disassembler, MI, tmp);
779 assert(FullValue >= 0 && "Negative in unsigned decoder");
780 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
781 return MCDisassembler::Success;
782}
783
784static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
785 uint64_t /*Address*/,
786 const MCDisassembler *Decoder) {
787 HexagonDisassembler const &Disassembler = disassembler(Decoder);
788 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
789 tmp = SignExtend64(tmp, Bits);
790 signedDecoder<32>(MI, tmp, Decoder);
791 return MCDisassembler::Success;
792}
793
794// custom decoder for various jump/call immediates
795static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
796 const MCDisassembler *Decoder) {
797 HexagonDisassembler const &Disassembler = disassembler(Decoder);
798 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
799 // r13_2 is not extendable, so if there are no extent bits, it's r13_2
800 if (Bits == 0)
801 Bits = 15;
802 uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
803 uint32_t Extended = FullValue + Address;
804 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 0,
805 4))
806 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
807 return MCDisassembler::Success;
808}
809
810static const uint16_t SysRegDecoderTable[] = {
811 Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID,
812 Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1,
813 Hexagon::SSR, Hexagon::CCR, Hexagon::HTID,
814 Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11,
815 Hexagon::S12, Hexagon::S13, Hexagon::S14,
816 Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL,
817 Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20,
818 Hexagon::VID, Hexagon::S22, Hexagon::S23,
819 Hexagon::S24, Hexagon::S25, Hexagon::S26,
820 Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV,
821 Hexagon::PCYCLELO, Hexagon::PCYCLEHI, Hexagon::ISDBST,
822 Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35,
823 Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,
824 Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,
825 Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44,
826 Hexagon::S45, Hexagon::S46, Hexagon::S47,
827 Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2,
828 Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG,
829 Hexagon::S54, Hexagon::S55, Hexagon::S56,
830 Hexagon::S57, Hexagon::S58, Hexagon::S59,
831 Hexagon::S60, Hexagon::S61, Hexagon::S62,
832 Hexagon::S63, Hexagon::S64, Hexagon::S65,
833 Hexagon::S66, Hexagon::S67, Hexagon::S68,
834 Hexagon::S69, Hexagon::S70, Hexagon::S71,
835 Hexagon::S72, Hexagon::S73, Hexagon::S74,
836 Hexagon::S75, Hexagon::S76, Hexagon::S77,
837 Hexagon::S78, Hexagon::S79, Hexagon::S80,
838};
839
840static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
841 uint64_t /*Address*/,
842 const MCDisassembler *Decoder) {
843 if (RegNo >= std::size(SysRegDecoderTable))
844 return MCDisassembler::Fail;
845
846 if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
847 return MCDisassembler::Fail;
848
849 unsigned Register = SysRegDecoderTable[RegNo];
850 Inst.addOperand(MCOperand::createReg(Register));
851 return MCDisassembler::Success;
852}
853
854static const uint16_t SysReg64DecoderTable[] = {
855 Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6,
856 Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
857 Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
858 Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
859 Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
860 Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
861 Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
862 Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
863 Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
864 Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
865};
866
867static DecodeStatus
868DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
869 const MCDisassembler *Decoder) {
870 RegNo = RegNo >> 1;
871 if (RegNo >= std::size(SysReg64DecoderTable))
872 return MCDisassembler::Fail;
873
874 if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
875 return MCDisassembler::Fail;
876
877 unsigned Register = SysReg64DecoderTable[RegNo];
878 Inst.addOperand(MCOperand::createReg(Register));
879 return MCDisassembler::Success;
880}
881
882static DecodeStatus
883DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
884 const MCDisassembler *Decoder) {
885 using namespace Hexagon;
886
887 static const MCPhysReg GuestRegDecoderTable[] = {
888 /* 0 */ GELR, GSR, GOSP, G3,
889 /* 4 */ G4, G5, G6, G7,
890 /* 8 */ G8, G9, G10, G11,
891 /* 12 */ G12, G13, G14, G15,
892 /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
893 /* 20 */ G20, G21, G22, G23,
894 /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
895 /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
896 };
897
898 if (RegNo >= std::size(GuestRegDecoderTable))
899 return MCDisassembler::Fail;
900 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
901 return MCDisassembler::Fail;
902
903 unsigned Register = GuestRegDecoderTable[RegNo];
904 Inst.addOperand(MCOperand::createReg(Register));
905 return MCDisassembler::Success;
906}
907
908static DecodeStatus
909DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
910 uint64_t /*Address*/,
911 const MCDisassembler *Decoder) {
912 using namespace Hexagon;
913
914 static const MCPhysReg GuestReg64DecoderTable[] = {
915 /* 0 */ G1_0, 0, G3_2, 0,
916 /* 4 */ G5_4, 0, G7_6, 0,
917 /* 8 */ G9_8, 0, G11_10, 0,
918 /* 12 */ G13_12, 0, G15_14, 0,
919 /* 16 */ G17_16, 0, G19_18, 0,
920 /* 20 */ G21_20, 0, G23_22, 0,
921 /* 24 */ G25_24, 0, G27_26, 0,
922 /* 28 */ G29_28, 0, G31_30, 0
923 };
924
925 if (RegNo >= std::size(GuestReg64DecoderTable))
926 return MCDisassembler::Fail;
927 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
928 return MCDisassembler::Fail;
929
930 unsigned Register = GuestReg64DecoderTable[RegNo];
931 Inst.addOperand(MCOperand::createReg(Register));
932 return MCDisassembler::Success;
933}
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition AArch64Disassembler.cpp:36
Success
#define Success
Definition AArch64Disassembler.cpp:42
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
LLVM_ABI
#define LLVM_ABI
Definition Compiler.h:213
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition Compiler.h:298
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
sgp10ConstDecoder
static DecodeStatus sgp10ConstDecoder(MCInst &MI, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:184
DecodeIntRegsLow8RegisterClass
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:581
DecodeGuestRegsRegisterClass
static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:883
DecodeCtrRegsRegisterClass
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:700
brtargetDecoder
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:795
DecodePredRegsRegisterClass
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:682
LLVMInitializeHexagonDisassembler
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler()
Definition HexagonDisassembler.cpp:200
s32_0ImmDecoder
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:784
DecodeHvxVQRRegisterClass
static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:672
unsignedImmDecoder
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:774
DecodeHvxVRRegisterClass
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:615
createHexagonDisassembler
static MCDisassembler * createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition HexagonDisassembler.cpp:193
DecodeSysRegs64RegisterClass
static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:868
DecodeModRegsRegisterClass
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:756
SysReg64DecoderTable
static const uint16_t SysReg64DecoderTable[]
Definition HexagonDisassembler.cpp:854
DecodeRegisterClass
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)
Definition HexagonDisassembler.cpp:570
DecodeSysRegsRegisterClass
static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:840
DecodeDoubleRegsRegisterClass
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:631
n1ConstDecoder
static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:178
SysRegDecoderTable
static const uint16_t SysRegDecoderTable[]
Definition HexagonDisassembler.cpp:810
DecodeGeneralSubRegsRegisterClass
static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:602
DecodeHvxWRRegisterClass
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:654
DecodeIntRegsRegisterClass
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:586
DecodeHvxQRRegisterClass
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:691
DecodeCtrRegs64RegisterClass
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:729
DecodeGeneralDoubleLow8RegsRegisterClass
static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:644
DecodeGuestRegs64RegisterClass
static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:909
HEXAGON_MAX_PACKET_SIZE
#define HEXAGON_MAX_PACKET_SIZE
Definition HexagonMCTargetDesc.h:36
HEXAGON_INSTR_SIZE
#define HEXAGON_INSTR_SIZE
Definition HexagonMCTargetDesc.h:32
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
I
#define I(x, y, z)
Definition MD5.cpp:58
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
T
#define T
Definition Mips16ISelLowering.cpp:353
OpIndex
unsigned OpIndex
Definition SPIRVModuleAnalysis.cpp:56
IntRegDecoderTable
static constexpr unsigned IntRegDecoderTable[]
Definition SparcDisassembler.cpp:65
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition ArrayRef.h:147
llvm::ArrayRef::data
const T * data() const
Definition ArrayRef.h:144
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition ArrayRef.h:191
llvm::MCConstantExpr::create
static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition MCExpr.cpp:212
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition MCDisassembler.h:85
llvm::MCDisassembler::getContext
MCContext & getContext() const
Definition MCDisassembler.h:228
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition MCDisassembler.h:109
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition MCInst.h:215
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition MCInst.h:210
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition MCInst.h:40
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition MCInst.h:166
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
llvm::MCOperand::setReg
void setReg(MCRegister Reg)
Set the register number.
Definition MCInst.h:79
llvm::MCOperand::isReg
bool isReg() const
Definition MCInst.h:65
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition MCInst.h:73
llvm::MCOperand::getInst
const MCInst * getInst() const
Definition MCInst.h:128
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition MCInst.h:118
llvm::MCOperand::createInst
static MCOperand createInst(const MCInst *Val)
Definition MCInst.h:173
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:77
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:19
llvm::Target
Target - Wrapper for Target specific information.
Definition TargetRegistry.h:146
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint16_t
uint32_t
uint64_t
llvm::HexagonMCInstrInfo::addConstant
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
Definition HexagonMCInstrInfo.cpp:82
llvm::HexagonMCInstrInfo::IsReverseVecRegPair
bool IsReverseVecRegPair(MCRegister VecReg)
Definition HexagonMCInstrInfo.cpp:699
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:116
llvm::HexagonMCInstrInfo::isDuplex
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:624
llvm::HexagonMCInstrInfo::getExtentBits
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:340
llvm::HexagonMCInstrInfo::isNewValue
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
Definition HexagonMCInstrInfo.cpp:670
llvm::HexagonMCInstrInfo::getNewValueOp
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:379
llvm::HexagonMCInstrInfo::getExtendableOp
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:316
llvm::HexagonMCInstrInfo::IsVecRegPair
bool IsVecRegPair(MCRegister VecReg)
Definition HexagonMCInstrInfo.cpp:694
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:103
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:628
llvm::HexagonMCInstrInfo::extenderForIndex
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
Definition HexagonMCInstrInfo.cpp:222
llvm::HexagonMCInstrInfo::isImmext
bool isImmext(MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:650
llvm::HexagonMCInstrInfo::getNewValueOperand
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:385
llvm::HexagonMCInstrInfo::hasNewValue2
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Definition HexagonMCInstrInfo.cpp:520
llvm::HexagonMCInstrInfo::getExtentAlignment
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:334
llvm::HexagonMCInstrInfo::isVector
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:869
llvm::HexagonMCInstrInfo::getNewValueOperand2
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:411
llvm::HexagonMCInstrInfo::isExtended
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:634
llvm::HexagonMCInstrInfo::hasNewValue
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
Definition HexagonMCInstrInfo.cpp:513
llvm::Hexagon_MC::getArchSubtarget
MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)
Definition HexagonMCTargetDesc.cpp:526
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
Definition MicrosoftDemangle.h:132
llvm::sandboxir::getContext
Context & getContext() const
Definition BasicBlock.h:99
llvm::sandboxir::Instruction
friend class Instruction
Iterator for Instructions in a `BasicBlock.
Definition BasicBlock.h:73
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition Endian.h:428
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::Offset
@ Offset
Definition DWP.cpp:477
llvm::getTheHexagonTarget
Target & getTheHexagonTarget()
Definition HexagonTargetInfo.cpp:14
llvm::M1
unsigned M1(unsigned Val)
Definition VE.h:377
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
llvm::M0
unsigned M0(unsigned Val)
Definition VE.h:376
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:583
raw_ostream.h
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition TargetRegistry.h:934
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