36 return Register != Hexagon::NoRegister;
41 : MCII(MCII), BundleCurrent(Inst.begin() +
43 BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
46 MCInst const &Inst, std::nullptr_t)
47 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
48 DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
51 if (DuplexCurrent != DuplexEnd) {
53 if (DuplexCurrent == DuplexEnd) {
54 DuplexCurrent = BundleEnd;
55 DuplexEnd = BundleEnd;
61 if (BundleCurrent != BundleEnd) {
62 MCInst const &Inst = *BundleCurrent->getInst();
64 DuplexCurrent = Inst.
begin();
65 DuplexEnd = Inst.
end();
72 if (DuplexCurrent != DuplexEnd)
73 return *DuplexCurrent->getInst();
74 return *BundleCurrent->getInst();
78 return BundleCurrent ==
Other.BundleCurrent && BundleEnd ==
Other.BundleEnd &&
79 DuplexCurrent ==
Other.DuplexCurrent && DuplexEnd ==
Other.DuplexEnd;
128 bool CheckOk =
Check ?
Check->check(
false) :
true;
157 Check->reportError(
"invalid instruction packet: out of slots");
175 bool AttemptCompatibility) {
177 if (!AttemptCompatibility || ArchSTI ==
nullptr)
178 return canonicalizePacketImpl(MCII, STI, Context, MCB,
Check);
184 if (canonicalizePacketImpl(MCII, STI, Context, MCB, &PerfCheck))
188 return canonicalizePacketImpl(MCII, *ArchSTI, Context, MCB, &ArchCheck);
211 assert((iClass <= 0xf) &&
"iClass must have range of 0 to 0xf");
213 duplexInst->
setOpcode(Hexagon::DuplexIClass0 + iClass);
261 using namespace Hexagon;
311 const auto &HExpr = cast<HexagonMCExpr>(Expr);
313 return *HExpr.getExpr();
436 int Size =
II[SchedClass].LastStage -
II[SchedClass].FirstStage;
442 unsigned Stage =
II[SchedClass].LastStage - 1;
471 for (
unsigned Stage =
II[SchedClass].FirstStage + 1;
472 Stage <
II[SchedClass].LastStage; ++Stage) {
540 auto Result = Hexagon::BUNDLE == MCI.
getOpcode();
552 if (isa<HexagonMCExpr>(MO.
getExpr()) &&
568 if (isa<HexagonMCExpr>(MO.
getExpr()) &&
576 int32_t SValue =
Value;
579 return SValue < MinValue || SValue > MaxValue;
584 return UValue < MinValue || UValue > MaxValue;
620 return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
621 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
651 return MCI.
getOpcode() == Hexagon::A4_ext;
661 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
665 return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
666 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
684 MCInst const &MCI,
unsigned short O) {
695 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) ||
696 (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
700 return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
704 return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31);
707std::pair<unsigned, unsigned>
710 "VecRegPair must be a vector register pair");
713 const unsigned PairIndex =
714 2 * (IsRev ? VecRegPair - Hexagon::WR0 : VecRegPair - Hexagon::W0);
716 return IsRev ? std::make_pair(PairIndex, PairIndex + 1)
717 : std::make_pair(PairIndex + 1, PairIndex);
724 ? Producer - Hexagon::WR0
725 : Producer - Hexagon::W0;
726 const unsigned ConsumerSingleIndex = (Consumer - Hexagon::V0) >> 1;
728 return ConsumerSingleIndex == ProdPairIndex;
764 auto &PredRegClass =
MRI.getRegClass(Hexagon::PredRegsRegClassID);
765 return PredRegClass.contains(Reg);
769 MCInst const &Inst,
unsigned I) {
773 Desc.operands()[
I].RegClass == Hexagon::PredRegsRegClassID;
813 case Hexagon::SA1_addi:
814 case Hexagon::SA1_addrx:
815 case Hexagon::SA1_addsp:
816 case Hexagon::SA1_and1:
817 case Hexagon::SA1_clrf:
818 case Hexagon::SA1_clrfnew:
819 case Hexagon::SA1_clrt:
820 case Hexagon::SA1_clrtnew:
821 case Hexagon::SA1_cmpeqi:
822 case Hexagon::SA1_combine0i:
823 case Hexagon::SA1_combine1i:
824 case Hexagon::SA1_combine2i:
825 case Hexagon::SA1_combine3i:
826 case Hexagon::SA1_combinerz:
827 case Hexagon::SA1_combinezr:
828 case Hexagon::SA1_dec:
829 case Hexagon::SA1_inc:
830 case Hexagon::SA1_seti:
831 case Hexagon::SA1_setin1:
832 case Hexagon::SA1_sxtb:
833 case Hexagon::SA1_sxth:
834 case Hexagon::SA1_tfr:
835 case Hexagon::SA1_zxtb:
836 case Hexagon::SA1_zxth:
837 case Hexagon::SL1_loadri_io:
838 case Hexagon::SL1_loadrub_io:
839 case Hexagon::SL2_deallocframe:
840 case Hexagon::SL2_jumpr31:
841 case Hexagon::SL2_jumpr31_f:
842 case Hexagon::SL2_jumpr31_fnew:
843 case Hexagon::SL2_jumpr31_t:
844 case Hexagon::SL2_jumpr31_tnew:
845 case Hexagon::SL2_loadrb_io:
846 case Hexagon::SL2_loadrd_sp:
847 case Hexagon::SL2_loadrh_io:
848 case Hexagon::SL2_loadri_sp:
849 case Hexagon::SL2_loadruh_io:
850 case Hexagon::SL2_return:
851 case Hexagon::SL2_return_f:
852 case Hexagon::SL2_return_fnew:
853 case Hexagon::SL2_return_t:
854 case Hexagon::SL2_return_tnew:
855 case Hexagon::SS1_storeb_io:
856 case Hexagon::SS1_storew_io:
857 case Hexagon::SS2_allocframe:
858 case Hexagon::SS2_storebi0:
859 case Hexagon::SS2_storebi1:
860 case Hexagon::SS2_stored_sp:
861 case Hexagon::SS2_storeh_io:
862 case Hexagon::SS2_storew_sp:
863 case Hexagon::SS2_storewi0:
864 case Hexagon::SS2_storewi1:
875 auto Sentinel =
static_cast<int64_t
>(std::numeric_limits<uint32_t>::max())
918 const bool IsTiny = STI.
hasFeature(Hexagon::ProcTinyCore);
925 .
Case(
"hexagonv67t", 3)
939 if (!isPredicated(MCII, MCI))
940 return {0, 0,
false};
942 for (
auto I =
Desc.getNumDefs(),
N =
Desc.getNumOperands();
I !=
N; ++
I)
943 if (
Desc.operands()[
I].RegClass == Hexagon::PredRegsRegClassID)
945 return {0, 0,
false};
958 case Hexagon::V6_vgathermh:
959 case Hexagon::V6_vgathermhq:
960 case Hexagon::V6_vgathermhw:
961 case Hexagon::V6_vgathermhwq:
962 case Hexagon::V6_vgathermw:
963 case Hexagon::V6_vgathermwq:
978 const bool NoSlotReqd = Hexagon::A4_ext == OpCode ||
979 (IsTiny && Hexagon::A2_nop == OpCode) ||
980 (IsTiny && Hexagon::J4_hintjumpr == OpCode);
988 unsigned slotsUsed = 0;
990 MCInst const &MCI = *HMI.getInst();
1010 assert(Duplex !=
nullptr);
1036 unsigned Producer2) {
1041 return ((Consumer - Hexagon::V0) & 0x1) ^ Rev;
1043 if (Producer2 != Hexagon::NoRegister)
1044 return Consumer == Producer;
1061 return (
Desc.isBranch() ||
Desc.isCall() ||
Desc.isReturn());
unsigned const MachineRegisterInfo * MRI
#define HEXAGON_PACKET_OUTER_SIZE
#define HEXAGON_PACKET_INNER_SIZE
#define HEXAGON_PACKET_SIZE
#define HEXAGON_PRESHUFFLE_PACKET_SIZE
uint64_t IntrinsicInst * II
static bool isBranch(unsigned Opcode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static SymbolRef::Type getType(const Symbol *Sym)
Check for a valid bundle.
void setMustNotExtend(bool Val=true)
bool mustNotExtend() const
void setMustExtend(bool Val=true)
void setS27_2_reloc(bool Val=true)
bool isPredicated() const
bool operator==(PacketIterator const &Other) const
PacketIterator & operator++()
MCInst const & operator*() const
PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
Base class for the full range of assembler expressions which are needed for parsing.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
void setInst(const MCInst *Val)
const MCInst * getInst() const
const MCExpr * getExpr() const
static MCOperand createInst(const MCInst *Val)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const FeatureBitset & getFeatureBits() const
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Wrapper class representing virtual and physical registers.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
LLVM Value Representation.
A range adaptor for a pair of iterators.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned const TypeCVI_LAST
@ RestrictNoSlot1StoreMask
@ RestrictNoSlot1StorePos
static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)
unsigned const TypeCVI_FIRST
bool IsReverseVecRegPair(unsigned VecReg)
bool isDblRegForSubInst(unsigned Reg)
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst deriveSubInst(MCInst const &Inst)
bool hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI)
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
void setOuterLoop(MCInst &MCI)
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
bool isOuterLoop(MCInst const &MCI)
bool isIntRegForSubInst(unsigned Reg)
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)
size_t bundleSize(MCInst const &MCI)
bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &I)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
bool IsVecRegPair(unsigned VecReg)
unsigned getCVIResources(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the resources used by this instruction.
void padEndloop(MCInst &MCI, MCContext &Context)
constexpr int64_t memReorderDisabledMask
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
void setInnerLoop(MCInst &MCI)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg)
bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)
bool isMemReorderDisabled(MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
std::pair< unsigned, unsigned > GetVecRegPairIndices(unsigned VecRegPair)
Returns an ordered pair of the constituent register ordinals for each of the elements of VecRegPair.
bool mustNotExtend(MCExpr const &Expr)
bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI)
Return true if the operand is a new-value store insn.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
bool LoopNeedsPadding(MCInst const &MCB)
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
void setMemReorderDisabled(MCInst &MCI)
bool isBundle(MCInst const &MCI)
int64_t minConstant(MCInst const &MCI, size_t Index)
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
MCExpr const & getExpr(MCExpr const &Expr)
bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer)
bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
Return whether the operand is extendable.
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
bool isImmext(MCInst const &MCI)
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I)
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
bool isIntReg(unsigned Reg)
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
constexpr int64_t innerLoopMask
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
constexpr size_t bundleInstructionsOffset
bool s27_2_reloc(MCExpr const &Expr)
bool hasImmExt(MCInst const &MCI)
bool isInnerLoop(MCInst const &MCI)
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of.
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned packetSizeSlots(MCSubtargetInfo const &STI)
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)
constexpr int64_t outerLoopMask
MCInst const & instruction(MCInst const &MCB, size_t Index)
bool IsVecRegSingle(unsigned VecReg)
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
bool mustExtend(MCExpr const &Expr)
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getDuplexRegisterNumbering(unsigned Reg)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isSubInstruction(MCInst const &MCI)
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
void setMustExtend(MCExpr const &Expr, bool Val=true)
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
unsigned packetSize(StringRef CPU)
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
cl::opt< bool > HexagonDisableCompound
bool HexagonMCShuffle(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
unsigned HexagonGetLastSlot()
const InstrStage HexagonStages[]
Description of the encoding of one expression Op.
An itinerary represents the scheduling information for an instruction.
const InstrItinerary * InstrItineraries