26using namespace Hexagon;
28#define DEBUG_TYPE "hexagon-mccompound"
42 J4_tstbit0_fp0_jump_nt, J4_tstbit0_fp0_jump_t, J4_tstbit0_fp1_jump_nt,
43 J4_tstbit0_fp1_jump_t, J4_tstbit0_tp0_jump_nt, J4_tstbit0_tp0_jump_t,
44 J4_tstbit0_tp1_jump_nt, J4_tstbit0_tp1_jump_t};
46 J4_cmpeq_fp0_jump_nt, J4_cmpeq_fp0_jump_t, J4_cmpeq_fp1_jump_nt,
47 J4_cmpeq_fp1_jump_t, J4_cmpeq_tp0_jump_nt, J4_cmpeq_tp0_jump_t,
48 J4_cmpeq_tp1_jump_nt, J4_cmpeq_tp1_jump_t};
50 J4_cmpgt_fp0_jump_nt, J4_cmpgt_fp0_jump_t, J4_cmpgt_fp1_jump_nt,
51 J4_cmpgt_fp1_jump_t, J4_cmpgt_tp0_jump_nt, J4_cmpgt_tp0_jump_t,
52 J4_cmpgt_tp1_jump_nt, J4_cmpgt_tp1_jump_t};
54 J4_cmpgtu_fp0_jump_nt, J4_cmpgtu_fp0_jump_t, J4_cmpgtu_fp1_jump_nt,
55 J4_cmpgtu_fp1_jump_t, J4_cmpgtu_tp0_jump_nt, J4_cmpgtu_tp0_jump_t,
56 J4_cmpgtu_tp1_jump_nt, J4_cmpgtu_tp1_jump_t};
58 J4_cmpeqi_fp0_jump_nt, J4_cmpeqi_fp0_jump_t, J4_cmpeqi_fp1_jump_nt,
59 J4_cmpeqi_fp1_jump_t, J4_cmpeqi_tp0_jump_nt, J4_cmpeqi_tp0_jump_t,
60 J4_cmpeqi_tp1_jump_nt, J4_cmpeqi_tp1_jump_t};
62 J4_cmpgti_fp0_jump_nt, J4_cmpgti_fp0_jump_t, J4_cmpgti_fp1_jump_nt,
63 J4_cmpgti_fp1_jump_t, J4_cmpgti_tp0_jump_nt, J4_cmpgti_tp0_jump_t,
64 J4_cmpgti_tp1_jump_nt, J4_cmpgti_tp1_jump_t};
66 J4_cmpgtui_fp0_jump_nt, J4_cmpgtui_fp0_jump_t, J4_cmpgtui_fp1_jump_nt,
67 J4_cmpgtui_fp1_jump_t, J4_cmpgtui_tp0_jump_nt, J4_cmpgtui_tp0_jump_t,
68 J4_cmpgtui_tp1_jump_nt, J4_cmpgtui_tp1_jump_t};
70 J4_cmpeqn1_fp0_jump_nt, J4_cmpeqn1_fp0_jump_t, J4_cmpeqn1_fp1_jump_nt,
71 J4_cmpeqn1_fp1_jump_t, J4_cmpeqn1_tp0_jump_nt, J4_cmpeqn1_tp0_jump_t,
72 J4_cmpeqn1_tp1_jump_nt, J4_cmpeqn1_tp1_jump_t};
74 J4_cmpgtn1_fp0_jump_nt, J4_cmpgtn1_fp0_jump_t, J4_cmpgtn1_fp1_jump_nt,
75 J4_cmpgtn1_fp1_jump_t, J4_cmpgtn1_tp0_jump_nt, J4_cmpgtn1_tp0_jump_t,
76 J4_cmpgtn1_tp1_jump_nt, J4_cmpgtn1_tp1_jump_t,
81 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
83 switch (
MI.getOpcode()) {
92 case Hexagon::C2_cmpeq:
93 case Hexagon::C2_cmpgt:
94 case Hexagon::C2_cmpgtu:
97 DstReg =
MI.getOperand(0).getReg();
98 Src1Reg =
MI.getOperand(1).getReg();
99 Src2Reg =
MI.getOperand(2).getReg();
100 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
105 case Hexagon::C2_cmpeqi:
106 case Hexagon::C2_cmpgti:
107 case Hexagon::C2_cmpgtui:
111 DstReg =
MI.getOperand(0).getReg();
112 SrcReg =
MI.getOperand(1).getReg();
113 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
115 (HexagonMCInstrInfo::inRange<5>(
MI, 2) ||
119 case Hexagon::A2_tfr:
123 DstReg =
MI.getOperand(0).getReg();
124 SrcReg =
MI.getOperand(1).getReg();
129 case Hexagon::A2_tfrsi:
133 DstReg =
MI.getOperand(0).getReg();
139 case Hexagon::S2_tstbit_i:
142 DstReg =
MI.getOperand(0).getReg();
143 Src1Reg =
MI.getOperand(1).getReg();
144 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
153 case Hexagon::J2_jumptnew:
154 case Hexagon::J2_jumpfnew:
155 case Hexagon::J2_jumptnewpt:
156 case Hexagon::J2_jumpfnewpt:
157 Src1Reg =
MI.getOperand(0).getReg();
158 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg)
165 case Hexagon::J2_jump:
166 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
177 unsigned PredReg = Predicate.getReg();
179 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) ||
180 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3));
186 case Hexagon::J2_jumpfnew:
188 case Hexagon::J2_jumpfnewpt:
190 case Hexagon::J2_jumptnew:
192 case Hexagon::J2_jumptnewpt:
199 MCInst *CompoundInsn =
nullptr;
200 unsigned compoundOpcode;
205 switch (L.getOpcode()) {
210 case Hexagon::A2_tfrsi:
211 Rt = L.getOperand(0);
212 compoundOpcode = J4_jumpseti;
221 case Hexagon::A2_tfr:
222 Rt = L.getOperand(0);
223 Rs = L.getOperand(1);
225 compoundOpcode = J4_jumpsetr;
234 case Hexagon::C2_cmpeq:
236 Rs = L.getOperand(1);
237 Rt = L.getOperand(2);
247 case Hexagon::C2_cmpgt:
249 Rs = L.getOperand(1);
250 Rt = L.getOperand(2);
260 case Hexagon::C2_cmpgtu:
262 Rs = L.getOperand(1);
263 Rt = L.getOperand(2);
273 case Hexagon::C2_cmpeqi:
275 Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(
Value);
283 Rs = L.getOperand(1);
291 case Hexagon::C2_cmpgti:
293 Success = L.getOperand(2).getExpr()->evaluateAsAbsolute(
Value);
301 Rs = L.getOperand(1);
309 case Hexagon::C2_cmpgtui:
311 Rs = L.getOperand(1);
320 case Hexagon::S2_tstbit_i:
322 Rs = L.getOperand(1);
336 MCInst const &MIb,
bool IsExtendedB) {
343 (Opca == Hexagon::A2_tfr || Opca == Hexagon::A2_tfrsi))
352 bool JExtended =
false;
355 J != MCI.
end(); ++J) {
356 MCInst const *JumpInst = J->getInst();
363 bool BExtended =
false;
366 B != MCI.
end(); ++
B) {
367 MCInst const *Inst =
B->getInst();
368 if (JumpInst == Inst) {
382 << JumpInst->
getOpcode() <<
" Compounds to "
384 J->setInst(CompoundInsn);
404 "Non-Bundle where Bundle expected");
414 MCInst LastValidBundle(MCI);
425 if (PreviouslyValid && !IsValid) {
427 MCI = LastValidBundle;
428 }
else if (IsValid) {
429 LastValidBundle = MCI;
430 PreviouslyValid =
true;
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static bool lookForCompound(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI)
static const unsigned cmpgtBitOpcode[8]
static unsigned getCompoundCandidateGroup(MCInst const &MI, bool IsExtended)
static const unsigned cmpeqiBitOpcode[8]
static const unsigned cmpgtuBitOpcode[8]
static const unsigned cmpeqn1BitOpcode[8]
static const unsigned cmpgtn1BitOpcode[8]
static unsigned getCompoundOp(MCInst const &HMCI)
getCompoundOp - Return the index from 0-7 into the above opcode lists.
static const unsigned cmpgtuiBitOpcode[8]
static bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, MCInst const &MIb, bool IsExtendedB)
Non-Symmetrical. See if these two instructions are fit for compound pair.
static const unsigned cmpeqBitOpcode[8]
static const unsigned cmpgtiBitOpcode[8]
static MCInst * getCompoundInsn(MCContext &Context, MCInst const &L, MCInst const &R)
static const unsigned tstBitOpcode[8]
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Context object for machine code objects.
MCInst * createMCInst()
Create and return a new MC instruction.
Instances of this class represent a single low-level machine instruction.
SmallVectorImpl< MCOperand >::iterator iterator
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
Generic base class for all target subtargets.
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isIntRegForSubInst(unsigned Reg)
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
bool isBundle(MCInst const &MCI)
int64_t minConstant(MCInst const &MCI, size_t Index)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
bool isImmext(MCInst const &MCI)
constexpr size_t bundleInstructionsOffset
This is an optimization pass for GlobalISel generic memory operations.
bool HexagonMCShuffle(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.