18#include "llvm/Config/llvm-config.h"
40#include <mach/host_info.h>
42#include <mach/mach_host.h>
43#include <mach/machine.h>
45#include <sys/sysctl.h>
48#include <sys/systemcfg.h>
50#if defined(__sun__) && defined(__svr4__)
54#define DEBUG_TYPE "host-detection"
64static std::unique_ptr<llvm::MemoryBuffer>
68 if (std::error_code EC = Text.getError()) {
70 <<
"/proc/cpuinfo: " << EC.message() <<
"\n";
73 return std::move(*Text);
80 const char *
generic =
"generic";
94 while (CIP < CPUInfoEnd && CPUStart ==
nullptr) {
95 if (CIP < CPUInfoEnd && *CIP ==
'\n')
98 if (CIP < CPUInfoEnd && *CIP ==
'c') {
100 if (CIP < CPUInfoEnd && *CIP ==
'p') {
102 if (CIP < CPUInfoEnd && *CIP ==
'u') {
104 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
107 if (CIP < CPUInfoEnd && *CIP ==
':') {
109 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
112 if (CIP < CPUInfoEnd) {
114 while (CIP < CPUInfoEnd && (*CIP !=
' ' && *CIP !=
'\t' &&
115 *CIP !=
',' && *CIP !=
'\n'))
117 CPULen = CIP - CPUStart;
124 if (CPUStart ==
nullptr)
125 while (CIP < CPUInfoEnd && *CIP !=
'\n')
129 if (CPUStart ==
nullptr)
133 .
Case(
"604e",
"604e")
135 .
Case(
"7400",
"7400")
136 .
Case(
"7410",
"7400")
137 .
Case(
"7447",
"7400")
138 .
Case(
"7455",
"7450")
140 .
Case(
"POWER4",
"970")
141 .
Case(
"PPC970FX",
"970")
142 .
Case(
"PPC970MP",
"970")
144 .
Case(
"POWER5",
"g5")
146 .
Case(
"POWER6",
"pwr6")
147 .
Case(
"POWER7",
"pwr7")
148 .
Case(
"POWER8",
"pwr8")
149 .
Case(
"POWER8E",
"pwr8")
150 .
Case(
"POWER8NVL",
"pwr8")
151 .
Case(
"POWER9",
"pwr9")
152 .
Case(
"POWER10",
"pwr10")
166 ProcCpuinfoContent.
split(Lines,
"\n");
172 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
174 Implementer = Lines[
I].substr(15).ltrim(
"\t :");
176 Hardware = Lines[
I].substr(8).ltrim(
"\t :");
178 Part = Lines[
I].substr(8).ltrim(
"\t :");
181 if (Implementer ==
"0x41") {
194 .
Case(
"0x926",
"arm926ej-s")
195 .
Case(
"0xb02",
"mpcore")
196 .
Case(
"0xb36",
"arm1136j-s")
197 .
Case(
"0xb56",
"arm1156t2-s")
198 .
Case(
"0xb76",
"arm1176jz-s")
199 .
Case(
"0xc05",
"cortex-a5")
200 .
Case(
"0xc07",
"cortex-a7")
201 .
Case(
"0xc08",
"cortex-a8")
202 .
Case(
"0xc09",
"cortex-a9")
203 .
Case(
"0xc0f",
"cortex-a15")
204 .
Case(
"0xc0e",
"cortex-a17")
205 .
Case(
"0xc20",
"cortex-m0")
206 .
Case(
"0xc23",
"cortex-m3")
207 .
Case(
"0xc24",
"cortex-m4")
208 .
Case(
"0xc27",
"cortex-m7")
209 .
Case(
"0xd20",
"cortex-m23")
210 .
Case(
"0xd21",
"cortex-m33")
211 .
Case(
"0xd24",
"cortex-m52")
212 .
Case(
"0xd22",
"cortex-m55")
213 .
Case(
"0xd23",
"cortex-m85")
214 .
Case(
"0xc18",
"cortex-r8")
215 .
Case(
"0xd13",
"cortex-r52")
216 .
Case(
"0xd16",
"cortex-r52plus")
217 .
Case(
"0xd15",
"cortex-r82")
218 .
Case(
"0xd14",
"cortex-r82ae")
219 .
Case(
"0xd02",
"cortex-a34")
220 .
Case(
"0xd04",
"cortex-a35")
221 .
Case(
"0xd03",
"cortex-a53")
222 .
Case(
"0xd05",
"cortex-a55")
223 .
Case(
"0xd46",
"cortex-a510")
224 .
Case(
"0xd80",
"cortex-a520")
225 .
Case(
"0xd88",
"cortex-a520ae")
226 .
Case(
"0xd07",
"cortex-a57")
227 .
Case(
"0xd06",
"cortex-a65")
228 .
Case(
"0xd43",
"cortex-a65ae")
229 .
Case(
"0xd08",
"cortex-a72")
230 .
Case(
"0xd09",
"cortex-a73")
231 .
Case(
"0xd0a",
"cortex-a75")
232 .
Case(
"0xd0b",
"cortex-a76")
233 .
Case(
"0xd0e",
"cortex-a76ae")
234 .
Case(
"0xd0d",
"cortex-a77")
235 .
Case(
"0xd41",
"cortex-a78")
236 .
Case(
"0xd42",
"cortex-a78ae")
237 .
Case(
"0xd4b",
"cortex-a78c")
238 .
Case(
"0xd47",
"cortex-a710")
239 .
Case(
"0xd4d",
"cortex-a715")
240 .
Case(
"0xd81",
"cortex-a720")
241 .
Case(
"0xd89",
"cortex-a720ae")
242 .
Case(
"0xd87",
"cortex-a725")
243 .
Case(
"0xd44",
"cortex-x1")
244 .
Case(
"0xd4c",
"cortex-x1c")
245 .
Case(
"0xd48",
"cortex-x2")
246 .
Case(
"0xd4e",
"cortex-x3")
247 .
Case(
"0xd82",
"cortex-x4")
248 .
Case(
"0xd85",
"cortex-x925")
249 .
Case(
"0xd4a",
"neoverse-e1")
250 .
Case(
"0xd0c",
"neoverse-n1")
251 .
Case(
"0xd49",
"neoverse-n2")
252 .
Case(
"0xd8e",
"neoverse-n3")
253 .
Case(
"0xd40",
"neoverse-v1")
254 .
Case(
"0xd4f",
"neoverse-v2")
255 .
Case(
"0xd84",
"neoverse-v3")
256 .
Case(
"0xd83",
"neoverse-v3ae")
260 if (Implementer ==
"0x42" || Implementer ==
"0x43") {
262 .
Case(
"0x516",
"thunderx2t99")
263 .
Case(
"0x0516",
"thunderx2t99")
264 .
Case(
"0xaf",
"thunderx2t99")
265 .
Case(
"0x0af",
"thunderx2t99")
266 .
Case(
"0xa1",
"thunderxt88")
267 .
Case(
"0x0a1",
"thunderxt88")
271 if (Implementer ==
"0x46") {
273 .
Case(
"0x001",
"a64fx")
277 if (Implementer ==
"0x4e") {
279 .
Case(
"0x004",
"carmel")
283 if (Implementer ==
"0x48")
288 .
Case(
"0xd01",
"tsv110")
291 if (Implementer ==
"0x51")
296 .
Case(
"0x06f",
"krait")
297 .
Case(
"0x201",
"kryo")
298 .
Case(
"0x205",
"kryo")
299 .
Case(
"0x211",
"kryo")
300 .
Case(
"0x800",
"cortex-a73")
301 .
Case(
"0x801",
"cortex-a73")
302 .
Case(
"0x802",
"cortex-a75")
303 .
Case(
"0x803",
"cortex-a75")
304 .
Case(
"0x804",
"cortex-a76")
305 .
Case(
"0x805",
"cortex-a76")
306 .
Case(
"0xc00",
"falkor")
307 .
Case(
"0xc01",
"saphira")
308 .
Case(
"0x001",
"oryon-1")
310 if (Implementer ==
"0x53") {
313 unsigned Variant = 0, Part = 0;
318 if (
I.consume_front(
"CPU variant"))
319 I.ltrim(
"\t :").getAsInteger(0, Variant);
324 if (
I.consume_front(
"CPU part"))
325 I.ltrim(
"\t :").getAsInteger(0, Part);
327 unsigned Exynos = (Variant << 12) | Part;
339 if (Implementer ==
"0x6d") {
342 .
Case(
"0xd49",
"neoverse-n2")
346 if (Implementer ==
"0xc0") {
348 .
Case(
"0xac3",
"ampere1")
349 .
Case(
"0xac4",
"ampere1a")
350 .
Case(
"0xac5",
"ampere1b")
358StringRef getCPUNameFromS390Model(
unsigned int Id,
bool HaveVectorSupport) {
378 return HaveVectorSupport?
"z13" :
"zEC12";
381 return HaveVectorSupport?
"z14" :
"zEC12";
384 return HaveVectorSupport?
"z15" :
"zEC12";
388 return HaveVectorSupport?
"z16" :
"zEC12";
399 ProcCpuinfoContent.
split(Lines,
"\n");
403 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I)
405 size_t Pos = Lines[
I].find(
':');
407 Lines[
I].drop_front(Pos + 1).split(CPUFeatures,
' ');
415 bool HaveVectorSupport =
false;
416 for (
unsigned I = 0, E = CPUFeatures.
size();
I != E; ++
I) {
417 if (CPUFeatures[
I] ==
"vx")
418 HaveVectorSupport =
true;
422 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
424 size_t Pos = Lines[
I].find(
"machine = ");
426 Pos +=
sizeof(
"machine = ") - 1;
428 if (!Lines[
I].drop_front(Pos).getAsInteger(10, Id))
429 return getCPUNameFromS390Model(Id, HaveVectorSupport);
441 ProcCpuinfoContent.
split(Lines,
"\n");
445 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
447 UArch = Lines[
I].substr(5).ltrim(
"\t :");
453 .
Case(
"sifive,u74-mc",
"sifive-u74")
454 .
Case(
"sifive,bullet0",
"sifive-u74")
459#if !defined(__linux__) || !defined(__x86_64__)
462 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
464 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
466 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
468 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
470 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
472 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
474 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
476 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
478 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
480 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
482 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
484 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
486 struct bpf_prog_load_attr {
502 int fd = syscall(321 , 5 , &attr,
510 memset(&attr, 0,
sizeof(attr));
515 fd = syscall(321 , 5 , &attr,
sizeof(attr));
524#if defined(__i386__) || defined(_M_IX86) || \
525 defined(__x86_64__) || defined(_M_X64)
534static bool isCpuIdSupported() {
535#if defined(__GNUC__) || defined(__clang__)
537 int __cpuid_supported;
540 " movl %%eax,%%ecx\n"
541 " xorl $0x00200000,%%eax\n"
547 " cmpl %%eax,%%ecx\n"
551 :
"=r"(__cpuid_supported)
554 if (!__cpuid_supported)
564static bool getX86CpuIDAndInfo(
unsigned value,
unsigned *rEAX,
unsigned *rEBX,
565 unsigned *rECX,
unsigned *rEDX) {
566#if defined(__GNUC__) || defined(__clang__)
567#if defined(__x86_64__)
570 __asm__(
"movq\t%%rbx, %%rsi\n\t"
572 "xchgq\t%%rbx, %%rsi\n\t"
573 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
576#elif defined(__i386__)
577 __asm__(
"movl\t%%ebx, %%esi\n\t"
579 "xchgl\t%%ebx, %%esi\n\t"
580 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
586#elif defined(_MSC_VER)
589 __cpuid(registers,
value);
590 *rEAX = registers[0];
591 *rEBX = registers[1];
592 *rECX = registers[2];
593 *rEDX = registers[3];
605VendorSignatures getVendorSignature(
unsigned *MaxLeaf) {
606 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
607 if (MaxLeaf ==
nullptr)
612 if (!isCpuIdSupported())
613 return VendorSignatures::UNKNOWN;
615 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
616 return VendorSignatures::UNKNOWN;
619 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
620 return VendorSignatures::GENUINE_INTEL;
623 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
624 return VendorSignatures::AUTHENTIC_AMD;
626 return VendorSignatures::UNKNOWN;
639static bool getX86CpuIDAndInfoEx(
unsigned value,
unsigned subleaf,
640 unsigned *rEAX,
unsigned *rEBX,
unsigned *rECX,
642#if defined(__GNUC__) || defined(__clang__)
643#if defined(__x86_64__)
646 __asm__(
"movq\t%%rbx, %%rsi\n\t"
648 "xchgq\t%%rbx, %%rsi\n\t"
649 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
650 :
"a"(
value),
"c"(subleaf));
652#elif defined(__i386__)
653 __asm__(
"movl\t%%ebx, %%esi\n\t"
655 "xchgl\t%%ebx, %%esi\n\t"
656 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
657 :
"a"(
value),
"c"(subleaf));
662#elif defined(_MSC_VER)
664 __cpuidex(registers,
value, subleaf);
665 *rEAX = registers[0];
666 *rEBX = registers[1];
667 *rECX = registers[2];
668 *rEDX = registers[3];
676static bool getX86XCR0(
unsigned *rEAX,
unsigned *rEDX) {
677#if defined(__GNUC__) || defined(__clang__)
681 __asm__(
".byte 0x0f, 0x01, 0xd0" :
"=a"(*rEAX),
"=d"(*rEDX) :
"c"(0));
683#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
684 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
693static void detectX86FamilyModel(
unsigned EAX,
unsigned *Family,
695 *Family = (
EAX >> 8) & 0xf;
697 if (*Family == 6 || *Family == 0xf) {
700 *Family += (
EAX >> 20) & 0xff;
706#define testFeature(F) (Features[F / 32] & (1 << (F % 32))) != 0
708static StringRef getIntelProcessorTypeAndSubtype(
unsigned Family,
710 const unsigned *Features,
723 if (testFeature(X86::FEATURE_MMX)) {
739 *
Type = X86::INTEL_CORE2;
748 *
Type = X86::INTEL_CORE2;
757 *
Type = X86::INTEL_COREI7;
758 *Subtype = X86::INTEL_COREI7_NEHALEM;
765 *
Type = X86::INTEL_COREI7;
766 *Subtype = X86::INTEL_COREI7_WESTMERE;
772 *
Type = X86::INTEL_COREI7;
773 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
778 *
Type = X86::INTEL_COREI7;
779 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
788 *
Type = X86::INTEL_COREI7;
789 *Subtype = X86::INTEL_COREI7_HASWELL;
798 *
Type = X86::INTEL_COREI7;
799 *Subtype = X86::INTEL_COREI7_BROADWELL;
810 *
Type = X86::INTEL_COREI7;
811 *Subtype = X86::INTEL_COREI7_SKYLAKE;
817 *
Type = X86::INTEL_COREI7;
818 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
823 *
Type = X86::INTEL_COREI7;
824 if (testFeature(X86::FEATURE_AVX512BF16)) {
826 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
827 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
829 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
831 CPU =
"skylake-avx512";
832 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
839 *
Type = X86::INTEL_COREI7;
840 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
846 CPU =
"icelake-client";
847 *
Type = X86::INTEL_COREI7;
848 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
855 *
Type = X86::INTEL_COREI7;
856 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
872 *
Type = X86::INTEL_COREI7;
873 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
879 *
Type = X86::INTEL_COREI7;
880 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
888 *
Type = X86::INTEL_COREI7;
889 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
895 *
Type = X86::INTEL_COREI7;
896 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;
901 CPU =
"graniterapids";
902 *
Type = X86::INTEL_COREI7;
903 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
908 CPU =
"graniterapids-d";
909 *
Type = X86::INTEL_COREI7;
910 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
916 CPU =
"icelake-server";
917 *
Type = X86::INTEL_COREI7;
918 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
925 CPU =
"sapphirerapids";
926 *
Type = X86::INTEL_COREI7;
927 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
936 *
Type = X86::INTEL_BONNELL;
947 *
Type = X86::INTEL_SILVERMONT;
953 *
Type = X86::INTEL_GOLDMONT;
956 CPU =
"goldmont-plus";
957 *
Type = X86::INTEL_GOLDMONT_PLUS;
964 *
Type = X86::INTEL_TREMONT;
969 CPU =
"sierraforest";
970 *
Type = X86::INTEL_SIERRAFOREST;
976 *
Type = X86::INTEL_GRANDRIDGE;
981 CPU =
"clearwaterforest";
982 *
Type = X86::INTEL_CLEARWATERFOREST;
988 *
Type = X86::INTEL_KNL;
992 *
Type = X86::INTEL_KNM;
999 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
1001 }
else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
1002 CPU =
"icelake-client";
1003 }
else if (testFeature(X86::FEATURE_AVX512VBMI)) {
1005 }
else if (testFeature(X86::FEATURE_AVX512BF16)) {
1007 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
1008 CPU =
"cascadelake";
1009 }
else if (testFeature(X86::FEATURE_AVX512VL)) {
1010 CPU =
"skylake-avx512";
1011 }
else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
1012 if (testFeature(X86::FEATURE_SHA))
1016 }
else if (testFeature(X86::FEATURE_ADX)) {
1018 }
else if (testFeature(X86::FEATURE_AVX2)) {
1020 }
else if (testFeature(X86::FEATURE_AVX)) {
1021 CPU =
"sandybridge";
1022 }
else if (testFeature(X86::FEATURE_SSE4_2)) {
1023 if (testFeature(X86::FEATURE_MOVBE))
1027 }
else if (testFeature(X86::FEATURE_SSE4_1)) {
1029 }
else if (testFeature(X86::FEATURE_SSSE3)) {
1030 if (testFeature(X86::FEATURE_MOVBE))
1034 }
else if (testFeature(X86::FEATURE_64BIT)) {
1036 }
else if (testFeature(X86::FEATURE_SSE3)) {
1038 }
else if (testFeature(X86::FEATURE_SSE2)) {
1040 }
else if (testFeature(X86::FEATURE_SSE)) {
1042 }
else if (testFeature(X86::FEATURE_MMX)) {
1051 if (testFeature(X86::FEATURE_64BIT)) {
1055 if (testFeature(X86::FEATURE_SSE3)) {
1069static const char *getAMDProcessorTypeAndSubtype(
unsigned Family,
1071 const unsigned *Features,
1073 unsigned *Subtype) {
1074 const char *CPU = 0;
1100 if (testFeature(X86::FEATURE_SSE)) {
1107 if (testFeature(X86::FEATURE_SSE3)) {
1115 *
Type = X86::AMDFAM10H;
1118 *Subtype = X86::AMDFAM10H_BARCELONA;
1121 *Subtype = X86::AMDFAM10H_SHANGHAI;
1124 *Subtype = X86::AMDFAM10H_ISTANBUL;
1130 *
Type = X86::AMD_BTVER1;
1134 *
Type = X86::AMDFAM15H;
1135 if (Model >= 0x60 && Model <= 0x7f) {
1137 *Subtype = X86::AMDFAM15H_BDVER4;
1140 if (Model >= 0x30 && Model <= 0x3f) {
1142 *Subtype = X86::AMDFAM15H_BDVER3;
1145 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
1147 *Subtype = X86::AMDFAM15H_BDVER2;
1150 if (Model <= 0x0f) {
1151 *Subtype = X86::AMDFAM15H_BDVER1;
1157 *
Type = X86::AMD_BTVER2;
1161 *
Type = X86::AMDFAM17H;
1162 if ((Model >= 0x30 && Model <= 0x3f) || (Model == 0x47) ||
1163 (Model >= 0x60 && Model <= 0x67) || (Model >= 0x68 && Model <= 0x6f) ||
1164 (Model >= 0x70 && Model <= 0x7f) || (Model >= 0x84 && Model <= 0x87) ||
1165 (Model >= 0x90 && Model <= 0x97) || (Model >= 0x98 && Model <= 0x9f) ||
1166 (Model >= 0xa0 && Model <= 0xaf)) {
1177 *Subtype = X86::AMDFAM17H_ZNVER2;
1180 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x20 && Model <= 0x2f)) {
1184 *Subtype = X86::AMDFAM17H_ZNVER1;
1190 *
Type = X86::AMDFAM19H;
1191 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) ||
1192 (Model >= 0x30 && Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) ||
1193 (Model >= 0x50 && Model <= 0x5f)) {
1199 *Subtype = X86::AMDFAM19H_ZNVER3;
1202 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x60 && Model <= 0x6f) ||
1203 (Model >= 0x70 && Model <= 0x77) || (Model >= 0x78 && Model <= 0x7f) ||
1204 (Model >= 0xa0 && Model <= 0xaf)) {
1211 *Subtype = X86::AMDFAM19H_ZNVER4;
1224static void getAvailableFeatures(
unsigned ECX,
unsigned EDX,
unsigned MaxLeaf,
1225 unsigned *Features) {
1228 auto setFeature = [&](
unsigned F) {
1229 Features[
F / 32] |= 1U << (
F % 32);
1232 if ((EDX >> 15) & 1)
1233 setFeature(X86::FEATURE_CMOV);
1234 if ((EDX >> 23) & 1)
1235 setFeature(X86::FEATURE_MMX);
1236 if ((EDX >> 25) & 1)
1237 setFeature(X86::FEATURE_SSE);
1238 if ((EDX >> 26) & 1)
1239 setFeature(X86::FEATURE_SSE2);
1242 setFeature(X86::FEATURE_SSE3);
1244 setFeature(X86::FEATURE_PCLMUL);
1246 setFeature(X86::FEATURE_SSSE3);
1247 if ((ECX >> 12) & 1)
1248 setFeature(X86::FEATURE_FMA);
1249 if ((ECX >> 19) & 1)
1250 setFeature(X86::FEATURE_SSE4_1);
1251 if ((ECX >> 20) & 1) {
1252 setFeature(X86::FEATURE_SSE4_2);
1253 setFeature(X86::FEATURE_CRC32);
1255 if ((ECX >> 23) & 1)
1256 setFeature(X86::FEATURE_POPCNT);
1257 if ((ECX >> 25) & 1)
1258 setFeature(X86::FEATURE_AES);
1260 if ((ECX >> 22) & 1)
1261 setFeature(X86::FEATURE_MOVBE);
1266 const unsigned AVXBits = (1 << 27) | (1 << 28);
1267 bool HasAVX = ((
ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1268 ((
EAX & 0x6) == 0x6);
1269#if defined(__APPLE__)
1273 bool HasAVX512Save =
true;
1276 bool HasAVX512Save = HasAVX && ((
EAX & 0xe0) == 0xe0);
1280 setFeature(X86::FEATURE_AVX);
1283 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1285 if (HasLeaf7 && ((EBX >> 3) & 1))
1286 setFeature(X86::FEATURE_BMI);
1287 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1288 setFeature(X86::FEATURE_AVX2);
1289 if (HasLeaf7 && ((EBX >> 8) & 1))
1290 setFeature(X86::FEATURE_BMI2);
1291 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) {
1292 setFeature(X86::FEATURE_AVX512F);
1293 setFeature(X86::FEATURE_EVEX512);
1295 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1296 setFeature(X86::FEATURE_AVX512DQ);
1297 if (HasLeaf7 && ((EBX >> 19) & 1))
1298 setFeature(X86::FEATURE_ADX);
1299 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1300 setFeature(X86::FEATURE_AVX512IFMA);
1301 if (HasLeaf7 && ((EBX >> 23) & 1))
1302 setFeature(X86::FEATURE_CLFLUSHOPT);
1303 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1304 setFeature(X86::FEATURE_AVX512CD);
1305 if (HasLeaf7 && ((EBX >> 29) & 1))
1306 setFeature(X86::FEATURE_SHA);
1307 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1308 setFeature(X86::FEATURE_AVX512BW);
1309 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1310 setFeature(X86::FEATURE_AVX512VL);
1312 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1313 setFeature(X86::FEATURE_AVX512VBMI);
1314 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1315 setFeature(X86::FEATURE_AVX512VBMI2);
1316 if (HasLeaf7 && ((ECX >> 8) & 1))
1317 setFeature(X86::FEATURE_GFNI);
1318 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1319 setFeature(X86::FEATURE_VPCLMULQDQ);
1320 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1321 setFeature(X86::FEATURE_AVX512VNNI);
1322 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1323 setFeature(X86::FEATURE_AVX512BITALG);
1324 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1325 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1327 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1328 setFeature(X86::FEATURE_AVX5124VNNIW);
1329 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1330 setFeature(X86::FEATURE_AVX5124FMAPS);
1331 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1332 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1336 bool HasLeaf7Subleaf1 =
1337 HasLeaf7 &&
EAX >= 1 &&
1338 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1339 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1340 setFeature(X86::FEATURE_AVX512BF16);
1342 unsigned MaxExtLevel;
1343 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1345 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1346 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1347 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1348 setFeature(X86::FEATURE_SSE4_A);
1349 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1350 setFeature(X86::FEATURE_XOP);
1351 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1352 setFeature(X86::FEATURE_FMA4);
1354 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1355 setFeature(X86::FEATURE_64BIT);
1359 unsigned MaxLeaf = 0;
1361 if (Vendor == VendorSignatures::UNKNOWN)
1365 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1367 unsigned Family = 0,
Model = 0;
1369 detectX86FamilyModel(EAX, &Family, &Model);
1370 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1375 unsigned Subtype = 0;
1379 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1380 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1382 }
else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1383 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1393#elif defined(__APPLE__) && defined(__powerpc__)
1395 host_basic_info_data_t hostInfo;
1396 mach_msg_type_number_t infoCount;
1398 infoCount = HOST_BASIC_INFO_COUNT;
1399 mach_port_t hostPort = mach_host_self();
1400 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1402 mach_port_deallocate(mach_task_self(), hostPort);
1404 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1407 switch (hostInfo.cpu_subtype) {
1437#elif defined(__linux__) && defined(__powerpc__)
1441 return detail::getHostCPUNameForPowerPC(
Content);
1443#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1447 return detail::getHostCPUNameForARM(
Content);
1449#elif defined(__linux__) && defined(__s390x__)
1453 return detail::getHostCPUNameForS390x(
Content);
1455#elif defined(__MVS__)
1460 int *StartToCVTOffset =
reinterpret_cast<int *
>(0x10);
1463 int ReadValue = *StartToCVTOffset;
1465 ReadValue = (ReadValue & 0x7FFFFFFF);
1466 char *CVT =
reinterpret_cast<char *
>(ReadValue);
1471 Id = decodePackedBCD<uint16_t>(Id,
false);
1475 bool HaveVectorSupport = CVT[244] & 0x80;
1476 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1478#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1479#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1480#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1481#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1482#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1483#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1484#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1485#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1486#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1487#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1488#define CPUFAMILY_ARM_BLIZZARD_AVALANCHE 0xda33d83d
1489#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea
1493 size_t Length =
sizeof(Family);
1494 sysctlbyname(
"hw.cpufamily", &Family, &
Length, NULL, 0);
1497 case CPUFAMILY_ARM_SWIFT:
1499 case CPUFAMILY_ARM_CYCLONE:
1501 case CPUFAMILY_ARM_TYPHOON:
1503 case CPUFAMILY_ARM_TWISTER:
1505 case CPUFAMILY_ARM_HURRICANE:
1507 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1509 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1511 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1513 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1515 case CPUFAMILY_ARM_BLIZZARD_AVALANCHE:
1517 case CPUFAMILY_ARM_EVEREST_SAWTOOTH:
1526 switch (_system_configuration.implementation) {
1528 if (_system_configuration.version == PV_4_3)
1532 if (_system_configuration.version == PV_5)
1536 if (_system_configuration.version == PV_6_Compat)
1556#elif defined(__loongarch__)
1560 __asm__(
"cpucfg %[prid], $zero\n\t" : [prid]
"=r"(processor_id));
1562 switch (processor_id & 0xf000) {
1571#elif defined(__riscv)
1573#if defined(__linux__)
1580#if __riscv_xlen == 64
1581 return "generic-rv64";
1582#elif __riscv_xlen == 32
1583 return "generic-rv32";
1585#error "Unhandled value of __riscv_xlen"
1588#elif defined(__sparc__)
1589#if defined(__linux__)
1592 ProcCpuinfoContent.
split(Lines,
"\n");
1596 for (
unsigned I = 0, E =
Lines.size();
I != E; ++
I) {
1598 Cpu =
Lines[
I].substr(5).ltrim(
"\t :");
1630#if defined(__linux__)
1633 return detail::getHostCPUNameForSPARC(
Content);
1634#elif defined(__sun__) && defined(__svr4__)
1638 kstat_named_t *brand = NULL;
1642 ksp = kstat_lookup(kc,
const_cast<char *
>(
"cpu_info"), -1, NULL);
1643 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1644 ksp->ks_type == KSTAT_TYPE_NAMED)
1646 (kstat_named_t *)kstat_data_lookup(ksp,
const_cast<char *
>(
"brand"));
1647 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1648 buf = KSTAT_NAMED_STR_PTR(brand);
1653 .
Case(
"TMS390S10",
"supersparc")
1654 .
Case(
"TMS390Z50",
"supersparc")
1657 .
Case(
"MB86904",
"supersparc")
1658 .
Case(
"MB86907",
"supersparc")
1659 .
Case(
"RT623",
"hypersparc")
1660 .
Case(
"RT625",
"hypersparc")
1661 .
Case(
"RT626",
"hypersparc")
1662 .
Case(
"UltraSPARC-I",
"ultrasparc")
1663 .
Case(
"UltraSPARC-II",
"ultrasparc")
1664 .
Case(
"UltraSPARC-IIe",
"ultrasparc")
1665 .
Case(
"UltraSPARC-IIi",
"ultrasparc")
1666 .
Case(
"SPARC64-III",
"ultrasparc")
1667 .
Case(
"SPARC64-IV",
"ultrasparc")
1668 .
Case(
"UltraSPARC-III",
"ultrasparc3")
1669 .
Case(
"UltraSPARC-III+",
"ultrasparc3")
1670 .
Case(
"UltraSPARC-IIIi",
"ultrasparc3")
1671 .
Case(
"UltraSPARC-IIIi+",
"ultrasparc3")
1672 .
Case(
"UltraSPARC-IV",
"ultrasparc3")
1673 .
Case(
"UltraSPARC-IV+",
"ultrasparc3")
1674 .
Case(
"SPARC64-V",
"ultrasparc3")
1675 .
Case(
"SPARC64-VI",
"ultrasparc3")
1676 .
Case(
"SPARC64-VII",
"ultrasparc3")
1677 .
Case(
"UltraSPARC-T1",
"niagara")
1678 .
Case(
"UltraSPARC-T2",
"niagara2")
1679 .
Case(
"UltraSPARC-T2",
"niagara2")
1680 .
Case(
"UltraSPARC-T2+",
"niagara2")
1681 .
Case(
"SPARC-T3",
"niagara3")
1682 .
Case(
"SPARC-T4",
"niagara4")
1683 .
Case(
"SPARC-T5",
"niagara4")
1685 .
Case(
"SPARC-M7",
"niagara4" )
1686 .
Case(
"SPARC-S7",
"niagara4" )
1687 .
Case(
"SPARC-M8",
"niagara4" )
1710#if defined(__i386__) || defined(_M_IX86) || \
1711 defined(__x86_64__) || defined(_M_X64)
1717 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1720 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1722 Features[
"cx8"] = (
EDX >> 8) & 1;
1723 Features[
"cmov"] = (
EDX >> 15) & 1;
1724 Features[
"mmx"] = (
EDX >> 23) & 1;
1725 Features[
"fxsr"] = (
EDX >> 24) & 1;
1726 Features[
"sse"] = (
EDX >> 25) & 1;
1727 Features[
"sse2"] = (
EDX >> 26) & 1;
1729 Features[
"sse3"] = (
ECX >> 0) & 1;
1730 Features[
"pclmul"] = (
ECX >> 1) & 1;
1731 Features[
"ssse3"] = (
ECX >> 9) & 1;
1732 Features[
"cx16"] = (
ECX >> 13) & 1;
1733 Features[
"sse4.1"] = (
ECX >> 19) & 1;
1734 Features[
"sse4.2"] = (
ECX >> 20) & 1;
1735 Features[
"crc32"] = Features[
"sse4.2"];
1736 Features[
"movbe"] = (
ECX >> 22) & 1;
1737 Features[
"popcnt"] = (
ECX >> 23) & 1;
1738 Features[
"aes"] = (
ECX >> 25) & 1;
1739 Features[
"rdrnd"] = (
ECX >> 30) & 1;
1744 bool HasXSave = ((
ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1745 bool HasAVXSave = HasXSave && ((
ECX >> 28) & 1) && ((
EAX & 0x6) == 0x6);
1746#if defined(__APPLE__)
1750 bool HasAVX512Save =
true;
1753 bool HasAVX512Save = HasAVXSave && ((
EAX & 0xe0) == 0xe0);
1756 const unsigned AMXBits = (1 << 17) | (1 << 18);
1757 bool HasAMXSave = HasXSave && ((
EAX & AMXBits) == AMXBits);
1759 Features[
"avx"] = HasAVXSave;
1760 Features[
"fma"] = ((
ECX >> 12) & 1) && HasAVXSave;
1762 Features[
"xsave"] = ((
ECX >> 26) & 1) && HasAVXSave;
1763 Features[
"f16c"] = ((
ECX >> 29) & 1) && HasAVXSave;
1765 unsigned MaxExtLevel;
1766 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1768 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1769 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1770 Features[
"sahf"] = HasExtLeaf1 && ((
ECX >> 0) & 1);
1771 Features[
"lzcnt"] = HasExtLeaf1 && ((
ECX >> 5) & 1);
1772 Features[
"sse4a"] = HasExtLeaf1 && ((
ECX >> 6) & 1);
1773 Features[
"prfchw"] = HasExtLeaf1 && ((
ECX >> 8) & 1);
1774 Features[
"xop"] = HasExtLeaf1 && ((
ECX >> 11) & 1) && HasAVXSave;
1775 Features[
"lwp"] = HasExtLeaf1 && ((
ECX >> 15) & 1);
1776 Features[
"fma4"] = HasExtLeaf1 && ((
ECX >> 16) & 1) && HasAVXSave;
1777 Features[
"tbm"] = HasExtLeaf1 && ((
ECX >> 21) & 1);
1778 Features[
"mwaitx"] = HasExtLeaf1 && ((
ECX >> 29) & 1);
1780 Features[
"64bit"] = HasExtLeaf1 && ((
EDX >> 29) & 1);
1784 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1785 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1786 Features[
"clzero"] = HasExtLeaf8 && ((
EBX >> 0) & 1);
1787 Features[
"rdpru"] = HasExtLeaf8 && ((
EBX >> 4) & 1);
1788 Features[
"wbnoinvd"] = HasExtLeaf8 && ((
EBX >> 9) & 1);
1791 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1793 Features[
"fsgsbase"] = HasLeaf7 && ((
EBX >> 0) & 1);
1794 Features[
"sgx"] = HasLeaf7 && ((
EBX >> 2) & 1);
1795 Features[
"bmi"] = HasLeaf7 && ((
EBX >> 3) & 1);
1797 Features[
"avx2"] = HasLeaf7 && ((
EBX >> 5) & 1) && HasAVXSave;
1798 Features[
"bmi2"] = HasLeaf7 && ((
EBX >> 8) & 1);
1799 Features[
"invpcid"] = HasLeaf7 && ((
EBX >> 10) & 1);
1800 Features[
"rtm"] = HasLeaf7 && ((
EBX >> 11) & 1);
1802 Features[
"avx512f"] = HasLeaf7 && ((
EBX >> 16) & 1) && HasAVX512Save;
1803 if (Features[
"avx512f"])
1804 Features[
"evex512"] =
true;
1805 Features[
"avx512dq"] = HasLeaf7 && ((
EBX >> 17) & 1) && HasAVX512Save;
1806 Features[
"rdseed"] = HasLeaf7 && ((
EBX >> 18) & 1);
1807 Features[
"adx"] = HasLeaf7 && ((
EBX >> 19) & 1);
1808 Features[
"avx512ifma"] = HasLeaf7 && ((
EBX >> 21) & 1) && HasAVX512Save;
1809 Features[
"clflushopt"] = HasLeaf7 && ((
EBX >> 23) & 1);
1810 Features[
"clwb"] = HasLeaf7 && ((
EBX >> 24) & 1);
1811 Features[
"avx512cd"] = HasLeaf7 && ((
EBX >> 28) & 1) && HasAVX512Save;
1812 Features[
"sha"] = HasLeaf7 && ((
EBX >> 29) & 1);
1813 Features[
"avx512bw"] = HasLeaf7 && ((
EBX >> 30) & 1) && HasAVX512Save;
1814 Features[
"avx512vl"] = HasLeaf7 && ((
EBX >> 31) & 1) && HasAVX512Save;
1816 Features[
"avx512vbmi"] = HasLeaf7 && ((
ECX >> 1) & 1) && HasAVX512Save;
1817 Features[
"pku"] = HasLeaf7 && ((
ECX >> 4) & 1);
1818 Features[
"waitpkg"] = HasLeaf7 && ((
ECX >> 5) & 1);
1819 Features[
"avx512vbmi2"] = HasLeaf7 && ((
ECX >> 6) & 1) && HasAVX512Save;
1820 Features[
"shstk"] = HasLeaf7 && ((
ECX >> 7) & 1);
1821 Features[
"gfni"] = HasLeaf7 && ((
ECX >> 8) & 1);
1822 Features[
"vaes"] = HasLeaf7 && ((
ECX >> 9) & 1) && HasAVXSave;
1823 Features[
"vpclmulqdq"] = HasLeaf7 && ((
ECX >> 10) & 1) && HasAVXSave;
1824 Features[
"avx512vnni"] = HasLeaf7 && ((
ECX >> 11) & 1) && HasAVX512Save;
1825 Features[
"avx512bitalg"] = HasLeaf7 && ((
ECX >> 12) & 1) && HasAVX512Save;
1826 Features[
"avx512vpopcntdq"] = HasLeaf7 && ((
ECX >> 14) & 1) && HasAVX512Save;
1827 Features[
"rdpid"] = HasLeaf7 && ((
ECX >> 22) & 1);
1828 Features[
"kl"] = HasLeaf7 && ((
ECX >> 23) & 1);
1829 Features[
"cldemote"] = HasLeaf7 && ((
ECX >> 25) & 1);
1830 Features[
"movdiri"] = HasLeaf7 && ((
ECX >> 27) & 1);
1831 Features[
"movdir64b"] = HasLeaf7 && ((
ECX >> 28) & 1);
1832 Features[
"enqcmd"] = HasLeaf7 && ((
ECX >> 29) & 1);
1834 Features[
"uintr"] = HasLeaf7 && ((
EDX >> 5) & 1);
1835 Features[
"avx512vp2intersect"] =
1836 HasLeaf7 && ((
EDX >> 8) & 1) && HasAVX512Save;
1837 Features[
"serialize"] = HasLeaf7 && ((
EDX >> 14) & 1);
1838 Features[
"tsxldtrk"] = HasLeaf7 && ((
EDX >> 16) & 1);
1849 Features[
"pconfig"] = HasLeaf7 && ((
EDX >> 18) & 1);
1850 Features[
"amx-bf16"] = HasLeaf7 && ((
EDX >> 22) & 1) && HasAMXSave;
1851 Features[
"avx512fp16"] = HasLeaf7 && ((
EDX >> 23) & 1) && HasAVX512Save;
1852 Features[
"amx-tile"] = HasLeaf7 && ((
EDX >> 24) & 1) && HasAMXSave;
1853 Features[
"amx-int8"] = HasLeaf7 && ((
EDX >> 25) & 1) && HasAMXSave;
1856 bool HasLeaf7Subleaf1 =
1857 HasLeaf7 &&
EAX >= 1 &&
1858 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1859 Features[
"sha512"] = HasLeaf7Subleaf1 && ((
EAX >> 0) & 1);
1860 Features[
"sm3"] = HasLeaf7Subleaf1 && ((
EAX >> 1) & 1);
1861 Features[
"sm4"] = HasLeaf7Subleaf1 && ((
EAX >> 2) & 1);
1862 Features[
"raoint"] = HasLeaf7Subleaf1 && ((
EAX >> 3) & 1);
1863 Features[
"avxvnni"] = HasLeaf7Subleaf1 && ((
EAX >> 4) & 1) && HasAVXSave;
1864 Features[
"avx512bf16"] = HasLeaf7Subleaf1 && ((
EAX >> 5) & 1) && HasAVX512Save;
1865 Features[
"amx-fp16"] = HasLeaf7Subleaf1 && ((
EAX >> 21) & 1) && HasAMXSave;
1866 Features[
"cmpccxadd"] = HasLeaf7Subleaf1 && ((
EAX >> 7) & 1);
1867 Features[
"hreset"] = HasLeaf7Subleaf1 && ((
EAX >> 22) & 1);
1868 Features[
"avxifma"] = HasLeaf7Subleaf1 && ((
EAX >> 23) & 1) && HasAVXSave;
1869 Features[
"avxvnniint8"] = HasLeaf7Subleaf1 && ((
EDX >> 4) & 1) && HasAVXSave;
1870 Features[
"avxneconvert"] = HasLeaf7Subleaf1 && ((
EDX >> 5) & 1) && HasAVXSave;
1871 Features[
"amx-complex"] = HasLeaf7Subleaf1 && ((
EDX >> 8) & 1) && HasAMXSave;
1872 Features[
"avxvnniint16"] = HasLeaf7Subleaf1 && ((
EDX >> 10) & 1) && HasAVXSave;
1873 Features[
"prefetchi"] = HasLeaf7Subleaf1 && ((
EDX >> 14) & 1);
1874 Features[
"usermsr"] = HasLeaf7Subleaf1 && ((
EDX >> 15) & 1);
1875 Features[
"avx10.1-256"] = HasLeaf7Subleaf1 && ((
EDX >> 19) & 1);
1876 bool HasAPXF = HasLeaf7Subleaf1 && ((
EDX >> 21) & 1);
1877 Features[
"egpr"] = HasAPXF;
1878 Features[
"push2pop2"] = HasAPXF;
1879 Features[
"ppx"] = HasAPXF;
1880 Features[
"ndd"] = HasAPXF;
1881 Features[
"ccmp"] = HasAPXF;
1882 Features[
"cf"] = HasAPXF;
1884 bool HasLeafD = MaxLevel >= 0xd &&
1885 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1888 Features[
"xsaveopt"] = HasLeafD && ((
EAX >> 0) & 1) && HasAVXSave;
1889 Features[
"xsavec"] = HasLeafD && ((
EAX >> 1) & 1) && HasAVXSave;
1890 Features[
"xsaves"] = HasLeafD && ((
EAX >> 3) & 1) && HasAVXSave;
1892 bool HasLeaf14 = MaxLevel >= 0x14 &&
1893 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1895 Features[
"ptwrite"] = HasLeaf14 && ((
EBX >> 4) & 1);
1898 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1899 Features[
"widekl"] = HasLeaf7 && HasLeaf19 && ((
EBX >> 2) & 1);
1902 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);
1903 Features[
"avx10.1-512"] =
1904 Features[
"avx10.1-256"] && HasLeaf24 && ((
EBX >> 18) & 1);
1908#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1916 P->getBuffer().split(Lines,
"\n");
1921 for (
unsigned I = 0, E =
Lines.size();
I != E; ++
I)
1923 Lines[
I].split(CPUFeatures,
' ');
1927#if defined(__aarch64__)
1929 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1933 for (
unsigned I = 0, E = CPUFeatures.
size();
I != E; ++
I) {
1935#if defined(__aarch64__)
1936 .
Case(
"asimd",
"neon")
1937 .
Case(
"fp",
"fp-armv8")
1938 .
Case(
"crc32",
"crc")
1939 .
Case(
"atomics",
"lse")
1941 .
Case(
"sve2",
"sve2")
1943 .
Case(
"half",
"fp16")
1944 .
Case(
"neon",
"neon")
1945 .
Case(
"vfpv3",
"vfp3")
1946 .
Case(
"vfpv3d16",
"vfp3d16")
1947 .
Case(
"vfpv4",
"vfp4")
1948 .
Case(
"idiva",
"hwdiv-arm")
1949 .
Case(
"idivt",
"hwdiv")
1953#if defined(__aarch64__)
1956 if (CPUFeatures[
I] ==
"aes")
1958 else if (CPUFeatures[
I] ==
"pmull")
1959 crypto |= CAP_PMULL;
1960 else if (CPUFeatures[
I] ==
"sha1")
1962 else if (CPUFeatures[
I] ==
"sha2")
1966 if (LLVMFeatureStr !=
"")
1967 Features[LLVMFeatureStr] =
true;
1970#if defined(__aarch64__)
1972 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1973 Features[
"crypto"] =
true;
1978#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1982 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1983 Features[
"neon"] =
true;
1984 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1985 Features[
"crc"] =
true;
1986 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1987 Features[
"crypto"] =
true;
1991#elif defined(__linux__) && defined(__loongarch__)
1992#include <sys/auxv.h>
1994 unsigned long hwcap = getauxval(AT_HWCAP);
1995 bool HasFPU = hwcap & (1UL << 3);
1997 __asm__(
"cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2]
"+r"(cpucfg2));
2001 Features[
"f"] = HasFPU && (cpucfg2 & (1U << 1));
2002 Features[
"d"] = HasFPU && (cpucfg2 & (1U << 2));
2004 Features[
"lsx"] = hwcap & (1UL << 4);
2005 Features[
"lasx"] = hwcap & (1UL << 5);
2006 Features[
"lvz"] = hwcap & (1UL << 9);
2010#elif defined(__linux__) && defined(__riscv)
2012struct RISCVHwProbe {
2017 RISCVHwProbe Query[]{{3, 0},
2019 int Ret = syscall(258, Query,
2020 std::size(Query), 0,
2026 uint64_t BaseMask = Query[0].Value;
2029 Features[
"i"] =
true;
2030 Features[
"m"] =
true;
2031 Features[
"a"] =
true;
2035 Features[
"f"] = ExtMask & (1 << 0);
2036 Features[
"d"] = ExtMask & (1 << 0);
2037 Features[
"c"] = ExtMask & (1 << 1);
2038 Features[
"v"] = ExtMask & (1 << 2);
2039 Features[
"zba"] = ExtMask & (1 << 3);
2040 Features[
"zbb"] = ExtMask & (1 << 4);
2041 Features[
"zbs"] = ExtMask & (1 << 5);
2042 Features[
"zicboz"] = ExtMask & (1 << 6);
2043 Features[
"zbc"] = ExtMask & (1 << 7);
2044 Features[
"zbkb"] = ExtMask & (1 << 8);
2045 Features[
"zbkc"] = ExtMask & (1 << 9);
2046 Features[
"zbkx"] = ExtMask & (1 << 10);
2047 Features[
"zknd"] = ExtMask & (1 << 11);
2048 Features[
"zkne"] = ExtMask & (1 << 12);
2049 Features[
"zknh"] = ExtMask & (1 << 13);
2050 Features[
"zksed"] = ExtMask & (1 << 14);
2051 Features[
"zksh"] = ExtMask & (1 << 15);
2052 Features[
"zkt"] = ExtMask & (1 << 16);
2053 Features[
"zvbb"] = ExtMask & (1 << 17);
2054 Features[
"zvbc"] = ExtMask & (1 << 18);
2055 Features[
"zvkb"] = ExtMask & (1 << 19);
2056 Features[
"zvkg"] = ExtMask & (1 << 20);
2057 Features[
"zvkned"] = ExtMask & (1 << 21);
2058 Features[
"zvknha"] = ExtMask & (1 << 22);
2059 Features[
"zvknhb"] = ExtMask & (1 << 23);
2060 Features[
"zvksed"] = ExtMask & (1 << 24);
2061 Features[
"zvksh"] = ExtMask & (1 << 25);
2062 Features[
"zvkt"] = ExtMask & (1 << 26);
2063 Features[
"zfh"] = ExtMask & (1 << 27);
2064 Features[
"zfhmin"] = ExtMask & (1 << 28);
2065 Features[
"zihintntl"] = ExtMask & (1 << 29);
2066 Features[
"zvfh"] = ExtMask & (1 << 30);
2067 Features[
"zvfhmin"] = ExtMask & (1ULL << 31);
2068 Features[
"zfa"] = ExtMask & (1ULL << 32);
2069 Features[
"ztso"] = ExtMask & (1ULL << 33);
2070 Features[
"zacas"] = ExtMask & (1ULL << 34);
2071 Features[
"zicond"] = ExtMask & (1ULL << 35);
2072 Features[
"zihintpause"] =
2073 ExtMask & (1ULL << 36);
2089 T.setArchName(
"arm");
2090#elif defined(__arm64e__)
2092 T.setArchName(
"arm64e");
2093#elif defined(__aarch64__)
2095 T.setArchName(
"arm64");
2096#elif defined(__x86_64h__)
2098 T.setArchName(
"x86_64h");
2099#elif defined(__x86_64__)
2101 T.setArchName(
"x86_64");
2102#elif defined(__i386__)
2104 T.setArchName(
"i386");
2105#elif defined(__powerpc__)
2107 T.setArchName(
"powerpc");
2109# error "Unimplemented host arch fixup"
2116 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
2122 PT = withHostArch(PT);
2134#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
2136 if (CPU ==
"generic")
2139 <<
" Host CPU: " << CPU <<
'\n';
This file defines the StringMap class.
#define LLVM_ATTRIBUTE_UNUSED
Given that RA is a live value
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Represents either an error or a value T.
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
constexpr bool empty() const
empty - Check if the string is empty.
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
static constexpr size_t npos
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
StringSwitch & StartsWith(StringLiteral S, T Value)
Triple - Helper class for working with autoconf configuration names.
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
std::string normalize() const
Return the normalized form of this triple's string.
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
const std::string & str() const
bool isArch64Bit() const
Test whether the architecture is 64-bit.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
@ CPU_SUBTYPE_POWERPC_970
@ CPU_SUBTYPE_POWERPC_604e
@ CPU_SUBTYPE_POWERPC_603e
@ CPU_SUBTYPE_POWERPC_7400
@ CPU_SUBTYPE_POWERPC_604
@ CPU_SUBTYPE_POWERPC_750
@ CPU_SUBTYPE_POWERPC_601
@ CPU_SUBTYPE_POWERPC_620
@ CPU_SUBTYPE_POWERPC_603ev
@ CPU_SUBTYPE_POWERPC_603
@ CPU_SUBTYPE_POWERPC_7450
@ CPU_SUBTYPE_POWERPC_602
Helper functions to extract CPU details from CPUID on x86.
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
StringRef getHostCPUNameForBPF()
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
const StringMap< bool, MallocAllocator > getHostCPUFeatures()
getHostCPUFeatures - Get the LLVM names for the host CPU features.
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
This is an optimization pass for GlobalISel generic memory operations.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.