MachineScheduler.h File Reference

#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include <algorithm>
#include <cassert>
#include <llvm/Support/raw_ostream.h>
#include <memory>
#include <string>
#include <vector>

Go to the source code of this file.

Classes
struct	llvm::MachineSchedContext
	MachineSchedContext provides enough context from the MachineScheduler pass for the target to instantiate a scheduler. More...
class	llvm::MachineSchedRegistry
	MachineSchedRegistry provides a selection of available machine instruction schedulers. More...
struct	llvm::MachineSchedPolicy
	Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy. More...
class	llvm::MachineSchedStrategy
	MachineSchedStrategy - Interface to the scheduling algorithm used by ScheduleDAGMI. More...
class	llvm::ScheduleDAGMI
	ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions according to the given MachineSchedStrategy without much extra book-keeping. More...
class	llvm::ScheduleDAGMILive
	ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while updating LiveIntervals and tracking regpressure. More...
class	llvm::ReadyQueue
	Helpers for implementing custom MachineSchedStrategy classes. More...
struct	llvm::SchedRemainder
	Summarize the unscheduled region. More...
class	llvm::ResourceSegments
	ResourceSegments are a collection of intervals closed on the left and opened on the right: More...
class	llvm::SchedBoundary
	Each Scheduling boundary is associated with ready queues. More...
class	llvm::GenericSchedulerBase
	Base class for GenericScheduler. More...
struct	llvm::GenericSchedulerBase::CandPolicy
	Policy for scheduling the next instruction in the candidate's zone. More...
struct	llvm::GenericSchedulerBase::SchedResourceDelta
	Status of an instruction's critical resource consumption. More...
struct	llvm::GenericSchedulerBase::SchedCandidate
	Store the state used by GenericScheduler heuristics, required for the lifetime of one invocation of pickNode(). More...
class	llvm::GenericScheduler
	GenericScheduler shrinks the unscheduled zone using heuristics to balance the schedule. More...
class	llvm::PostGenericScheduler
	PostGenericScheduler - Interface to the scheduling algorithm used by ScheduleDAGMI. More...

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::MISched

Enumerations
enum	llvm::MISched::Direction { llvm::MISched::Unspecified , llvm::MISched::TopDown , llvm::MISched::BottomUp , llvm::MISched::Bidirectional }

Functions
bool	llvm::tryLess (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)
	Return true if this heuristic determines order.
bool	llvm::tryGreater (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)
bool	llvm::tryLatency (GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone)
bool	llvm::tryPressure (const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason, const TargetRegisterInfo *TRI, const MachineFunction &MF)
unsigned	llvm::getWeakLeft (const SUnit *SU, bool isTop)
int	llvm::biasPhysReg (const SUnit *SU, bool isTop)
	Minimize physical register live ranges.
ScheduleDAGMILive *	llvm::createGenericSchedLive (MachineSchedContext *C)
	Create the standard converging machine scheduler.
ScheduleDAGMI *	llvm::createGenericSchedPostRA (MachineSchedContext *C)
	Create a generic scheduler with no vreg liveness or DAG mutation passes.
std::unique_ptr< ScheduleDAGMutation >	llvm::createLoadClusterDAGMutation (const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
	If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store clustering.
std::unique_ptr< ScheduleDAGMutation >	llvm::createStoreClusterDAGMutation (const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
	If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store clustering.
std::unique_ptr< ScheduleDAGMutation >	llvm::createCopyConstrainDAGMutation (const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)

Variables
cl::opt< MISched::Direction >	llvm::PreRADirection
cl::opt< bool >	llvm::VerifyScheduling
cl::opt< bool >	llvm::ViewMISchedDAGs
cl::opt< bool >	llvm::PrintDAGs