22#define DEBUG_TYPE "pre-RA-sched"
24bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(
SUnit *SU) {
26 if (isBCTRAfterSet(SU))
38 for (
unsigned i = 0, ie = (
unsigned) SU->
Preds.size(); i != ie; ++i) {
40 if (!PredMCID || !PredMCID->
mayStore())
43 if (!SU->
Preds[i].isNormalMemory() && !SU->
Preds[i].isBarrier())
46 for (
unsigned j = 0, je = CurGroup.size(); j != je; ++j)
47 if (SU->
Preds[i].getSUnit() == CurGroup[j])
54bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(
SUnit *SU) {
64 for (
unsigned i = 0, ie = (
unsigned) SU->
Preds.size(); i != ie; ++i) {
66 if (!PredMCID || PredMCID->
getSchedClass() != PPC::Sched::IIC_SprMTSPR)
69 if (SU->
Preds[i].isCtrl())
72 for (
unsigned j = 0, je = CurGroup.size(); j != je; ++j)
73 if (SU->
Preds[i].getSUnit() == CurGroup[j])
85bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(
const MCInstrDesc *MCID,
95 case PPC::Sched::IIC_IntDivW:
96 case PPC::Sched::IIC_IntDivD:
97 case PPC::Sched::IIC_LdStLoadUpd:
98 case PPC::Sched::IIC_LdStLDU:
99 case PPC::Sched::IIC_LdStLFDU:
100 case PPC::Sched::IIC_LdStLFDUX:
101 case PPC::Sched::IIC_LdStLHA:
102 case PPC::Sched::IIC_LdStLHAU:
103 case PPC::Sched::IIC_LdStLWA:
104 case PPC::Sched::IIC_LdStSTU:
105 case PPC::Sched::IIC_LdStSTFDU:
108 case PPC::Sched::IIC_LdStLoadUpdX:
109 case PPC::Sched::IIC_LdStLDUX:
110 case PPC::Sched::IIC_LdStLHAUX:
111 case PPC::Sched::IIC_LdStLWARX:
112 case PPC::Sched::IIC_LdStLDARX:
113 case PPC::Sched::IIC_LdStSTUX:
114 case PPC::Sched::IIC_LdStSTDCX:
115 case PPC::Sched::IIC_LdStSTWCX:
116 case PPC::Sched::IIC_BrMCRX:
130 case PPC::Sched::IIC_BrCR:
131 case PPC::Sched::IIC_SprMFCR:
132 case PPC::Sched::IIC_SprMFCRF:
133 case PPC::Sched::IIC_SprMTSPR:
140 if (Stalls == 0 && isLoadAfterStore(SU))
149 if (MCID && mustComeFirst(MCID, NSlots) && CurSlots)
159 if (isLoadAfterStore(SU) && CurSlots < 6) {
177 if (CurSlots == 5 || (MCID->
isBranch() && CurBranches == 1)) {
179 CurSlots = CurBranches = 0;
185 bool MustBeFirst = mustComeFirst(MCID, NSlots);
189 if (MustBeFirst && CurSlots) {
190 CurSlots = CurBranches = 0;
195 CurGroup.push_back(SU);
215 CurSlots = CurBranches = 0;
229 CurSlots = CurBranches = 0;
231 CurGroup.push_back(
nullptr);
267void PPCHazardRecognizer970::EndDispatchGroup() {
278PPCHazardRecognizer970::GetInstrType(
unsigned Opcode,
279 bool &isFirst,
bool &isSingle,
297bool PPCHazardRecognizer970::
298isLoadOfStoredAddress(
uint64_t LoadSize, int64_t LoadOffset,
300 for (
unsigned i = 0, e = NumStores; i !=
e; ++i) {
302 if (
LoadValue == StoreValue[i] && LoadOffset == StoreOffset[i])
310 if (StoreOffset[i] < LoadOffset) {
311 if (int64_t(StoreOffset[i]+StoreSize[i]) > LoadOffset)
return true;
313 if (int64_t(LoadOffset+LoadSize) > StoreOffset[i])
return true;
326 assert(Stalls == 0 &&
"PPC hazards don't support scoreboard lookahead");
330 if (
MI->isDebugInstr())
333 unsigned Opcode =
MI->getOpcode();
336 GetInstrType(Opcode, isFirst, isSingle, isCracked,
342 if (NumIssued != 0 && (isFirst || isSingle))
348 if (isCracked && NumIssued > 2)
359 if (NumIssued == 4)
return Hazard;
363 if (NumIssued >= 2)
return Hazard;
370 if (HasCTRSet && Opcode == PPC::BCTRL)
375 if (
isLoad && NumStores && !
MI->memoperands_empty()) {
389 if (
MI->isDebugInstr())
392 unsigned Opcode =
MI->getOpcode();
395 GetInstrType(Opcode, isFirst, isSingle, isCracked,
400 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet =
true;
403 if (
isStore && NumStores < 4 && !MI->memoperands_empty() &&
404 (*
MI->memoperands_begin())->getSize().hasValue()) {
407 StoreOffset[NumStores] = MO->
getOffset();
408 StoreValue[NumStores] = MO->
getValue();
426 assert(NumIssued < 5 &&
"Illegal dispatch group!");
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
TypeSize getValue() const
Describe properties that are true of each instruction in the target description file.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
bool mayStore() const
Return true if this instruction could possibly modify memory.
bool mayLoad() const
Return true if this instruction could possibly read memory.
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
unsigned getOpcode() const
Return the opcode number for this descriptor.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const Value * getValue() const
Return the base address of the memory access.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
unsigned PreEmitNoops(SUnit *SU) override
PreEmitNoops - This callback is invoked prior to emitting an instruction.
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...
bool ShouldPreferAnother(SUnit *SU) override
ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard.
void EmitNoop() override
EmitNoop - This callback is invoked when a noop was added to the instruction stream.
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
PPCHazardRecognizer970(const ScheduleDAG &DAG)
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - We return hazard for any non-branch instruction that would terminate the dispatch gro...
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
Scheduling unit. This is a node in the scheduling DAG.
SmallVector< SDep, 4 > Preds
All sunit predecessors.
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
const MCInstrDesc * getInstrDesc(const SUnit *SU) const
Returns the MCInstrDesc of this SUnit.
const TargetInstrInfo * TII
Target instruction information.
MachineFunction & MF
Machine function.
virtual void dumpNode(const SUnit &SU) const =0
virtual bool ShouldPreferAnother(SUnit *)
ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard.
virtual unsigned PreEmitNoops(SUnit *)
PreEmitNoops - This callback is invoked prior to emitting an instruction.
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
InstrType
This represents what is and is not supported when finding similarity in Instructions.
@ PPC970_First
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
@ PPC970_Cracked
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
@ PPC970_Single
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
@ PPC970_Pseudo
These are the various PPC970 execution unit pipelines.
int getNonRecordFormOpcode(uint16_t)
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.