This file implements the targeting of the InstructionSelector class for RISC-V. More...

#include "MCTargetDesc/RISCVMatInt.h"
#include "RISCVRegisterBankInfo.h"
#include "RISCVSubtarget.h"
#include "RISCVTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/Support/Debug.h"
#include "RISCVGenGlobalISel.inc"

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Macros
#define	DEBUG_TYPE "riscv-isel"
#define	GET_GLOBALISEL_PREDICATE_BITSET
#define	GET_GLOBALISEL_PREDICATES_DECL
#define	GET_GLOBALISEL_TEMPORARIES_DECL
#define	GET_GLOBALISEL_IMPL
#define	GET_GLOBALISEL_PREDICATES_INIT
#define	GET_GLOBALISEL_TEMPORARIES_INIT

Functions
static void	getOperandsForBranch (Register CondReg, RISCVCC::CondCode &CC, Register &LHS, Register &RHS, MachineRegisterInfo &MRI)
static unsigned	getFCmpOpcode (CmpInst::Predicate Pred, unsigned Size)
static bool	legalizeFCmpPredicate (Register &LHS, Register &RHS, CmpInst::Predicate &Pred, bool &NeedInvert)
InstructionSelector *	llvm::createRISCVInstructionSelector (const RISCVTargetMachine &TM, const RISCVSubtarget &Subtarget, const RISCVRegisterBankInfo &RBI)