#include "Target/AMDGPU/GCNSchedStrategy.h"
Inheritance diagram for llvm::GCNPostScheduleDAGMILive:
Public Member Functions | |
| void | schedule () override |
| Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions. | |
| void | finalizeSchedule () override |
| Allow targets to perform final scheduling actions at the level of the whole MachineFunction. | |
| GCNPostScheduleDAGMILive (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S, bool RemoveKillFlags) | |
 Public Member Functions inherited from llvm::ScheduleDAGMI | |
| ScheduleDAGMI (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S, bool RemoveKillFlags) | |
| ~ScheduleDAGMI () override | |
| bool | doMBBSchedRegionsTopDown () const override |
| If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB. | |
| LiveIntervals * | getLIS () const |
| virtual bool | hasVRegLiveness () const |
| Return true if this DAG supports VReg liveness and RegPressure. | |
| void | addMutation (std::unique_ptr< ScheduleDAGMutation > Mutation) |
| Add a postprocessing step to the DAG builder. | |
| MachineBasicBlock::iterator | top () const |
| MachineBasicBlock::iterator | bottom () const |
| void | enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) override |
| Implement the ScheduleDAGInstrs interface for handling the next scheduling region. | |
| void | schedule () override |
| Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions. | |
| void | startBlock (MachineBasicBlock *bb) override |
| Prepares to perform scheduling in the given block. | |
| void | finishBlock () override |
| Cleans up after scheduling in the given block. | |
| void | moveInstruction (MachineInstr *MI, MachineBasicBlock::iterator InsertPos) |
| Change the position of an instruction within the basic block and update live ranges and region boundary iterators. | |
| const SUnit * | getNextClusterPred () const |
| const SUnit * | getNextClusterSucc () const |
| void | viewGraph (const Twine &Name, const Twine &Title) override |
| viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'. | |
| void | viewGraph () override |
| Out-of-line implementation with no arguments is handy for gdb. | |
| Public Member Functions inherited from llvm::ScheduleDAGInstrs | |
| void | setDumpDirection (DumpDirection D) |
| ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false) | |
| ~ScheduleDAGInstrs () override=default | |
| const TargetSchedModel * | getSchedModel () const |
| Gets the machine model for instruction scheduling. | |
| const MCSchedClassDesc * | getSchedClass (SUnit *SU) const |
| Resolves and cache a resolved scheduling class for an SUnit. | |
| bool | IsReachable (SUnit *SU, SUnit *TargetSU) |
| IsReachable - Checks if SU is reachable from TargetSU. | |
| MachineBasicBlock::iterator | begin () const |
| Returns an iterator to the top of the current scheduling region. | |
| MachineBasicBlock::iterator | end () const |
| Returns an iterator to the bottom of the current scheduling region. | |
| SUnit * | newSUnit (MachineInstr *MI) |
| Creates a new SUnit and return a ptr to it. | |
| SUnit * | getSUnit (MachineInstr *MI) const |
| Returns an existing SUnit for this MI, or nullptr. | |
| virtual bool | doMBBSchedRegionsTopDown () const |
| If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB. | |
| virtual void | startBlock (MachineBasicBlock *BB) |
| Prepares to perform scheduling in the given block. | |
| virtual void | finishBlock () |
| Cleans up after scheduling in the given block. | |
| virtual void | enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) |
| Initialize the DAG and common scheduler state for a new scheduling region. | |
| virtual void | exitRegion () |
| Called when the scheduler has finished scheduling the current region. | |
| void | buildSchedGraph (AAResults *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false) |
| Builds SUnits for the current region. | |
| void | addSchedBarrierDeps () |
| Adds dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. | |
| virtual void | schedule ()=0 |
| Orders nodes according to selected style. | |
| virtual void | finalizeSchedule () |
| Allow targets to perform final scheduling actions at the level of the whole MachineFunction. | |
| void | dumpNode (const SUnit &SU) const override |
| void | dump () const override |
| std::string | getGraphNodeLabel (const SUnit *SU) const override |
| Returns a label for a DAG node that points to an instruction. | |
| std::string | getDAGName () const override |
| Returns a label for the region of code covered by the DAG. | |
| void | fixupKills (MachineBasicBlock &MBB) |
| Fixes register kill flags that scheduling has made invalid. | |
| bool | canAddEdge (SUnit *SuccSU, SUnit *PredSU) |
| True if an edge can be added from PredSU to SuccSU without creating a cycle. | |
| bool | addEdge (SUnit *SuccSU, const SDep &PredDep) |
| Add a DAG edge to the given SU with the given predecessor dependence data. | |
| Public Member Functions inherited from llvm::ScheduleDAG | |
| ScheduleDAG (const ScheduleDAG &)=delete | |
| ScheduleDAG & | operator= (const ScheduleDAG &)=delete |
| ScheduleDAG (MachineFunction &mf) | |
| virtual | ~ScheduleDAG () |
| void | clearDAG () |
| Clears the DAG state (between regions). | |
| const MCInstrDesc * | getInstrDesc (const SUnit *SU) const |
| Returns the MCInstrDesc of this SUnit. | |
| virtual void | viewGraph (const Twine &Name, const Twine &Title) |
| Pops up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'. | |
| virtual void | viewGraph () |
| Out-of-line implementation with no arguments is handy for gdb. | |
| virtual void | dumpNode (const SUnit &SU) const =0 |
| virtual void | dump () const =0 |
| void | dumpNodeName (const SUnit &SU) const |
| virtual std::string | getGraphNodeLabel (const SUnit *SU) const =0 |
| Returns a label for an SUnit node in a visualization of the ScheduleDAG. | |
| virtual std::string | getDAGName () const =0 |
| Returns a label for the region of code covered by the DAG. | |
| virtual void | addCustomGraphFeatures (GraphWriter< ScheduleDAG * > &) const |
| Adds custom features for a visualization of the ScheduleDAG. | |
| unsigned | VerifyScheduledDAG (bool isBottomUp) |
| Verifies that all SUnits were scheduled and that their state is consistent. | |
Additional Inherited Members | |
| Public Types inherited from llvm::ScheduleDAGInstrs | |
| enum | DumpDirection { TopDown , BottomUp , Bidirectional , NotSet } |
| The direction that should be used to dump the scheduled Sequence. More... | |
| using | SUList = std::list< SUnit * > |
| A list of SUnits, used in Value2SUsMap, during DAG construction. | |
| Public Attributes inherited from llvm::ScheduleDAG | |
| const TargetMachine & | TM |
| Target processor. | |
| const TargetInstrInfo * | TII |
| Target instruction information. | |
| const TargetRegisterInfo * | TRI |
| Target processor register info. | |
| MachineFunction & | MF |
| Machine function. | |
| MachineRegisterInfo & | MRI |
| Virtual/real register map. | |
| std::vector< SUnit > | SUnits |
| The scheduling units. | |
| SUnit | EntrySU |
| Special node for the region entry. | |
| SUnit | ExitSU |
| Special node for the region exit. | |
| bool | StressSched |
| Protected Types inherited from llvm::ScheduleDAGInstrs | |
| using | DbgValueVector = std::vector< std::pair< MachineInstr *, MachineInstr * > > |
| Protected Member Functions inherited from llvm::ScheduleDAGMI | |
| void | postProcessDAG () |
| Apply each ScheduleDAGMutation step in order. | |
| void | initQueues (ArrayRef< SUnit * > TopRoots, ArrayRef< SUnit * > BotRoots) |
| Release ExitSU predecessors and setup scheduler queues. | |
| void | updateQueues (SUnit *SU, bool IsTopNode) |
| Update scheduler DAG and queues after scheduling an instruction. | |
| void | placeDebugValues () |
| Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues. | |
| void | dumpSchedule () const |
| dump the scheduled Sequence. | |
| void | dumpScheduleTraceTopDown () const |
| Print execution trace of the schedule top-down or bottom-up. | |
| void | dumpScheduleTraceBottomUp () const |
| bool | checkSchedLimit () |
| void | findRootsAndBiasEdges (SmallVectorImpl< SUnit * > &TopRoots, SmallVectorImpl< SUnit * > &BotRoots) |
| void | releaseSucc (SUnit *SU, SDep *SuccEdge) |
| ReleaseSucc - Decrement the NumPredsLeft count of a successor. | |
| void | releaseSuccessors (SUnit *SU) |
| releaseSuccessors - Call releaseSucc on each of SU's successors. | |
| void | releasePred (SUnit *SU, SDep *PredEdge) |
| ReleasePred - Decrement the NumSuccsLeft count of a predecessor. | |
| void | releasePredecessors (SUnit *SU) |
| releasePredecessors - Call releasePred on each of SU's predecessors. | |
| Protected Member Functions inherited from llvm::ScheduleDAGInstrs | |
| void | reduceHugeMemNodeMaps (Value2SUsMap &stores, Value2SUsMap &loads, unsigned N) |
| Reduces maps in FIFO order, by N SUs. | |
| void | addChainDependency (SUnit *SUa, SUnit *SUb, unsigned Latency=0) |
| Adds a chain edge between SUa and SUb, but only if both AAResults and Target fail to deny the dependency. | |
| void | addChainDependencies (SUnit *SU, SUList &SUs, unsigned Latency) |
| Adds dependencies as needed from all SUs in list to SU. | |
| void | addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap) |
| Adds dependencies as needed from all SUs in map, to SU. | |
| void | addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V) |
| Adds dependencies as needed to SU, from all SUs mapped to V. | |
| void | addBarrierChain (Value2SUsMap &map) |
| Adds barrier chain edges from all SUs in map, and then clear the map. | |
| void | insertBarrierChain (Value2SUsMap &map) |
| Inserts a barrier chain in a huge region, far below current SU. | |
| void | initSUnits () |
| Creates an SUnit for each real instruction, numbered in top-down topological order. | |
| void | addPhysRegDataDeps (SUnit *SU, unsigned OperIdx) |
| MO is an operand of SU's instruction that defines a physical register. | |
| void | addPhysRegDeps (SUnit *SU, unsigned OperIdx) |
| Adds register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx. | |
| void | addVRegDefDeps (SUnit *SU, unsigned OperIdx) |
| Adds register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx. | |
| void | addVRegUseDeps (SUnit *SU, unsigned OperIdx) |
| Adds a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit. | |
| LaneBitmask | getLaneMaskForMO (const MachineOperand &MO) const |
| Returns a mask for which lanes get read/written by the given (register) machine operand. | |
| bool | deadDefHasNoUse (const MachineOperand &MO) |
Returns true if the def register in MO has no uses. | |
| Protected Member Functions inherited from llvm::ScheduleDAG | |
| void | dumpNodeAll (const SUnit &SU) const |
| Protected Attributes inherited from llvm::ScheduleDAGMI | |
| AAResults * | AA |
| LiveIntervals * | LIS |
| std::unique_ptr< MachineSchedStrategy > | SchedImpl |
| std::vector< std::unique_ptr< ScheduleDAGMutation > > | Mutations |
| Ordered list of DAG postprocessing steps. | |
| MachineBasicBlock::iterator | CurrentTop |
| The top of the unscheduled zone. | |
| MachineBasicBlock::iterator | CurrentBottom |
| The bottom of the unscheduled zone. | |
| const SUnit * | NextClusterPred = nullptr |
| Record the next node in a scheduled cluster. | |
| const SUnit * | NextClusterSucc = nullptr |
| Protected Attributes inherited from llvm::ScheduleDAGInstrs | |
| const MachineLoopInfo * | MLI = nullptr |
| const MachineFrameInfo & | MFI |
| TargetSchedModel | SchedModel |
| TargetSchedModel provides an interface to the machine model. | |
| bool | RemoveKillFlags |
| True if the DAG builder should remove kill flags (in preparation for rescheduling). | |
| bool | CanHandleTerminators = false |
| The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. | |
| bool | TrackLaneMasks = false |
| Whether lane masks should get tracked. | |
| MachineBasicBlock * | BB = nullptr |
| The block in which to insert instructions. | |
| MachineBasicBlock::iterator | RegionBegin |
| The beginning of the range to be scheduled. | |
| MachineBasicBlock::iterator | RegionEnd |
| The end of the range to be scheduled. | |
| unsigned | NumRegionInstrs = 0 |
| Instructions in this region (distance(RegionBegin, RegionEnd)). | |
| DenseMap< MachineInstr *, SUnit * > | MISUnitMap |
| After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit. | |
| RegUnit2SUnitsMap | Defs |
| Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions. | |
| RegUnit2SUnitsMap | Uses |
| VReg2SUnitMultiMap | CurrentVRegDefs |
| Tracks the last instruction(s) in this region defining each virtual register. | |
| VReg2SUnitOperIdxMultiMap | CurrentVRegUses |
| Tracks the last instructions in this region using each virtual register. | |
| AAResults * | AAForDep = nullptr |
| SUnit * | BarrierChain = nullptr |
| Remember a generic side-effecting instruction as we proceed. | |
| DumpDirection | DumpDir = NotSet |
| UndefValue * | UnknownValue |
| For an unanalyzable memory access, this Value is used in maps. | |
| ScheduleDAGTopologicalSort | Topo |
| Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries. | |
| DbgValueVector | DbgValues |
| Remember instruction that precedes DBG_VALUE. | |
| MachineInstr * | FirstDbgValue = nullptr |
| LiveRegUnits | LiveRegs |
| Set of live physical registers for updating kill flags. | |
Detailed Description
Definition at line 487 of file GCNSchedStrategy.h.
Constructor & Destructor Documentation
◆ GCNPostScheduleDAGMILive()
| GCNPostScheduleDAGMILive::GCNPostScheduleDAGMILive | ( | MachineSchedContext * | C, |
| std::unique_ptr< MachineSchedStrategy > | S, | ||
| bool | RemoveKillFlags | ||
| ) |
Definition at line 1902 of file GCNSchedStrategy.cpp.
Member Function Documentation
◆ finalizeSchedule()
|
overridevirtual |
Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
By default does nothing.
Reimplemented from llvm::ScheduleDAGInstrs.
Definition at line 1918 of file GCNSchedStrategy.cpp.
References llvm::ScheduleDAGInstrs::finalizeSchedule(), and llvm::ScheduleDAGMI::Mutations.
◆ schedule()
|
overridevirtual |
Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.
Per-region scheduling driver, called back from PostMachineScheduler::runOnMachineFunction.
This is a simplified driver that does not consider liveness or register pressure. It is useful for PostRA scheduling and potentially other custom schedulers.
Reimplemented from llvm::ScheduleDAGMI.
Definition at line 1907 of file GCNSchedStrategy.cpp.
References llvm::ScheduleDAGMI::addMutation(), llvm::createIGroupLPDAGMutation(), hasIGLPInstrs(), llvm::ScheduleDAGMI::Mutations, llvm::AMDGPU::PostRA, and llvm::ScheduleDAGMI::schedule().
The documentation for this class was generated from the following files:
- lib/Target/AMDGPU/GCNSchedStrategy.h
- lib/Target/AMDGPU/GCNSchedStrategy.cpp
