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24 #define DEBUG_TYPE "R600tti"
29 TLI(
ST->getTargetLowering()), CommonTTI(
TM,
F) {}
66 unsigned AddrSpace)
const {
75 unsigned AddrSpace)
const {
81 unsigned AddrSpace)
const {
102 case Instruction::Br:
115 case Instruction::ExtractElement:
116 case Instruction::InsertElement: {
129 return Index == ~0u ? 2 : 0;
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
This is an optimization pass for GlobalISel generic memory operations.
@ LOCAL_ADDRESS
Address space for local memory.
Represents a single loop in the control flow graph.
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
The main scalar evolution driver.
unsigned getHardwareNumberOfRegisters(bool Vec) const
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
@ PARAM_I_ADDRESS
Address space for indirect addressable parameter memory (VTX1).
unsigned getMaxInterleaveFactor(unsigned VF)
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
This struct is a compact representation of a valid (non-zero power of two) alignment.
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
static constexpr TypeSize getFixed(ScalarTy ExactSize)
@ PRIVATE_ADDRESS
Address space for private memory.
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
static const Function * getParent(const Value *V)
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const
unsigned getMinVectorRegisterBitWidth() const
@ REGION_ADDRESS
Address space for region memory. (GDS)
R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
@ PARAM_D_ADDRESS
Address space for direct addressable parameter memory (CONST0).
const char LLVMTargetMachineRef TM
unsigned getNumberOfRegisters(bool Vec) const
LLVM Value Representation.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).