35#include "llvm/IR/IntrinsicsSPIRV.h"
38#define GET_GICOMBINER_DEPS
39#include "SPIRVGenPreLegalizeGICombiner.inc"
40#undef GET_GICOMBINER_DEPS
42#define DEBUG_TYPE "spirv-prelegalizer-combiner"
45using namespace MIPatternMatch;
49#define GET_GICOMBINER_TYPES
50#include "SPIRVGenPreLegalizeGICombiner.inc"
51#undef GET_GICOMBINER_TYPES
62 if (
MI.getOpcode() != TargetOpcode::G_INTRINSIC ||
63 cast<GIntrinsic>(
MI).getIntrinsicID() != Intrinsic::spv_length)
69 if (!SubInstr || SubInstr->
getOpcode() != TargetOpcode::G_FSUB)
78 Register SubDestReg =
MI.getOperand(2).getReg();
85 Register ResultReg =
MI.getOperand(0).getReg();
92 BuildMI(
MBB, InsertPt,
DL,
B.getTII().get(TargetOpcode::G_INTRINSIC));
101 for (
auto &
UseMI :
MRI.use_instructions(Reg))
105 for (
auto *MIToErase : UsesToErase)
106 MIToErase->eraseFromParent();
108 RemoveAllUses(SubDestReg);
112class SPIRVPreLegalizerCombinerImpl :
public Combiner {
115 const SPIRVPreLegalizerCombinerImplRuleConfig &RuleConfig;
119 SPIRVPreLegalizerCombinerImpl(
122 const SPIRVPreLegalizerCombinerImplRuleConfig &RuleConfig,
126 static const char *
getName() {
return "SPIRVPreLegalizerCombiner"; }
133#define GET_GICOMBINER_CLASS_MEMBERS
134#include "SPIRVGenPreLegalizeGICombiner.inc"
135#undef GET_GICOMBINER_CLASS_MEMBERS
138#define GET_GICOMBINER_IMPL
139#include "SPIRVGenPreLegalizeGICombiner.inc"
140#undef GET_GICOMBINER_IMPL
142SPIRVPreLegalizerCombinerImpl::SPIRVPreLegalizerCombinerImpl(
145 const SPIRVPreLegalizerCombinerImplRuleConfig &RuleConfig,
148 :
Combiner(MF, CInfo, TPC, &KB, CSEInfo),
149 Helper(Observer,
B,
true, &KB, MDT, LI),
150 RuleConfig(RuleConfig), STI(STI),
152#include
"SPIRVGenPreLegalizeGICombiner.inc"
157bool SPIRVPreLegalizerCombinerImpl::tryCombineAll(
MachineInstr &
MI)
const {
158 return tryCombineAllImpl(
MI);
168 SPIRVPreLegalizerCombiner();
177 SPIRVPreLegalizerCombinerImplRuleConfig RuleConfig;
182void SPIRVPreLegalizerCombiner::getAnalysisUsage(
AnalysisUsage &AU)
const {
193SPIRVPreLegalizerCombiner::SPIRVPreLegalizerCombiner()
197 if (!RuleConfig.parseCommandLineOption())
201bool SPIRVPreLegalizerCombiner::runOnMachineFunction(
MachineFunction &MF) {
203 MachineFunctionProperties::Property::FailedISel))
205 auto &TPC = getAnalysis<TargetPassConfig>();
208 const auto *LI =
ST.getLegalizerInfo();
213 GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
215 &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
217 nullptr, EnableOpt,
F.hasOptSize(),
220 CInfo.MaxIterations = 1;
221 CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
224 CInfo.EnableFullDCE =
false;
225 SPIRVPreLegalizerCombinerImpl Impl(MF, CInfo, &TPC, *KB,
nullptr,
226 RuleConfig, ST, MDT, LI);
227 return Impl.combineMachineInstrs();
230char SPIRVPreLegalizerCombiner::ID = 0;
232 "Combine SPIRV machine instrs before legalization",
false,
242 return new SPIRVPreLegalizerCombiner();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Provides analysis for continuously CSEing during GISel passes.
This file implements a version of MachineIRBuilder which CSEs insts within a MachineBasicBlock.
This contains common combine transformations that may be used in a combine pass,or by the target else...
Option class for Targets to specify which operations are combined how and when.
This contains the base class for all Combiners generated by TableGen.
This contains common code to allow clients to notify changes to machine instr.
Provides analysis for querying information about KnownBits during GISel passes.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
Contains matchers for matching SSA Machine Instructions.
This file declares the MachineIRBuilder class.
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
static StringRef getName(Value *V)
#define GET_GICOMBINER_CONSTRUCTOR_INITS
Combine SPIRV machine instrs before legalization
Target-Independent Code Generator Pass Configuration Options pass.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
virtual bool tryCombineAll(MachineInstr &I) const =0
FunctionPass class - This class is used to implement most global optimizations.
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelKnownBitsInfoAnalysis...
Analysis pass which computes a MachineDominatorTree.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineFunctionProperties & getProperties() const
Get the function properties.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Helper class to build MachineInstr.
const MachineInstrBuilder & addIntrinsicID(Intrinsic::ID ID) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Target-Independent Code Generator Pass Configuration Options.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void initializeSPIRVPreLegalizerCombinerPass(PassRegistry &)
FunctionPass * createSPIRVPreLegalizerCombiner()
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
auto instrs(const MachineBasicBlock &BB)