13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
31struct ImageDimIntrinsicInfo;
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
40class MachineIRBuilder;
42class MachineRegisterInfo;
46class TargetRegisterClass;
86 unsigned SubIdx)
const;
88 bool constrainCopyLikeIntrin(
MachineInstr &
MI,
unsigned NewOpc)
const;
125 bool selectDSAppendConsume(
MachineInstr &
MI,
bool IsAppend)
const;
131 bool selectG_INTRINSIC_W_SIDE_EFFECTS(
MachineInstr &
I)
const;
156 std::pair<Register, unsigned> selectVOP3ModsImpl(
MachineOperand &Root,
157 bool IsCanonicalizing =
true,
158 bool AllowAbs =
true,
159 bool OpSel =
false)
const;
163 bool ForceVGPR =
false)
const;
186 std::pair<Register, unsigned>
188 bool IsDOT =
false)
const;
234 std::pair<Register, int> selectFlatOffsetImpl(
MachineOperand &Root,
260 bool isDSOffset2Legal(
Register Base, int64_t Offset0, int64_t Offset1,
261 unsigned Size)
const;
266 std::pair<Register, unsigned>
277 std::pair<Register, unsigned> selectDSReadWrite2Impl(
MachineOperand &Root,
278 unsigned size)
const;
282 std::pair<Register, int64_t>
283 getPtrBaseWithConstantOffset(
Register Root,
289 struct MUBUFAddressData {
294 bool shouldUseAddr64(MUBUFAddressData AddrData)
const;
296 void splitIllegalMUBUFOffset(MachineIRBuilder &
B,
297 Register &SOffset, int64_t &ImmOffset)
const;
299 MUBUFAddressData parseMUBUFAddress(Register Src)
const;
301 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
302 Register &RSrcReg, Register &SOffset,
305 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
306 Register &SOffset, int64_t &
Offset)
const;
309 selectBUFSOffset(MachineOperand &Root)
const;
312 selectMUBUFAddr64(MachineOperand &Root)
const;
315 selectMUBUFOffset(MachineOperand &Root)
const;
321 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
322 bool &Matched)
const;
326 void renderTruncImm32(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
327 int OpIdx = -1)
const;
329 void renderTruncTImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
332 void renderOpSelTImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
335 void renderNegateImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
338 void renderBitcastImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
341 void renderPopcntImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
343 void renderExtractCPol(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
345 void renderExtractSWZ(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
347 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
350 void renderFrameIndex(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
353 void renderFPPow2ToExponent(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
356 bool isInlineImmediate(
const APInt &Imm)
const;
357 bool isInlineImmediate(
const APFloat &Imm)
const;
361 bool isUnneededShiftMask(
const MachineInstr &
MI,
unsigned ShAmtBits)
const;
363 const SIInstrInfo &TII;
364 const SIRegisterInfo &TRI;
365 const AMDGPURegisterBankInfo &RBI;
366 const AMDGPUTargetMachine &
TM;
367 const GCNSubtarget &STI;
368 bool EnableLateStructurizeCFG;
369#define GET_GLOBALISEL_PREDICATES_DECL
370#define AMDGPUSubtarget GCNSubtarget
371#include "AMDGPUGenGlobalISel.inc"
372#undef GET_GLOBALISEL_PREDICATES_DECL
373#undef AMDGPUSubtarget
375#define GET_GLOBALISEL_TEMPORARIES_DECL
376#include "AMDGPUGenGlobalISel.inc"
377#undef GET_GLOBALISEL_TEMPORARIES_DECL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const char LLVMTargetMachineRef TM
static const char * getName()
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
CodeGenCoverage * CoverageInfo
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Analysis providing profile information.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.