LLVM API Documentation

InstrEmitter.cpp
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00001 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This implements the Emit routines for the SelectionDAG class, which creates
00011 // MachineInstrs based on the decisions of the SelectionDAG instruction
00012 // selection.
00013 //
00014 //===----------------------------------------------------------------------===//
00015 
00016 #include "InstrEmitter.h"
00017 #include "SDNodeDbgValue.h"
00018 #include "llvm/ADT/Statistic.h"
00019 #include "llvm/CodeGen/MachineConstantPool.h"
00020 #include "llvm/CodeGen/MachineFunction.h"
00021 #include "llvm/CodeGen/MachineInstrBuilder.h"
00022 #include "llvm/CodeGen/MachineRegisterInfo.h"
00023 #include "llvm/CodeGen/StackMaps.h"
00024 #include "llvm/IR/DataLayout.h"
00025 #include "llvm/Support/Debug.h"
00026 #include "llvm/Support/ErrorHandling.h"
00027 #include "llvm/Support/MathExtras.h"
00028 #include "llvm/Target/TargetInstrInfo.h"
00029 #include "llvm/Target/TargetLowering.h"
00030 #include "llvm/Target/TargetMachine.h"
00031 using namespace llvm;
00032 
00033 #define DEBUG_TYPE "instr-emitter"
00034 
00035 /// MinRCSize - Smallest register class we allow when constraining virtual
00036 /// registers.  If satisfying all register class constraints would require
00037 /// using a smaller register class, emit a COPY to a new virtual register
00038 /// instead.
00039 const unsigned MinRCSize = 4;
00040 
00041 /// CountResults - The results of target nodes have register or immediate
00042 /// operands first, then an optional chain, and optional glue operands (which do
00043 /// not go into the resulting MachineInstr).
00044 unsigned InstrEmitter::CountResults(SDNode *Node) {
00045   unsigned N = Node->getNumValues();
00046   while (N && Node->getValueType(N - 1) == MVT::Glue)
00047     --N;
00048   if (N && Node->getValueType(N - 1) == MVT::Other)
00049     --N;    // Skip over chain result.
00050   return N;
00051 }
00052 
00053 /// countOperands - The inputs to target nodes have any actual inputs first,
00054 /// followed by an optional chain operand, then an optional glue operand.
00055 /// Compute the number of actual operands that will go into the resulting
00056 /// MachineInstr.
00057 ///
00058 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
00059 /// the chain and glue. These operands may be implicit on the machine instr.
00060 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
00061                               unsigned &NumImpUses) {
00062   unsigned N = Node->getNumOperands();
00063   while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
00064     --N;
00065   if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
00066     --N; // Ignore chain if it exists.
00067 
00068   // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
00069   NumImpUses = N - NumExpUses;
00070   for (unsigned I = N; I > NumExpUses; --I) {
00071     if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
00072       continue;
00073     if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
00074       if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
00075         continue;
00076     NumImpUses = N - I;
00077     break;
00078   }
00079 
00080   return N;
00081 }
00082 
00083 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
00084 /// implicit physical register output.
00085 void InstrEmitter::
00086 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
00087                 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
00088   unsigned VRBase = 0;
00089   if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00090     // Just use the input register directly!
00091     SDValue Op(Node, ResNo);
00092     if (IsClone)
00093       VRBaseMap.erase(Op);
00094     bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
00095     (void)isNew; // Silence compiler warning.
00096     assert(isNew && "Node emitted out of order - early");
00097     return;
00098   }
00099 
00100   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
00101   // the CopyToReg'd destination register instead of creating a new vreg.
00102   bool MatchReg = true;
00103   const TargetRegisterClass *UseRC = nullptr;
00104   MVT VT = Node->getSimpleValueType(ResNo);
00105 
00106   // Stick to the preferred register classes for legal types.
00107   if (TLI->isTypeLegal(VT))
00108     UseRC = TLI->getRegClassFor(VT);
00109 
00110   if (!IsClone && !IsCloned)
00111     for (SDNode *User : Node->uses()) {
00112       bool Match = true;
00113       if (User->getOpcode() == ISD::CopyToReg &&
00114           User->getOperand(2).getNode() == Node &&
00115           User->getOperand(2).getResNo() == ResNo) {
00116         unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
00117         if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
00118           VRBase = DestReg;
00119           Match = false;
00120         } else if (DestReg != SrcReg)
00121           Match = false;
00122       } else {
00123         for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
00124           SDValue Op = User->getOperand(i);
00125           if (Op.getNode() != Node || Op.getResNo() != ResNo)
00126             continue;
00127           MVT VT = Node->getSimpleValueType(Op.getResNo());
00128           if (VT == MVT::Other || VT == MVT::Glue)
00129             continue;
00130           Match = false;
00131           if (User->isMachineOpcode()) {
00132             const MCInstrDesc &II = TII->get(User->getMachineOpcode());
00133             const TargetRegisterClass *RC = nullptr;
00134             if (i+II.getNumDefs() < II.getNumOperands()) {
00135               RC = TRI->getAllocatableClass(
00136                 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
00137             }
00138             if (!UseRC)
00139               UseRC = RC;
00140             else if (RC) {
00141               const TargetRegisterClass *ComRC =
00142                 TRI->getCommonSubClass(UseRC, RC);
00143               // If multiple uses expect disjoint register classes, we emit
00144               // copies in AddRegisterOperand.
00145               if (ComRC)
00146                 UseRC = ComRC;
00147             }
00148           }
00149         }
00150       }
00151       MatchReg &= Match;
00152       if (VRBase)
00153         break;
00154     }
00155 
00156   const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
00157   SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
00158 
00159   // Figure out the register class to create for the destreg.
00160   if (VRBase) {
00161     DstRC = MRI->getRegClass(VRBase);
00162   } else if (UseRC) {
00163     assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
00164     DstRC = UseRC;
00165   } else {
00166     DstRC = TLI->getRegClassFor(VT);
00167   }
00168 
00169   // If all uses are reading from the src physical register and copying the
00170   // register is either impossible or very expensive, then don't create a copy.
00171   if (MatchReg && SrcRC->getCopyCost() < 0) {
00172     VRBase = SrcReg;
00173   } else {
00174     // Create the reg, emit the copy.
00175     VRBase = MRI->createVirtualRegister(DstRC);
00176     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
00177             VRBase).addReg(SrcReg);
00178   }
00179 
00180   SDValue Op(Node, ResNo);
00181   if (IsClone)
00182     VRBaseMap.erase(Op);
00183   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
00184   (void)isNew; // Silence compiler warning.
00185   assert(isNew && "Node emitted out of order - early");
00186 }
00187 
00188 /// getDstOfCopyToRegUse - If the only use of the specified result number of
00189 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
00190 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
00191                                                 unsigned ResNo) const {
00192   if (!Node->hasOneUse())
00193     return 0;
00194 
00195   SDNode *User = *Node->use_begin();
00196   if (User->getOpcode() == ISD::CopyToReg &&
00197       User->getOperand(2).getNode() == Node &&
00198       User->getOperand(2).getResNo() == ResNo) {
00199     unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
00200     if (TargetRegisterInfo::isVirtualRegister(Reg))
00201       return Reg;
00202   }
00203   return 0;
00204 }
00205 
00206 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
00207                                        MachineInstrBuilder &MIB,
00208                                        const MCInstrDesc &II,
00209                                        bool IsClone, bool IsCloned,
00210                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
00211   assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
00212          "IMPLICIT_DEF should have been handled as a special case elsewhere!");
00213 
00214   unsigned NumResults = CountResults(Node);
00215   for (unsigned i = 0; i < II.getNumDefs(); ++i) {
00216     // If the specific node value is only used by a CopyToReg and the dest reg
00217     // is a vreg in the same register class, use the CopyToReg'd destination
00218     // register instead of creating a new vreg.
00219     unsigned VRBase = 0;
00220     const TargetRegisterClass *RC =
00221       TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
00222     // Always let the value type influence the used register class. The
00223     // constraints on the instruction may be too lax to represent the value
00224     // type correctly. For example, a 64-bit float (X86::FR64) can't live in
00225     // the 32-bit float super-class (X86::FR32).
00226     if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
00227       const TargetRegisterClass *VTRC =
00228         TLI->getRegClassFor(Node->getSimpleValueType(i));
00229       if (RC)
00230         VTRC = TRI->getCommonSubClass(RC, VTRC);
00231       if (VTRC)
00232         RC = VTRC;
00233     }
00234 
00235     if (II.OpInfo[i].isOptionalDef()) {
00236       // Optional def must be a physical register.
00237       unsigned NumResults = CountResults(Node);
00238       VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
00239       assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
00240       MIB.addReg(VRBase, RegState::Define);
00241     }
00242 
00243     if (!VRBase && !IsClone && !IsCloned)
00244       for (SDNode *User : Node->uses()) {
00245         if (User->getOpcode() == ISD::CopyToReg &&
00246             User->getOperand(2).getNode() == Node &&
00247             User->getOperand(2).getResNo() == i) {
00248           unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
00249           if (TargetRegisterInfo::isVirtualRegister(Reg)) {
00250             const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
00251             if (RegRC == RC) {
00252               VRBase = Reg;
00253               MIB.addReg(VRBase, RegState::Define);
00254               break;
00255             }
00256           }
00257         }
00258       }
00259 
00260     // Create the result registers for this node and add the result regs to
00261     // the machine instruction.
00262     if (VRBase == 0) {
00263       assert(RC && "Isn't a register operand!");
00264       VRBase = MRI->createVirtualRegister(RC);
00265       MIB.addReg(VRBase, RegState::Define);
00266     }
00267 
00268     SDValue Op(Node, i);
00269     if (IsClone)
00270       VRBaseMap.erase(Op);
00271     bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
00272     (void)isNew; // Silence compiler warning.
00273     assert(isNew && "Node emitted out of order - early");
00274   }
00275 }
00276 
00277 /// getVR - Return the virtual register corresponding to the specified result
00278 /// of the specified node.
00279 unsigned InstrEmitter::getVR(SDValue Op,
00280                              DenseMap<SDValue, unsigned> &VRBaseMap) {
00281   if (Op.isMachineOpcode() &&
00282       Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
00283     // Add an IMPLICIT_DEF instruction before every use.
00284     unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
00285     // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
00286     // does not include operand register class info.
00287     if (!VReg) {
00288       const TargetRegisterClass *RC =
00289         TLI->getRegClassFor(Op.getSimpleValueType());
00290       VReg = MRI->createVirtualRegister(RC);
00291     }
00292     BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
00293             TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
00294     return VReg;
00295   }
00296 
00297   DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
00298   assert(I != VRBaseMap.end() && "Node emitted out of order - late");
00299   return I->second;
00300 }
00301 
00302 
00303 /// AddRegisterOperand - Add the specified register as an operand to the
00304 /// specified machine instr. Insert register copies if the register is
00305 /// not in the required register class.
00306 void
00307 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
00308                                  SDValue Op,
00309                                  unsigned IIOpNum,
00310                                  const MCInstrDesc *II,
00311                                  DenseMap<SDValue, unsigned> &VRBaseMap,
00312                                  bool IsDebug, bool IsClone, bool IsCloned) {
00313   assert(Op.getValueType() != MVT::Other &&
00314          Op.getValueType() != MVT::Glue &&
00315          "Chain and glue operands should occur at end of operand list!");
00316   // Get/emit the operand.
00317   unsigned VReg = getVR(Op, VRBaseMap);
00318   assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
00319 
00320   const MCInstrDesc &MCID = MIB->getDesc();
00321   bool isOptDef = IIOpNum < MCID.getNumOperands() &&
00322     MCID.OpInfo[IIOpNum].isOptionalDef();
00323 
00324   // If the instruction requires a register in a different class, create
00325   // a new virtual register and copy the value into it, but first attempt to
00326   // shrink VReg's register class within reason.  For example, if VReg == GR32
00327   // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
00328   if (II) {
00329     const TargetRegisterClass *DstRC = nullptr;
00330     if (IIOpNum < II->getNumOperands())
00331       DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
00332     if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
00333       unsigned NewVReg = MRI->createVirtualRegister(DstRC);
00334       BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
00335               TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
00336       VReg = NewVReg;
00337     }
00338   }
00339 
00340   // If this value has only one use, that use is a kill. This is a
00341   // conservative approximation. InstrEmitter does trivial coalescing
00342   // with CopyFromReg nodes, so don't emit kill flags for them.
00343   // Avoid kill flags on Schedule cloned nodes, since there will be
00344   // multiple uses.
00345   // Tied operands are never killed, so we need to check that. And that
00346   // means we need to determine the index of the operand.
00347   bool isKill = Op.hasOneUse() &&
00348                 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
00349                 !IsDebug &&
00350                 !(IsClone || IsCloned);
00351   if (isKill) {
00352     unsigned Idx = MIB->getNumOperands();
00353     while (Idx > 0 &&
00354            MIB->getOperand(Idx-1).isReg() &&
00355            MIB->getOperand(Idx-1).isImplicit())
00356       --Idx;
00357     bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
00358     if (isTied)
00359       isKill = false;
00360   }
00361 
00362   MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
00363              getDebugRegState(IsDebug));
00364 }
00365 
00366 /// AddOperand - Add the specified operand to the specified machine instr.  II
00367 /// specifies the instruction information for the node, and IIOpNum is the
00368 /// operand number (in the II) that we are adding.
00369 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
00370                               SDValue Op,
00371                               unsigned IIOpNum,
00372                               const MCInstrDesc *II,
00373                               DenseMap<SDValue, unsigned> &VRBaseMap,
00374                               bool IsDebug, bool IsClone, bool IsCloned) {
00375   if (Op.isMachineOpcode()) {
00376     AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
00377                        IsDebug, IsClone, IsCloned);
00378   } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
00379     MIB.addImm(C->getSExtValue());
00380   } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
00381     MIB.addFPImm(F->getConstantFPValue());
00382   } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
00383     // Turn additional physreg operands into implicit uses on non-variadic
00384     // instructions. This is used by call and return instructions passing
00385     // arguments in registers.
00386     bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
00387     MIB.addReg(R->getReg(), getImplRegState(Imp));
00388   } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
00389     MIB.addRegMask(RM->getRegMask());
00390   } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
00391     MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
00392                          TGA->getTargetFlags());
00393   } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
00394     MIB.addMBB(BBNode->getBasicBlock());
00395   } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
00396     MIB.addFrameIndex(FI->getIndex());
00397   } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
00398     MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
00399   } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
00400     int Offset = CP->getOffset();
00401     unsigned Align = CP->getAlignment();
00402     Type *Type = CP->getType();
00403     // MachineConstantPool wants an explicit alignment.
00404     if (Align == 0) {
00405       Align = TM->getDataLayout()->getPrefTypeAlignment(Type);
00406       if (Align == 0) {
00407         // Alignment of vector types.  FIXME!
00408         Align = TM->getDataLayout()->getTypeAllocSize(Type);
00409       }
00410     }
00411 
00412     unsigned Idx;
00413     MachineConstantPool *MCP = MF->getConstantPool();
00414     if (CP->isMachineConstantPoolEntry())
00415       Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
00416     else
00417       Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
00418     MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
00419   } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
00420     MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
00421   } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
00422     MIB.addBlockAddress(BA->getBlockAddress(),
00423                         BA->getOffset(),
00424                         BA->getTargetFlags());
00425   } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
00426     MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
00427   } else {
00428     assert(Op.getValueType() != MVT::Other &&
00429            Op.getValueType() != MVT::Glue &&
00430            "Chain and glue operands should occur at end of operand list!");
00431     AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
00432                        IsDebug, IsClone, IsCloned);
00433   }
00434 }
00435 
00436 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
00437                                           MVT VT, DebugLoc DL) {
00438   const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
00439   const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
00440 
00441   // RC is a sub-class of VRC that supports SubIdx.  Try to constrain VReg
00442   // within reason.
00443   if (RC && RC != VRC)
00444     RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
00445 
00446   // VReg has been adjusted.  It can be used with SubIdx operands now.
00447   if (RC)
00448     return VReg;
00449 
00450   // VReg couldn't be reasonably constrained.  Emit a COPY to a new virtual
00451   // register instead.
00452   RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
00453   assert(RC && "No legal register class for VT supports that SubIdx");
00454   unsigned NewReg = MRI->createVirtualRegister(RC);
00455   BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
00456     .addReg(VReg);
00457   return NewReg;
00458 }
00459 
00460 /// EmitSubregNode - Generate machine code for subreg nodes.
00461 ///
00462 void InstrEmitter::EmitSubregNode(SDNode *Node,
00463                                   DenseMap<SDValue, unsigned> &VRBaseMap,
00464                                   bool IsClone, bool IsCloned) {
00465   unsigned VRBase = 0;
00466   unsigned Opc = Node->getMachineOpcode();
00467 
00468   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
00469   // the CopyToReg'd destination register instead of creating a new vreg.
00470   for (SDNode *User : Node->uses()) {
00471     if (User->getOpcode() == ISD::CopyToReg &&
00472         User->getOperand(2).getNode() == Node) {
00473       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
00474       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
00475         VRBase = DestReg;
00476         break;
00477       }
00478     }
00479   }
00480 
00481   if (Opc == TargetOpcode::EXTRACT_SUBREG) {
00482     // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub.  There are no
00483     // constraints on the %dst register, COPY can target all legal register
00484     // classes.
00485     unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
00486     const TargetRegisterClass *TRC =
00487       TLI->getRegClassFor(Node->getSimpleValueType(0));
00488 
00489     unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
00490     MachineInstr *DefMI = MRI->getVRegDef(VReg);
00491     unsigned SrcReg, DstReg, DefSubIdx;
00492     if (DefMI &&
00493         TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
00494         SubIdx == DefSubIdx &&
00495         TRC == MRI->getRegClass(SrcReg)) {
00496       // Optimize these:
00497       // r1025 = s/zext r1024, 4
00498       // r1026 = extract_subreg r1025, 4
00499       // to a copy
00500       // r1026 = copy r1024
00501       VRBase = MRI->createVirtualRegister(TRC);
00502       BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
00503               TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
00504       MRI->clearKillFlags(SrcReg);
00505     } else {
00506       // VReg may not support a SubIdx sub-register, and we may need to
00507       // constrain its register class or issue a COPY to a compatible register
00508       // class.
00509       VReg = ConstrainForSubReg(VReg, SubIdx,
00510                                 Node->getOperand(0).getSimpleValueType(),
00511                                 Node->getDebugLoc());
00512 
00513       // Create the destreg if it is missing.
00514       if (VRBase == 0)
00515         VRBase = MRI->createVirtualRegister(TRC);
00516 
00517       // Create the extract_subreg machine instruction.
00518       BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
00519               TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
00520     }
00521   } else if (Opc == TargetOpcode::INSERT_SUBREG ||
00522              Opc == TargetOpcode::SUBREG_TO_REG) {
00523     SDValue N0 = Node->getOperand(0);
00524     SDValue N1 = Node->getOperand(1);
00525     SDValue N2 = Node->getOperand(2);
00526     unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
00527 
00528     // Figure out the register class to create for the destreg.  It should be
00529     // the largest legal register class supporting SubIdx sub-registers.
00530     // RegisterCoalescer will constrain it further if it decides to eliminate
00531     // the INSERT_SUBREG instruction.
00532     //
00533     //   %dst = INSERT_SUBREG %src, %sub, SubIdx
00534     //
00535     // is lowered by TwoAddressInstructionPass to:
00536     //
00537     //   %dst = COPY %src
00538     //   %dst:SubIdx = COPY %sub
00539     //
00540     // There is no constraint on the %src register class.
00541     //
00542     const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
00543     SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
00544     assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
00545 
00546     if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
00547       VRBase = MRI->createVirtualRegister(SRC);
00548 
00549     // Create the insert_subreg or subreg_to_reg machine instruction.
00550     MachineInstrBuilder MIB =
00551       BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
00552 
00553     // If creating a subreg_to_reg, then the first input operand
00554     // is an implicit value immediate, otherwise it's a register
00555     if (Opc == TargetOpcode::SUBREG_TO_REG) {
00556       const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
00557       MIB.addImm(SD->getZExtValue());
00558     } else
00559       AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
00560                  IsClone, IsCloned);
00561     // Add the subregster being inserted
00562     AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
00563                IsClone, IsCloned);
00564     MIB.addImm(SubIdx);
00565     MBB->insert(InsertPos, MIB);
00566   } else
00567     llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
00568 
00569   SDValue Op(Node, 0);
00570   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
00571   (void)isNew; // Silence compiler warning.
00572   assert(isNew && "Node emitted out of order - early");
00573 }
00574 
00575 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
00576 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
00577 /// register is constrained to be in a particular register class.
00578 ///
00579 void
00580 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
00581                                      DenseMap<SDValue, unsigned> &VRBaseMap) {
00582   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
00583 
00584   // Create the new VReg in the destination class and emit a copy.
00585   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
00586   const TargetRegisterClass *DstRC =
00587     TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
00588   unsigned NewVReg = MRI->createVirtualRegister(DstRC);
00589   BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
00590     NewVReg).addReg(VReg);
00591 
00592   SDValue Op(Node, 0);
00593   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
00594   (void)isNew; // Silence compiler warning.
00595   assert(isNew && "Node emitted out of order - early");
00596 }
00597 
00598 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
00599 ///
00600 void InstrEmitter::EmitRegSequence(SDNode *Node,
00601                                   DenseMap<SDValue, unsigned> &VRBaseMap,
00602                                   bool IsClone, bool IsCloned) {
00603   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
00604   const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
00605   unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
00606   const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
00607   MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
00608   unsigned NumOps = Node->getNumOperands();
00609   assert((NumOps & 1) == 1 &&
00610          "REG_SEQUENCE must have an odd number of operands!");
00611   for (unsigned i = 1; i != NumOps; ++i) {
00612     SDValue Op = Node->getOperand(i);
00613     if ((i & 1) == 0) {
00614       RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
00615       // Skip physical registers as they don't have a vreg to get and we'll
00616       // insert copies for them in TwoAddressInstructionPass anyway.
00617       if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
00618         unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
00619         unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
00620         const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
00621         const TargetRegisterClass *SRC =
00622         TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
00623         if (SRC && SRC != RC) {
00624           MRI->setRegClass(NewVReg, SRC);
00625           RC = SRC;
00626         }
00627       }
00628     }
00629     AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
00630                IsClone, IsCloned);
00631   }
00632 
00633   MBB->insert(InsertPos, MIB);
00634   SDValue Op(Node, 0);
00635   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
00636   (void)isNew; // Silence compiler warning.
00637   assert(isNew && "Node emitted out of order - early");
00638 }
00639 
00640 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
00641 ///
00642 MachineInstr *
00643 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
00644                            DenseMap<SDValue, unsigned> &VRBaseMap) {
00645   uint64_t Offset = SD->getOffset();
00646   MDNode* MDPtr = SD->getMDPtr();
00647   DebugLoc DL = SD->getDebugLoc();
00648 
00649   if (SD->getKind() == SDDbgValue::FRAMEIX) {
00650     // Stack address; this needs to be lowered in target-dependent fashion.
00651     // EmitTargetCodeForFrameDebugValue is responsible for allocation.
00652     return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
00653         .addFrameIndex(SD->getFrameIx()).addImm(Offset).addMetadata(MDPtr);
00654   }
00655   // Otherwise, we're going to create an instruction here.
00656   const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
00657   MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
00658   if (SD->getKind() == SDDbgValue::SDNODE) {
00659     SDNode *Node = SD->getSDNode();
00660     SDValue Op = SDValue(Node, SD->getResNo());
00661     // It's possible we replaced this SDNode with other(s) and therefore
00662     // didn't generate code for it.  It's better to catch these cases where
00663     // they happen and transfer the debug info, but trying to guarantee that
00664     // in all cases would be very fragile; this is a safeguard for any
00665     // that were missed.
00666     DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
00667     if (I==VRBaseMap.end())
00668       MIB.addReg(0U);       // undef
00669     else
00670       AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
00671                  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
00672   } else if (SD->getKind() == SDDbgValue::CONST) {
00673     const Value *V = SD->getConst();
00674     if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00675       if (CI->getBitWidth() > 64)
00676         MIB.addCImm(CI);
00677       else
00678         MIB.addImm(CI->getSExtValue());
00679     } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
00680       MIB.addFPImm(CF);
00681     } else {
00682       // Could be an Undef.  In any case insert an Undef so we can see what we
00683       // dropped.
00684       MIB.addReg(0U);
00685     }
00686   } else {
00687     // Insert an Undef so we can see what we dropped.
00688     MIB.addReg(0U);
00689   }
00690 
00691   // Indirect addressing is indicated by an Imm as the second parameter.
00692   if (SD->isIndirect())
00693     MIB.addImm(Offset);
00694   else {
00695     assert(Offset == 0 && "direct value cannot have an offset");
00696     MIB.addReg(0U, RegState::Debug);
00697   }
00698 
00699   MIB.addMetadata(MDPtr);
00700 
00701   return &*MIB;
00702 }
00703 
00704 /// EmitMachineNode - Generate machine code for a target-specific node and
00705 /// needed dependencies.
00706 ///
00707 void InstrEmitter::
00708 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
00709                 DenseMap<SDValue, unsigned> &VRBaseMap) {
00710   unsigned Opc = Node->getMachineOpcode();
00711 
00712   // Handle subreg insert/extract specially
00713   if (Opc == TargetOpcode::EXTRACT_SUBREG ||
00714       Opc == TargetOpcode::INSERT_SUBREG ||
00715       Opc == TargetOpcode::SUBREG_TO_REG) {
00716     EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
00717     return;
00718   }
00719 
00720   // Handle COPY_TO_REGCLASS specially.
00721   if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
00722     EmitCopyToRegClassNode(Node, VRBaseMap);
00723     return;
00724   }
00725 
00726   // Handle REG_SEQUENCE specially.
00727   if (Opc == TargetOpcode::REG_SEQUENCE) {
00728     EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
00729     return;
00730   }
00731 
00732   if (Opc == TargetOpcode::IMPLICIT_DEF)
00733     // We want a unique VR for each IMPLICIT_DEF use.
00734     return;
00735 
00736   const MCInstrDesc &II = TII->get(Opc);
00737   unsigned NumResults = CountResults(Node);
00738   unsigned NumDefs = II.getNumDefs();
00739   const MCPhysReg *ScratchRegs = nullptr;
00740 
00741   // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
00742   if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
00743     // Stackmaps do not have arguments and do not preserve their calling
00744     // convention. However, to simplify runtime support, they clobber the same
00745     // scratch registers as AnyRegCC.
00746     unsigned CC = CallingConv::AnyReg;
00747     if (Opc == TargetOpcode::PATCHPOINT) {
00748       CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
00749       NumDefs = NumResults;
00750     }
00751     ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
00752   }
00753 
00754   unsigned NumImpUses = 0;
00755   unsigned NodeOperands =
00756     countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
00757   bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
00758 #ifndef NDEBUG
00759   unsigned NumMIOperands = NodeOperands + NumResults;
00760   if (II.isVariadic())
00761     assert(NumMIOperands >= II.getNumOperands() &&
00762            "Too few operands for a variadic node!");
00763   else
00764     assert(NumMIOperands >= II.getNumOperands() &&
00765            NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
00766                             NumImpUses &&
00767            "#operands for dag node doesn't match .td file!");
00768 #endif
00769 
00770   // Create the new machine instruction.
00771   MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
00772 
00773   // Add result register values for things that are defined by this
00774   // instruction.
00775   if (NumResults)
00776     CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
00777 
00778   // Emit all of the actual operands of this instruction, adding them to the
00779   // instruction as appropriate.
00780   bool HasOptPRefs = NumDefs > NumResults;
00781   assert((!HasOptPRefs || !HasPhysRegOuts) &&
00782          "Unable to cope with optional defs and phys regs defs!");
00783   unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
00784   for (unsigned i = NumSkip; i != NodeOperands; ++i)
00785     AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
00786                VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
00787 
00788   // Add scratch registers as implicit def and early clobber
00789   if (ScratchRegs)
00790     for (unsigned i = 0; ScratchRegs[i]; ++i)
00791       MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
00792                                  RegState::EarlyClobber);
00793 
00794   // Transfer all of the memory reference descriptions of this instruction.
00795   MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
00796                  cast<MachineSDNode>(Node)->memoperands_end());
00797 
00798   // Insert the instruction into position in the block. This needs to
00799   // happen before any custom inserter hook is called so that the
00800   // hook knows where in the block to insert the replacement code.
00801   MBB->insert(InsertPos, MIB);
00802 
00803   // The MachineInstr may also define physregs instead of virtregs.  These
00804   // physreg values can reach other instructions in different ways:
00805   //
00806   // 1. When there is a use of a Node value beyond the explicitly defined
00807   //    virtual registers, we emit a CopyFromReg for one of the implicitly
00808   //    defined physregs.  This only happens when HasPhysRegOuts is true.
00809   //
00810   // 2. A CopyFromReg reading a physreg may be glued to this instruction.
00811   //
00812   // 3. A glued instruction may implicitly use a physreg.
00813   //
00814   // 4. A glued instruction may use a RegisterSDNode operand.
00815   //
00816   // Collect all the used physreg defs, and make sure that any unused physreg
00817   // defs are marked as dead.
00818   SmallVector<unsigned, 8> UsedRegs;
00819 
00820   // Additional results must be physical register defs.
00821   if (HasPhysRegOuts) {
00822     for (unsigned i = NumDefs; i < NumResults; ++i) {
00823       unsigned Reg = II.getImplicitDefs()[i - NumDefs];
00824       if (!Node->hasAnyUseOfValue(i))
00825         continue;
00826       // This implicitly defined physreg has a use.
00827       UsedRegs.push_back(Reg);
00828       EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
00829     }
00830   }
00831 
00832   // Scan the glue chain for any used physregs.
00833   if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
00834     for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
00835       if (F->getOpcode() == ISD::CopyFromReg) {
00836         UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
00837         continue;
00838       } else if (F->getOpcode() == ISD::CopyToReg) {
00839         // Skip CopyToReg nodes that are internal to the glue chain.
00840         continue;
00841       }
00842       // Collect declared implicit uses.
00843       const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
00844       UsedRegs.append(MCID.getImplicitUses(),
00845                       MCID.getImplicitUses() + MCID.getNumImplicitUses());
00846       // In addition to declared implicit uses, we must also check for
00847       // direct RegisterSDNode operands.
00848       for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
00849         if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
00850           unsigned Reg = R->getReg();
00851           if (TargetRegisterInfo::isPhysicalRegister(Reg))
00852             UsedRegs.push_back(Reg);
00853         }
00854     }
00855   }
00856 
00857   // Finally mark unused registers as dead.
00858   if (!UsedRegs.empty() || II.getImplicitDefs())
00859     MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
00860 
00861   // Run post-isel target hook to adjust this instruction if needed.
00862 #ifdef NDEBUG
00863   if (II.hasPostISelHook())
00864 #endif
00865     TLI->AdjustInstrPostInstrSelection(MIB, Node);
00866 }
00867 
00868 /// EmitSpecialNode - Generate machine code for a target-independent node and
00869 /// needed dependencies.
00870 void InstrEmitter::
00871 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
00872                 DenseMap<SDValue, unsigned> &VRBaseMap) {
00873   switch (Node->getOpcode()) {
00874   default:
00875 #ifndef NDEBUG
00876     Node->dump();
00877 #endif
00878     llvm_unreachable("This target-independent node should have been selected!");
00879   case ISD::EntryToken:
00880     llvm_unreachable("EntryToken should have been excluded from the schedule!");
00881   case ISD::MERGE_VALUES:
00882   case ISD::TokenFactor: // fall thru
00883     break;
00884   case ISD::CopyToReg: {
00885     unsigned SrcReg;
00886     SDValue SrcVal = Node->getOperand(2);
00887     if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
00888       SrcReg = R->getReg();
00889     else
00890       SrcReg = getVR(SrcVal, VRBaseMap);
00891 
00892     unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
00893     if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
00894       break;
00895 
00896     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
00897             DestReg).addReg(SrcReg);
00898     break;
00899   }
00900   case ISD::CopyFromReg: {
00901     unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
00902     EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
00903     break;
00904   }
00905   case ISD::EH_LABEL: {
00906     MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
00907     BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
00908             TII->get(TargetOpcode::EH_LABEL)).addSym(S);
00909     break;
00910   }
00911 
00912   case ISD::LIFETIME_START:
00913   case ISD::LIFETIME_END: {
00914     unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
00915     TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
00916 
00917     FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
00918     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
00919     .addFrameIndex(FI->getIndex());
00920     break;
00921   }
00922 
00923   case ISD::INLINEASM: {
00924     unsigned NumOps = Node->getNumOperands();
00925     if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
00926       --NumOps;  // Ignore the glue operand.
00927 
00928     // Create the inline asm machine instruction.
00929     MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(),
00930                                       TII->get(TargetOpcode::INLINEASM));
00931 
00932     // Add the asm string as an external symbol operand.
00933     SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
00934     const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
00935     MIB.addExternalSymbol(AsmStr);
00936 
00937     // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
00938     // bits.
00939     int64_t ExtraInfo =
00940       cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
00941                           getZExtValue();
00942     MIB.addImm(ExtraInfo);
00943 
00944     // Remember to operand index of the group flags.
00945     SmallVector<unsigned, 8> GroupIdx;
00946 
00947     // Add all of the operand registers to the instruction.
00948     for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
00949       unsigned Flags =
00950         cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
00951       const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
00952 
00953       GroupIdx.push_back(MIB->getNumOperands());
00954       MIB.addImm(Flags);
00955       ++i;  // Skip the ID value.
00956 
00957       switch (InlineAsm::getKind(Flags)) {
00958       default: llvm_unreachable("Bad flags!");
00959         case InlineAsm::Kind_RegDef:
00960         for (unsigned j = 0; j != NumVals; ++j, ++i) {
00961           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
00962           // FIXME: Add dead flags for physical and virtual registers defined.
00963           // For now, mark physical register defs as implicit to help fast
00964           // regalloc. This makes inline asm look a lot like calls.
00965           MIB.addReg(Reg, RegState::Define |
00966                   getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
00967         }
00968         break;
00969       case InlineAsm::Kind_RegDefEarlyClobber:
00970       case InlineAsm::Kind_Clobber:
00971         for (unsigned j = 0; j != NumVals; ++j, ++i) {
00972           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
00973           MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
00974                   getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
00975         }
00976         break;
00977       case InlineAsm::Kind_RegUse:  // Use of register.
00978       case InlineAsm::Kind_Imm:  // Immediate.
00979       case InlineAsm::Kind_Mem:  // Addressing mode.
00980         // The addressing mode has been selected, just add all of the
00981         // operands to the machine instruction.
00982         for (unsigned j = 0; j != NumVals; ++j, ++i)
00983           AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
00984                      /*IsDebug=*/false, IsClone, IsCloned);
00985 
00986         // Manually set isTied bits.
00987         if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
00988           unsigned DefGroup = 0;
00989           if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
00990             unsigned DefIdx = GroupIdx[DefGroup] + 1;
00991             unsigned UseIdx = GroupIdx.back() + 1;
00992             for (unsigned j = 0; j != NumVals; ++j)
00993               MIB->tieOperands(DefIdx + j, UseIdx + j);
00994           }
00995         }
00996         break;
00997       }
00998     }
00999 
01000     // Get the mdnode from the asm if it exists and add it to the instruction.
01001     SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
01002     const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
01003     if (MD)
01004       MIB.addMetadata(MD);
01005 
01006     MBB->insert(InsertPos, MIB);
01007     break;
01008   }
01009   }
01010 }
01011 
01012 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
01013 /// at the given position in the given block.
01014 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
01015                            MachineBasicBlock::iterator insertpos)
01016   : MF(mbb->getParent()),
01017     MRI(&MF->getRegInfo()),
01018     TM(&MF->getTarget()),
01019     TII(TM->getInstrInfo()),
01020     TRI(TM->getRegisterInfo()),
01021     TLI(TM->getTargetLowering()),
01022     MBB(mbb), InsertPos(insertpos) {
01023 }