LLVM API Documentation

InstrEmitter.cpp
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00001 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This implements the Emit routines for the SelectionDAG class, which creates
00011 // MachineInstrs based on the decisions of the SelectionDAG instruction
00012 // selection.
00013 //
00014 //===----------------------------------------------------------------------===//
00015 
00016 #define DEBUG_TYPE "instr-emitter"
00017 #include "InstrEmitter.h"
00018 #include "SDNodeDbgValue.h"
00019 #include "llvm/ADT/Statistic.h"
00020 #include "llvm/CodeGen/MachineConstantPool.h"
00021 #include "llvm/CodeGen/MachineFunction.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineRegisterInfo.h"
00024 #include "llvm/CodeGen/StackMaps.h"
00025 #include "llvm/IR/DataLayout.h"
00026 #include "llvm/Support/Debug.h"
00027 #include "llvm/Support/ErrorHandling.h"
00028 #include "llvm/Support/MathExtras.h"
00029 #include "llvm/Target/TargetInstrInfo.h"
00030 #include "llvm/Target/TargetLowering.h"
00031 #include "llvm/Target/TargetMachine.h"
00032 using namespace llvm;
00033 
00034 /// MinRCSize - Smallest register class we allow when constraining virtual
00035 /// registers.  If satisfying all register class constraints would require
00036 /// using a smaller register class, emit a COPY to a new virtual register
00037 /// instead.
00038 const unsigned MinRCSize = 4;
00039 
00040 /// CountResults - The results of target nodes have register or immediate
00041 /// operands first, then an optional chain, and optional glue operands (which do
00042 /// not go into the resulting MachineInstr).
00043 unsigned InstrEmitter::CountResults(SDNode *Node) {
00044   unsigned N = Node->getNumValues();
00045   while (N && Node->getValueType(N - 1) == MVT::Glue)
00046     --N;
00047   if (N && Node->getValueType(N - 1) == MVT::Other)
00048     --N;    // Skip over chain result.
00049   return N;
00050 }
00051 
00052 /// countOperands - The inputs to target nodes have any actual inputs first,
00053 /// followed by an optional chain operand, then an optional glue operand.
00054 /// Compute the number of actual operands that will go into the resulting
00055 /// MachineInstr.
00056 ///
00057 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
00058 /// the chain and glue. These operands may be implicit on the machine instr.
00059 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
00060                               unsigned &NumImpUses) {
00061   unsigned N = Node->getNumOperands();
00062   while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
00063     --N;
00064   if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
00065     --N; // Ignore chain if it exists.
00066 
00067   // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
00068   NumImpUses = N - NumExpUses;
00069   for (unsigned I = N; I > NumExpUses; --I) {
00070     if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
00071       continue;
00072     if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
00073       if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
00074         continue;
00075     NumImpUses = N - I;
00076     break;
00077   }
00078 
00079   return N;
00080 }
00081 
00082 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
00083 /// implicit physical register output.
00084 void InstrEmitter::
00085 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
00086                 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
00087   unsigned VRBase = 0;
00088   if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00089     // Just use the input register directly!
00090     SDValue Op(Node, ResNo);
00091     if (IsClone)
00092       VRBaseMap.erase(Op);
00093     bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
00094     (void)isNew; // Silence compiler warning.
00095     assert(isNew && "Node emitted out of order - early");
00096     return;
00097   }
00098 
00099   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
00100   // the CopyToReg'd destination register instead of creating a new vreg.
00101   bool MatchReg = true;
00102   const TargetRegisterClass *UseRC = nullptr;
00103   MVT VT = Node->getSimpleValueType(ResNo);
00104 
00105   // Stick to the preferred register classes for legal types.
00106   if (TLI->isTypeLegal(VT))
00107     UseRC = TLI->getRegClassFor(VT);
00108 
00109   if (!IsClone && !IsCloned)
00110     for (SDNode *User : Node->uses()) {
00111       bool Match = true;
00112       if (User->getOpcode() == ISD::CopyToReg &&
00113           User->getOperand(2).getNode() == Node &&
00114           User->getOperand(2).getResNo() == ResNo) {
00115         unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
00116         if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
00117           VRBase = DestReg;
00118           Match = false;
00119         } else if (DestReg != SrcReg)
00120           Match = false;
00121       } else {
00122         for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
00123           SDValue Op = User->getOperand(i);
00124           if (Op.getNode() != Node || Op.getResNo() != ResNo)
00125             continue;
00126           MVT VT = Node->getSimpleValueType(Op.getResNo());
00127           if (VT == MVT::Other || VT == MVT::Glue)
00128             continue;
00129           Match = false;
00130           if (User->isMachineOpcode()) {
00131             const MCInstrDesc &II = TII->get(User->getMachineOpcode());
00132             const TargetRegisterClass *RC = nullptr;
00133             if (i+II.getNumDefs() < II.getNumOperands()) {
00134               RC = TRI->getAllocatableClass(
00135                 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
00136             }
00137             if (!UseRC)
00138               UseRC = RC;
00139             else if (RC) {
00140               const TargetRegisterClass *ComRC =
00141                 TRI->getCommonSubClass(UseRC, RC);
00142               // If multiple uses expect disjoint register classes, we emit
00143               // copies in AddRegisterOperand.
00144               if (ComRC)
00145                 UseRC = ComRC;
00146             }
00147           }
00148         }
00149       }
00150       MatchReg &= Match;
00151       if (VRBase)
00152         break;
00153     }
00154 
00155   const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
00156   SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
00157 
00158   // Figure out the register class to create for the destreg.
00159   if (VRBase) {
00160     DstRC = MRI->getRegClass(VRBase);
00161   } else if (UseRC) {
00162     assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
00163     DstRC = UseRC;
00164   } else {
00165     DstRC = TLI->getRegClassFor(VT);
00166   }
00167 
00168   // If all uses are reading from the src physical register and copying the
00169   // register is either impossible or very expensive, then don't create a copy.
00170   if (MatchReg && SrcRC->getCopyCost() < 0) {
00171     VRBase = SrcReg;
00172   } else {
00173     // Create the reg, emit the copy.
00174     VRBase = MRI->createVirtualRegister(DstRC);
00175     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
00176             VRBase).addReg(SrcReg);
00177   }
00178 
00179   SDValue Op(Node, ResNo);
00180   if (IsClone)
00181     VRBaseMap.erase(Op);
00182   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
00183   (void)isNew; // Silence compiler warning.
00184   assert(isNew && "Node emitted out of order - early");
00185 }
00186 
00187 /// getDstOfCopyToRegUse - If the only use of the specified result number of
00188 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
00189 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
00190                                                 unsigned ResNo) const {
00191   if (!Node->hasOneUse())
00192     return 0;
00193 
00194   SDNode *User = *Node->use_begin();
00195   if (User->getOpcode() == ISD::CopyToReg &&
00196       User->getOperand(2).getNode() == Node &&
00197       User->getOperand(2).getResNo() == ResNo) {
00198     unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
00199     if (TargetRegisterInfo::isVirtualRegister(Reg))
00200       return Reg;
00201   }
00202   return 0;
00203 }
00204 
00205 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
00206                                        MachineInstrBuilder &MIB,
00207                                        const MCInstrDesc &II,
00208                                        bool IsClone, bool IsCloned,
00209                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
00210   assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
00211          "IMPLICIT_DEF should have been handled as a special case elsewhere!");
00212 
00213   unsigned NumResults = CountResults(Node);
00214   for (unsigned i = 0; i < II.getNumDefs(); ++i) {
00215     // If the specific node value is only used by a CopyToReg and the dest reg
00216     // is a vreg in the same register class, use the CopyToReg'd destination
00217     // register instead of creating a new vreg.
00218     unsigned VRBase = 0;
00219     const TargetRegisterClass *RC =
00220       TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
00221     // Always let the value type influence the used register class. The
00222     // constraints on the instruction may be too lax to represent the value
00223     // type correctly. For example, a 64-bit float (X86::FR64) can't live in
00224     // the 32-bit float super-class (X86::FR32).
00225     if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
00226       const TargetRegisterClass *VTRC =
00227         TLI->getRegClassFor(Node->getSimpleValueType(i));
00228       if (RC)
00229         VTRC = TRI->getCommonSubClass(RC, VTRC);
00230       if (VTRC)
00231         RC = VTRC;
00232     }
00233 
00234     if (II.OpInfo[i].isOptionalDef()) {
00235       // Optional def must be a physical register.
00236       unsigned NumResults = CountResults(Node);
00237       VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
00238       assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
00239       MIB.addReg(VRBase, RegState::Define);
00240     }
00241 
00242     if (!VRBase && !IsClone && !IsCloned)
00243       for (SDNode *User : Node->uses()) {
00244         if (User->getOpcode() == ISD::CopyToReg &&
00245             User->getOperand(2).getNode() == Node &&
00246             User->getOperand(2).getResNo() == i) {
00247           unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
00248           if (TargetRegisterInfo::isVirtualRegister(Reg)) {
00249             const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
00250             if (RegRC == RC) {
00251               VRBase = Reg;
00252               MIB.addReg(VRBase, RegState::Define);
00253               break;
00254             }
00255           }
00256         }
00257       }
00258 
00259     // Create the result registers for this node and add the result regs to
00260     // the machine instruction.
00261     if (VRBase == 0) {
00262       assert(RC && "Isn't a register operand!");
00263       VRBase = MRI->createVirtualRegister(RC);
00264       MIB.addReg(VRBase, RegState::Define);
00265     }
00266 
00267     SDValue Op(Node, i);
00268     if (IsClone)
00269       VRBaseMap.erase(Op);
00270     bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
00271     (void)isNew; // Silence compiler warning.
00272     assert(isNew && "Node emitted out of order - early");
00273   }
00274 }
00275 
00276 /// getVR - Return the virtual register corresponding to the specified result
00277 /// of the specified node.
00278 unsigned InstrEmitter::getVR(SDValue Op,
00279                              DenseMap<SDValue, unsigned> &VRBaseMap) {
00280   if (Op.isMachineOpcode() &&
00281       Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
00282     // Add an IMPLICIT_DEF instruction before every use.
00283     unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
00284     // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
00285     // does not include operand register class info.
00286     if (!VReg) {
00287       const TargetRegisterClass *RC =
00288         TLI->getRegClassFor(Op.getSimpleValueType());
00289       VReg = MRI->createVirtualRegister(RC);
00290     }
00291     BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
00292             TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
00293     return VReg;
00294   }
00295 
00296   DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
00297   assert(I != VRBaseMap.end() && "Node emitted out of order - late");
00298   return I->second;
00299 }
00300 
00301 
00302 /// AddRegisterOperand - Add the specified register as an operand to the
00303 /// specified machine instr. Insert register copies if the register is
00304 /// not in the required register class.
00305 void
00306 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
00307                                  SDValue Op,
00308                                  unsigned IIOpNum,
00309                                  const MCInstrDesc *II,
00310                                  DenseMap<SDValue, unsigned> &VRBaseMap,
00311                                  bool IsDebug, bool IsClone, bool IsCloned) {
00312   assert(Op.getValueType() != MVT::Other &&
00313          Op.getValueType() != MVT::Glue &&
00314          "Chain and glue operands should occur at end of operand list!");
00315   // Get/emit the operand.
00316   unsigned VReg = getVR(Op, VRBaseMap);
00317   assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
00318 
00319   const MCInstrDesc &MCID = MIB->getDesc();
00320   bool isOptDef = IIOpNum < MCID.getNumOperands() &&
00321     MCID.OpInfo[IIOpNum].isOptionalDef();
00322 
00323   // If the instruction requires a register in a different class, create
00324   // a new virtual register and copy the value into it, but first attempt to
00325   // shrink VReg's register class within reason.  For example, if VReg == GR32
00326   // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
00327   if (II) {
00328     const TargetRegisterClass *DstRC = nullptr;
00329     if (IIOpNum < II->getNumOperands())
00330       DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
00331     if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
00332       unsigned NewVReg = MRI->createVirtualRegister(DstRC);
00333       BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
00334               TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
00335       VReg = NewVReg;
00336     }
00337   }
00338 
00339   // If this value has only one use, that use is a kill. This is a
00340   // conservative approximation. InstrEmitter does trivial coalescing
00341   // with CopyFromReg nodes, so don't emit kill flags for them.
00342   // Avoid kill flags on Schedule cloned nodes, since there will be
00343   // multiple uses.
00344   // Tied operands are never killed, so we need to check that. And that
00345   // means we need to determine the index of the operand.
00346   bool isKill = Op.hasOneUse() &&
00347                 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
00348                 !IsDebug &&
00349                 !(IsClone || IsCloned);
00350   if (isKill) {
00351     unsigned Idx = MIB->getNumOperands();
00352     while (Idx > 0 &&
00353            MIB->getOperand(Idx-1).isReg() &&
00354            MIB->getOperand(Idx-1).isImplicit())
00355       --Idx;
00356     bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
00357     if (isTied)
00358       isKill = false;
00359   }
00360 
00361   MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
00362              getDebugRegState(IsDebug));
00363 }
00364 
00365 /// AddOperand - Add the specified operand to the specified machine instr.  II
00366 /// specifies the instruction information for the node, and IIOpNum is the
00367 /// operand number (in the II) that we are adding.
00368 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
00369                               SDValue Op,
00370                               unsigned IIOpNum,
00371                               const MCInstrDesc *II,
00372                               DenseMap<SDValue, unsigned> &VRBaseMap,
00373                               bool IsDebug, bool IsClone, bool IsCloned) {
00374   if (Op.isMachineOpcode()) {
00375     AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
00376                        IsDebug, IsClone, IsCloned);
00377   } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
00378     MIB.addImm(C->getSExtValue());
00379   } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
00380     MIB.addFPImm(F->getConstantFPValue());
00381   } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
00382     // Turn additional physreg operands into implicit uses on non-variadic
00383     // instructions. This is used by call and return instructions passing
00384     // arguments in registers.
00385     bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
00386     MIB.addReg(R->getReg(), getImplRegState(Imp));
00387   } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
00388     MIB.addRegMask(RM->getRegMask());
00389   } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
00390     MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
00391                          TGA->getTargetFlags());
00392   } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
00393     MIB.addMBB(BBNode->getBasicBlock());
00394   } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
00395     MIB.addFrameIndex(FI->getIndex());
00396   } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
00397     MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
00398   } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
00399     int Offset = CP->getOffset();
00400     unsigned Align = CP->getAlignment();
00401     Type *Type = CP->getType();
00402     // MachineConstantPool wants an explicit alignment.
00403     if (Align == 0) {
00404       Align = TM->getDataLayout()->getPrefTypeAlignment(Type);
00405       if (Align == 0) {
00406         // Alignment of vector types.  FIXME!
00407         Align = TM->getDataLayout()->getTypeAllocSize(Type);
00408       }
00409     }
00410 
00411     unsigned Idx;
00412     MachineConstantPool *MCP = MF->getConstantPool();
00413     if (CP->isMachineConstantPoolEntry())
00414       Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
00415     else
00416       Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
00417     MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
00418   } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
00419     MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
00420   } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
00421     MIB.addBlockAddress(BA->getBlockAddress(),
00422                         BA->getOffset(),
00423                         BA->getTargetFlags());
00424   } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
00425     MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
00426   } else {
00427     assert(Op.getValueType() != MVT::Other &&
00428            Op.getValueType() != MVT::Glue &&
00429            "Chain and glue operands should occur at end of operand list!");
00430     AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
00431                        IsDebug, IsClone, IsCloned);
00432   }
00433 }
00434 
00435 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
00436                                           MVT VT, DebugLoc DL) {
00437   const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
00438   const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
00439 
00440   // RC is a sub-class of VRC that supports SubIdx.  Try to constrain VReg
00441   // within reason.
00442   if (RC && RC != VRC)
00443     RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
00444 
00445   // VReg has been adjusted.  It can be used with SubIdx operands now.
00446   if (RC)
00447     return VReg;
00448 
00449   // VReg couldn't be reasonably constrained.  Emit a COPY to a new virtual
00450   // register instead.
00451   RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
00452   assert(RC && "No legal register class for VT supports that SubIdx");
00453   unsigned NewReg = MRI->createVirtualRegister(RC);
00454   BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
00455     .addReg(VReg);
00456   return NewReg;
00457 }
00458 
00459 /// EmitSubregNode - Generate machine code for subreg nodes.
00460 ///
00461 void InstrEmitter::EmitSubregNode(SDNode *Node,
00462                                   DenseMap<SDValue, unsigned> &VRBaseMap,
00463                                   bool IsClone, bool IsCloned) {
00464   unsigned VRBase = 0;
00465   unsigned Opc = Node->getMachineOpcode();
00466 
00467   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
00468   // the CopyToReg'd destination register instead of creating a new vreg.
00469   for (SDNode *User : Node->uses()) {
00470     if (User->getOpcode() == ISD::CopyToReg &&
00471         User->getOperand(2).getNode() == Node) {
00472       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
00473       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
00474         VRBase = DestReg;
00475         break;
00476       }
00477     }
00478   }
00479 
00480   if (Opc == TargetOpcode::EXTRACT_SUBREG) {
00481     // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub.  There are no
00482     // constraints on the %dst register, COPY can target all legal register
00483     // classes.
00484     unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
00485     const TargetRegisterClass *TRC =
00486       TLI->getRegClassFor(Node->getSimpleValueType(0));
00487 
00488     unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
00489     MachineInstr *DefMI = MRI->getVRegDef(VReg);
00490     unsigned SrcReg, DstReg, DefSubIdx;
00491     if (DefMI &&
00492         TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
00493         SubIdx == DefSubIdx &&
00494         TRC == MRI->getRegClass(SrcReg)) {
00495       // Optimize these:
00496       // r1025 = s/zext r1024, 4
00497       // r1026 = extract_subreg r1025, 4
00498       // to a copy
00499       // r1026 = copy r1024
00500       VRBase = MRI->createVirtualRegister(TRC);
00501       BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
00502               TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
00503       MRI->clearKillFlags(SrcReg);
00504     } else {
00505       // VReg may not support a SubIdx sub-register, and we may need to
00506       // constrain its register class or issue a COPY to a compatible register
00507       // class.
00508       VReg = ConstrainForSubReg(VReg, SubIdx,
00509                                 Node->getOperand(0).getSimpleValueType(),
00510                                 Node->getDebugLoc());
00511 
00512       // Create the destreg if it is missing.
00513       if (VRBase == 0)
00514         VRBase = MRI->createVirtualRegister(TRC);
00515 
00516       // Create the extract_subreg machine instruction.
00517       BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
00518               TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
00519     }
00520   } else if (Opc == TargetOpcode::INSERT_SUBREG ||
00521              Opc == TargetOpcode::SUBREG_TO_REG) {
00522     SDValue N0 = Node->getOperand(0);
00523     SDValue N1 = Node->getOperand(1);
00524     SDValue N2 = Node->getOperand(2);
00525     unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
00526 
00527     // Figure out the register class to create for the destreg.  It should be
00528     // the largest legal register class supporting SubIdx sub-registers.
00529     // RegisterCoalescer will constrain it further if it decides to eliminate
00530     // the INSERT_SUBREG instruction.
00531     //
00532     //   %dst = INSERT_SUBREG %src, %sub, SubIdx
00533     //
00534     // is lowered by TwoAddressInstructionPass to:
00535     //
00536     //   %dst = COPY %src
00537     //   %dst:SubIdx = COPY %sub
00538     //
00539     // There is no constraint on the %src register class.
00540     //
00541     const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
00542     SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
00543     assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
00544 
00545     if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
00546       VRBase = MRI->createVirtualRegister(SRC);
00547 
00548     // Create the insert_subreg or subreg_to_reg machine instruction.
00549     MachineInstrBuilder MIB =
00550       BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
00551 
00552     // If creating a subreg_to_reg, then the first input operand
00553     // is an implicit value immediate, otherwise it's a register
00554     if (Opc == TargetOpcode::SUBREG_TO_REG) {
00555       const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
00556       MIB.addImm(SD->getZExtValue());
00557     } else
00558       AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
00559                  IsClone, IsCloned);
00560     // Add the subregster being inserted
00561     AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
00562                IsClone, IsCloned);
00563     MIB.addImm(SubIdx);
00564     MBB->insert(InsertPos, MIB);
00565   } else
00566     llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
00567 
00568   SDValue Op(Node, 0);
00569   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
00570   (void)isNew; // Silence compiler warning.
00571   assert(isNew && "Node emitted out of order - early");
00572 }
00573 
00574 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
00575 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
00576 /// register is constrained to be in a particular register class.
00577 ///
00578 void
00579 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
00580                                      DenseMap<SDValue, unsigned> &VRBaseMap) {
00581   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
00582 
00583   // Create the new VReg in the destination class and emit a copy.
00584   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
00585   const TargetRegisterClass *DstRC =
00586     TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
00587   unsigned NewVReg = MRI->createVirtualRegister(DstRC);
00588   BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
00589     NewVReg).addReg(VReg);
00590 
00591   SDValue Op(Node, 0);
00592   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
00593   (void)isNew; // Silence compiler warning.
00594   assert(isNew && "Node emitted out of order - early");
00595 }
00596 
00597 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
00598 ///
00599 void InstrEmitter::EmitRegSequence(SDNode *Node,
00600                                   DenseMap<SDValue, unsigned> &VRBaseMap,
00601                                   bool IsClone, bool IsCloned) {
00602   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
00603   const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
00604   unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
00605   const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
00606   MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
00607   unsigned NumOps = Node->getNumOperands();
00608   assert((NumOps & 1) == 1 &&
00609          "REG_SEQUENCE must have an odd number of operands!");
00610   for (unsigned i = 1; i != NumOps; ++i) {
00611     SDValue Op = Node->getOperand(i);
00612     if ((i & 1) == 0) {
00613       RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
00614       // Skip physical registers as they don't have a vreg to get and we'll
00615       // insert copies for them in TwoAddressInstructionPass anyway.
00616       if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
00617         unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
00618         unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
00619         const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
00620         const TargetRegisterClass *SRC =
00621         TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
00622         if (SRC && SRC != RC) {
00623           MRI->setRegClass(NewVReg, SRC);
00624           RC = SRC;
00625         }
00626       }
00627     }
00628     AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
00629                IsClone, IsCloned);
00630   }
00631 
00632   MBB->insert(InsertPos, MIB);
00633   SDValue Op(Node, 0);
00634   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
00635   (void)isNew; // Silence compiler warning.
00636   assert(isNew && "Node emitted out of order - early");
00637 }
00638 
00639 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
00640 ///
00641 MachineInstr *
00642 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
00643                            DenseMap<SDValue, unsigned> &VRBaseMap) {
00644   uint64_t Offset = SD->getOffset();
00645   MDNode* MDPtr = SD->getMDPtr();
00646   DebugLoc DL = SD->getDebugLoc();
00647 
00648   if (SD->getKind() == SDDbgValue::FRAMEIX) {
00649     // Stack address; this needs to be lowered in target-dependent fashion.
00650     // EmitTargetCodeForFrameDebugValue is responsible for allocation.
00651     return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
00652         .addFrameIndex(SD->getFrameIx()).addImm(Offset).addMetadata(MDPtr);
00653   }
00654   // Otherwise, we're going to create an instruction here.
00655   const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
00656   MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
00657   if (SD->getKind() == SDDbgValue::SDNODE) {
00658     SDNode *Node = SD->getSDNode();
00659     SDValue Op = SDValue(Node, SD->getResNo());
00660     // It's possible we replaced this SDNode with other(s) and therefore
00661     // didn't generate code for it.  It's better to catch these cases where
00662     // they happen and transfer the debug info, but trying to guarantee that
00663     // in all cases would be very fragile; this is a safeguard for any
00664     // that were missed.
00665     DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
00666     if (I==VRBaseMap.end())
00667       MIB.addReg(0U);       // undef
00668     else
00669       AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
00670                  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
00671   } else if (SD->getKind() == SDDbgValue::CONST) {
00672     const Value *V = SD->getConst();
00673     if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00674       if (CI->getBitWidth() > 64)
00675         MIB.addCImm(CI);
00676       else
00677         MIB.addImm(CI->getSExtValue());
00678     } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
00679       MIB.addFPImm(CF);
00680     } else {
00681       // Could be an Undef.  In any case insert an Undef so we can see what we
00682       // dropped.
00683       MIB.addReg(0U);
00684     }
00685   } else {
00686     // Insert an Undef so we can see what we dropped.
00687     MIB.addReg(0U);
00688   }
00689 
00690   if (Offset != 0) // Indirect addressing.
00691     MIB.addImm(Offset);
00692   else
00693     MIB.addReg(0U, RegState::Debug);
00694 
00695   MIB.addMetadata(MDPtr);
00696 
00697   return &*MIB;
00698 }
00699 
00700 /// EmitMachineNode - Generate machine code for a target-specific node and
00701 /// needed dependencies.
00702 ///
00703 void InstrEmitter::
00704 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
00705                 DenseMap<SDValue, unsigned> &VRBaseMap) {
00706   unsigned Opc = Node->getMachineOpcode();
00707 
00708   // Handle subreg insert/extract specially
00709   if (Opc == TargetOpcode::EXTRACT_SUBREG ||
00710       Opc == TargetOpcode::INSERT_SUBREG ||
00711       Opc == TargetOpcode::SUBREG_TO_REG) {
00712     EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
00713     return;
00714   }
00715 
00716   // Handle COPY_TO_REGCLASS specially.
00717   if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
00718     EmitCopyToRegClassNode(Node, VRBaseMap);
00719     return;
00720   }
00721 
00722   // Handle REG_SEQUENCE specially.
00723   if (Opc == TargetOpcode::REG_SEQUENCE) {
00724     EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
00725     return;
00726   }
00727 
00728   if (Opc == TargetOpcode::IMPLICIT_DEF)
00729     // We want a unique VR for each IMPLICIT_DEF use.
00730     return;
00731 
00732   const MCInstrDesc &II = TII->get(Opc);
00733   unsigned NumResults = CountResults(Node);
00734   unsigned NumDefs = II.getNumDefs();
00735   const MCPhysReg *ScratchRegs = nullptr;
00736 
00737   // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
00738   if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
00739     // Stackmaps do not have arguments and do not preserve their calling
00740     // convention. However, to simplify runtime support, they clobber the same
00741     // scratch registers as AnyRegCC.
00742     unsigned CC = CallingConv::AnyReg;
00743     if (Opc == TargetOpcode::PATCHPOINT) {
00744       CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
00745       NumDefs = NumResults;
00746     }
00747     ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
00748   }
00749 
00750   unsigned NumImpUses = 0;
00751   unsigned NodeOperands =
00752     countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
00753   bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
00754 #ifndef NDEBUG
00755   unsigned NumMIOperands = NodeOperands + NumResults;
00756   if (II.isVariadic())
00757     assert(NumMIOperands >= II.getNumOperands() &&
00758            "Too few operands for a variadic node!");
00759   else
00760     assert(NumMIOperands >= II.getNumOperands() &&
00761            NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
00762                             NumImpUses &&
00763            "#operands for dag node doesn't match .td file!");
00764 #endif
00765 
00766   // Create the new machine instruction.
00767   MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
00768 
00769   // Add result register values for things that are defined by this
00770   // instruction.
00771   if (NumResults)
00772     CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
00773 
00774   // Emit all of the actual operands of this instruction, adding them to the
00775   // instruction as appropriate.
00776   bool HasOptPRefs = NumDefs > NumResults;
00777   assert((!HasOptPRefs || !HasPhysRegOuts) &&
00778          "Unable to cope with optional defs and phys regs defs!");
00779   unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
00780   for (unsigned i = NumSkip; i != NodeOperands; ++i)
00781     AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
00782                VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
00783 
00784   // Add scratch registers as implicit def and early clobber
00785   if (ScratchRegs)
00786     for (unsigned i = 0; ScratchRegs[i]; ++i)
00787       MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
00788                                  RegState::EarlyClobber);
00789 
00790   // Transfer all of the memory reference descriptions of this instruction.
00791   MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
00792                  cast<MachineSDNode>(Node)->memoperands_end());
00793 
00794   // Insert the instruction into position in the block. This needs to
00795   // happen before any custom inserter hook is called so that the
00796   // hook knows where in the block to insert the replacement code.
00797   MBB->insert(InsertPos, MIB);
00798 
00799   // The MachineInstr may also define physregs instead of virtregs.  These
00800   // physreg values can reach other instructions in different ways:
00801   //
00802   // 1. When there is a use of a Node value beyond the explicitly defined
00803   //    virtual registers, we emit a CopyFromReg for one of the implicitly
00804   //    defined physregs.  This only happens when HasPhysRegOuts is true.
00805   //
00806   // 2. A CopyFromReg reading a physreg may be glued to this instruction.
00807   //
00808   // 3. A glued instruction may implicitly use a physreg.
00809   //
00810   // 4. A glued instruction may use a RegisterSDNode operand.
00811   //
00812   // Collect all the used physreg defs, and make sure that any unused physreg
00813   // defs are marked as dead.
00814   SmallVector<unsigned, 8> UsedRegs;
00815 
00816   // Additional results must be physical register defs.
00817   if (HasPhysRegOuts) {
00818     for (unsigned i = NumDefs; i < NumResults; ++i) {
00819       unsigned Reg = II.getImplicitDefs()[i - NumDefs];
00820       if (!Node->hasAnyUseOfValue(i))
00821         continue;
00822       // This implicitly defined physreg has a use.
00823       UsedRegs.push_back(Reg);
00824       EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
00825     }
00826   }
00827 
00828   // Scan the glue chain for any used physregs.
00829   if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
00830     for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
00831       if (F->getOpcode() == ISD::CopyFromReg) {
00832         UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
00833         continue;
00834       } else if (F->getOpcode() == ISD::CopyToReg) {
00835         // Skip CopyToReg nodes that are internal to the glue chain.
00836         continue;
00837       }
00838       // Collect declared implicit uses.
00839       const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
00840       UsedRegs.append(MCID.getImplicitUses(),
00841                       MCID.getImplicitUses() + MCID.getNumImplicitUses());
00842       // In addition to declared implicit uses, we must also check for
00843       // direct RegisterSDNode operands.
00844       for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
00845         if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
00846           unsigned Reg = R->getReg();
00847           if (TargetRegisterInfo::isPhysicalRegister(Reg))
00848             UsedRegs.push_back(Reg);
00849         }
00850     }
00851   }
00852 
00853   // Finally mark unused registers as dead.
00854   if (!UsedRegs.empty() || II.getImplicitDefs())
00855     MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
00856 
00857   // Run post-isel target hook to adjust this instruction if needed.
00858 #ifdef NDEBUG
00859   if (II.hasPostISelHook())
00860 #endif
00861     TLI->AdjustInstrPostInstrSelection(MIB, Node);
00862 }
00863 
00864 /// EmitSpecialNode - Generate machine code for a target-independent node and
00865 /// needed dependencies.
00866 void InstrEmitter::
00867 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
00868                 DenseMap<SDValue, unsigned> &VRBaseMap) {
00869   switch (Node->getOpcode()) {
00870   default:
00871 #ifndef NDEBUG
00872     Node->dump();
00873 #endif
00874     llvm_unreachable("This target-independent node should have been selected!");
00875   case ISD::EntryToken:
00876     llvm_unreachable("EntryToken should have been excluded from the schedule!");
00877   case ISD::MERGE_VALUES:
00878   case ISD::TokenFactor: // fall thru
00879     break;
00880   case ISD::CopyToReg: {
00881     unsigned SrcReg;
00882     SDValue SrcVal = Node->getOperand(2);
00883     if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
00884       SrcReg = R->getReg();
00885     else
00886       SrcReg = getVR(SrcVal, VRBaseMap);
00887 
00888     unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
00889     if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
00890       break;
00891 
00892     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
00893             DestReg).addReg(SrcReg);
00894     break;
00895   }
00896   case ISD::CopyFromReg: {
00897     unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
00898     EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
00899     break;
00900   }
00901   case ISD::EH_LABEL: {
00902     MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
00903     BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
00904             TII->get(TargetOpcode::EH_LABEL)).addSym(S);
00905     break;
00906   }
00907 
00908   case ISD::LIFETIME_START:
00909   case ISD::LIFETIME_END: {
00910     unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
00911     TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
00912 
00913     FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
00914     BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
00915     .addFrameIndex(FI->getIndex());
00916     break;
00917   }
00918 
00919   case ISD::INLINEASM: {
00920     unsigned NumOps = Node->getNumOperands();
00921     if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
00922       --NumOps;  // Ignore the glue operand.
00923 
00924     // Create the inline asm machine instruction.
00925     MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(),
00926                                       TII->get(TargetOpcode::INLINEASM));
00927 
00928     // Add the asm string as an external symbol operand.
00929     SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
00930     const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
00931     MIB.addExternalSymbol(AsmStr);
00932 
00933     // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
00934     // bits.
00935     int64_t ExtraInfo =
00936       cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
00937                           getZExtValue();
00938     MIB.addImm(ExtraInfo);
00939 
00940     // Remember to operand index of the group flags.
00941     SmallVector<unsigned, 8> GroupIdx;
00942 
00943     // Add all of the operand registers to the instruction.
00944     for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
00945       unsigned Flags =
00946         cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
00947       const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
00948 
00949       GroupIdx.push_back(MIB->getNumOperands());
00950       MIB.addImm(Flags);
00951       ++i;  // Skip the ID value.
00952 
00953       switch (InlineAsm::getKind(Flags)) {
00954       default: llvm_unreachable("Bad flags!");
00955         case InlineAsm::Kind_RegDef:
00956         for (unsigned j = 0; j != NumVals; ++j, ++i) {
00957           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
00958           // FIXME: Add dead flags for physical and virtual registers defined.
00959           // For now, mark physical register defs as implicit to help fast
00960           // regalloc. This makes inline asm look a lot like calls.
00961           MIB.addReg(Reg, RegState::Define |
00962                   getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
00963         }
00964         break;
00965       case InlineAsm::Kind_RegDefEarlyClobber:
00966       case InlineAsm::Kind_Clobber:
00967         for (unsigned j = 0; j != NumVals; ++j, ++i) {
00968           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
00969           MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
00970                   getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
00971         }
00972         break;
00973       case InlineAsm::Kind_RegUse:  // Use of register.
00974       case InlineAsm::Kind_Imm:  // Immediate.
00975       case InlineAsm::Kind_Mem:  // Addressing mode.
00976         // The addressing mode has been selected, just add all of the
00977         // operands to the machine instruction.
00978         for (unsigned j = 0; j != NumVals; ++j, ++i)
00979           AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
00980                      /*IsDebug=*/false, IsClone, IsCloned);
00981 
00982         // Manually set isTied bits.
00983         if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
00984           unsigned DefGroup = 0;
00985           if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
00986             unsigned DefIdx = GroupIdx[DefGroup] + 1;
00987             unsigned UseIdx = GroupIdx.back() + 1;
00988             for (unsigned j = 0; j != NumVals; ++j)
00989               MIB->tieOperands(DefIdx + j, UseIdx + j);
00990           }
00991         }
00992         break;
00993       }
00994     }
00995 
00996     // Get the mdnode from the asm if it exists and add it to the instruction.
00997     SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
00998     const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
00999     if (MD)
01000       MIB.addMetadata(MD);
01001 
01002     MBB->insert(InsertPos, MIB);
01003     break;
01004   }
01005   }
01006 }
01007 
01008 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
01009 /// at the given position in the given block.
01010 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
01011                            MachineBasicBlock::iterator insertpos)
01012   : MF(mbb->getParent()),
01013     MRI(&MF->getRegInfo()),
01014     TM(&MF->getTarget()),
01015     TII(TM->getInstrInfo()),
01016     TRI(TM->getRegisterInfo()),
01017     TLI(TM->getTargetLowering()),
01018     MBB(mbb), InsertPos(insertpos) {
01019 }