LLVM  mainline
llvm::ISD Namespace Reference

ISD namespace - This namespace contains an enum which represents all of the SelectionDAG node types and value types. More...

## Classes

struct  ArgFlagsTy
struct  InputArg
InputArg - This struct carries flags and type information about a single incoming (formal) argument or incoming (from the perspective of the caller) return value virtual register. More...
struct  OutputArg
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing (from the perspective of the caller) return value virtual register. More...

## Enumerations

enum  NodeType {
DELETED_NODE, EntryToken, TokenFactor, AssertSext,
AssertZext, BasicBlock, VALUETYPE, CONDCODE,
Register, RegisterMask, Constant, ConstantFP,
GlobalAddress, GlobalTLSAddress, FrameIndex, JumpTable,
ConstantPool, ExternalSymbol, BlockAddress, GLOBAL_OFFSET_TABLE,
FRAMEADDR, RETURNADDR, LOCAL_RECOVER, READ_REGISTER,
WRITE_REGISTER, FRAME_TO_ARGS_OFFSET, EH_RETURN, EH_SJLJ_SETJMP,
EH_SJLJ_LONGJMP, EH_SJLJ_SETUP_DISPATCH, TargetConstant, TargetConstantFP,
TargetGlobalAddress, TargetGlobalTLSAddress, TargetFrameIndex, TargetJumpTable,
TargetConstantPool, TargetExternalSymbol, TargetBlockAddress, MCSymbol,
TargetIndex, INTRINSIC_WO_CHAIN, INTRINSIC_W_CHAIN, INTRINSIC_VOID,
CopyToReg, CopyFromReg, UNDEF, EXTRACT_ELEMENT,
BUILD_PAIR, MERGE_VALUES, ADD, SUB,
MUL, SDIV, UDIV, SREM,
UREM, SMUL_LOHI, UMUL_LOHI, SDIVREM,
UDIVREM, CARRY_FALSE, ADDC, SUBC,
ADDE, SUBE, SADDO, UADDO,
SSUBO, USUBO, SMULO, UMULO,
FADD, FSUB, FMUL, FDIV,
FREM, FMA, FMAD, FCOPYSIGN,
FGETSIGN, BUILD_VECTOR, INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT,
CONCAT_VECTORS, INSERT_SUBVECTOR, EXTRACT_SUBVECTOR, VECTOR_SHUFFLE,
SCALAR_TO_VECTOR, MULHU, MULHS, SMIN,
SMAX, UMIN, UMAX, AND,
OR, XOR, SHL, SRA,
SRL, ROTL, ROTR, BSWAP,
CTTZ, CTLZ, CTPOP, BITREVERSE,
CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, SELECT, VSELECT,
SELECT_CC, SETCC, SETCCE, SHL_PARTS,
SRA_PARTS, SRL_PARTS, SIGN_EXTEND, ZERO_EXTEND,
ANY_EXTEND, TRUNCATE, SINT_TO_FP, UINT_TO_FP,
SIGN_EXTEND_INREG, ANY_EXTEND_VECTOR_INREG, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
FP_TO_SINT, FP_TO_UINT, FP_ROUND, FLT_ROUNDS_,
FP_ROUND_INREG, FP_EXTEND, BITCAST, ADDRSPACECAST,
CONVERT_RNDSAT, FP16_TO_FP, FP_TO_FP16, FNEG,
FABS, FSQRT, FSIN, FCOS,
FPOWI, FPOW, FLOG, FLOG2,
FLOG10, FEXP, FEXP2, FCEIL,
FTRUNC, FRINT, FNEARBYINT, FROUND,
FFLOOR, FMINNUM, FMAXNUM, FMINNAN,
FMAXNAN, FSINCOS, LOAD, STORE,
DYNAMIC_STACKALLOC, BR, BRIND, BR_JT,
BRCOND, BR_CC, INLINEASM, EH_LABEL,
CATCHPAD, CATCHRET, CLEANUPRET, STACKSAVE,
STACKRESTORE, CALLSEQ_START, CALLSEQ_END, VAARG,
VACOPY, VAEND, VASTART, SRCVALUE,
MDNODE_SDNODE, PCMARKER, READCYCLECOUNTER, HANDLENODE,
INIT_TRAMPOLINE, ADJUST_TRAMPOLINE, TRAP, DEBUGTRAP,
PREFETCH, ATOMIC_FENCE, ATOMIC_LOAD, ATOMIC_STORE,
ATOMIC_CMP_SWAP, ATOMIC_CMP_SWAP_WITH_SUCCESS, ATOMIC_SWAP, ATOMIC_LOAD_ADD,
ATOMIC_LOAD_SUB, ATOMIC_LOAD_AND, ATOMIC_LOAD_OR, ATOMIC_LOAD_XOR,
ATOMIC_LOAD_NAND, ATOMIC_LOAD_MIN, ATOMIC_LOAD_MAX, ATOMIC_LOAD_UMIN,
ATOMIC_LOAD_UMAX, MLOAD, MSTORE, MGATHER,
MSCATTER, LIFETIME_START, LIFETIME_END, GC_TRANSITION_START,
GC_TRANSITION_END, GET_DYNAMIC_AREA_OFFSET, BUILTIN_OP_END
}
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG. More...
enum  MemIndexedMode {
UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC,
POST_DEC, LAST_INDEXED_MODE
}
MemIndexedMode enum - This enum defines the load / store indexed addressing modes. More...
enum  LoadExtType {
NON_EXTLOAD = 0, EXTLOAD, SEXTLOAD, ZEXTLOAD,
LAST_LOADEXT_TYPE
}
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension). More...
enum  CondCode {
SETFALSE, SETOEQ, SETOGT, SETOGE,
SETOLT, SETOLE, SETONE, SETO,
SETUO, SETUEQ, SETUGT, SETUGE,
SETULT, SETULE, SETUNE, SETTRUE,
SETFALSE2, SETEQ, SETGT, SETGE,
SETLT, SETLE, SETNE, SETTRUE2,
SETCC_INVALID
}
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out, when considering SETFALSE (something that never exists dynamically) as 0. More...
enum  CvtCode {
CVT_FF, CVT_FS, CVT_FU, CVT_SF,
CVT_UF, CVT_SS, CVT_SU, CVT_US,
CVT_UU, CVT_INVALID
}
CvtCode enum - This enum defines the various converts CONVERT_RNDSAT supports. More...

## Functions

NodeType getExtForLoadExtType (bool IsFP, LoadExtType)
bool isSignedIntSetCC (CondCode Code)
isSignedIntSetCC - Return true if this is a setcc instruction that performs a signed comparison when used with integer operands.
bool isUnsignedIntSetCC (CondCode Code)
isUnsignedIntSetCC - Return true if this is a setcc instruction that performs an unsigned comparison when used with integer operands.
bool isTrueWhenEqual (CondCode Cond)
isTrueWhenEqual - Return true if the specified condition returns true if the two operands to the condition are equal.
unsigned getUnorderedFlavor (CondCode Cond)
getUnorderedFlavor - This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if the condition is undefined if the operand is a NaN.
CondCode getSetCCInverse (CondCode Operation, bool isInteger)
getSetCCInverse - Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode getSetCCSwappedOperands (CondCode Operation)
getSetCCSwappedOperands - Return the operation corresponding to (Y op X) when given the operation for (X op Y).
CondCode getSetCCOrOperation (CondCode Op1, CondCode Op2, bool isInteger)
getSetCCOrOperation - Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X op2 Y)).
CondCode getSetCCAndOperation (CondCode Op1, CondCode Op2, bool isInteger)
getSetCCAndOperation - Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X op2 Y)).
bool isBuildVectorAllOnes (const SDNode *N)
Node predicates.
bool isBuildVectorAllZeros (const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.
bool isBuildVectorOfConstantSDNodes (const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantSDNode or undef.
bool isBuildVectorOfConstantFPSDNodes (const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantFPSDNode or undef.
bool allOperandsUndef (const SDNode *N)
Return true if the node has at least one operand and all operands of the specified node are ISD::UNDEF.
bool isNormalLoad (const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
bool isNON_EXTLoad (const SDNode *N)
Returns true if the specified node is a non-extending load.
bool isEXTLoad (const SDNode *N)
Returns true if the specified node is a EXTLOAD.
bool isSEXTLoad (const SDNode *N)
Returns true if the specified node is a SEXTLOAD.
bool isZEXTLoad (const SDNode *N)
Returns true if the specified node is a ZEXTLOAD.
bool isUNINDEXEDLoad (const SDNode *N)
Returns true if the specified node is an unindexed load.
bool isNormalStore (const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
bool isNON_TRUNCStore (const SDNode *N)
Returns true if the specified node is a non-truncating store.
bool isTRUNCStore (const SDNode *N)
Returns true if the specified node is a truncating store.
bool isUNINDEXEDStore (const SDNode *N)
Returns true if the specified node is an unindexed store.

## Variables

static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+300
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific memory location should be less than this value.

## Detailed Description

ISD namespace - This namespace contains an enum which represents all of the SelectionDAG node types and value types.

## Enumeration Type Documentation

 enum llvm::ISD::CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out, when considering SETFALSE (something that never exists dynamically) as 0.

"U" -> Unsigned (for integer operands) or Unordered (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal to. If the "N" column is 1, the result of the comparison is undefined if the input is a NAN.

All of these (except for the 'always folded ops') should be handled for floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.

Note that these are laid out in a specific order to allow bit-twiddling to transform conditions.

Enumerator:
 SETFALSE SETOEQ SETOGT SETOGE SETOLT SETOLE SETONE SETO SETUO SETUEQ SETUGT SETUGE SETULT SETULE SETUNE SETTRUE SETFALSE2 SETEQ SETGT SETGE SETLT SETLE SETNE SETTRUE2 SETCC_INVALID

Definition at line 841 of file ISDOpcodes.h.

 enum llvm::ISD::CvtCode

CvtCode enum - This enum defines the various converts CONVERT_RNDSAT supports.

Enumerator:
 CVT_FF CVT_FS Float from Float. CVT_FU Float from Signed. CVT_SF Float from Unsigned. CVT_UF Signed from Float. CVT_SS Unsigned from Float. CVT_SU Signed from Signed. CVT_US Signed from Unsigned. CVT_UU Unsigned from Signed. CVT_INVALID Unsigned from Unsigned. Marker - Invalid opcode

Definition at line 922 of file ISDOpcodes.h.

LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).

SEXTLOAD loads the integer operand and sign extends it to a larger integer result type. ZEXTLOAD loads the integer operand and zero extends it to a larger integer result type. EXTLOAD is used for two things: floating point extending loads and integer extending loads [the top bits are undefined].

Enumerator:
 NON_EXTLOAD EXTLOAD SEXTLOAD ZEXTLOAD LAST_LOADEXT_TYPE

Definition at line 817 of file ISDOpcodes.h.

MemIndexedMode enum - This enum defines the load / store indexed addressing modes.

UNINDEXED "Normal" load / store. The effective address is already computed and is available in the base pointer. The offset operand is always undefined. In addition to producing a chain, an unindexed load produces one value (result of the load); an unindexed store does not produce a value.

PRE_INC Similar to the unindexed mode where the effective address is PRE_DEC the value of the base pointer add / subtract the offset. It considers the computation as being folded into the load / store operation (i.e. the load / store does the address computation as well as performing the memory transaction). The base operand is always undefined. In addition to producing a chain, pre-indexed load produces two values (result of the load and the result of the address computation); a pre-indexed store produces one value (result of the address computation).

POST_INC The effective address is the value of the base pointer. The POST_DEC value of the offset operand is then added to / subtracted from the base after memory transaction. In addition to producing a chain, post-indexed load produces two values (the result of the load and the result of the base +/- offset computation); a post-indexed store produces one value (the the result of the base +/- offset computation).

Enumerator:
 UNINDEXED PRE_INC PRE_DEC POST_INC POST_DEC LAST_INDEXED_MODE

Definition at line 798 of file ISDOpcodes.h.

 enum llvm::ISD::NodeType

ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.

Targets may also define target-dependent operator codes for SDNodes. For example, on x86, these are the enum values in the X86ISD namespace. Targets should aim to use target-independent operators to model their instruction sets as much as possible, and only use target-dependent operators when they have special requirements.

Finally, during and after selection proper, SNodes may use special operator codes that correspond directly with MachineInstr opcodes. These are used to represent selected instructions. See the isMachineOpcode() and getMachineOpcode() member functions of SDNode.

Enumerator:
 DELETED_NODE DELETED_NODE - This is an illegal value that is used to catch errors. This opcode is not a legal opcode for any node. EntryToken EntryToken - This is the marker used to indicate the start of a region. TokenFactor TokenFactor - This node takes multiple tokens as input and produces a single token result. This is used to represent the fact that the operand operators are independent of each other. AssertSext AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero or sign extended from a narrower type. These nodes take two operands. The first is the node that has already been extended, and the second is a value type node indicating the width of the extension AssertZext BasicBlock Various leaf nodes. VALUETYPE CONDCODE Register RegisterMask Constant ConstantFP GlobalAddress GlobalTLSAddress FrameIndex JumpTable ConstantPool ExternalSymbol BlockAddress GLOBAL_OFFSET_TABLE The address of the GOT. FRAMEADDR FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG. These nodes take one operand, the index of the frame or return address to return. An index of zero corresponds to the current function's frame or return address, an index of one to the parent's frame or return address, and so on. RETURNADDR LOCAL_RECOVER LOCAL_RECOVER - Represents the llvm.localrecover intrinsic. Materializes the offset from the local object pointer of another function to a particular local object passed to llvm.localescape. The operand is the MCSymbol label used to represent this offset, since typically the offset is not known until after code generation of the parent. READ_REGISTER READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the named register global variables extension. WRITE_REGISTER FRAME_TO_ARGS_OFFSET FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack argument. This is needed for correct stack adjustment during unwind. EH_RETURN OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin, which is used to return from exception. The general meaning is: adjust stack by OFFSET and pass execution to HANDLER. Many platform-related details also :) EH_SJLJ_SETJMP RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.setjmp intrinsic. It takes an input chain and a pointer to the jump buffer as inputs and returns an outchain. EH_SJLJ_LONGJMP OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic. It takes an input chain and a pointer to the jump buffer as inputs and returns an outchain. EH_SJLJ_SETUP_DISPATCH OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here. TargetConstant TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant. They are used for constants which are known to fit in the immediate fields of their users, or for carrying magic numbers which are not values which need to be materialized in registers. TargetConstantFP TargetGlobalAddress TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node, and this is valid in the target-specific dag, turning into a GlobalAddress operand. TargetGlobalTLSAddress TargetFrameIndex TargetJumpTable TargetConstantPool TargetExternalSymbol TargetBlockAddress MCSymbol TargetIndex TargetIndex - Like a constant pool entry, but with completely target-dependent semantics. Holds target flags, a 32-bit index, and a 64-bit index. Targets can use this however they like. INTRINSIC_WO_CHAIN RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic function with no side effects. The first operand is the ID number of the intrinsic from the llvm::Intrinsic namespace. The operands to the intrinsic follow. The node returns the result of the intrinsic. INTRINSIC_W_CHAIN RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target intrinsic function with side effects that returns a result. The first operand is a chain pointer. The second is the ID number of the intrinsic from the llvm::Intrinsic namespace. The operands to the intrinsic follow. The node has two results, the result of the intrinsic and an output chain. INTRINSIC_VOID OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic function with side effects that does not return a result. The first operand is a chain pointer. The second is the ID number of the intrinsic from the llvm::Intrinsic namespace. The operands to the intrinsic follow. CopyToReg CopyToReg - This node has three operands: a chain, a register number to set to this value, and a value. CopyFromReg CopyFromReg - This node indicates that the input value is a virtual or physical register that is defined outside of the scope of this SelectionDAG. The register is available from the RegisterSDNode object. UNDEF UNDEF - An undefined node. EXTRACT_ELEMENT EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0. This is only for use before legalization, for values that will be broken into multiple registers. BUILD_PAIR BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. Given two values of the same integer value type, this produces a value twice as big. Like EXTRACT_ELEMENT, this can only be used before legalization. MERGE_VALUES MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual results. This nodes has exactly the same number of inputs and outputs. This node is useful for some pieces of the code generator that want to think about a single node with multiple results, not multiple nodes. ADD Simple integer binary arithmetic operators. SUB MUL SDIV UDIV SREM UREM SMUL_LOHI SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2*N], and return the full value as two results, each of type iN. UMUL_LOHI SDIVREM SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result. UDIVREM CARRY_FALSE CARRY_FALSE - This node is used when folding other nodes, like ADDC/SUBC, which indicate the carry result is always false. ADDC Carry-setting nodes for multiple precision addition and subtraction. These nodes take two operands of the same value type, and produce two results. The first result is the normal add or sub result, the second result is the carry flag result. SUBC ADDE Carry-using nodes for multiple precision addition and subtraction. These nodes take three operands: The first two are the normal lhs and rhs to the add or sub, and the third is the input carry flag. These nodes produce two results; the normal result of the add or sub, and the output carry flag. These nodes both read and write a carry flag to allow them to them to be chained together for add and sub of arbitrarily large values. SUBE SADDO RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. These nodes take two operands: the normal LHS and RHS to the add. They produce two results: the normal result of the add, and a boolean that indicates if an overflow occurred (*not* a flag, because it may be store to memory, etc.). If the type of the boolean is not i1 then the high bits conform to getBooleanContents. These nodes are generated from llvm.[su]add.with.overflow intrinsics. UADDO SSUBO Same for subtraction. USUBO SMULO Same for multiplication. UMULO FADD Simple binary floating point operators. FSUB FMUL FDIV FREM FMA FMA - Perform a * b + c with no intermediate rounding step. FMAD FMAD - Perform a * b + c, while getting the same result as the separately rounded operations. FCOPYSIGN FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This DAG node does not require that X and Y have the same type, just that they are both floating point. X and the result must have the same type. FCOPYSIGN(f32, f64) is allowed. FGETSIGN INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 value. BUILD_VECTOR BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable, elements. The number of elements is required to be a power of two. The types of the operands must all be the same and must match the vector element type, except that integer types are allowed to be larger than the element type, in which case the operands are implicitly truncated. INSERT_VECTOR_ELT INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL. If the type of VAL is larger than the vector element type then VAL is truncated before replacement. EXTRACT_VECTOR_ELT EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially variable) element number IDX. If the return type is an integer type larger than the element type of the vector, the result is extended to the width of the return type. CONCAT_VECTORS CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length and element type, this produces a concatenated vector result value, with length equal to the sum of the lengths of the input vectors. INSERT_SUBVECTOR INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the (potentially variable) element number IDX, which must be a multiple of the VECTOR2 vector length. The elements of VECTOR1 starting at IDX are overwritten with VECTOR2. Elements IDX through vector_length(VECTOR2) must be valid VECTOR1 indices. EXTRACT_SUBVECTOR EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the element number IDX, which must be a constant multiple of the result vector length. VECTOR_SHUFFLE VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int values that indicate which value (or undef) each result element will get. These constant ints are accessible through the ShuffleVectorSDNode class. This is quite similar to the Altivec 'vperm' instruction, except that the indices must be constants and are in terms of the element size of VEC1/VEC2, not in terms of bytes. SCALAR_TO_VECTOR SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the resultant vector type. The top elements 1 to N-1 of the N-element vector are undefined. The type of the operand must match the vector element type, except when they are integer types. In this case the operand is allowed to be wider than the vector element type, and is implicitly truncated to it. MULHU MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of type i[2*N], then return the top part. MULHS SMIN [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers. SMAX UMIN UMAX AND Bitwise operators - logical and, logical or, logical xor. OR XOR SHL Shift and rotation operations. After legalization, the type of the shift amount is known to be TLI.getShiftAmountTy(). Before legalization the shift amount can be any type, but care must be taken to ensure it is large enough. TLI.getShiftAmountTy() is i8 on some targets, but before legalization, types like i1024 can occur and i8 doesn't have enough bits to represent the shift amount. When the 1st operand is a vector, the shift amount must be in the same type. (TLI.getShiftAmountTy() will return the same type when the input type is a vector.) SRA SRL ROTL ROTR BSWAP Byte Swap and Counting operators. CTTZ CTLZ CTPOP BITREVERSE CTTZ_ZERO_UNDEF Bit counting operators with an undefined result for zero inputs. CTLZ_ZERO_UNDEF SELECT Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not i1 then the high bits must conform to getBooleanContents. VSELECT Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector result. All vectors have the same length. Much like the scalar select and setcc, each bit in the condition selects whether the corresponding result element is taken from op #1 or op #2. At first, the VSELECT condition is of vXi1 type. Later, targets may change the condition type in order to match the VSELECT node using a pattern. The condition follows the BooleanContent format of the target. SELECT_CC Select with condition operator - This selects between a true value and a false value (ops #2 and #3) based on the boolean result of comparing the lhs and rhs (ops #0 and #1) of a conditional expression with the condition code in op #4, a CondCodeSDNode. SETCC SetCC operator - This evaluates to a true value iff the condition is true. If the result value type is not i1 then the high bits conform to getBooleanContents. The operands to this are the left and right operands to compare (ops #0, and #1) and the condition code to compare them with (op #2) as a CondCodeSDNode. If the operands are vector types then the result type must also be a vector type. SETCCE Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a *carry value*. This operator checks the result of "LHS - RHS - Carry", and can be used to compare two wide integers: (setcce lhshi rhshi (subc lhslo rhslo) cc). Only valid for integers. SHL_PARTS SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations. The operation ordering is: [Lo,Hi] = op [LoLHS,HiLHS], Amt SRA_PARTS SRL_PARTS SIGN_EXTEND Conversion operators. These are all single input single output operations. For all of these, the result type must be strictly wider or narrower (depending on the operation) than the source type. SIGN_EXTEND - Used for integer types, replicating the sign bit into new bits. ZERO_EXTEND ZERO_EXTEND - Used for integer types, zeroing the new bits. ANY_EXTEND ANY_EXTEND - Used for integer types. The high bits are undefined. TRUNCATE TRUNCATE - Completely drop the high bits. SINT_TO_FP [SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter) to floating point. UINT_TO_FP SIGN_EXTEND_INREG SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in a large integer register (e.g. sign extending the low 8 bits of a 32-bit register to fill the top 24 bits with the 7th bit). The size of the smaller type is indicated by the 1th operand, a ValueType node. ANY_EXTEND_VECTOR_INREG ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low lanes of an integer vector. The result type must have fewer elements than the operand type, and those elements must be larger integer types such that the total size of the operand type and the result type match. Each of the low operand elements is any-extended into the corresponding, wider result elements with the high bits becoming undef. SIGN_EXTEND_VECTOR_INREG SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low lanes of an integer vector. The result type must have fewer elements than the operand type, and those elements must be larger integer types such that the total size of the operand type and the result type match. Each of the low operand elements is sign-extended into the corresponding, wider result elements. ZERO_EXTEND_VECTOR_INREG ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low lanes of an integer vector. The result type must have fewer elements than the operand type, and those elements must be larger integer types such that the total size of the operand type and the result type match. Each of the low operand elements is zero-extended into the corresponding, wider result elements. FP_TO_SINT FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer. FP_TO_UINT FP_ROUND X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the destination VT. TRUNC is a flag, which is always an integer that is zero or one. If TRUNC is 0, this is a normal rounding, if it is 1, this FP_ROUND is known to not change the value of Y. The TRUNC = 1 case is used in cases where we know that the value will not be modified by the node, because Y is not using any of the extra precision of source type. This allows certain transformations like FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. FLT_ROUNDS_ FLT_ROUNDS_ - Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest 2 Round to +inf 3 Round to -inf FP_ROUND_INREG X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and rounds it to a floating point value. It then promotes it and returns it in a register of the same size. This operation effectively just discards excess precision. The type to round down to is specified by the VT operand, a VTSDNode. FP_EXTEND X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. BITCAST BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to memory with one type and loaded from the same address with the other type (or equivalently for vector format conversions, etc). The source and result are required to have the same bit size (e.g. f32 <-> i32). This can also be used for int-to-int or fp-to-fp conversions, but that is a noop, deleted by getNode(). ADDRSPACECAST ADDRSPACECAST - This operator converts between pointers of different address spaces. CONVERT_RNDSAT CONVERT_RNDSAT - This operator is used to support various conversions between various types (float, signed, unsigned and vectors of those types) with rounding and saturation. NOTE: Avoid using this operator as most target don't support it and the operator might be removed in the future. It takes the following arguments: 0) value 1) dest type (type to convert to) 2) src type (type to convert from) 3) rounding imm 4) saturation imm 5) ISD::CvtCode indicating the type of conversion to do FP16_TO_FP FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-precision (16 bit) floating numbers. These nodes form a semi-softened interface for dealing with f16 (as an i16), which is often a storage-only type but has native conversions. FP_TO_FP16 FNEG FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations. These are inspired by libm. FABS FSQRT FSIN FCOS FPOWI FPOW FLOG FLOG2 FLOG10 FEXP FEXP2 FCEIL FTRUNC FRINT FNEARBYINT FROUND FFLOOR FMINNUM FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values. In the case where a single input is NaN, the non-NaN input is returned. The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0. FMAXNUM FMINNAN FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that when a single input is NaN, NaN is returned. FMAXNAN FSINCOS FSINCOS - Compute both fsin and fcos as a single operation. LOAD LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store instruction, then an offset node that is added / subtracted from the base pointer to form the address (for indexed memory ops). STORE DYNAMIC_STACKALLOC DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary. This node always has two return values: a new stack pointer value and a chain. The first operand is the token chain, the second is the number of bytes to allocate, and the third is the alignment boundary. The size is guaranteed to be a multiple of the stack alignment, and the alignment is guaranteed to be bigger than the stack alignment (if required) or 0 to get standard stack alignment. BR Control flow instructions. These all have token chains. BR - Unconditional branch. The first operand is the chain operand, the second is the MBB to branch to. BRIND BRIND - Indirect branch. The first operand is the chain, the second is the value to branch to, which must be of the same type as the target's pointer type. BR_JT BR_JT - Jumptable branch. The first operand is the chain, the second is the jumptable index, the last one is the jumptable entry index. BRCOND BRCOND - Conditional branch. The first operand is the chain, the second is the condition, the third is the block to branch to if the condition is true. If the type of the condition is not i1, then the high bits must conform to getBooleanContents. BR_CC BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in that the condition is represented as condition code, and two nodes to compare, rather than as a combined SetCC node. The operands in order are chain, cc, lhs, rhs, block to branch to if condition is true. INLINEASM INLINEASM - Represents an inline asm block. This node always has two return values: a chain and a flag result. The inputs are as follows: Operand #0 : Input chain. Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. Operand #2 : a MDNodeSDNode with the !srcloc metadata. Operand #3 : HasSideEffect, IsAlignStack bits. After this, it is followed by a list of operands with this format: ConstantSDNode: Flags that encode whether it is a mem or not, the of operands that follow, etc. See InlineAsm.h. ... however many operands ... Operand #last: Optional, an incoming flag. The variable width operands are required to represent target addressing modes as a single "operand", even though they may have multiple SDOperands. EH_LABEL EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and exception handling tables. These nodes take a chain as input and return a chain. CATCHPAD CATCHPAD - Represents a catchpad instruction. CATCHRET CATCHRET - Represents a return from a catch block funclet. Used for MSVC compatible exception handling. Takes a chain operand and a destination basic block operand. CLEANUPRET CLEANUPRET - Represents a return from a cleanup block funclet. Used for MSVC compatible exception handling. Takes only a chain operand. STACKSAVE STACKSAVE - STACKSAVE has one operand, an input chain. It produces a value, the same type as the pointer type for the system, and an output chain. STACKRESTORE STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain. CALLSEQ_START CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence, and carry arbitrary information that target might want to know. The first operand is a chain, the rest are specified by the target and not touched by the DAG optimizers. CALLSEQ_START..CALLSEQ_END pairs may not be nested. CALLSEQ_END VAARG VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment. It returns a pair of values: the vaarg value and a new chain. VACOPY VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source. VAEND VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE. VASTART SRCVALUE SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the LLVM IR. MDNODE_SDNODE MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR. PCMARKER PCMARKER - This corresponds to the pcmarker intrinsic. READCYCLECOUNTER READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. It produces a chain and one i64 value. The only operand is a chain. If i64 is not legal, the result will be expanded into smaller values. Still, it returns an i64, so targets should set legality for i64. The result is the content of the architecture-specific cycle counter-like register (or other high accuracy low latency clock source). HANDLENODE HANDLENODE node - Used as a handle for various purposes. INIT_TRAMPOLINE INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It takes as input a token chain, the pointer to the trampoline, the pointer to the nested function, the pointer to pass for the 'nest' parameter, a SRCVALUE for the trampoline and another for the nested function (allowing targets to access the original Function*). It produces a token chain as output. ADJUST_TRAMPOLINE ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. It takes a pointer to the trampoline and produces a (possibly) new pointer to the same trampoline with platform-specific adjustments applied. The pointer it returns points to an executable block of code. TRAP TRAP - Trapping instruction. DEBUGTRAP DEBUGTRAP - Trap intended to get the attention of a debugger. PREFETCH PREFETCH - This corresponds to a prefetch intrinsic. The first operand is the chain. The other operands are the address to prefetch, read / write specifier, locality specifier and instruction / data cache specifier. ATOMIC_FENCE OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction. It takes an input chain, and two integer constants: an AtomicOrdering and a SynchronizationScope. ATOMIC_LOAD Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction. ATOMIC_STORE OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction. ATOMIC_CMP_SWAP Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi, swapLo, swapHi) This corresponds to the cmpxchg instruction. ATOMIC_CMP_SWAP_WITH_SUCCESS Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b. this is still a strong cmpxchg operation, so Success == "Val == cmp". ATOMIC_SWAP Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction. ATOMIC_LOAD_ADD ATOMIC_LOAD_SUB ATOMIC_LOAD_AND ATOMIC_LOAD_OR ATOMIC_LOAD_XOR ATOMIC_LOAD_NAND ATOMIC_LOAD_MIN ATOMIC_LOAD_MAX ATOMIC_LOAD_UMIN ATOMIC_LOAD_UMAX MLOAD MSTORE MGATHER MSCATTER LIFETIME_START This corresponds to the llvm.lifetime. * intrinsics. The first operand is the chain and the second operand is the alloca pointer. LIFETIME_END GC_TRANSITION_START GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the beginning and end of GC transition sequence, and carry arbitrary information that target might need for lowering. The first operand is a chain, the rest are specified by the target and not touched by the DAG optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be nested. GC_TRANSITION_END GET_DYNAMIC_AREA_OFFSET GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca. For most targets that would be 0, but for some others (e.g. PowerPC, PowerPC64) that would be compile-time known nonzero constant. The only operand here is the chain. BUILTIN_OP_END BUILTIN_OP_END - This must be the last enum value in this list. The target-specific pre-isel opcode values start here.

Definition at line 39 of file ISDOpcodes.h.

## Function Documentation

 bool llvm::ISD::allOperandsUndef ( const SDNode * N )

Return true if the node has at least one operand and all operands of the specified node are ISD::UNDEF.

allOperandsUndef - Return true if the node has at least one operand and all operands of the specified node are ISD::UNDEF.

Definition at line 216 of file SelectionDAG.cpp.

References llvm::SDNode::getNumOperands(), llvm::SDNode::op_values(), and UNDEF.

 ISD::NodeType llvm::ISD::getExtForLoadExtType ( bool IsFP, ISD::LoadExtType ExtType )
 ISD::CondCode llvm::ISD::getSetCCAndOperation ( ISD::CondCode Op1, ISD::CondCode Op2, bool isInteger )

getSetCCAndOperation - Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X op2 Y)).

This function returns SETCC_INVALID if it is not possible to represent the resultant comparison.

This function returns zero if it is not possible to represent the resultant comparison.

Definition at line 320 of file SelectionDAG.cpp.

References isSignedOp(), SETCC_INVALID, SETEQ, SETFALSE, SETOEQ, SETOGT, SETOLT, SETUEQ, SETUGT, SETULT, and SETUO.

 ISD::CondCode llvm::ISD::getSetCCInverse ( ISD::CondCode Op, bool isInteger )

getSetCCInverse - Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.

Definition at line 259 of file SelectionDAG.cpp.

References SETTRUE2.

 ISD::CondCode llvm::ISD::getSetCCOrOperation ( ISD::CondCode Op1, ISD::CondCode Op2, bool isInteger )

getSetCCOrOperation - Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X op2 Y)).

This function returns SETCC_INVALID if it is not possible to represent the resultant comparison.

Definition at line 296 of file SelectionDAG.cpp.

References isSignedOp(), SETCC_INVALID, SETNE, SETTRUE2, and SETUNE.

 ISD::CondCode llvm::ISD::getSetCCSwappedOperands ( ISD::CondCode Operation )

getSetCCSwappedOperands - Return the operation corresponding to (Y op X) when given the operation for (X op Y).

Definition at line 247 of file SelectionDAG.cpp.

 unsigned llvm::ISD::getUnorderedFlavor ( CondCode Cond )  [inline]

getUnorderedFlavor - This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if the condition is undefined if the operand is a NaN.

Definition at line 895 of file ISDOpcodes.h.

Referenced by llvm::TargetLowering::SimplifySetCC().

 bool llvm::ISD::isBuildVectorAllOnes ( const SDNode * N )

Node predicates.

isBuildVectorAllOnes - Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef.

Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef.

Definition at line 99 of file SelectionDAG.cpp.

 bool llvm::ISD::isBuildVectorAllZeros ( const SDNode * N )

Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.

isBuildVectorAllZeros - Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.

Definition at line 147 of file SelectionDAG.cpp.

 bool llvm::ISD::isBuildVectorOfConstantFPSDNodes ( const SDNode * N )

Return true if the specified node is a BUILD_VECTOR node of all ConstantFPSDNode or undef.

Definition at line 201 of file SelectionDAG.cpp.

References BUILD_VECTOR, llvm::SDNode::getOpcode(), llvm::SDNode::op_values(), and UNDEF.

Referenced by ExtendToType(), and isConstantFPBuildVectorOrConstantFP().

 bool llvm::ISD::isBuildVectorOfConstantSDNodes ( const SDNode * N )

Return true if the specified node is a BUILD_VECTOR node of all ConstantSDNode or undef.

Definition at line 186 of file SelectionDAG.cpp.

References BUILD_VECTOR, llvm::SDNode::getOpcode(), llvm::SDNode::op_values(), and UNDEF.

 bool llvm::ISD::isEXTLoad ( const SDNode * N )  [inline]

Returns true if the specified node is a EXTLOAD.

Definition at line 2288 of file SelectionDAGNodes.h.

References EXTLOAD.

Referenced by isFloatingPointZero().

 bool llvm::ISD::isNON_EXTLoad ( const SDNode * N )  [inline]

Returns true if the specified node is a non-extending load.

Definition at line 2282 of file SelectionDAGNodes.h.

References NON_EXTLOAD.

 bool llvm::ISD::isNON_TRUNCStore ( const SDNode * N )  [inline]

Returns true if the specified node is a non-truncating store.

Definition at line 2320 of file SelectionDAGNodes.h.

 bool llvm::ISD::isNormalLoad ( const SDNode * N )  [inline]

Returns true if the specified node is a non-extending and unindexed load.

Definition at line 2275 of file SelectionDAGNodes.h.

 bool llvm::ISD::isNormalStore ( const SDNode * N )  [inline]

Returns true if the specified node is a non-truncating and unindexed store.

Definition at line 2313 of file SelectionDAGNodes.h.

Referenced by isLoadIncOrDecStore(), MayFoldIntoStore(), PerformSTORECombine(), and usesAllNormalStores().

 bool llvm::ISD::isSEXTLoad ( const SDNode * N )  [inline]

Returns true if the specified node is a SEXTLOAD.

Definition at line 2294 of file SelectionDAGNodes.h.

References SEXTLOAD.

 bool llvm::ISD::isSignedIntSetCC ( CondCode Code )  [inline]

isSignedIntSetCC - Return true if this is a setcc instruction that performs a signed comparison when used with integer operands.

Definition at line 874 of file ISDOpcodes.h.

References SETGE, SETGT, SETLE, and SETLT.

 bool llvm::ISD::isTrueWhenEqual ( CondCode Cond )  [inline]

isTrueWhenEqual - Return true if the specified condition returns true if the two operands to the condition are equal.

Note that if one of the two operands is a NaN, this value is meaningless.

Definition at line 887 of file ISDOpcodes.h.

 bool llvm::ISD::isTRUNCStore ( const SDNode * N )  [inline]

Returns true if the specified node is a truncating store.

Definition at line 2325 of file SelectionDAGNodes.h.

 bool llvm::ISD::isUNINDEXEDLoad ( const SDNode * N )  [inline]

Returns true if the specified node is an unindexed load.

Definition at line 2306 of file SelectionDAGNodes.h.

References UNINDEXED.

 bool llvm::ISD::isUNINDEXEDStore ( const SDNode * N )  [inline]

Returns true if the specified node is an unindexed store.

Definition at line 2330 of file SelectionDAGNodes.h.

References UNINDEXED.

 bool llvm::ISD::isUnsignedIntSetCC ( CondCode Code )  [inline]

isUnsignedIntSetCC - Return true if this is a setcc instruction that performs an unsigned comparison when used with integer operands.

Definition at line 880 of file ISDOpcodes.h.

References SETUGE, SETUGT, SETULE, and SETULT.

Referenced by emitComparison(), llvm::HexagonTargetLowering::LowerSETCC(), and LowerVSETCC().

 bool llvm::ISD::isZEXTLoad ( const SDNode * N )  [inline]

Returns true if the specified node is a ZEXTLOAD.

Definition at line 2300 of file SelectionDAGNodes.h.

References ZEXTLOAD.

Referenced by llvm::SelectionDAG::computeKnownBits(), and isZeroExtended().

## Variable Documentation

 const int llvm::ISD::FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+300 [static]

FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific memory location should be less than this value.

Those that do must not be less than this value, and can be used with SelectionDAG::getMemIntrinsicNode.

Definition at line 768 of file ISDOpcodes.h.