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TargetLowering.cpp
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00001 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This implements the TargetLowering class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "llvm/Target/TargetLowering.h"
00015 #include "llvm/ADT/BitVector.h"
00016 #include "llvm/ADT/STLExtras.h"
00017 #include "llvm/CodeGen/Analysis.h"
00018 #include "llvm/CodeGen/MachineFrameInfo.h"
00019 #include "llvm/CodeGen/MachineFunction.h"
00020 #include "llvm/CodeGen/MachineJumpTableInfo.h"
00021 #include "llvm/CodeGen/SelectionDAG.h"
00022 #include "llvm/IR/DataLayout.h"
00023 #include "llvm/IR/DerivedTypes.h"
00024 #include "llvm/IR/GlobalVariable.h"
00025 #include "llvm/IR/LLVMContext.h"
00026 #include "llvm/MC/MCAsmInfo.h"
00027 #include "llvm/MC/MCExpr.h"
00028 #include "llvm/Support/CommandLine.h"
00029 #include "llvm/Support/ErrorHandling.h"
00030 #include "llvm/Support/MathExtras.h"
00031 #include "llvm/Target/TargetLoweringObjectFile.h"
00032 #include "llvm/Target/TargetMachine.h"
00033 #include "llvm/Target/TargetRegisterInfo.h"
00034 #include "llvm/Target/TargetSubtargetInfo.h"
00035 #include <cctype>
00036 using namespace llvm;
00037 
00038 /// NOTE: The constructor takes ownership of TLOF.
00039 TargetLowering::TargetLowering(const TargetMachine &tm,
00040                                const TargetLoweringObjectFile *tlof)
00041   : TargetLoweringBase(tm, tlof) {}
00042 
00043 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
00044   return nullptr;
00045 }
00046 
00047 /// Check whether a given call node is in tail position within its function. If
00048 /// so, it sets Chain to the input chain of the tail call.
00049 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
00050                                           SDValue &Chain) const {
00051   const Function *F = DAG.getMachineFunction().getFunction();
00052 
00053   // Conservatively require the attributes of the call to match those of
00054   // the return. Ignore noalias because it doesn't affect the call sequence.
00055   AttributeSet CallerAttrs = F->getAttributes();
00056   if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
00057       .removeAttribute(Attribute::NoAlias).hasAttributes())
00058     return false;
00059 
00060   // It's not safe to eliminate the sign / zero extension of the return value.
00061   if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
00062       CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
00063     return false;
00064 
00065   // Check if the only use is a function return node.
00066   return isUsedByReturnOnly(Node, Chain);
00067 }
00068 
00069 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
00070 /// and called function attributes.
00071 void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS,
00072                                                  unsigned AttrIdx) {
00073   isSExt     = CS->paramHasAttr(AttrIdx, Attribute::SExt);
00074   isZExt     = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
00075   isInReg    = CS->paramHasAttr(AttrIdx, Attribute::InReg);
00076   isSRet     = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
00077   isNest     = CS->paramHasAttr(AttrIdx, Attribute::Nest);
00078   isByVal    = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
00079   isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
00080   isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
00081   Alignment  = CS->getParamAlignment(AttrIdx);
00082 }
00083 
00084 /// Generate a libcall taking the given operands as arguments and returning a
00085 /// result of type RetVT.
00086 std::pair<SDValue, SDValue>
00087 TargetLowering::makeLibCall(SelectionDAG &DAG,
00088                             RTLIB::Libcall LC, EVT RetVT,
00089                             const SDValue *Ops, unsigned NumOps,
00090                             bool isSigned, SDLoc dl,
00091                             bool doesNotReturn,
00092                             bool isReturnValueUsed) const {
00093   TargetLowering::ArgListTy Args;
00094   Args.reserve(NumOps);
00095 
00096   TargetLowering::ArgListEntry Entry;
00097   for (unsigned i = 0; i != NumOps; ++i) {
00098     Entry.Node = Ops[i];
00099     Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
00100     Entry.isSExt = isSigned;
00101     Entry.isZExt = !isSigned;
00102     Args.push_back(Entry);
00103   }
00104   SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
00105 
00106   Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
00107   TargetLowering::CallLoweringInfo CLI(DAG);
00108   CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
00109     .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
00110     .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
00111     .setSExtResult(isSigned).setZExtResult(!isSigned);
00112   return LowerCallTo(CLI);
00113 }
00114 
00115 
00116 /// SoftenSetCCOperands - Soften the operands of a comparison.  This code is
00117 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
00118 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
00119                                          SDValue &NewLHS, SDValue &NewRHS,
00120                                          ISD::CondCode &CCCode,
00121                                          SDLoc dl) const {
00122   assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
00123          && "Unsupported setcc type!");
00124 
00125   // Expand into one or more soft-fp libcall(s).
00126   RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
00127   switch (CCCode) {
00128   case ISD::SETEQ:
00129   case ISD::SETOEQ:
00130     LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
00131           (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
00132     break;
00133   case ISD::SETNE:
00134   case ISD::SETUNE:
00135     LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
00136           (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
00137     break;
00138   case ISD::SETGE:
00139   case ISD::SETOGE:
00140     LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
00141           (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
00142     break;
00143   case ISD::SETLT:
00144   case ISD::SETOLT:
00145     LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
00146           (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
00147     break;
00148   case ISD::SETLE:
00149   case ISD::SETOLE:
00150     LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
00151           (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
00152     break;
00153   case ISD::SETGT:
00154   case ISD::SETOGT:
00155     LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
00156           (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
00157     break;
00158   case ISD::SETUO:
00159     LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
00160           (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
00161     break;
00162   case ISD::SETO:
00163     LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
00164           (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
00165     break;
00166   default:
00167     LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
00168           (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
00169     switch (CCCode) {
00170     case ISD::SETONE:
00171       // SETONE = SETOLT | SETOGT
00172       LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
00173             (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
00174       // Fallthrough
00175     case ISD::SETUGT:
00176       LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
00177             (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
00178       break;
00179     case ISD::SETUGE:
00180       LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
00181             (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
00182       break;
00183     case ISD::SETULT:
00184       LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
00185             (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
00186       break;
00187     case ISD::SETULE:
00188       LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
00189             (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
00190       break;
00191     case ISD::SETUEQ:
00192       LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
00193             (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
00194       break;
00195     default: llvm_unreachable("Do not know how to soften this setcc!");
00196     }
00197   }
00198 
00199   // Use the target specific return value for comparions lib calls.
00200   EVT RetVT = getCmpLibcallReturnType();
00201   SDValue Ops[2] = { NewLHS, NewRHS };
00202   NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
00203                        dl).first;
00204   NewRHS = DAG.getConstant(0, RetVT);
00205   CCCode = getCmpLibcallCC(LC1);
00206   if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
00207     SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
00208                               getSetCCResultType(*DAG.getContext(), RetVT),
00209                               NewLHS, NewRHS, DAG.getCondCode(CCCode));
00210     NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
00211                          dl).first;
00212     NewLHS = DAG.getNode(ISD::SETCC, dl,
00213                          getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
00214                          NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
00215     NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
00216     NewRHS = SDValue();
00217   }
00218 }
00219 
00220 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
00221 /// current function.  The returned value is a member of the
00222 /// MachineJumpTableInfo::JTEntryKind enum.
00223 unsigned TargetLowering::getJumpTableEncoding() const {
00224   // In non-pic modes, just use the address of a block.
00225   if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
00226     return MachineJumpTableInfo::EK_BlockAddress;
00227 
00228   // In PIC mode, if the target supports a GPRel32 directive, use it.
00229   if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
00230     return MachineJumpTableInfo::EK_GPRel32BlockAddress;
00231 
00232   // Otherwise, use a label difference.
00233   return MachineJumpTableInfo::EK_LabelDifference32;
00234 }
00235 
00236 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
00237                                                  SelectionDAG &DAG) const {
00238   // If our PIC model is GP relative, use the global offset table as the base.
00239   unsigned JTEncoding = getJumpTableEncoding();
00240 
00241   if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
00242       (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
00243     return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
00244 
00245   return Table;
00246 }
00247 
00248 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
00249 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
00250 /// MCExpr.
00251 const MCExpr *
00252 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
00253                                              unsigned JTI,MCContext &Ctx) const{
00254   // The normal PIC reloc base is the label at the start of the jump table.
00255   return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
00256 }
00257 
00258 bool
00259 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
00260   // Assume that everything is safe in static mode.
00261   if (getTargetMachine().getRelocationModel() == Reloc::Static)
00262     return true;
00263 
00264   // In dynamic-no-pic mode, assume that known defined values are safe.
00265   if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
00266       GA &&
00267       !GA->getGlobal()->isDeclaration() &&
00268       !GA->getGlobal()->isWeakForLinker())
00269     return true;
00270 
00271   // Otherwise assume nothing is safe.
00272   return false;
00273 }
00274 
00275 //===----------------------------------------------------------------------===//
00276 //  Optimization Methods
00277 //===----------------------------------------------------------------------===//
00278 
00279 /// ShrinkDemandedConstant - Check to see if the specified operand of the
00280 /// specified instruction is a constant integer.  If so, check to see if there
00281 /// are any bits set in the constant that are not demanded.  If so, shrink the
00282 /// constant and return true.
00283 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
00284                                                         const APInt &Demanded) {
00285   SDLoc dl(Op);
00286 
00287   // FIXME: ISD::SELECT, ISD::SELECT_CC
00288   switch (Op.getOpcode()) {
00289   default: break;
00290   case ISD::XOR:
00291   case ISD::AND:
00292   case ISD::OR: {
00293     ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
00294     if (!C) return false;
00295 
00296     if (Op.getOpcode() == ISD::XOR &&
00297         (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
00298       return false;
00299 
00300     // if we can expand it to have all bits set, do it
00301     if (C->getAPIntValue().intersects(~Demanded)) {
00302       EVT VT = Op.getValueType();
00303       SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
00304                                 DAG.getConstant(Demanded &
00305                                                 C->getAPIntValue(),
00306                                                 VT));
00307       return CombineTo(Op, New);
00308     }
00309 
00310     break;
00311   }
00312   }
00313 
00314   return false;
00315 }
00316 
00317 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
00318 /// casts are free.  This uses isZExtFree and ZERO_EXTEND for the widening
00319 /// cast, but it could be generalized for targets with other types of
00320 /// implicit widening casts.
00321 bool
00322 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
00323                                                     unsigned BitWidth,
00324                                                     const APInt &Demanded,
00325                                                     SDLoc dl) {
00326   assert(Op.getNumOperands() == 2 &&
00327          "ShrinkDemandedOp only supports binary operators!");
00328   assert(Op.getNode()->getNumValues() == 1 &&
00329          "ShrinkDemandedOp only supports nodes with one result!");
00330 
00331   // Early return, as this function cannot handle vector types.
00332   if (Op.getValueType().isVector())
00333     return false;
00334 
00335   // Don't do this if the node has another user, which may require the
00336   // full value.
00337   if (!Op.getNode()->hasOneUse())
00338     return false;
00339 
00340   // Search for the smallest integer type with free casts to and from
00341   // Op's type. For expedience, just check power-of-2 integer types.
00342   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
00343   unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
00344   unsigned SmallVTBits = DemandedSize;
00345   if (!isPowerOf2_32(SmallVTBits))
00346     SmallVTBits = NextPowerOf2(SmallVTBits);
00347   for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
00348     EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
00349     if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
00350         TLI.isZExtFree(SmallVT, Op.getValueType())) {
00351       // We found a type with free casts.
00352       SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
00353                               DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
00354                                           Op.getNode()->getOperand(0)),
00355                               DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
00356                                           Op.getNode()->getOperand(1)));
00357       bool NeedZext = DemandedSize > SmallVTBits;
00358       SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
00359                               dl, Op.getValueType(), X);
00360       return CombineTo(Op, Z);
00361     }
00362   }
00363   return false;
00364 }
00365 
00366 /// SimplifyDemandedBits - Look at Op.  At this point, we know that only the
00367 /// DemandedMask bits of the result of Op are ever used downstream.  If we can
00368 /// use this information to simplify Op, create a new simplified DAG node and
00369 /// return true, returning the original and new nodes in Old and New. Otherwise,
00370 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
00371 /// the expression (used to simplify the caller).  The KnownZero/One bits may
00372 /// only be accurate for those bits in the DemandedMask.
00373 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
00374                                           const APInt &DemandedMask,
00375                                           APInt &KnownZero,
00376                                           APInt &KnownOne,
00377                                           TargetLoweringOpt &TLO,
00378                                           unsigned Depth) const {
00379   unsigned BitWidth = DemandedMask.getBitWidth();
00380   assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
00381          "Mask size mismatches value type size!");
00382   APInt NewMask = DemandedMask;
00383   SDLoc dl(Op);
00384 
00385   // Don't know anything.
00386   KnownZero = KnownOne = APInt(BitWidth, 0);
00387 
00388   // Other users may use these bits.
00389   if (!Op.getNode()->hasOneUse()) {
00390     if (Depth != 0) {
00391       // If not at the root, Just compute the KnownZero/KnownOne bits to
00392       // simplify things downstream.
00393       TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
00394       return false;
00395     }
00396     // If this is the root being simplified, allow it to have multiple uses,
00397     // just set the NewMask to all bits.
00398     NewMask = APInt::getAllOnesValue(BitWidth);
00399   } else if (DemandedMask == 0) {
00400     // Not demanding any bits from Op.
00401     if (Op.getOpcode() != ISD::UNDEF)
00402       return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
00403     return false;
00404   } else if (Depth == 6) {        // Limit search depth.
00405     return false;
00406   }
00407 
00408   APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
00409   switch (Op.getOpcode()) {
00410   case ISD::Constant:
00411     // We know all of the bits for a constant!
00412     KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
00413     KnownZero = ~KnownOne;
00414     return false;   // Don't fall through, will infinitely loop.
00415   case ISD::AND:
00416     // If the RHS is a constant, check to see if the LHS would be zero without
00417     // using the bits from the RHS.  Below, we use knowledge about the RHS to
00418     // simplify the LHS, here we're using information from the LHS to simplify
00419     // the RHS.
00420     if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
00421       APInt LHSZero, LHSOne;
00422       // Do not increment Depth here; that can cause an infinite loop.
00423       TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
00424       // If the LHS already has zeros where RHSC does, this and is dead.
00425       if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
00426         return TLO.CombineTo(Op, Op.getOperand(0));
00427       // If any of the set bits in the RHS are known zero on the LHS, shrink
00428       // the constant.
00429       if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
00430         return true;
00431     }
00432 
00433     if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
00434                              KnownOne, TLO, Depth+1))
00435       return true;
00436     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
00437     if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
00438                              KnownZero2, KnownOne2, TLO, Depth+1))
00439       return true;
00440     assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
00441 
00442     // If all of the demanded bits are known one on one side, return the other.
00443     // These bits cannot contribute to the result of the 'and'.
00444     if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
00445       return TLO.CombineTo(Op, Op.getOperand(0));
00446     if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
00447       return TLO.CombineTo(Op, Op.getOperand(1));
00448     // If all of the demanded bits in the inputs are known zeros, return zero.
00449     if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
00450       return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
00451     // If the RHS is a constant, see if we can simplify it.
00452     if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
00453       return true;
00454     // If the operation can be done in a smaller type, do so.
00455     if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
00456       return true;
00457 
00458     // Output known-1 bits are only known if set in both the LHS & RHS.
00459     KnownOne &= KnownOne2;
00460     // Output known-0 are known to be clear if zero in either the LHS | RHS.
00461     KnownZero |= KnownZero2;
00462     break;
00463   case ISD::OR:
00464     if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
00465                              KnownOne, TLO, Depth+1))
00466       return true;
00467     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
00468     if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
00469                              KnownZero2, KnownOne2, TLO, Depth+1))
00470       return true;
00471     assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
00472 
00473     // If all of the demanded bits are known zero on one side, return the other.
00474     // These bits cannot contribute to the result of the 'or'.
00475     if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
00476       return TLO.CombineTo(Op, Op.getOperand(0));
00477     if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
00478       return TLO.CombineTo(Op, Op.getOperand(1));
00479     // If all of the potentially set bits on one side are known to be set on
00480     // the other side, just use the 'other' side.
00481     if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
00482       return TLO.CombineTo(Op, Op.getOperand(0));
00483     if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
00484       return TLO.CombineTo(Op, Op.getOperand(1));
00485     // If the RHS is a constant, see if we can simplify it.
00486     if (TLO.ShrinkDemandedConstant(Op, NewMask))
00487       return true;
00488     // If the operation can be done in a smaller type, do so.
00489     if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
00490       return true;
00491 
00492     // Output known-0 bits are only known if clear in both the LHS & RHS.
00493     KnownZero &= KnownZero2;
00494     // Output known-1 are known to be set if set in either the LHS | RHS.
00495     KnownOne |= KnownOne2;
00496     break;
00497   case ISD::XOR:
00498     if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
00499                              KnownOne, TLO, Depth+1))
00500       return true;
00501     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
00502     if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
00503                              KnownOne2, TLO, Depth+1))
00504       return true;
00505     assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
00506 
00507     // If all of the demanded bits are known zero on one side, return the other.
00508     // These bits cannot contribute to the result of the 'xor'.
00509     if ((KnownZero & NewMask) == NewMask)
00510       return TLO.CombineTo(Op, Op.getOperand(0));
00511     if ((KnownZero2 & NewMask) == NewMask)
00512       return TLO.CombineTo(Op, Op.getOperand(1));
00513     // If the operation can be done in a smaller type, do so.
00514     if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
00515       return true;
00516 
00517     // If all of the unknown bits are known to be zero on one side or the other
00518     // (but not both) turn this into an *inclusive* or.
00519     //    e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
00520     if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
00521       return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
00522                                                Op.getOperand(0),
00523                                                Op.getOperand(1)));
00524 
00525     // Output known-0 bits are known if clear or set in both the LHS & RHS.
00526     KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
00527     // Output known-1 are known to be set if set in only one of the LHS, RHS.
00528     KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
00529 
00530     // If all of the demanded bits on one side are known, and all of the set
00531     // bits on that side are also known to be set on the other side, turn this
00532     // into an AND, as we know the bits will be cleared.
00533     //    e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
00534     // NB: it is okay if more bits are known than are requested
00535     if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
00536       if (KnownOne == KnownOne2) { // set bits are the same on both sides
00537         EVT VT = Op.getValueType();
00538         SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
00539         return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
00540                                                  Op.getOperand(0), ANDC));
00541       }
00542     }
00543 
00544     // If the RHS is a constant, see if we can simplify it.
00545     // for XOR, we prefer to force bits to 1 if they will make a -1.
00546     // if we can't force bits, try to shrink constant
00547     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
00548       APInt Expanded = C->getAPIntValue() | (~NewMask);
00549       // if we can expand it to have all bits set, do it
00550       if (Expanded.isAllOnesValue()) {
00551         if (Expanded != C->getAPIntValue()) {
00552           EVT VT = Op.getValueType();
00553           SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
00554                                           TLO.DAG.getConstant(Expanded, VT));
00555           return TLO.CombineTo(Op, New);
00556         }
00557         // if it already has all the bits set, nothing to change
00558         // but don't shrink either!
00559       } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
00560         return true;
00561       }
00562     }
00563 
00564     KnownZero = KnownZeroOut;
00565     KnownOne  = KnownOneOut;
00566     break;
00567   case ISD::SELECT:
00568     if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
00569                              KnownOne, TLO, Depth+1))
00570       return true;
00571     if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
00572                              KnownOne2, TLO, Depth+1))
00573       return true;
00574     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
00575     assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
00576 
00577     // If the operands are constants, see if we can simplify them.
00578     if (TLO.ShrinkDemandedConstant(Op, NewMask))
00579       return true;
00580 
00581     // Only known if known in both the LHS and RHS.
00582     KnownOne &= KnownOne2;
00583     KnownZero &= KnownZero2;
00584     break;
00585   case ISD::SELECT_CC:
00586     if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
00587                              KnownOne, TLO, Depth+1))
00588       return true;
00589     if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
00590                              KnownOne2, TLO, Depth+1))
00591       return true;
00592     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
00593     assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
00594 
00595     // If the operands are constants, see if we can simplify them.
00596     if (TLO.ShrinkDemandedConstant(Op, NewMask))
00597       return true;
00598 
00599     // Only known if known in both the LHS and RHS.
00600     KnownOne &= KnownOne2;
00601     KnownZero &= KnownZero2;
00602     break;
00603   case ISD::SHL:
00604     if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
00605       unsigned ShAmt = SA->getZExtValue();
00606       SDValue InOp = Op.getOperand(0);
00607 
00608       // If the shift count is an invalid immediate, don't do anything.
00609       if (ShAmt >= BitWidth)
00610         break;
00611 
00612       // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
00613       // single shift.  We can do this if the bottom bits (which are shifted
00614       // out) are never demanded.
00615       if (InOp.getOpcode() == ISD::SRL &&
00616           isa<ConstantSDNode>(InOp.getOperand(1))) {
00617         if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
00618           unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
00619           unsigned Opc = ISD::SHL;
00620           int Diff = ShAmt-C1;
00621           if (Diff < 0) {
00622             Diff = -Diff;
00623             Opc = ISD::SRL;
00624           }
00625 
00626           SDValue NewSA =
00627             TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
00628           EVT VT = Op.getValueType();
00629           return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
00630                                                    InOp.getOperand(0), NewSA));
00631         }
00632       }
00633 
00634       if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
00635                                KnownZero, KnownOne, TLO, Depth+1))
00636         return true;
00637 
00638       // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
00639       // are not demanded. This will likely allow the anyext to be folded away.
00640       if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
00641         SDValue InnerOp = InOp.getNode()->getOperand(0);
00642         EVT InnerVT = InnerOp.getValueType();
00643         unsigned InnerBits = InnerVT.getSizeInBits();
00644         if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
00645             isTypeDesirableForOp(ISD::SHL, InnerVT)) {
00646           EVT ShTy = getShiftAmountTy(InnerVT);
00647           if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
00648             ShTy = InnerVT;
00649           SDValue NarrowShl =
00650             TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
00651                             TLO.DAG.getConstant(ShAmt, ShTy));
00652           return
00653             TLO.CombineTo(Op,
00654                           TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
00655                                           NarrowShl));
00656         }
00657         // Repeat the SHL optimization above in cases where an extension
00658         // intervenes: (shl (anyext (shr x, c1)), c2) to
00659         // (shl (anyext x), c2-c1).  This requires that the bottom c1 bits
00660         // aren't demanded (as above) and that the shifted upper c1 bits of
00661         // x aren't demanded.
00662         if (InOp.hasOneUse() &&
00663             InnerOp.getOpcode() == ISD::SRL &&
00664             InnerOp.hasOneUse() &&
00665             isa<ConstantSDNode>(InnerOp.getOperand(1))) {
00666           uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
00667             ->getZExtValue();
00668           if (InnerShAmt < ShAmt &&
00669               InnerShAmt < InnerBits &&
00670               NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
00671               NewMask.trunc(ShAmt) == 0) {
00672             SDValue NewSA =
00673               TLO.DAG.getConstant(ShAmt - InnerShAmt,
00674                                   Op.getOperand(1).getValueType());
00675             EVT VT = Op.getValueType();
00676             SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
00677                                              InnerOp.getOperand(0));
00678             return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
00679                                                      NewExt, NewSA));
00680           }
00681         }
00682       }
00683 
00684       KnownZero <<= SA->getZExtValue();
00685       KnownOne  <<= SA->getZExtValue();
00686       // low bits known zero.
00687       KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
00688     }
00689     break;
00690   case ISD::SRL:
00691     if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
00692       EVT VT = Op.getValueType();
00693       unsigned ShAmt = SA->getZExtValue();
00694       unsigned VTSize = VT.getSizeInBits();
00695       SDValue InOp = Op.getOperand(0);
00696 
00697       // If the shift count is an invalid immediate, don't do anything.
00698       if (ShAmt >= BitWidth)
00699         break;
00700 
00701       // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
00702       // single shift.  We can do this if the top bits (which are shifted out)
00703       // are never demanded.
00704       if (InOp.getOpcode() == ISD::SHL &&
00705           isa<ConstantSDNode>(InOp.getOperand(1))) {
00706         if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
00707           unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
00708           unsigned Opc = ISD::SRL;
00709           int Diff = ShAmt-C1;
00710           if (Diff < 0) {
00711             Diff = -Diff;
00712             Opc = ISD::SHL;
00713           }
00714 
00715           SDValue NewSA =
00716             TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
00717           return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
00718                                                    InOp.getOperand(0), NewSA));
00719         }
00720       }
00721 
00722       // Compute the new bits that are at the top now.
00723       if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
00724                                KnownZero, KnownOne, TLO, Depth+1))
00725         return true;
00726       assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
00727       KnownZero = KnownZero.lshr(ShAmt);
00728       KnownOne  = KnownOne.lshr(ShAmt);
00729 
00730       APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
00731       KnownZero |= HighBits;  // High bits known zero.
00732     }
00733     break;
00734   case ISD::SRA:
00735     // If this is an arithmetic shift right and only the low-bit is set, we can
00736     // always convert this into a logical shr, even if the shift amount is
00737     // variable.  The low bit of the shift cannot be an input sign bit unless
00738     // the shift amount is >= the size of the datatype, which is undefined.
00739     if (NewMask == 1)
00740       return TLO.CombineTo(Op,
00741                            TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
00742                                            Op.getOperand(0), Op.getOperand(1)));
00743 
00744     if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
00745       EVT VT = Op.getValueType();
00746       unsigned ShAmt = SA->getZExtValue();
00747 
00748       // If the shift count is an invalid immediate, don't do anything.
00749       if (ShAmt >= BitWidth)
00750         break;
00751 
00752       APInt InDemandedMask = (NewMask << ShAmt);
00753 
00754       // If any of the demanded bits are produced by the sign extension, we also
00755       // demand the input sign bit.
00756       APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
00757       if (HighBits.intersects(NewMask))
00758         InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
00759 
00760       if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
00761                                KnownZero, KnownOne, TLO, Depth+1))
00762         return true;
00763       assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
00764       KnownZero = KnownZero.lshr(ShAmt);
00765       KnownOne  = KnownOne.lshr(ShAmt);
00766 
00767       // Handle the sign bit, adjusted to where it is now in the mask.
00768       APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
00769 
00770       // If the input sign bit is known to be zero, or if none of the top bits
00771       // are demanded, turn this into an unsigned shift right.
00772       if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
00773         return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
00774                                                  Op.getOperand(0),
00775                                                  Op.getOperand(1)));
00776 
00777       int Log2 = NewMask.exactLogBase2();
00778       if (Log2 >= 0) {
00779         // The bit must come from the sign.
00780         SDValue NewSA =
00781           TLO.DAG.getConstant(BitWidth - 1 - Log2,
00782                               Op.getOperand(1).getValueType());
00783         return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
00784                                                  Op.getOperand(0), NewSA));
00785       }
00786 
00787       if (KnownOne.intersects(SignBit))
00788         // New bits are known one.
00789         KnownOne |= HighBits;
00790     }
00791     break;
00792   case ISD::SIGN_EXTEND_INREG: {
00793     EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
00794 
00795     APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
00796     // If we only care about the highest bit, don't bother shifting right.
00797     if (MsbMask == DemandedMask) {
00798       unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
00799       SDValue InOp = Op.getOperand(0);
00800 
00801       // Compute the correct shift amount type, which must be getShiftAmountTy
00802       // for scalar types after legalization.
00803       EVT ShiftAmtTy = Op.getValueType();
00804       if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
00805         ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
00806 
00807       SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
00808       return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
00809                                             Op.getValueType(), InOp, ShiftAmt));
00810     }
00811 
00812     // Sign extension.  Compute the demanded bits in the result that are not
00813     // present in the input.
00814     APInt NewBits =
00815       APInt::getHighBitsSet(BitWidth,
00816                             BitWidth - ExVT.getScalarType().getSizeInBits());
00817 
00818     // If none of the extended bits are demanded, eliminate the sextinreg.
00819     if ((NewBits & NewMask) == 0)
00820       return TLO.CombineTo(Op, Op.getOperand(0));
00821 
00822     APInt InSignBit =
00823       APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
00824     APInt InputDemandedBits =
00825       APInt::getLowBitsSet(BitWidth,
00826                            ExVT.getScalarType().getSizeInBits()) &
00827       NewMask;
00828 
00829     // Since the sign extended bits are demanded, we know that the sign
00830     // bit is demanded.
00831     InputDemandedBits |= InSignBit;
00832 
00833     if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
00834                              KnownZero, KnownOne, TLO, Depth+1))
00835       return true;
00836     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
00837 
00838     // If the sign bit of the input is known set or clear, then we know the
00839     // top bits of the result.
00840 
00841     // If the input sign bit is known zero, convert this into a zero extension.
00842     if (KnownZero.intersects(InSignBit))
00843       return TLO.CombineTo(Op,
00844                           TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
00845 
00846     if (KnownOne.intersects(InSignBit)) {    // Input sign bit known set
00847       KnownOne |= NewBits;
00848       KnownZero &= ~NewBits;
00849     } else {                       // Input sign bit unknown
00850       KnownZero &= ~NewBits;
00851       KnownOne &= ~NewBits;
00852     }
00853     break;
00854   }
00855   case ISD::BUILD_PAIR: {
00856     EVT HalfVT = Op.getOperand(0).getValueType();
00857     unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
00858 
00859     APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
00860     APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
00861 
00862     APInt KnownZeroLo, KnownOneLo;
00863     APInt KnownZeroHi, KnownOneHi;
00864 
00865     if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
00866                              KnownOneLo, TLO, Depth + 1))
00867       return true;
00868 
00869     if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
00870                              KnownOneHi, TLO, Depth + 1))
00871       return true;
00872 
00873     KnownZero = KnownZeroLo.zext(BitWidth) |
00874                 KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
00875 
00876     KnownOne = KnownOneLo.zext(BitWidth) |
00877                KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
00878     break;
00879   }
00880   case ISD::ZERO_EXTEND: {
00881     unsigned OperandBitWidth =
00882       Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
00883     APInt InMask = NewMask.trunc(OperandBitWidth);
00884 
00885     // If none of the top bits are demanded, convert this into an any_extend.
00886     APInt NewBits =
00887       APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
00888     if (!NewBits.intersects(NewMask))
00889       return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
00890                                                Op.getValueType(),
00891                                                Op.getOperand(0)));
00892 
00893     if (SimplifyDemandedBits(Op.getOperand(0), InMask,
00894                              KnownZero, KnownOne, TLO, Depth+1))
00895       return true;
00896     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
00897     KnownZero = KnownZero.zext(BitWidth);
00898     KnownOne = KnownOne.zext(BitWidth);
00899     KnownZero |= NewBits;
00900     break;
00901   }
00902   case ISD::SIGN_EXTEND: {
00903     EVT InVT = Op.getOperand(0).getValueType();
00904     unsigned InBits = InVT.getScalarType().getSizeInBits();
00905     APInt InMask    = APInt::getLowBitsSet(BitWidth, InBits);
00906     APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
00907     APInt NewBits   = ~InMask & NewMask;
00908 
00909     // If none of the top bits are demanded, convert this into an any_extend.
00910     if (NewBits == 0)
00911       return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
00912                                               Op.getValueType(),
00913                                               Op.getOperand(0)));
00914 
00915     // Since some of the sign extended bits are demanded, we know that the sign
00916     // bit is demanded.
00917     APInt InDemandedBits = InMask & NewMask;
00918     InDemandedBits |= InSignBit;
00919     InDemandedBits = InDemandedBits.trunc(InBits);
00920 
00921     if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
00922                              KnownOne, TLO, Depth+1))
00923       return true;
00924     KnownZero = KnownZero.zext(BitWidth);
00925     KnownOne = KnownOne.zext(BitWidth);
00926 
00927     // If the sign bit is known zero, convert this to a zero extend.
00928     if (KnownZero.intersects(InSignBit))
00929       return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
00930                                                Op.getValueType(),
00931                                                Op.getOperand(0)));
00932 
00933     // If the sign bit is known one, the top bits match.
00934     if (KnownOne.intersects(InSignBit)) {
00935       KnownOne |= NewBits;
00936       assert((KnownZero & NewBits) == 0);
00937     } else {   // Otherwise, top bits aren't known.
00938       assert((KnownOne & NewBits) == 0);
00939       assert((KnownZero & NewBits) == 0);
00940     }
00941     break;
00942   }
00943   case ISD::ANY_EXTEND: {
00944     unsigned OperandBitWidth =
00945       Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
00946     APInt InMask = NewMask.trunc(OperandBitWidth);
00947     if (SimplifyDemandedBits(Op.getOperand(0), InMask,
00948                              KnownZero, KnownOne, TLO, Depth+1))
00949       return true;
00950     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
00951     KnownZero = KnownZero.zext(BitWidth);
00952     KnownOne = KnownOne.zext(BitWidth);
00953     break;
00954   }
00955   case ISD::TRUNCATE: {
00956     // Simplify the input, using demanded bit information, and compute the known
00957     // zero/one bits live out.
00958     unsigned OperandBitWidth =
00959       Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
00960     APInt TruncMask = NewMask.zext(OperandBitWidth);
00961     if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
00962                              KnownZero, KnownOne, TLO, Depth+1))
00963       return true;
00964     KnownZero = KnownZero.trunc(BitWidth);
00965     KnownOne = KnownOne.trunc(BitWidth);
00966 
00967     // If the input is only used by this truncate, see if we can shrink it based
00968     // on the known demanded bits.
00969     if (Op.getOperand(0).getNode()->hasOneUse()) {
00970       SDValue In = Op.getOperand(0);
00971       switch (In.getOpcode()) {
00972       default: break;
00973       case ISD::SRL:
00974         // Shrink SRL by a constant if none of the high bits shifted in are
00975         // demanded.
00976         if (TLO.LegalTypes() &&
00977             !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
00978           // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
00979           // undesirable.
00980           break;
00981         ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
00982         if (!ShAmt)
00983           break;
00984         SDValue Shift = In.getOperand(1);
00985         if (TLO.LegalTypes()) {
00986           uint64_t ShVal = ShAmt->getZExtValue();
00987           Shift =
00988             TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
00989         }
00990 
00991         APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
00992                                                OperandBitWidth - BitWidth);
00993         HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
00994 
00995         if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
00996           // None of the shifted in bits are needed.  Add a truncate of the
00997           // shift input, then shift it.
00998           SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
00999                                              Op.getValueType(),
01000                                              In.getOperand(0));
01001           return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
01002                                                    Op.getValueType(),
01003                                                    NewTrunc,
01004                                                    Shift));
01005         }
01006         break;
01007       }
01008     }
01009 
01010     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
01011     break;
01012   }
01013   case ISD::AssertZext: {
01014     // AssertZext demands all of the high bits, plus any of the low bits
01015     // demanded by its users.
01016     EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
01017     APInt InMask = APInt::getLowBitsSet(BitWidth,
01018                                         VT.getSizeInBits());
01019     if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
01020                              KnownZero, KnownOne, TLO, Depth+1))
01021       return true;
01022     assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
01023 
01024     KnownZero |= ~InMask & NewMask;
01025     break;
01026   }
01027   case ISD::BITCAST:
01028     // If this is an FP->Int bitcast and if the sign bit is the only
01029     // thing demanded, turn this into a FGETSIGN.
01030     if (!TLO.LegalOperations() &&
01031         !Op.getValueType().isVector() &&
01032         !Op.getOperand(0).getValueType().isVector() &&
01033         NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
01034         Op.getOperand(0).getValueType().isFloatingPoint()) {
01035       bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
01036       bool i32Legal  = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
01037       if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
01038         EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
01039         // Make a FGETSIGN + SHL to move the sign bit into the appropriate
01040         // place.  We expect the SHL to be eliminated by other optimizations.
01041         SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
01042         unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
01043         if (!OpVTLegal && OpVTSizeInBits > 32)
01044           Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
01045         unsigned ShVal = Op.getValueType().getSizeInBits()-1;
01046         SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
01047         return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
01048                                                  Op.getValueType(),
01049                                                  Sign, ShAmt));
01050       }
01051     }
01052     break;
01053   case ISD::ADD:
01054   case ISD::MUL:
01055   case ISD::SUB: {
01056     // Add, Sub, and Mul don't demand any bits in positions beyond that
01057     // of the highest bit demanded of them.
01058     APInt LoMask = APInt::getLowBitsSet(BitWidth,
01059                                         BitWidth - NewMask.countLeadingZeros());
01060     if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
01061                              KnownOne2, TLO, Depth+1))
01062       return true;
01063     if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
01064                              KnownOne2, TLO, Depth+1))
01065       return true;
01066     // See if the operation should be performed at a smaller bit width.
01067     if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
01068       return true;
01069   }
01070   // FALL THROUGH
01071   default:
01072     // Just use computeKnownBits to compute output bits.
01073     TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
01074     break;
01075   }
01076 
01077   // If we know the value of all of the demanded bits, return this as a
01078   // constant.
01079   if ((NewMask & (KnownZero|KnownOne)) == NewMask)
01080     return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
01081 
01082   return false;
01083 }
01084 
01085 /// computeKnownBitsForTargetNode - Determine which of the bits specified
01086 /// in Mask are known to be either zero or one and return them in the
01087 /// KnownZero/KnownOne bitsets.
01088 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
01089                                                    APInt &KnownZero,
01090                                                    APInt &KnownOne,
01091                                                    const SelectionDAG &DAG,
01092                                                    unsigned Depth) const {
01093   assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
01094           Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
01095           Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
01096           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
01097          "Should use MaskedValueIsZero if you don't know whether Op"
01098          " is a target node!");
01099   KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
01100 }
01101 
01102 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
01103 /// targets that want to expose additional information about sign bits to the
01104 /// DAG Combiner.
01105 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
01106                                                          const SelectionDAG &,
01107                                                          unsigned Depth) const {
01108   assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
01109           Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
01110           Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
01111           Op.getOpcode() == ISD::INTRINSIC_VOID) &&
01112          "Should use ComputeNumSignBits if you don't know whether Op"
01113          " is a target node!");
01114   return 1;
01115 }
01116 
01117 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
01118 /// one bit set. This differs from computeKnownBits in that it doesn't need to
01119 /// determine which bit is set.
01120 ///
01121 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
01122   // A left-shift of a constant one will have exactly one bit set, because
01123   // shifting the bit off the end is undefined.
01124   if (Val.getOpcode() == ISD::SHL)
01125     if (ConstantSDNode *C =
01126          dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
01127       if (C->getAPIntValue() == 1)
01128         return true;
01129 
01130   // Similarly, a right-shift of a constant sign-bit will have exactly
01131   // one bit set.
01132   if (Val.getOpcode() == ISD::SRL)
01133     if (ConstantSDNode *C =
01134          dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
01135       if (C->getAPIntValue().isSignBit())
01136         return true;
01137 
01138   // More could be done here, though the above checks are enough
01139   // to handle some common cases.
01140 
01141   // Fall back to computeKnownBits to catch other known cases.
01142   EVT OpVT = Val.getValueType();
01143   unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
01144   APInt KnownZero, KnownOne;
01145   DAG.computeKnownBits(Val, KnownZero, KnownOne);
01146   return (KnownZero.countPopulation() == BitWidth - 1) &&
01147          (KnownOne.countPopulation() == 1);
01148 }
01149 
01150 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
01151   if (!N)
01152     return false;
01153 
01154   const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
01155   if (!CN) {
01156     const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
01157     if (!BV)
01158       return false;
01159 
01160     BitVector UndefElements;
01161     CN = BV->getConstantSplatNode(&UndefElements);
01162     // Only interested in constant splats, and we don't try to handle undef
01163     // elements in identifying boolean constants.
01164     if (!CN || UndefElements.none())
01165       return false;
01166   }
01167 
01168   switch (getBooleanContents(N->getValueType(0))) {
01169   case UndefinedBooleanContent:
01170     return CN->getAPIntValue()[0];
01171   case ZeroOrOneBooleanContent:
01172     return CN->isOne();
01173   case ZeroOrNegativeOneBooleanContent:
01174     return CN->isAllOnesValue();
01175   }
01176 
01177   llvm_unreachable("Invalid boolean contents");
01178 }
01179 
01180 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
01181   if (!N)
01182     return false;
01183 
01184   const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
01185   if (!CN) {
01186     const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
01187     if (!BV)
01188       return false;
01189 
01190     BitVector UndefElements;
01191     CN = BV->getConstantSplatNode(&UndefElements);
01192     // Only interested in constant splats, and we don't try to handle undef
01193     // elements in identifying boolean constants.
01194     if (!CN || UndefElements.none())
01195       return false;
01196   }
01197 
01198   if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
01199     return !CN->getAPIntValue()[0];
01200 
01201   return CN->isNullValue();
01202 }
01203 
01204 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
01205 /// and cc. If it is unable to simplify it, return a null SDValue.
01206 SDValue
01207 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
01208                               ISD::CondCode Cond, bool foldBooleans,
01209                               DAGCombinerInfo &DCI, SDLoc dl) const {
01210   SelectionDAG &DAG = DCI.DAG;
01211 
01212   // These setcc operations always fold.
01213   switch (Cond) {
01214   default: break;
01215   case ISD::SETFALSE:
01216   case ISD::SETFALSE2: return DAG.getConstant(0, VT);
01217   case ISD::SETTRUE:
01218   case ISD::SETTRUE2: {
01219     TargetLowering::BooleanContent Cnt =
01220         getBooleanContents(N0->getValueType(0));
01221     return DAG.getConstant(
01222         Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
01223   }
01224   }
01225 
01226   // Ensure that the constant occurs on the RHS, and fold constant
01227   // comparisons.
01228   ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
01229   if (isa<ConstantSDNode>(N0.getNode()) &&
01230       (DCI.isBeforeLegalizeOps() ||
01231        isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
01232     return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
01233 
01234   if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
01235     const APInt &C1 = N1C->getAPIntValue();
01236 
01237     // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
01238     // equality comparison, then we're just comparing whether X itself is
01239     // zero.
01240     if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
01241         N0.getOperand(0).getOpcode() == ISD::CTLZ &&
01242         N0.getOperand(1).getOpcode() == ISD::Constant) {
01243       const APInt &ShAmt
01244         = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
01245       if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
01246           ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
01247         if ((C1 == 0) == (Cond == ISD::SETEQ)) {
01248           // (srl (ctlz x), 5) == 0  -> X != 0
01249           // (srl (ctlz x), 5) != 1  -> X != 0
01250           Cond = ISD::SETNE;
01251         } else {
01252           // (srl (ctlz x), 5) != 0  -> X == 0
01253           // (srl (ctlz x), 5) == 1  -> X == 0
01254           Cond = ISD::SETEQ;
01255         }
01256         SDValue Zero = DAG.getConstant(0, N0.getValueType());
01257         return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
01258                             Zero, Cond);
01259       }
01260     }
01261 
01262     SDValue CTPOP = N0;
01263     // Look through truncs that don't change the value of a ctpop.
01264     if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
01265       CTPOP = N0.getOperand(0);
01266 
01267     if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
01268         (N0 == CTPOP || N0.getValueType().getSizeInBits() >
01269                         Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
01270       EVT CTVT = CTPOP.getValueType();
01271       SDValue CTOp = CTPOP.getOperand(0);
01272 
01273       // (ctpop x) u< 2 -> (x & x-1) == 0
01274       // (ctpop x) u> 1 -> (x & x-1) != 0
01275       if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
01276         SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
01277                                   DAG.getConstant(1, CTVT));
01278         SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
01279         ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
01280         return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
01281       }
01282 
01283       // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
01284     }
01285 
01286     // (zext x) == C --> x == (trunc C)
01287     if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
01288         (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
01289       unsigned MinBits = N0.getValueSizeInBits();
01290       SDValue PreZExt;
01291       if (N0->getOpcode() == ISD::ZERO_EXTEND) {
01292         // ZExt
01293         MinBits = N0->getOperand(0).getValueSizeInBits();
01294         PreZExt = N0->getOperand(0);
01295       } else if (N0->getOpcode() == ISD::AND) {
01296         // DAGCombine turns costly ZExts into ANDs
01297         if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
01298           if ((C->getAPIntValue()+1).isPowerOf2()) {
01299             MinBits = C->getAPIntValue().countTrailingOnes();
01300             PreZExt = N0->getOperand(0);
01301           }
01302       } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
01303         // ZEXTLOAD
01304         if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
01305           MinBits = LN0->getMemoryVT().getSizeInBits();
01306           PreZExt = N0;
01307         }
01308       }
01309 
01310       // Make sure we're not losing bits from the constant.
01311       if (MinBits > 0 &&
01312           MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
01313         EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
01314         if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
01315           // Will get folded away.
01316           SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
01317           SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
01318           return DAG.getSetCC(dl, VT, Trunc, C, Cond);
01319         }
01320       }
01321     }
01322 
01323     // If the LHS is '(and load, const)', the RHS is 0,
01324     // the test is for equality or unsigned, and all 1 bits of the const are
01325     // in the same partial word, see if we can shorten the load.
01326     if (DCI.isBeforeLegalize() &&
01327         !ISD::isSignedIntSetCC(Cond) &&
01328         N0.getOpcode() == ISD::AND && C1 == 0 &&
01329         N0.getNode()->hasOneUse() &&
01330         isa<LoadSDNode>(N0.getOperand(0)) &&
01331         N0.getOperand(0).getNode()->hasOneUse() &&
01332         isa<ConstantSDNode>(N0.getOperand(1))) {
01333       LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
01334       APInt bestMask;
01335       unsigned bestWidth = 0, bestOffset = 0;
01336       if (!Lod->isVolatile() && Lod->isUnindexed()) {
01337         unsigned origWidth = N0.getValueType().getSizeInBits();
01338         unsigned maskWidth = origWidth;
01339         // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
01340         // 8 bits, but have to be careful...
01341         if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
01342           origWidth = Lod->getMemoryVT().getSizeInBits();
01343         const APInt &Mask =
01344           cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
01345         for (unsigned width = origWidth / 2; width>=8; width /= 2) {
01346           APInt newMask = APInt::getLowBitsSet(maskWidth, width);
01347           for (unsigned offset=0; offset<origWidth/width; offset++) {
01348             if ((newMask & Mask) == Mask) {
01349               if (!getDataLayout()->isLittleEndian())
01350                 bestOffset = (origWidth/width - offset - 1) * (width/8);
01351               else
01352                 bestOffset = (uint64_t)offset * (width/8);
01353               bestMask = Mask.lshr(offset * (width/8) * 8);
01354               bestWidth = width;
01355               break;
01356             }
01357             newMask = newMask << width;
01358           }
01359         }
01360       }
01361       if (bestWidth) {
01362         EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
01363         if (newVT.isRound()) {
01364           EVT PtrType = Lod->getOperand(1).getValueType();
01365           SDValue Ptr = Lod->getBasePtr();
01366           if (bestOffset != 0)
01367             Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
01368                               DAG.getConstant(bestOffset, PtrType));
01369           unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
01370           SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
01371                                 Lod->getPointerInfo().getWithOffset(bestOffset),
01372                                         false, false, false, NewAlign);
01373           return DAG.getSetCC(dl, VT,
01374                               DAG.getNode(ISD::AND, dl, newVT, NewLoad,
01375                                       DAG.getConstant(bestMask.trunc(bestWidth),
01376                                                       newVT)),
01377                               DAG.getConstant(0LL, newVT), Cond);
01378         }
01379       }
01380     }
01381 
01382     // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
01383     if (N0.getOpcode() == ISD::ZERO_EXTEND) {
01384       unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
01385 
01386       // If the comparison constant has bits in the upper part, the
01387       // zero-extended value could never match.
01388       if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
01389                                               C1.getBitWidth() - InSize))) {
01390         switch (Cond) {
01391         case ISD::SETUGT:
01392         case ISD::SETUGE:
01393         case ISD::SETEQ: return DAG.getConstant(0, VT);
01394         case ISD::SETULT:
01395         case ISD::SETULE:
01396         case ISD::SETNE: return DAG.getConstant(1, VT);
01397         case ISD::SETGT:
01398         case ISD::SETGE:
01399           // True if the sign bit of C1 is set.
01400           return DAG.getConstant(C1.isNegative(), VT);
01401         case ISD::SETLT:
01402         case ISD::SETLE:
01403           // True if the sign bit of C1 isn't set.
01404           return DAG.getConstant(C1.isNonNegative(), VT);
01405         default:
01406           break;
01407         }
01408       }
01409 
01410       // Otherwise, we can perform the comparison with the low bits.
01411       switch (Cond) {
01412       case ISD::SETEQ:
01413       case ISD::SETNE:
01414       case ISD::SETUGT:
01415       case ISD::SETUGE:
01416       case ISD::SETULT:
01417       case ISD::SETULE: {
01418         EVT newVT = N0.getOperand(0).getValueType();
01419         if (DCI.isBeforeLegalizeOps() ||
01420             (isOperationLegal(ISD::SETCC, newVT) &&
01421              getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
01422           EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
01423           SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT);
01424 
01425           SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
01426                                           NewConst, Cond);
01427           return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
01428         }
01429         break;
01430       }
01431       default:
01432         break;   // todo, be more careful with signed comparisons
01433       }
01434     } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
01435                (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
01436       EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
01437       unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
01438       EVT ExtDstTy = N0.getValueType();
01439       unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
01440 
01441       // If the constant doesn't fit into the number of bits for the source of
01442       // the sign extension, it is impossible for both sides to be equal.
01443       if (C1.getMinSignedBits() > ExtSrcTyBits)
01444         return DAG.getConstant(Cond == ISD::SETNE, VT);
01445 
01446       SDValue ZextOp;
01447       EVT Op0Ty = N0.getOperand(0).getValueType();
01448       if (Op0Ty == ExtSrcTy) {
01449         ZextOp = N0.getOperand(0);
01450       } else {
01451         APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
01452         ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
01453                               DAG.getConstant(Imm, Op0Ty));
01454       }
01455       if (!DCI.isCalledByLegalizer())
01456         DCI.AddToWorklist(ZextOp.getNode());
01457       // Otherwise, make this a use of a zext.
01458       return DAG.getSetCC(dl, VT, ZextOp,
01459                           DAG.getConstant(C1 & APInt::getLowBitsSet(
01460                                                               ExtDstTyBits,
01461                                                               ExtSrcTyBits),
01462                                           ExtDstTy),
01463                           Cond);
01464     } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
01465                 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
01466       // SETCC (SETCC), [0|1], [EQ|NE]  -> SETCC
01467       if (N0.getOpcode() == ISD::SETCC &&
01468           isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
01469         bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
01470         if (TrueWhenTrue)
01471           return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
01472         // Invert the condition.
01473         ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
01474         CC = ISD::getSetCCInverse(CC,
01475                                   N0.getOperand(0).getValueType().isInteger());
01476         if (DCI.isBeforeLegalizeOps() ||
01477             isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
01478           return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
01479       }
01480 
01481       if ((N0.getOpcode() == ISD::XOR ||
01482            (N0.getOpcode() == ISD::AND &&
01483             N0.getOperand(0).getOpcode() == ISD::XOR &&
01484             N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
01485           isa<ConstantSDNode>(N0.getOperand(1)) &&
01486           cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
01487         // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We
01488         // can only do this if the top bits are known zero.
01489         unsigned BitWidth = N0.getValueSizeInBits();
01490         if (DAG.MaskedValueIsZero(N0,
01491                                   APInt::getHighBitsSet(BitWidth,
01492                                                         BitWidth-1))) {
01493           // Okay, get the un-inverted input value.
01494           SDValue Val;
01495           if (N0.getOpcode() == ISD::XOR)
01496             Val = N0.getOperand(0);
01497           else {
01498             assert(N0.getOpcode() == ISD::AND &&
01499                     N0.getOperand(0).getOpcode() == ISD::XOR);
01500             // ((X^1)&1)^1 -> X & 1
01501             Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
01502                               N0.getOperand(0).getOperand(0),
01503                               N0.getOperand(1));
01504           }
01505 
01506           return DAG.getSetCC(dl, VT, Val, N1,
01507                               Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
01508         }
01509       } else if (N1C->getAPIntValue() == 1 &&
01510                  (VT == MVT::i1 ||
01511                   getBooleanContents(N0->getValueType(0)) ==
01512                       ZeroOrOneBooleanContent)) {
01513         SDValue Op0 = N0;
01514         if (Op0.getOpcode() == ISD::TRUNCATE)
01515           Op0 = Op0.getOperand(0);
01516 
01517         if ((Op0.getOpcode() == ISD::XOR) &&
01518             Op0.getOperand(0).getOpcode() == ISD::SETCC &&
01519             Op0.getOperand(1).getOpcode() == ISD::SETCC) {
01520           // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
01521           Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
01522           return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
01523                               Cond);
01524         }
01525         if (Op0.getOpcode() == ISD::AND &&
01526             isa<ConstantSDNode>(Op0.getOperand(1)) &&
01527             cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
01528           // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
01529           if (Op0.getValueType().bitsGT(VT))
01530             Op0 = DAG.getNode(ISD::AND, dl, VT,
01531                           DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
01532                           DAG.getConstant(1, VT));
01533           else if (Op0.getValueType().bitsLT(VT))
01534             Op0 = DAG.getNode(ISD::AND, dl, VT,
01535                         DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
01536                         DAG.getConstant(1, VT));
01537 
01538           return DAG.getSetCC(dl, VT, Op0,
01539                               DAG.getConstant(0, Op0.getValueType()),
01540                               Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
01541         }
01542         if (Op0.getOpcode() == ISD::AssertZext &&
01543             cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
01544           return DAG.getSetCC(dl, VT, Op0,
01545                               DAG.getConstant(0, Op0.getValueType()),
01546                               Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
01547       }
01548     }
01549 
01550     APInt MinVal, MaxVal;
01551     unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
01552     if (ISD::isSignedIntSetCC(Cond)) {
01553       MinVal = APInt::getSignedMinValue(OperandBitSize);
01554       MaxVal = APInt::getSignedMaxValue(OperandBitSize);
01555     } else {
01556       MinVal = APInt::getMinValue(OperandBitSize);
01557       MaxVal = APInt::getMaxValue(OperandBitSize);
01558     }
01559 
01560     // Canonicalize GE/LE comparisons to use GT/LT comparisons.
01561     if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
01562       if (C1 == MinVal) return DAG.getConstant(1, VT);   // X >= MIN --> true
01563       // X >= C0 --> X > (C0 - 1)
01564       APInt C = C1 - 1;
01565       ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
01566       if ((DCI.isBeforeLegalizeOps() ||
01567            isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
01568           (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
01569                                 isLegalICmpImmediate(C.getSExtValue())))) {
01570         return DAG.getSetCC(dl, VT, N0,
01571                             DAG.getConstant(C, N1.getValueType()),
01572                             NewCC);
01573       }
01574     }
01575 
01576     if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
01577       if (C1 == MaxVal) return DAG.getConstant(1, VT);   // X <= MAX --> true
01578       // X <= C0 --> X < (C0 + 1)
01579       APInt C = C1 + 1;
01580       ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
01581       if ((DCI.isBeforeLegalizeOps() ||
01582            isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
01583           (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
01584                                 isLegalICmpImmediate(C.getSExtValue())))) {
01585         return DAG.getSetCC(dl, VT, N0,
01586                             DAG.getConstant(C, N1.getValueType()),
01587                             NewCC);
01588       }
01589     }
01590 
01591     if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
01592       return DAG.getConstant(0, VT);      // X < MIN --> false
01593     if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
01594       return DAG.getConstant(1, VT);      // X >= MIN --> true
01595     if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
01596       return DAG.getConstant(0, VT);      // X > MAX --> false
01597     if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
01598       return DAG.getConstant(1, VT);      // X <= MAX --> true
01599 
01600     // Canonicalize setgt X, Min --> setne X, Min
01601     if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
01602       return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
01603     // Canonicalize setlt X, Max --> setne X, Max
01604     if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
01605       return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
01606 
01607     // If we have setult X, 1, turn it into seteq X, 0
01608     if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
01609       return DAG.getSetCC(dl, VT, N0,
01610                           DAG.getConstant(MinVal, N0.getValueType()),
01611                           ISD::SETEQ);
01612     // If we have setugt X, Max-1, turn it into seteq X, Max
01613     if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
01614       return DAG.getSetCC(dl, VT, N0,
01615                           DAG.getConstant(MaxVal, N0.getValueType()),
01616                           ISD::SETEQ);
01617 
01618     // If we have "setcc X, C0", check to see if we can shrink the immediate
01619     // by changing cc.
01620 
01621     // SETUGT X, SINTMAX  -> SETLT X, 0
01622     if (Cond == ISD::SETUGT &&
01623         C1 == APInt::getSignedMaxValue(OperandBitSize))
01624       return DAG.getSetCC(dl, VT, N0,
01625                           DAG.getConstant(0, N1.getValueType()),
01626                           ISD::SETLT);
01627 
01628     // SETULT X, SINTMIN  -> SETGT X, -1
01629     if (Cond == ISD::SETULT &&
01630         C1 == APInt::getSignedMinValue(OperandBitSize)) {
01631       SDValue ConstMinusOne =
01632           DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
01633                           N1.getValueType());
01634       return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
01635     }
01636 
01637     // Fold bit comparisons when we can.
01638     if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
01639         (VT == N0.getValueType() ||
01640          (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
01641         N0.getOpcode() == ISD::AND)
01642       if (ConstantSDNode *AndRHS =
01643                   dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
01644         EVT ShiftTy = DCI.isBeforeLegalize() ?
01645           getPointerTy() : getShiftAmountTy(N0.getValueType());
01646         if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
01647           // Perform the xform if the AND RHS is a single bit.
01648           if (AndRHS->getAPIntValue().isPowerOf2()) {
01649             return DAG.getNode(ISD::TRUNCATE, dl, VT,
01650                               DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
01651                    DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
01652           }
01653         } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
01654           // (X & 8) == 8  -->  (X & 8) >> 3
01655           // Perform the xform if C1 is a single bit.
01656           if (C1.isPowerOf2()) {
01657             return DAG.getNode(ISD::TRUNCATE, dl, VT,
01658                                DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
01659                                       DAG.getConstant(C1.logBase2(), ShiftTy)));
01660           }
01661         }
01662       }
01663 
01664     if (C1.getMinSignedBits() <= 64 &&
01665         !isLegalICmpImmediate(C1.getSExtValue())) {
01666       // (X & -256) == 256 -> (X >> 8) == 1
01667       if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
01668           N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
01669         if (ConstantSDNode *AndRHS =
01670             dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
01671           const APInt &AndRHSC = AndRHS->getAPIntValue();
01672           if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
01673             unsigned ShiftBits = AndRHSC.countTrailingZeros();
01674             EVT ShiftTy = DCI.isBeforeLegalize() ?
01675               getPointerTy() : getShiftAmountTy(N0.getValueType());
01676             EVT CmpTy = N0.getValueType();
01677             SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
01678                                         DAG.getConstant(ShiftBits, ShiftTy));
01679             SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
01680             return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
01681           }
01682         }
01683       } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
01684                  Cond == ISD::SETULE || Cond == ISD::SETUGT) {
01685         bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
01686         // X <  0x100000000 -> (X >> 32) <  1
01687         // X >= 0x100000000 -> (X >> 32) >= 1
01688         // X <= 0x0ffffffff -> (X >> 32) <  1
01689         // X >  0x0ffffffff -> (X >> 32) >= 1
01690         unsigned ShiftBits;
01691         APInt NewC = C1;
01692         ISD::CondCode NewCond = Cond;
01693         if (AdjOne) {
01694           ShiftBits = C1.countTrailingOnes();
01695           NewC = NewC + 1;
01696           NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
01697         } else {
01698           ShiftBits = C1.countTrailingZeros();
01699         }
01700         NewC = NewC.lshr(ShiftBits);
01701         if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
01702           EVT ShiftTy = DCI.isBeforeLegalize() ?
01703             getPointerTy() : getShiftAmountTy(N0.getValueType());
01704           EVT CmpTy = N0.getValueType();
01705           SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
01706                                       DAG.getConstant(ShiftBits, ShiftTy));
01707           SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
01708           return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
01709         }
01710       }
01711     }
01712   }
01713 
01714   if (isa<ConstantFPSDNode>(N0.getNode())) {
01715     // Constant fold or commute setcc.
01716     SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
01717     if (O.getNode()) return O;
01718   } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
01719     // If the RHS of an FP comparison is a constant, simplify it away in
01720     // some cases.
01721     if (CFP->getValueAPF().isNaN()) {
01722       // If an operand is known to be a nan, we can fold it.
01723       switch (ISD::getUnorderedFlavor(Cond)) {
01724       default: llvm_unreachable("Unknown flavor!");
01725       case 0:  // Known false.
01726         return DAG.getConstant(0, VT);
01727       case 1:  // Known true.
01728         return DAG.getConstant(1, VT);
01729       case 2:  // Undefined.
01730         return DAG.getUNDEF(VT);
01731       }
01732     }
01733 
01734     // Otherwise, we know the RHS is not a NaN.  Simplify the node to drop the
01735     // constant if knowing that the operand is non-nan is enough.  We prefer to
01736     // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
01737     // materialize 0.0.
01738     if (Cond == ISD::SETO || Cond == ISD::SETUO)
01739       return DAG.getSetCC(dl, VT, N0, N0, Cond);
01740 
01741     // If the condition is not legal, see if we can find an equivalent one
01742     // which is legal.
01743     if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
01744       // If the comparison was an awkward floating-point == or != and one of
01745       // the comparison operands is infinity or negative infinity, convert the
01746       // condition to a less-awkward <= or >=.
01747       if (CFP->getValueAPF().isInfinity()) {
01748         if (CFP->getValueAPF().isNegative()) {
01749           if (Cond == ISD::SETOEQ &&
01750               isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
01751             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
01752           if (Cond == ISD::SETUEQ &&
01753               isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
01754             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
01755           if (Cond == ISD::SETUNE &&
01756               isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
01757             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
01758           if (Cond == ISD::SETONE &&
01759               isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
01760             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
01761         } else {
01762           if (Cond == ISD::SETOEQ &&
01763               isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
01764             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
01765           if (Cond == ISD::SETUEQ &&
01766               isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
01767             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
01768           if (Cond == ISD::SETUNE &&
01769               isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
01770             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
01771           if (Cond == ISD::SETONE &&
01772               isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
01773             return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
01774         }
01775       }
01776     }
01777   }
01778 
01779   if (N0 == N1) {
01780     // The sext(setcc()) => setcc() optimization relies on the appropriate
01781     // constant being emitted.
01782     uint64_t EqVal = 0;
01783     switch (getBooleanContents(N0.getValueType())) {
01784     case UndefinedBooleanContent:
01785     case ZeroOrOneBooleanContent:
01786       EqVal = ISD::isTrueWhenEqual(Cond);
01787       break;
01788     case ZeroOrNegativeOneBooleanContent:
01789       EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
01790       break;
01791     }
01792 
01793     // We can always fold X == X for integer setcc's.
01794     if (N0.getValueType().isInteger()) {
01795       return DAG.getConstant(EqVal, VT);
01796     }
01797     unsigned UOF = ISD::getUnorderedFlavor(Cond);
01798     if (UOF == 2)   // FP operators that are undefined on NaNs.
01799       return DAG.getConstant(EqVal, VT);
01800     if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
01801       return DAG.getConstant(EqVal, VT);
01802     // Otherwise, we can't fold it.  However, we can simplify it to SETUO/SETO
01803     // if it is not already.
01804     ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
01805     if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
01806           getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
01807       return DAG.getSetCC(dl, VT, N0, N1, NewCond);
01808   }
01809 
01810   if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
01811       N0.getValueType().isInteger()) {
01812     if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
01813         N0.getOpcode() == ISD::XOR) {
01814       // Simplify (X+Y) == (X+Z) -->  Y == Z
01815       if (N0.getOpcode() == N1.getOpcode()) {
01816         if (N0.getOperand(0) == N1.getOperand(0))
01817           return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
01818         if (N0.getOperand(1) == N1.getOperand(1))
01819           return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
01820         if (DAG.isCommutativeBinOp(N0.getOpcode())) {
01821           // If X op Y == Y op X, try other combinations.
01822           if (N0.getOperand(0) == N1.getOperand(1))
01823             return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
01824                                 Cond);
01825           if (N0.getOperand(1) == N1.getOperand(0))
01826             return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
01827                                 Cond);
01828         }
01829       }
01830 
01831       // If RHS is a legal immediate value for a compare instruction, we need
01832       // to be careful about increasing register pressure needlessly.
01833       bool LegalRHSImm = false;
01834 
01835       if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
01836         if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
01837           // Turn (X+C1) == C2 --> X == C2-C1
01838           if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
01839             return DAG.getSetCC(dl, VT, N0.getOperand(0),
01840                                 DAG.getConstant(RHSC->getAPIntValue()-
01841                                                 LHSR->getAPIntValue(),
01842                                 N0.getValueType()), Cond);
01843           }
01844 
01845           // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
01846           if (N0.getOpcode() == ISD::XOR)
01847             // If we know that all of the inverted bits are zero, don't bother
01848             // performing the inversion.
01849             if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
01850               return
01851                 DAG.getSetCC(dl, VT, N0.getOperand(0),
01852                              DAG.getConstant(LHSR->getAPIntValue() ^
01853                                                RHSC->getAPIntValue(),
01854                                              N0.getValueType()),
01855                              Cond);
01856         }
01857 
01858         // Turn (C1-X) == C2 --> X == C1-C2
01859         if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
01860           if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
01861             return
01862               DAG.getSetCC(dl, VT, N0.getOperand(1),
01863                            DAG.getConstant(SUBC->getAPIntValue() -
01864                                              RHSC->getAPIntValue(),
01865                                            N0.getValueType()),
01866                            Cond);
01867           }
01868         }
01869 
01870         // Could RHSC fold directly into a compare?
01871         if (RHSC->getValueType(0).getSizeInBits() <= 64)
01872           LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
01873       }
01874 
01875       // Simplify (X+Z) == X -->  Z == 0
01876       // Don't do this if X is an immediate that can fold into a cmp
01877       // instruction and X+Z has other uses. It could be an induction variable
01878       // chain, and the transform would increase register pressure.
01879       if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
01880         if (N0.getOperand(0) == N1)
01881           return DAG.getSetCC(dl, VT, N0.getOperand(1),
01882                               DAG.getConstant(0, N0.getValueType()), Cond);
01883         if (N0.getOperand(1) == N1) {
01884           if (DAG.isCommutativeBinOp(N0.getOpcode()))
01885             return DAG.getSetCC(dl, VT, N0.getOperand(0),
01886                                 DAG.getConstant(0, N0.getValueType()), Cond);
01887           if (N0.getNode()->hasOneUse()) {
01888             assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
01889             // (Z-X) == X  --> Z == X<<1
01890             SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
01891                        DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
01892             if (!DCI.isCalledByLegalizer())
01893               DCI.AddToWorklist(SH.getNode());
01894             return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
01895           }
01896         }
01897       }
01898     }
01899 
01900     if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
01901         N1.getOpcode() == ISD::XOR) {
01902       // Simplify  X == (X+Z) -->  Z == 0
01903       if (N1.getOperand(0) == N0)
01904         return DAG.getSetCC(dl, VT, N1.getOperand(1),
01905                         DAG.getConstant(0, N1.getValueType()), Cond);
01906       if (N1.getOperand(1) == N0) {
01907         if (DAG.isCommutativeBinOp(N1.getOpcode()))
01908           return DAG.getSetCC(dl, VT, N1.getOperand(0),
01909                           DAG.getConstant(0, N1.getValueType()), Cond);
01910         if (N1.getNode()->hasOneUse()) {
01911           assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
01912           // X == (Z-X)  --> X<<1 == Z
01913           SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
01914                        DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
01915           if (!DCI.isCalledByLegalizer())
01916             DCI.AddToWorklist(SH.getNode());
01917           return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
01918         }
01919       }
01920     }
01921 
01922     // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
01923     // Note that where y is variable and is known to have at most
01924     // one bit set (for example, if it is z&1) we cannot do this;
01925     // the expressions are not equivalent when y==0.
01926     if (N0.getOpcode() == ISD::AND)
01927       if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
01928         if (ValueHasExactlyOneBitSet(N1, DAG)) {
01929           Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
01930           if (DCI.isBeforeLegalizeOps() ||
01931               isCondCodeLegal(Cond, N0.getSimpleValueType())) {
01932             SDValue Zero = DAG.getConstant(0, N1.getValueType());
01933             return DAG.getSetCC(dl, VT, N0, Zero, Cond);
01934           }
01935         }
01936       }
01937     if (N1.getOpcode() == ISD::AND)
01938       if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
01939         if (ValueHasExactlyOneBitSet(N0, DAG)) {
01940           Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
01941           if (DCI.isBeforeLegalizeOps() ||
01942               isCondCodeLegal(Cond, N1.getSimpleValueType())) {
01943             SDValue Zero = DAG.getConstant(0, N0.getValueType());
01944             return DAG.getSetCC(dl, VT, N1, Zero, Cond);
01945           }
01946         }
01947       }
01948   }
01949 
01950   // Fold away ALL boolean setcc's.
01951   SDValue Temp;
01952   if (N0.getValueType() == MVT::i1 && foldBooleans) {
01953     switch (Cond) {
01954     default: llvm_unreachable("Unknown integer setcc!");
01955     case ISD::SETEQ:  // X == Y  -> ~(X^Y)
01956       Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
01957       N0 = DAG.getNOT(dl, Temp, MVT::i1);
01958       if (!DCI.isCalledByLegalizer())
01959         DCI.AddToWorklist(Temp.getNode());
01960       break;
01961     case ISD::SETNE:  // X != Y   -->  (X^Y)
01962       N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
01963       break;
01964     case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  ~X & Y
01965     case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  ~X & Y
01966       Temp = DAG.getNOT(dl, N0, MVT::i1);
01967       N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
01968       if (!DCI.isCalledByLegalizer())
01969         DCI.AddToWorklist(Temp.getNode());
01970       break;
01971     case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  ~Y & X
01972     case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  ~Y & X
01973       Temp = DAG.getNOT(dl, N1, MVT::i1);
01974       N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
01975       if (!DCI.isCalledByLegalizer())
01976         DCI.AddToWorklist(Temp.getNode());
01977       break;
01978     case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  ~X | Y
01979     case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  ~X | Y
01980       Temp = DAG.getNOT(dl, N0, MVT::i1);
01981       N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
01982       if (!DCI.isCalledByLegalizer())
01983         DCI.AddToWorklist(Temp.getNode());
01984       break;
01985     case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  ~Y | X
01986     case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  ~Y | X
01987       Temp = DAG.getNOT(dl, N1, MVT::i1);
01988       N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
01989       break;
01990     }
01991     if (VT != MVT::i1) {
01992       if (!DCI.isCalledByLegalizer())
01993         DCI.AddToWorklist(N0.getNode());
01994       // FIXME: If running after legalize, we probably can't do this.
01995       N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
01996     }
01997     return N0;
01998   }
01999 
02000   // Could not fold it.
02001   return SDValue();
02002 }
02003 
02004 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
02005 /// node is a GlobalAddress + offset.
02006 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
02007                                     int64_t &Offset) const {
02008   if (isa<GlobalAddressSDNode>(N)) {
02009     GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
02010     GA = GASD->getGlobal();
02011     Offset += GASD->getOffset();
02012     return true;
02013   }
02014 
02015   if (N->getOpcode() == ISD::ADD) {
02016     SDValue N1 = N->getOperand(0);
02017     SDValue N2 = N->getOperand(1);
02018     if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
02019       ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
02020       if (V) {
02021         Offset += V->getSExtValue();
02022         return true;
02023       }
02024     } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
02025       ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
02026       if (V) {
02027         Offset += V->getSExtValue();
02028         return true;
02029       }
02030     }
02031   }
02032 
02033   return false;
02034 }
02035 
02036 
02037 SDValue TargetLowering::
02038 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
02039   // Default implementation: no optimization.
02040   return SDValue();
02041 }
02042 
02043 //===----------------------------------------------------------------------===//
02044 //  Inline Assembler Implementation Methods
02045 //===----------------------------------------------------------------------===//
02046 
02047 
02048 TargetLowering::ConstraintType
02049 TargetLowering::getConstraintType(const std::string &Constraint) const {
02050   unsigned S = Constraint.size();
02051 
02052   if (S == 1) {
02053     switch (Constraint[0]) {
02054     default: break;
02055     case 'r': return C_RegisterClass;
02056     case 'm':    // memory
02057     case 'o':    // offsetable
02058     case 'V':    // not offsetable
02059       return C_Memory;
02060     case 'i':    // Simple Integer or Relocatable Constant
02061     case 'n':    // Simple Integer
02062     case 'E':    // Floating Point Constant
02063     case 'F':    // Floating Point Constant
02064     case 's':    // Relocatable Constant
02065     case 'p':    // Address.
02066     case 'X':    // Allow ANY value.
02067     case 'I':    // Target registers.
02068     case 'J':
02069     case 'K':
02070     case 'L':
02071     case 'M':
02072     case 'N':
02073     case 'O':
02074     case 'P':
02075     case '<':
02076     case '>':
02077       return C_Other;
02078     }
02079   }
02080 
02081   if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
02082     if (S == 8 && !Constraint.compare(1, 6, "memory", 6))  // "{memory}"
02083       return C_Memory;
02084     return C_Register;
02085   }
02086   return C_Unknown;
02087 }
02088 
02089 /// LowerXConstraint - try to replace an X constraint, which matches anything,
02090 /// with another that has more specific requirements based on the type of the
02091 /// corresponding operand.
02092 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
02093   if (ConstraintVT.isInteger())
02094     return "r";
02095   if (ConstraintVT.isFloatingPoint())
02096     return "f";      // works for many targets
02097   return nullptr;
02098 }
02099 
02100 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
02101 /// vector.  If it is invalid, don't add anything to Ops.
02102 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
02103                                                   std::string &Constraint,
02104                                                   std::vector<SDValue> &Ops,
02105                                                   SelectionDAG &DAG) const {
02106 
02107   if (Constraint.length() > 1) return;
02108 
02109   char ConstraintLetter = Constraint[0];
02110   switch (ConstraintLetter) {
02111   default: break;
02112   case 'X':     // Allows any operand; labels (basic block) use this.
02113     if (Op.getOpcode() == ISD::BasicBlock) {
02114       Ops.push_back(Op);
02115       return;
02116     }
02117     // fall through
02118   case 'i':    // Simple Integer or Relocatable Constant
02119   case 'n':    // Simple Integer
02120   case 's': {  // Relocatable Constant
02121     // These operands are interested in values of the form (GV+C), where C may
02122     // be folded in as an offset of GV, or it may be explicitly added.  Also, it
02123     // is possible and fine if either GV or C are missing.
02124     ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
02125     GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
02126 
02127     // If we have "(add GV, C)", pull out GV/C
02128     if (Op.getOpcode() == ISD::ADD) {
02129       C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
02130       GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
02131       if (!C || !GA) {
02132         C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
02133         GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
02134       }
02135       if (!C || !GA)
02136         C = nullptr, GA = nullptr;
02137     }
02138 
02139     // If we find a valid operand, map to the TargetXXX version so that the
02140     // value itself doesn't get selected.
02141     if (GA) {   // Either &GV   or   &GV+C
02142       if (ConstraintLetter != 'n') {
02143         int64_t Offs = GA->getOffset();
02144         if (C) Offs += C->getZExtValue();
02145         Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
02146                                                  C ? SDLoc(C) : SDLoc(),
02147                                                  Op.getValueType(), Offs));
02148         return;
02149       }
02150     }
02151     if (C) {   // just C, no GV.
02152       // Simple constants are not allowed for 's'.
02153       if (ConstraintLetter != 's') {
02154         // gcc prints these as sign extended.  Sign extend value to 64 bits
02155         // now; without this it would get ZExt'd later in
02156         // ScheduleDAGSDNodes::EmitNode, which is very generic.
02157         Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
02158                                             MVT::i64));
02159         return;
02160       }
02161     }
02162     break;
02163   }
02164   }
02165 }
02166 
02167 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
02168 getRegForInlineAsmConstraint(const std::string &Constraint,
02169                              MVT VT) const {
02170   if (Constraint.empty() || Constraint[0] != '{')
02171     return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
02172   assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
02173 
02174   // Remove the braces from around the name.
02175   StringRef RegName(Constraint.data()+1, Constraint.size()-2);
02176 
02177   std::pair<unsigned, const TargetRegisterClass*> R =
02178     std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
02179 
02180   // Figure out which register class contains this reg.
02181   const TargetRegisterInfo *RI =
02182       getTargetMachine().getSubtargetImpl()->getRegisterInfo();
02183   for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
02184        E = RI->regclass_end(); RCI != E; ++RCI) {
02185     const TargetRegisterClass *RC = *RCI;
02186 
02187     // If none of the value types for this register class are valid, we
02188     // can't use it.  For example, 64-bit reg classes on 32-bit targets.
02189     if (!isLegalRC(RC))
02190       continue;
02191 
02192     for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
02193          I != E; ++I) {
02194       if (RegName.equals_lower(RI->getName(*I))) {
02195         std::pair<unsigned, const TargetRegisterClass*> S =
02196           std::make_pair(*I, RC);
02197 
02198         // If this register class has the requested value type, return it,
02199         // otherwise keep searching and return the first class found
02200         // if no other is found which explicitly has the requested type.
02201         if (RC->hasType(VT))
02202           return S;
02203         else if (!R.second)
02204           R = S;
02205       }
02206     }
02207   }
02208 
02209   return R;
02210 }
02211 
02212 //===----------------------------------------------------------------------===//
02213 // Constraint Selection.
02214 
02215 /// isMatchingInputConstraint - Return true of this is an input operand that is
02216 /// a matching constraint like "4".
02217 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
02218   assert(!ConstraintCode.empty() && "No known constraint!");
02219   return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
02220 }
02221 
02222 /// getMatchedOperand - If this is an input matching constraint, this method
02223 /// returns the output operand it matches.
02224 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
02225   assert(!ConstraintCode.empty() && "No known constraint!");
02226   return atoi(ConstraintCode.c_str());
02227 }
02228 
02229 
02230 /// ParseConstraints - Split up the constraint string from the inline
02231 /// assembly value into the specific constraints and their prefixes,
02232 /// and also tie in the associated operand values.
02233 /// If this returns an empty vector, and if the constraint string itself
02234 /// isn't empty, there was an error parsing.
02235 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
02236     ImmutableCallSite CS) const {
02237   /// ConstraintOperands - Information about all of the constraints.
02238   AsmOperandInfoVector ConstraintOperands;
02239   const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
02240   unsigned maCount = 0; // Largest number of multiple alternative constraints.
02241 
02242   // Do a prepass over the constraints, canonicalizing them, and building up the
02243   // ConstraintOperands list.
02244   unsigned ArgNo = 0;   // ArgNo - The argument of the CallInst.
02245   unsigned ResNo = 0;   // ResNo - The result number of the next output.
02246 
02247   for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
02248     ConstraintOperands.emplace_back(std::move(CI));
02249     AsmOperandInfo &OpInfo = ConstraintOperands.back();
02250 
02251     // Update multiple alternative constraint count.
02252     if (OpInfo.multipleAlternatives.size() > maCount)
02253       maCount = OpInfo.multipleAlternatives.size();
02254 
02255     OpInfo.ConstraintVT = MVT::Other;
02256 
02257     // Compute the value type for each operand.
02258     switch (OpInfo.Type) {
02259     case InlineAsm::isOutput:
02260       // Indirect outputs just consume an argument.
02261       if (OpInfo.isIndirect) {
02262         OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
02263         break;
02264       }
02265 
02266       // The return value of the call is this value.  As such, there is no
02267       // corresponding argument.
02268       assert(!CS.getType()->isVoidTy() &&
02269              "Bad inline asm!");
02270       if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
02271         OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
02272       } else {
02273         assert(ResNo == 0 && "Asm only has one result!");
02274         OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
02275       }
02276       ++ResNo;
02277       break;
02278     case InlineAsm::isInput:
02279       OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
02280       break;
02281     case InlineAsm::isClobber:
02282       // Nothing to do.
02283       break;
02284     }
02285 
02286     if (OpInfo.CallOperandVal) {
02287       llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
02288       if (OpInfo.isIndirect) {
02289         llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
02290         if (!PtrTy)
02291           report_fatal_error("Indirect operand for inline asm not a pointer!");
02292         OpTy = PtrTy->getElementType();
02293       }
02294 
02295       // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
02296       if (StructType *STy = dyn_cast<StructType>(OpTy))
02297         if (STy->getNumElements() == 1)
02298           OpTy = STy->getElementType(0);
02299 
02300       // If OpTy is not a single value, it may be a struct/union that we
02301       // can tile with integers.
02302       if (!OpTy->isSingleValueType() && OpTy->isSized()) {
02303         unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
02304         switch (BitSize) {
02305         default: break;
02306         case 1:
02307         case 8:
02308         case 16:
02309         case 32:
02310         case 64:
02311         case 128:
02312           OpInfo.ConstraintVT =
02313             MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
02314           break;
02315         }
02316       } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
02317         unsigned PtrSize
02318           = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
02319         OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
02320       } else {
02321         OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
02322       }
02323     }
02324   }
02325 
02326   // If we have multiple alternative constraints, select the best alternative.
02327   if (ConstraintOperands.size()) {
02328     if (maCount) {
02329       unsigned bestMAIndex = 0;
02330       int bestWeight = -1;
02331       // weight:  -1 = invalid match, and 0 = so-so match to 5 = good match.
02332       int weight = -1;
02333       unsigned maIndex;
02334       // Compute the sums of the weights for each alternative, keeping track
02335       // of the best (highest weight) one so far.
02336       for (maIndex = 0; maIndex < maCount; ++maIndex) {
02337         int weightSum = 0;
02338         for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
02339             cIndex != eIndex; ++cIndex) {
02340           AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
02341           if (OpInfo.Type == InlineAsm::isClobber)
02342             continue;
02343 
02344           // If this is an output operand with a matching input operand,
02345           // look up the matching input. If their types mismatch, e.g. one
02346           // is an integer, the other is floating point, or their sizes are
02347           // different, flag it as an maCantMatch.
02348           if (OpInfo.hasMatchingInput()) {
02349             AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
02350             if (OpInfo.ConstraintVT != Input.ConstraintVT) {
02351               if ((OpInfo.ConstraintVT.isInteger() !=
02352                    Input.ConstraintVT.isInteger()) ||
02353                   (OpInfo.ConstraintVT.getSizeInBits() !=
02354                    Input.ConstraintVT.getSizeInBits())) {
02355                 weightSum = -1;  // Can't match.
02356                 break;
02357               }
02358             }
02359           }
02360           weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
02361           if (weight == -1) {
02362             weightSum = -1;
02363             break;
02364           }
02365           weightSum += weight;
02366         }
02367         // Update best.
02368         if (weightSum > bestWeight) {
02369           bestWeight = weightSum;
02370           bestMAIndex = maIndex;
02371         }
02372       }
02373 
02374       // Now select chosen alternative in each constraint.
02375       for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
02376           cIndex != eIndex; ++cIndex) {
02377         AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
02378         if (cInfo.Type == InlineAsm::isClobber)
02379           continue;
02380         cInfo.selectAlternative(bestMAIndex);
02381       }
02382     }
02383   }
02384 
02385   // Check and hook up tied operands, choose constraint code to use.
02386   for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
02387       cIndex != eIndex; ++cIndex) {
02388     AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
02389 
02390     // If this is an output operand with a matching input operand, look up the
02391     // matching input. If their types mismatch, e.g. one is an integer, the
02392     // other is floating point, or their sizes are different, flag it as an
02393     // error.
02394     if (OpInfo.hasMatchingInput()) {
02395       AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
02396 
02397       if (OpInfo.ConstraintVT != Input.ConstraintVT) {
02398         std::pair<unsigned, const TargetRegisterClass*> MatchRC =
02399           getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
02400                                        OpInfo.ConstraintVT);
02401         std::pair<unsigned, const TargetRegisterClass*> InputRC =
02402           getRegForInlineAsmConstraint(Input.ConstraintCode,
02403                                        Input.ConstraintVT);
02404         if ((OpInfo.ConstraintVT.isInteger() !=
02405              Input.ConstraintVT.isInteger()) ||
02406             (MatchRC.second != InputRC.second)) {
02407           report_fatal_error("Unsupported asm: input constraint"
02408                              " with a matching output constraint of"
02409                              " incompatible type!");
02410         }
02411       }
02412 
02413     }
02414   }
02415 
02416   return ConstraintOperands;
02417 }
02418 
02419 
02420 /// getConstraintGenerality - Return an integer indicating how general CT
02421 /// is.
02422 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
02423   switch (CT) {
02424   case TargetLowering::C_Other:
02425   case TargetLowering::C_Unknown:
02426     return 0;
02427   case TargetLowering::C_Register:
02428     return 1;
02429   case TargetLowering::C_RegisterClass:
02430     return 2;
02431   case TargetLowering::C_Memory:
02432     return 3;
02433   }
02434   llvm_unreachable("Invalid constraint type");
02435 }
02436 
02437 /// Examine constraint type and operand type and determine a weight value.
02438 /// This object must already have been set up with the operand type
02439 /// and the current alternative constraint selected.
02440 TargetLowering::ConstraintWeight
02441   TargetLowering::getMultipleConstraintMatchWeight(
02442     AsmOperandInfo &info, int maIndex) const {
02443   InlineAsm::ConstraintCodeVector *rCodes;
02444   if (maIndex >= (int)info.multipleAlternatives.size())
02445     rCodes = &info.Codes;
02446   else
02447     rCodes = &info.multipleAlternatives[maIndex].Codes;
02448   ConstraintWeight BestWeight = CW_Invalid;
02449 
02450   // Loop over the options, keeping track of the most general one.
02451   for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
02452     ConstraintWeight weight =
02453       getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
02454     if (weight > BestWeight)
02455       BestWeight = weight;
02456   }
02457 
02458   return BestWeight;
02459 }
02460 
02461 /// Examine constraint type and operand type and determine a weight value.
02462 /// This object must already have been set up with the operand type
02463 /// and the current alternative constraint selected.
02464 TargetLowering::ConstraintWeight
02465   TargetLowering::getSingleConstraintMatchWeight(
02466     AsmOperandInfo &info, const char *constraint) const {
02467   ConstraintWeight weight = CW_Invalid;
02468   Value *CallOperandVal = info.CallOperandVal;
02469     // If we don't have a value, we can't do a match,
02470     // but allow it at the lowest weight.
02471   if (!CallOperandVal)
02472     return CW_Default;
02473   // Look at the constraint type.
02474   switch (*constraint) {
02475     case 'i': // immediate integer.
02476     case 'n': // immediate integer with a known value.
02477       if (isa<ConstantInt>(CallOperandVal))
02478         weight = CW_Constant;
02479       break;
02480     case 's': // non-explicit intregal immediate.
02481       if (isa<GlobalValue>(CallOperandVal))
02482         weight = CW_Constant;
02483       break;
02484     case 'E': // immediate float if host format.
02485     case 'F': // immediate float.
02486       if (isa<ConstantFP>(CallOperandVal))
02487         weight = CW_Constant;
02488       break;
02489     case '<': // memory operand with autodecrement.
02490     case '>': // memory operand with autoincrement.
02491     case 'm': // memory operand.
02492     case 'o': // offsettable memory operand
02493     case 'V': // non-offsettable memory operand
02494       weight = CW_Memory;
02495       break;
02496     case 'r': // general register.
02497     case 'g': // general register, memory operand or immediate integer.
02498               // note: Clang converts "g" to "imr".
02499       if (CallOperandVal->getType()->isIntegerTy())
02500         weight = CW_Register;
02501       break;
02502     case 'X': // any operand.
02503     default:
02504       weight = CW_Default;
02505       break;
02506   }
02507   return weight;
02508 }
02509 
02510 /// ChooseConstraint - If there are multiple different constraints that we
02511 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
02512 /// This is somewhat tricky: constraints fall into four classes:
02513 ///    Other         -> immediates and magic values
02514 ///    Register      -> one specific register
02515 ///    RegisterClass -> a group of regs
02516 ///    Memory        -> memory
02517 /// Ideally, we would pick the most specific constraint possible: if we have
02518 /// something that fits into a register, we would pick it.  The problem here
02519 /// is that if we have something that could either be in a register or in
02520 /// memory that use of the register could cause selection of *other*
02521 /// operands to fail: they might only succeed if we pick memory.  Because of
02522 /// this the heuristic we use is:
02523 ///
02524 ///  1) If there is an 'other' constraint, and if the operand is valid for
02525 ///     that constraint, use it.  This makes us take advantage of 'i'
02526 ///     constraints when available.
02527 ///  2) Otherwise, pick the most general constraint present.  This prefers
02528 ///     'm' over 'r', for example.
02529 ///
02530 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
02531                              const TargetLowering &TLI,
02532                              SDValue Op, SelectionDAG *DAG) {
02533   assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
02534   unsigned BestIdx = 0;
02535   TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
02536   int BestGenerality = -1;
02537 
02538   // Loop over the options, keeping track of the most general one.
02539   for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
02540     TargetLowering::ConstraintType CType =
02541       TLI.getConstraintType(OpInfo.Codes[i]);
02542 
02543     // If this is an 'other' constraint, see if the operand is valid for it.
02544     // For example, on X86 we might have an 'rI' constraint.  If the operand
02545     // is an integer in the range [0..31] we want to use I (saving a load
02546     // of a register), otherwise we must use 'r'.
02547     if (CType == TargetLowering::C_Other && Op.getNode()) {
02548       assert(OpInfo.Codes[i].size() == 1 &&
02549              "Unhandled multi-letter 'other' constraint");
02550       std::vector<SDValue> ResultOps;
02551       TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
02552                                        ResultOps, *DAG);
02553       if (!ResultOps.empty()) {
02554         BestType = CType;
02555         BestIdx = i;
02556         break;
02557       }
02558     }
02559 
02560     // Things with matching constraints can only be registers, per gcc
02561     // documentation.  This mainly affects "g" constraints.
02562     if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
02563       continue;
02564 
02565     // This constraint letter is more general than the previous one, use it.
02566     int Generality = getConstraintGenerality(CType);
02567     if (Generality > BestGenerality) {
02568       BestType = CType;
02569       BestIdx = i;
02570       BestGenerality = Generality;
02571     }
02572   }
02573 
02574   OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
02575   OpInfo.ConstraintType = BestType;
02576 }
02577 
02578 /// ComputeConstraintToUse - Determines the constraint code and constraint
02579 /// type to use for the specific AsmOperandInfo, setting
02580 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
02581 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
02582                                             SDValue Op,
02583                                             SelectionDAG *DAG) const {
02584   assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
02585 
02586   // Single-letter constraints ('r') are very common.
02587   if (OpInfo.Codes.size() == 1) {
02588     OpInfo.ConstraintCode = OpInfo.Codes[0];
02589     OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
02590   } else {
02591     ChooseConstraint(OpInfo, *this, Op, DAG);
02592   }
02593 
02594   // 'X' matches anything.
02595   if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
02596     // Labels and constants are handled elsewhere ('X' is the only thing
02597     // that matches labels).  For Functions, the type here is the type of
02598     // the result, which is not what we want to look at; leave them alone.
02599     Value *v = OpInfo.CallOperandVal;
02600     if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
02601       OpInfo.CallOperandVal = v;
02602       return;
02603     }
02604 
02605     // Otherwise, try to resolve it to something we know about by looking at
02606     // the actual operand type.
02607     if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
02608       OpInfo.ConstraintCode = Repl;
02609       OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
02610     }
02611   }
02612 }
02613 
02614 /// \brief Given an exact SDIV by a constant, create a multiplication
02615 /// with the multiplicative inverse of the constant.
02616 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
02617                                        SelectionDAG &DAG) const {
02618   ConstantSDNode *C = cast<ConstantSDNode>(Op2);
02619   APInt d = C->getAPIntValue();
02620   assert(d != 0 && "Division by zero!");
02621 
02622   // Shift the value upfront if it is even, so the LSB is one.
02623   unsigned ShAmt = d.countTrailingZeros();
02624   if (ShAmt) {
02625     // TODO: For UDIV use SRL instead of SRA.
02626     SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
02627     Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
02628                       true);
02629     d = d.ashr(ShAmt);
02630   }
02631 
02632   // Calculate the multiplicative inverse, using Newton's method.
02633   APInt t, xn = d;
02634   while ((t = d*xn) != 1)
02635     xn *= APInt(d.getBitWidth(), 2) - t;
02636 
02637   Op2 = DAG.getConstant(xn, Op1.getValueType());
02638   return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
02639 }
02640 
02641 /// \brief Given an ISD::SDIV node expressing a divide by constant,
02642 /// return a DAG expression to select that will generate the same value by
02643 /// multiplying by a magic number.
02644 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
02645 SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
02646                                   SelectionDAG &DAG, bool IsAfterLegalization,
02647                                   std::vector<SDNode *> *Created) const {
02648   assert(Created && "No vector to hold sdiv ops.");
02649 
02650   EVT VT = N->getValueType(0);
02651   SDLoc dl(N);
02652 
02653   // Check to see if we can do this.
02654   // FIXME: We should be more aggressive here.
02655   if (!isTypeLegal(VT))
02656     return SDValue();
02657 
02658   APInt::ms magics = Divisor.magic();
02659 
02660   // Multiply the numerator (operand 0) by the magic value
02661   // FIXME: We should support doing a MUL in a wider type
02662   SDValue Q;
02663   if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
02664                             isOperationLegalOrCustom(ISD::MULHS, VT))
02665     Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
02666                     DAG.getConstant(magics.m, VT));
02667   else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
02668                                  isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
02669     Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
02670                               N->getOperand(0),
02671                               DAG.getConstant(magics.m, VT)).getNode(), 1);
02672   else
02673     return SDValue();       // No mulhs or equvialent
02674   // If d > 0 and m < 0, add the numerator
02675   if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
02676     Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
02677     Created->push_back(Q.getNode());
02678   }
02679   // If d < 0 and m > 0, subtract the numerator.
02680   if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
02681     Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
02682     Created->push_back(Q.getNode());
02683   }
02684   // Shift right algebraic if shift value is nonzero
02685   if (magics.s > 0) {
02686     Q = DAG.getNode(ISD::SRA, dl, VT, Q,
02687                  DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
02688     Created->push_back(Q.getNode());
02689   }
02690   // Extract the sign bit and add it to the quotient
02691   SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
02692                           DAG.getConstant(VT.getScalarSizeInBits() - 1,
02693                                           getShiftAmountTy(Q.getValueType())));
02694   Created->push_back(T.getNode());
02695   return DAG.getNode(ISD::ADD, dl, VT, Q, T);
02696 }
02697 
02698 /// \brief Given an ISD::UDIV node expressing a divide by constant,
02699 /// return a DAG expression to select that will generate the same value by
02700 /// multiplying by a magic number.
02701 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
02702 SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
02703                                   SelectionDAG &DAG, bool IsAfterLegalization,
02704                                   std::vector<SDNode *> *Created) const {
02705   assert(Created && "No vector to hold udiv ops.");
02706   
02707   EVT VT = N->getValueType(0);
02708   SDLoc dl(N);
02709 
02710   // Check to see if we can do this.
02711   // FIXME: We should be more aggressive here.
02712   if (!isTypeLegal(VT))
02713     return SDValue();
02714 
02715   // FIXME: We should use a narrower constant when the upper
02716   // bits are known to be zero.
02717   APInt::mu magics = Divisor.magicu();
02718 
02719   SDValue Q = N->getOperand(0);
02720 
02721   // If the divisor is even, we can avoid using the expensive fixup by shifting
02722   // the divided value upfront.
02723   if (magics.a != 0 && !Divisor[0]) {
02724     unsigned Shift = Divisor.countTrailingZeros();
02725     Q = DAG.getNode(ISD::SRL, dl, VT, Q,
02726                     DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
02727     Created->push_back(Q.getNode());
02728 
02729     // Get magic number for the shifted divisor.
02730     magics = Divisor.lshr(Shift).magicu(Shift);
02731     assert(magics.a == 0 && "Should use cheap fixup now");
02732   }
02733 
02734   // Multiply the numerator (operand 0) by the magic value
02735   // FIXME: We should support doing a MUL in a wider type
02736   if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
02737                             isOperationLegalOrCustom(ISD::MULHU, VT))
02738     Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
02739   else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
02740                                  isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
02741     Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
02742                             DAG.getConstant(magics.m, VT)).getNode(), 1);
02743   else
02744     return SDValue();       // No mulhu or equvialent
02745 
02746   Created->push_back(Q.getNode());
02747 
02748   if (magics.a == 0) {
02749     assert(magics.s < Divisor.getBitWidth() &&
02750            "We shouldn't generate an undefined shift!");
02751     return DAG.getNode(ISD::SRL, dl, VT, Q,
02752                  DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
02753   } else {
02754     SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
02755     Created->push_back(NPQ.getNode());
02756     NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
02757                       DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
02758     Created->push_back(NPQ.getNode());
02759     NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
02760     Created->push_back(NPQ.getNode());
02761     return DAG.getNode(ISD::SRL, dl, VT, NPQ,
02762              DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
02763   }
02764 }
02765 
02766 bool TargetLowering::
02767 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
02768   if (!isa<ConstantSDNode>(Op.getOperand(0))) {
02769     DAG.getContext()->emitError("argument to '__builtin_return_address' must "
02770                                 "be a constant integer");
02771     return true;
02772   }
02773 
02774   return false;
02775 }
02776 
02777 //===----------------------------------------------------------------------===//
02778 // Legalization Utilities
02779 //===----------------------------------------------------------------------===//
02780 
02781 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
02782                                SelectionDAG &DAG, SDValue LL, SDValue LH,
02783              SDValue RL, SDValue RH) const {
02784   EVT VT = N->getValueType(0);
02785   SDLoc dl(N);
02786 
02787   bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
02788   bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
02789   bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
02790   bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
02791   if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
02792     unsigned OuterBitSize = VT.getSizeInBits();
02793     unsigned InnerBitSize = HiLoVT.getSizeInBits();
02794     unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
02795     unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
02796 
02797     // LL, LH, RL, and RH must be either all NULL or all set to a value.
02798     assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
02799            (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
02800 
02801     if (!LL.getNode() && !RL.getNode() &&
02802         isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
02803       LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
02804       RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
02805     }
02806 
02807     if (!LL.getNode())
02808       return false;
02809 
02810     APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
02811     if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
02812         DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
02813       // The inputs are both zero-extended.
02814       if (HasUMUL_LOHI) {
02815         // We can emit a umul_lohi.
02816         Lo = DAG.getNode(ISD::UMUL_LOHI, dl,
02817                    DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
02818         Hi = SDValue(Lo.getNode(), 1);
02819         return true;
02820       }
02821       if (HasMULHU) {
02822         // We can emit a mulhu+mul.
02823         Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
02824         Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
02825         return true;
02826       }
02827     }
02828     if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
02829       // The input values are both sign-extended.
02830       if (HasSMUL_LOHI) {
02831         // We can emit a smul_lohi.
02832         Lo = DAG.getNode(ISD::SMUL_LOHI, dl,
02833                    DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
02834         Hi = SDValue(Lo.getNode(), 1);
02835         return true;
02836       }
02837       if (HasMULHS) {
02838         // We can emit a mulhs+mul.
02839         Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
02840         Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
02841         return true;
02842       }
02843     }
02844 
02845     if (!LH.getNode() && !RH.getNode() &&
02846         isOperationLegalOrCustom(ISD::SRL, VT) &&
02847         isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
02848       unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
02849       SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT));
02850       LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
02851       LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
02852       RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
02853       RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
02854     }
02855 
02856     if (!LH.getNode())
02857       return false;
02858 
02859     if (HasUMUL_LOHI) {
02860       // Lo,Hi = umul LHS, RHS.
02861       SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
02862                                      DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
02863       Lo = UMulLOHI;
02864       Hi = UMulLOHI.getValue(1);
02865       RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
02866       LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
02867       Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
02868       Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
02869       return true;
02870     }
02871     if (HasMULHU) {
02872       Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
02873       Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
02874       RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
02875       LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
02876       Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
02877       Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
02878       return true;
02879     }
02880   }
02881   return false;
02882 }
02883 
02884 bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
02885                                SelectionDAG &DAG) const {
02886   EVT VT = Node->getOperand(0).getValueType();
02887   EVT NVT = Node->getValueType(0);
02888   SDLoc dl(SDValue(Node, 0));
02889 
02890   // FIXME: Only f32 to i64 conversions are supported.
02891   if (VT != MVT::f32 || NVT != MVT::i64)
02892     return false;
02893 
02894   // Expand f32 -> i64 conversion
02895   // This algorithm comes from compiler-rt's implementation of fixsfdi:
02896   // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
02897   EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
02898                                 VT.getSizeInBits());
02899   SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
02900   SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
02901   SDValue Bias = DAG.getConstant(127, IntVT);
02902   SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
02903                                      IntVT);
02904   SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
02905   SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
02906 
02907   SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
02908 
02909   SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
02910       DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
02911       DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT)));
02912   SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
02913 
02914   SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
02915       DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
02916       DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT)));
02917   Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
02918 
02919   SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
02920       DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
02921       DAG.getConstant(0x00800000, IntVT));
02922 
02923   R = DAG.getZExtOrTrunc(R, dl, NVT);
02924 
02925 
02926   R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
02927      DAG.getNode(ISD::SHL, dl, NVT, R,
02928                  DAG.getZExtOrTrunc(
02929                     DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
02930                     dl, getShiftAmountTy(IntVT))),
02931      DAG.getNode(ISD::SRL, dl, NVT, R,
02932                  DAG.getZExtOrTrunc(
02933                     DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
02934                     dl, getShiftAmountTy(IntVT))),
02935      ISD::SETGT);
02936 
02937   SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
02938       DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
02939       Sign);
02940 
02941   Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
02942       DAG.getConstant(0, NVT), Ret, ISD::SETLT);
02943   return true;
02944 }