99void SelectionDAG::DAGNodeDeletedListener::anchor() {}
100void SelectionDAG::DAGNodeInsertedListener::anchor() {}
102#define DEBUG_TYPE "selectiondag"
106 cl::desc(
"Gang up loads and stores generated by inlining of memcpy"));
109 cl::desc(
"Number limit for gluing ld/st of memcpy."),
125 return getValueAPF().bitwiseIsEqual(V);
148 N->getValueType(0).getVectorElementType().getSizeInBits();
149 if (
auto *Op0 = dyn_cast<ConstantSDNode>(
N->getOperand(0))) {
150 SplatVal = Op0->getAPIntValue().
trunc(EltSize);
153 if (
auto *Op0 = dyn_cast<ConstantFPSDNode>(
N->getOperand(0))) {
154 SplatVal = Op0->getValueAPF().bitcastToAPInt().
trunc(EltSize);
159 auto *BV = dyn_cast<BuildVectorSDNode>(
N);
164 unsigned SplatBitSize;
166 unsigned EltSize =
N->getValueType(0).getVectorElementType().getSizeInBits();
171 const bool IsBigEndian =
false;
172 return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs,
173 EltSize, IsBigEndian) &&
174 EltSize == SplatBitSize;
183 N =
N->getOperand(0).getNode();
192 unsigned i = 0, e =
N->getNumOperands();
195 while (i != e &&
N->getOperand(i).isUndef())
199 if (i == e)
return false;
210 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
212 if (CN->getAPIntValue().countr_one() < EltSize)
215 if (CFPN->getValueAPF().bitcastToAPInt().countr_one() < EltSize)
223 for (++i; i != e; ++i)
224 if (
N->getOperand(i) != NotZero && !
N->getOperand(i).isUndef())
232 N =
N->getOperand(0).getNode();
241 bool IsAllUndef =
true;
254 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
256 if (CN->getAPIntValue().countr_zero() < EltSize)
259 if (CFPN->getValueAPF().bitcastToAPInt().countr_zero() < EltSize)
286 if (!isa<ConstantSDNode>(
Op))
299 if (!isa<ConstantFPSDNode>(
Op))
307 assert(
N->getValueType(0).isVector() &&
"Expected a vector!");
309 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
310 if (EltSize <= NewEltSize)
314 return (
N->getOperand(0).getValueType().getScalarSizeInBits() <=
319 return (
N->getOperand(0).getValueType().getScalarSizeInBits() <=
329 if (!isa<ConstantSDNode>(
Op))
332 APInt C =
Op->getAsAPIntVal().trunc(EltSize);
333 if (
Signed &&
C.trunc(NewEltSize).sext(EltSize) !=
C)
335 if (!
Signed &&
C.trunc(NewEltSize).zext(EltSize) !=
C)
346 if (
N->getNumOperands() == 0)
352 return N->getOpcode() ==
ISD::FREEZE &&
N->getOperand(0).isUndef();
355template <
typename ConstNodeType>
357 std::function<
bool(ConstNodeType *)>
Match,
360 if (
auto *
C = dyn_cast<ConstNodeType>(
Op))
368 EVT SVT =
Op.getValueType().getScalarType();
370 if (AllowUndefs &&
Op.getOperand(i).isUndef()) {
376 auto *Cst = dyn_cast<ConstNodeType>(
Op.getOperand(i));
377 if (!Cst || Cst->getValueType(0) != SVT || !
Match(Cst))
383template bool ISD::matchUnaryPredicateImpl<ConstantSDNode>(
385template bool ISD::matchUnaryPredicateImpl<ConstantFPSDNode>(
391 bool AllowUndefs,
bool AllowTypeMismatch) {
392 if (!AllowTypeMismatch &&
LHS.getValueType() !=
RHS.getValueType())
396 if (
auto *LHSCst = dyn_cast<ConstantSDNode>(
LHS))
397 if (
auto *RHSCst = dyn_cast<ConstantSDNode>(
RHS))
398 return Match(LHSCst, RHSCst);
401 if (
LHS.getOpcode() !=
RHS.getOpcode() ||
406 EVT SVT =
LHS.getValueType().getScalarType();
407 for (
unsigned i = 0, e =
LHS.getNumOperands(); i != e; ++i) {
410 bool LHSUndef = AllowUndefs && LHSOp.
isUndef();
411 bool RHSUndef = AllowUndefs && RHSOp.
isUndef();
412 auto *LHSCst = dyn_cast<ConstantSDNode>(LHSOp);
413 auto *RHSCst = dyn_cast<ConstantSDNode>(RHSOp);
414 if ((!LHSCst && !LHSUndef) || (!RHSCst && !RHSUndef))
416 if (!AllowTypeMismatch && (LHSOp.
getValueType() != SVT ||
419 if (!
Match(LHSCst, RHSCst))
426 switch (VecReduceOpcode) {
431 case ISD::VP_REDUCE_FADD:
432 case ISD::VP_REDUCE_SEQ_FADD:
436 case ISD::VP_REDUCE_FMUL:
437 case ISD::VP_REDUCE_SEQ_FMUL:
440 case ISD::VP_REDUCE_ADD:
443 case ISD::VP_REDUCE_MUL:
446 case ISD::VP_REDUCE_AND:
449 case ISD::VP_REDUCE_OR:
452 case ISD::VP_REDUCE_XOR:
455 case ISD::VP_REDUCE_SMAX:
458 case ISD::VP_REDUCE_SMIN:
461 case ISD::VP_REDUCE_UMAX:
464 case ISD::VP_REDUCE_UMIN:
467 case ISD::VP_REDUCE_FMAX:
470 case ISD::VP_REDUCE_FMIN:
483#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) \
486#include "llvm/IR/VPIntrinsics.def"
494#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
495#define VP_PROPERTY_BINARYOP return true;
496#define END_REGISTER_VP_SDNODE(VPSD) break;
497#include "llvm/IR/VPIntrinsics.def"
506#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
507#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true;
508#define END_REGISTER_VP_SDNODE(VPSD) break;
509#include "llvm/IR/VPIntrinsics.def"
519#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, ...) \
522#include "llvm/IR/VPIntrinsics.def"
531#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, EVLPOS) \
534#include "llvm/IR/VPIntrinsics.def"
544#define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) case ISD::VPOPC:
545#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) return ISD::SDOPC;
546#define END_REGISTER_VP_SDNODE(VPOPC) break;
547#include "llvm/IR/VPIntrinsics.def"
556#define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) break;
557#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) case ISD::SDOPC:
558#define END_REGISTER_VP_SDNODE(VPOPC) return ISD::VPOPC;
559#include "llvm/IR/VPIntrinsics.def"
606 bool isIntegerLike) {
631 bool IsInteger =
Type.isInteger();
636 unsigned Op = Op1 | Op2;
652 bool IsInteger =
Type.isInteger();
687 ID.AddPointer(VTList.
VTs);
693 for (
const auto &
Op : Ops) {
694 ID.AddPointer(
Op.getNode());
695 ID.AddInteger(
Op.getResNo());
702 for (
const auto &
Op : Ops) {
703 ID.AddPointer(
Op.getNode());
704 ID.AddInteger(
Op.getResNo());
717 switch (
N->getOpcode()) {
726 ID.AddPointer(
C->getConstantIntValue());
727 ID.AddBoolean(
C->isOpaque());
732 ID.AddPointer(cast<ConstantFPSDNode>(
N)->getConstantFPValue());
748 ID.AddInteger(cast<RegisterSDNode>(
N)->
getReg());
751 ID.AddPointer(cast<RegisterMaskSDNode>(
N)->getRegMask());
754 ID.AddPointer(cast<SrcValueSDNode>(
N)->getValue());
758 ID.AddInteger(cast<FrameIndexSDNode>(
N)->getIndex());
762 if (cast<LifetimeSDNode>(
N)->hasOffset()) {
763 ID.AddInteger(cast<LifetimeSDNode>(
N)->
getSize());
768 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getGuid());
769 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getIndex());
770 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getAttributes());
774 ID.AddInteger(cast<JumpTableSDNode>(
N)->getIndex());
775 ID.AddInteger(cast<JumpTableSDNode>(
N)->getTargetFlags());
780 ID.AddInteger(CP->getAlign().value());
781 ID.AddInteger(CP->getOffset());
782 if (CP->isMachineConstantPoolEntry())
783 CP->getMachineCPVal()->addSelectionDAGCSEId(
ID);
785 ID.AddPointer(CP->getConstVal());
786 ID.AddInteger(CP->getTargetFlags());
798 ID.AddInteger(LD->getMemoryVT().getRawBits());
799 ID.AddInteger(LD->getRawSubclassData());
800 ID.AddInteger(LD->getPointerInfo().getAddrSpace());
801 ID.AddInteger(LD->getMemOperand()->getFlags());
806 ID.AddInteger(ST->getMemoryVT().getRawBits());
807 ID.AddInteger(ST->getRawSubclassData());
808 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
809 ID.AddInteger(ST->getMemOperand()->getFlags());
820 case ISD::VP_STORE: {
828 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD: {
835 case ISD::EXPERIMENTAL_VP_STRIDED_STORE: {
842 case ISD::VP_GATHER: {
850 case ISD::VP_SCATTER: {
939 if (
auto *MN = dyn_cast<MemIntrinsicSDNode>(
N)) {
940 ID.AddInteger(MN->getRawSubclassData());
941 ID.AddInteger(MN->getPointerInfo().getAddrSpace());
942 ID.AddInteger(MN->getMemOperand()->getFlags());
943 ID.AddInteger(MN->getMemoryVT().getRawBits());
966 if (
N->getValueType(0) == MVT::Glue)
969 switch (
N->getOpcode()) {
977 for (
unsigned i = 1, e =
N->getNumValues(); i != e; ++i)
978 if (
N->getValueType(i) == MVT::Glue)
995 if (Node.use_empty())
1010 while (!DeadNodes.
empty()) {
1019 DUL->NodeDeleted(
N,
nullptr);
1022 RemoveNodeFromCSEMaps(
N);
1053 RemoveNodeFromCSEMaps(
N);
1057 DeleteNodeNotInCSEMaps(
N);
1060void SelectionDAG::DeleteNodeNotInCSEMaps(
SDNode *
N) {
1061 assert(
N->getIterator() != AllNodes.begin() &&
1062 "Cannot delete the entry node!");
1063 assert(
N->use_empty() &&
"Cannot delete a node that is not dead!");
1072 assert(!(V->isVariadic() && isParameter));
1074 ByvalParmDbgValues.push_back(V);
1076 DbgValues.push_back(V);
1077 for (
const SDNode *Node : V->getSDNodes())
1079 DbgValMap[Node].push_back(V);
1084 if (
I == DbgValMap.end())
1086 for (
auto &Val:
I->second)
1087 Val->setIsInvalidated();
1091void SelectionDAG::DeallocateNode(
SDNode *
N) {
1115 switch (
N->getOpcode()) {
1121 EVT VT =
N->getValueType(0);
1122 assert(
N->getNumValues() == 1 &&
"Too many results!");
1124 "Wrong return type!");
1125 assert(
N->getNumOperands() == 2 &&
"Wrong number of operands!");
1126 assert(
N->getOperand(0).getValueType() ==
N->getOperand(1).getValueType() &&
1127 "Mismatched operand types!");
1129 "Wrong operand type!");
1131 "Wrong return type size");
1135 assert(
N->getNumValues() == 1 &&
"Too many results!");
1136 assert(
N->getValueType(0).isVector() &&
"Wrong return type!");
1137 assert(
N->getNumOperands() ==
N->getValueType(0).getVectorNumElements() &&
1138 "Wrong number of operands!");
1139 EVT EltVT =
N->getValueType(0).getVectorElementType();
1141 assert((
Op.getValueType() == EltVT ||
1142 (EltVT.
isInteger() &&
Op.getValueType().isInteger() &&
1143 EltVT.
bitsLE(
Op.getValueType()))) &&
1144 "Wrong operand type!");
1145 assert(
Op.getValueType() ==
N->getOperand(0).getValueType() &&
1146 "Operands must all have the same type");
1158void SelectionDAG::InsertNode(
SDNode *
N) {
1159 AllNodes.push_back(
N);
1161 N->PersistentId = NextPersistentId++;
1164 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1165 DUL->NodeInserted(
N);
1172bool SelectionDAG::RemoveNodeFromCSEMaps(
SDNode *
N) {
1173 bool Erased =
false;
1174 switch (
N->getOpcode()) {
1177 assert(CondCodeNodes[cast<CondCodeSDNode>(
N)->
get()] &&
1178 "Cond code doesn't exist!");
1179 Erased = CondCodeNodes[cast<CondCodeSDNode>(
N)->get()] !=
nullptr;
1180 CondCodeNodes[cast<CondCodeSDNode>(
N)->get()] =
nullptr;
1183 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(
N)->getSymbol());
1187 Erased = TargetExternalSymbols.erase(std::pair<std::string, unsigned>(
1192 auto *MCSN = cast<MCSymbolSDNode>(
N);
1193 Erased = MCSymbols.erase(MCSN->getMCSymbol());
1197 EVT VT = cast<VTSDNode>(
N)->getVT();
1199 Erased = ExtendedValueTypeNodes.erase(VT);
1210 Erased = CSEMap.RemoveNode(
N);
1217 if (!Erased &&
N->getValueType(
N->getNumValues()-1) != MVT::Glue &&
1232SelectionDAG::AddModifiedNodeToCSEMaps(
SDNode *
N) {
1236 SDNode *Existing = CSEMap.GetOrInsertNode(
N);
1237 if (Existing !=
N) {
1244 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1245 DUL->NodeDeleted(
N, Existing);
1246 DeleteNodeNotInCSEMaps(
N);
1252 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1253 DUL->NodeUpdated(
N);
1271 Node->intersectFlagsWith(
N->getFlags());
1291 Node->intersectFlagsWith(
N->getFlags());
1309 Node->intersectFlagsWith(
N->getFlags());
1322 : TM(tm), OptLevel(OL), EntryNode(ISD::EntryToken, 0,
DebugLoc(),
1325 InsertNode(&EntryNode);
1336 SDAGISelPass = PassPtr;
1340 LibInfo = LibraryInfo;
1345 FnVarLocs = VarLocs;
1349 assert(!UpdateListeners &&
"Dangling registered DAGUpdateListeners");
1351 OperandRecycler.clear(OperandAllocator);
1360void SelectionDAG::allnodes_clear() {
1361 assert(&*AllNodes.begin() == &EntryNode);
1362 AllNodes.remove(AllNodes.begin());
1363 while (!AllNodes.empty())
1364 DeallocateNode(&AllNodes.front());
1366 NextPersistentId = 0;
1372 SDNode *
N = CSEMap.FindNodeOrInsertPos(
ID, InsertPos);
1374 switch (
N->getOpcode()) {
1379 "debug location. Use another overload.");
1386 const SDLoc &
DL,
void *&InsertPos) {
1387 SDNode *
N = CSEMap.FindNodeOrInsertPos(
ID, InsertPos);
1389 switch (
N->getOpcode()) {
1395 if (
N->getDebugLoc() !=
DL.getDebugLoc())
1402 if (
DL.getIROrder() &&
DL.getIROrder() <
N->getIROrder())
1403 N->setDebugLoc(
DL.getDebugLoc());
1412 OperandRecycler.clear(OperandAllocator);
1413 OperandAllocator.
Reset();
1416 ExtendedValueTypeNodes.clear();
1417 ExternalSymbols.clear();
1418 TargetExternalSymbols.clear();
1421 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(),
1423 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(),
1424 static_cast<SDNode*
>(
nullptr));
1426 EntryNode.UseList =
nullptr;
1427 InsertNode(&EntryNode);
1433 return VT.
bitsGT(
Op.getValueType())
1439std::pair<SDValue, SDValue>
1443 "Strict no-op FP extend/round not allowed.");
1450 return std::pair<SDValue, SDValue>(Res,
SDValue(Res.
getNode(), 1));
1454 return VT.
bitsGT(
Op.getValueType()) ?
1460 return VT.
bitsGT(
Op.getValueType()) ?
1466 return VT.
bitsGT(
Op.getValueType()) ?
1474 auto Type =
Op.getValueType();
1478 auto Size =
Op.getValueSizeInBits();
1489 auto Type =
Op.getValueType();
1493 auto Size =
Op.getValueSizeInBits();
1504 auto Type =
Op.getValueType();
1508 auto Size =
Op.getValueSizeInBits();
1526 EVT OpVT =
Op.getValueType();
1528 "Cannot getZeroExtendInReg FP types");
1530 "getZeroExtendInReg type should be vector iff the operand "
1534 "Vector element counts must match in getZeroExtendInReg");
1572 return getNode(ISD::VP_XOR,
DL, VT, Val, TrueValue, Mask, EVL);
1583 return getNode(ISD::VP_ZERO_EXTEND,
DL, VT,
Op, Mask, EVL);
1585 return getNode(ISD::VP_TRUNCATE,
DL, VT,
Op, Mask, EVL);
1605 bool isT,
bool isO) {
1609 "getConstant with a uint64_t value that doesn't fit in the type!");
1614 bool isT,
bool isO) {
1615 return getConstant(*ConstantInt::get(*Context, Val),
DL, VT, isT, isO);
1619 EVT VT,
bool isT,
bool isO) {
1637 Elt = ConstantInt::get(*
getContext(), NewVal);
1656 "Can only handle an even split!");
1660 for (
unsigned i = 0; i != Parts; ++i)
1662 NewVal.
extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits),
DL,
1663 ViaEltVT, isT, isO));
1668 unsigned ViaVecNumElts = VT.
getSizeInBits() / ViaEltSizeInBits;
1679 NewVal.
extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits),
DL,
1680 ViaEltVT, isT, isO));
1685 std::reverse(EltParts.
begin(), EltParts.
end());
1704 "APInt size does not match type size!");
1712 if ((
N = FindNodeOrInsertPos(
ID,
DL, IP)))
1717 N = newSDNode<ConstantSDNode>(isT, isO, Elt, EltVT);
1718 CSEMap.InsertNode(
N, IP);
1735 const SDLoc &
DL,
bool LegalTypes) {
1742 const SDLoc &
DL,
bool LegalTypes) {
1758 EVT VT,
bool isTarget) {
1772 if ((
N = FindNodeOrInsertPos(
ID,
DL, IP)))
1777 N = newSDNode<ConstantFPSDNode>(isTarget, &V, EltVT);
1778 CSEMap.InsertNode(
N, IP);
1792 if (EltVT == MVT::f32)
1794 if (EltVT == MVT::f64)
1796 if (EltVT == MVT::f80 || EltVT == MVT::f128 || EltVT == MVT::ppcf128 ||
1797 EltVT == MVT::f16 || EltVT == MVT::bf16) {
1808 EVT VT, int64_t
Offset,
bool isTargetGA,
1809 unsigned TargetFlags) {
1810 assert((TargetFlags == 0 || isTargetGA) &&
1811 "Cannot set target flags on target-independent globals");
1828 ID.AddInteger(TargetFlags);
1830 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
1833 auto *
N = newSDNode<GlobalAddressSDNode>(
1834 Opc,
DL.getIROrder(),
DL.getDebugLoc(), GV, VT,
Offset, TargetFlags);
1835 CSEMap.InsertNode(
N, IP);
1846 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1849 auto *
N = newSDNode<FrameIndexSDNode>(FI, VT, isTarget);
1850 CSEMap.InsertNode(
N, IP);
1856 unsigned TargetFlags) {
1857 assert((TargetFlags == 0 || isTarget) &&
1858 "Cannot set target flags on target-independent jump tables");
1863 ID.AddInteger(TargetFlags);
1865 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1868 auto *
N = newSDNode<JumpTableSDNode>(JTI, VT, isTarget, TargetFlags);
1869 CSEMap.InsertNode(
N, IP);
1883 bool isTarget,
unsigned TargetFlags) {
1884 assert((TargetFlags == 0 || isTarget) &&
1885 "Cannot set target flags on target-independent globals");
1893 ID.AddInteger(Alignment->value());
1896 ID.AddInteger(TargetFlags);
1898 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1901 auto *
N = newSDNode<ConstantPoolSDNode>(isTarget,
C, VT,
Offset, *Alignment,
1903 CSEMap.InsertNode(
N, IP);
1912 bool isTarget,
unsigned TargetFlags) {
1913 assert((TargetFlags == 0 || isTarget) &&
1914 "Cannot set target flags on target-independent globals");
1920 ID.AddInteger(Alignment->value());
1922 C->addSelectionDAGCSEId(
ID);
1923 ID.AddInteger(TargetFlags);
1925 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1928 auto *
N = newSDNode<ConstantPoolSDNode>(isTarget,
C, VT,
Offset, *Alignment,
1930 CSEMap.InsertNode(
N, IP);
1940 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1943 auto *
N = newSDNode<BasicBlockSDNode>(
MBB);
1944 CSEMap.InsertNode(
N, IP);
1951 ValueTypeNodes.size())
1958 N = newSDNode<VTSDNode>(VT);
1966 N = newSDNode<ExternalSymbolSDNode>(
false,
Sym, 0, VT);
1975 N = newSDNode<MCSymbolSDNode>(
Sym, VT);
1981 unsigned TargetFlags) {
1983 TargetExternalSymbols[std::pair<std::string, unsigned>(
Sym, TargetFlags)];
1985 N = newSDNode<ExternalSymbolSDNode>(
true,
Sym, TargetFlags, VT);
1991 if ((
unsigned)
Cond >= CondCodeNodes.size())
1992 CondCodeNodes.resize(
Cond+1);
1994 if (!CondCodeNodes[
Cond]) {
1995 auto *
N = newSDNode<CondCodeSDNode>(
Cond);
1996 CondCodeNodes[
Cond] =
N;
2006 "APInt size does not match type size!");
2024 if (EC.isScalable())
2037 const APInt &StepVal) {
2061 "Must have the same number of vector elements as mask elements!");
2063 "Invalid VECTOR_SHUFFLE");
2071 int NElts = Mask.size();
2073 [&](
int M) {
return M < (NElts * 2) && M >= -1; }) &&
2074 "Index out of range");
2082 for (
int i = 0; i != NElts; ++i)
2083 if (MaskVec[i] >= NElts) MaskVec[i] -= NElts;
2099 for (
int i = 0; i < NElts; ++i) {
2100 if (MaskVec[i] <
Offset || MaskVec[i] >= (
Offset + NElts))
2104 if (UndefElements[MaskVec[i] -
Offset]) {
2110 if (!UndefElements[i])
2114 if (
auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
2115 BlendSplat(N1BV, 0);
2116 if (
auto *N2BV = dyn_cast<BuildVectorSDNode>(N2))
2117 BlendSplat(N2BV, NElts);
2122 bool AllLHS =
true, AllRHS =
true;
2124 for (
int i = 0; i != NElts; ++i) {
2125 if (MaskVec[i] >= NElts) {
2130 }
else if (MaskVec[i] >= 0) {
2134 if (AllLHS && AllRHS)
2136 if (AllLHS && !N2Undef)
2149 bool Identity =
true, AllSame =
true;
2150 for (
int i = 0; i != NElts; ++i) {
2151 if (MaskVec[i] >= 0 && MaskVec[i] != i) Identity =
false;
2152 if (MaskVec[i] != MaskVec[0]) AllSame =
false;
2154 if (Identity && NElts)
2164 V = V->getOperand(0);
2167 if (
auto *BV = dyn_cast<BuildVectorSDNode>(V)) {
2187 if (AllSame && SameNumElts) {
2188 EVT BuildVT = BV->getValueType(0);
2204 for (
int i = 0; i != NElts; ++i)
2205 ID.AddInteger(MaskVec[i]);
2208 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
2214 int *MaskAlloc = OperandAllocator.
Allocate<
int>(NElts);
2217 auto *
N = newSDNode<ShuffleVectorSDNode>(VT, dl.
getIROrder(),
2219 createOperands(
N, Ops);
2221 CSEMap.InsertNode(
N, IP);
2241 ID.AddInteger(RegNo);
2243 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2246 auto *
N = newSDNode<RegisterSDNode>(RegNo, VT);
2248 CSEMap.InsertNode(
N, IP);
2256 ID.AddPointer(RegMask);
2258 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2261 auto *
N = newSDNode<RegisterMaskSDNode>(RegMask);
2262 CSEMap.InsertNode(
N, IP);
2277 ID.AddPointer(Label);
2279 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2284 createOperands(
N, Ops);
2286 CSEMap.InsertNode(
N, IP);
2292 int64_t
Offset,
bool isTarget,
2293 unsigned TargetFlags) {
2300 ID.AddInteger(TargetFlags);
2302 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2305 auto *
N = newSDNode<BlockAddressSDNode>(Opc, VT, BA,
Offset, TargetFlags);
2306 CSEMap.InsertNode(
N, IP);
2317 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2320 auto *
N = newSDNode<SrcValueSDNode>(V);
2321 CSEMap.InsertNode(
N, IP);
2332 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2335 auto *
N = newSDNode<MDNodeSDNode>(MD);
2336 CSEMap.InsertNode(
N, IP);
2342 if (VT == V.getValueType())
2349 unsigned SrcAS,
unsigned DestAS) {
2353 ID.AddInteger(SrcAS);
2354 ID.AddInteger(DestAS);
2357 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
2362 createOperands(
N, Ops);
2364 CSEMap.InsertNode(
N, IP);
2376 EVT OpTy =
Op.getValueType();
2378 if (OpTy == ShTy || OpTy.
isVector())
return Op;
2386 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2387 EVT VT = Node->getValueType(0);
2388 SDValue Tmp1 = Node->getOperand(0);
2389 SDValue Tmp2 = Node->getOperand(1);
2390 const MaybeAlign MA(Node->getConstantOperandVal(3));
2422 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2423 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2434 Align RedAlign = UseABI ?
DL.getABITypeAlign(Ty) :
DL.getPrefTypeAlign(Ty);
2444 if (RedAlign > StackAlign) {
2447 unsigned NumIntermediates;
2449 NumIntermediates, RegisterVT);
2451 Align RedAlign2 = UseABI ?
DL.getABITypeAlign(Ty) :
DL.getPrefTypeAlign(Ty);
2452 if (RedAlign2 < RedAlign)
2453 RedAlign = RedAlign2;
2468 false,
nullptr, StackID);
2483 "Don't know how to choose the maximum size when creating a stack "
2492 Align Align = std::max(
DL.getPrefTypeAlign(Ty1),
DL.getPrefTypeAlign(Ty2));
2500 auto GetUndefBooleanConstant = [&]() {
2539 return GetUndefBooleanConstant();
2544 return GetUndefBooleanConstant();
2553 const APInt &C2 = N2C->getAPIntValue();
2555 const APInt &C1 = N1C->getAPIntValue();
2562 auto *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2563 auto *N2CFP = dyn_cast<ConstantFPSDNode>(N2);
2565 if (N1CFP && N2CFP) {
2570 return GetUndefBooleanConstant();
2575 return GetUndefBooleanConstant();
2581 return GetUndefBooleanConstant();
2586 return GetUndefBooleanConstant();
2591 return GetUndefBooleanConstant();
2597 return GetUndefBooleanConstant();
2626 return getSetCC(dl, VT, N2, N1, SwappedCond);
2627 }
else if ((N2CFP && N2CFP->getValueAPF().isNaN()) ||
2642 return GetUndefBooleanConstant();
2653 unsigned BitWidth =
Op.getScalarValueSizeInBits();
2661 unsigned Depth)
const {
2669 const APInt &DemandedElts,
2670 unsigned Depth)
const {
2677 unsigned Depth )
const {
2683 unsigned Depth)
const {
2688 const APInt &DemandedElts,
2689 unsigned Depth)
const {
2690 EVT VT =
Op.getValueType();
2697 for (
unsigned EltIdx = 0; EltIdx != NumElts; ++EltIdx) {
2698 if (!DemandedElts[EltIdx])
2702 KnownZeroElements.
setBit(EltIdx);
2704 return KnownZeroElements;
2714 unsigned Opcode = V.getOpcode();
2715 EVT VT = V.getValueType();
2718 "scalable demanded bits are ignored");
2730 UndefElts = V.getOperand(0).isUndef()
2739 APInt UndefLHS, UndefRHS;
2744 UndefElts = UndefLHS | UndefRHS;
2774 for (
unsigned i = 0; i != NumElts; ++i) {
2780 if (!DemandedElts[i])
2782 if (Scl && Scl !=
Op)
2792 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(V)->getMask();
2793 for (
int i = 0; i != (int)NumElts; ++i) {
2799 if (!DemandedElts[i])
2801 if (M < (
int)NumElts)
2804 DemandedRHS.
setBit(M - NumElts);
2816 auto CheckSplatSrc = [&](
SDValue Src,
const APInt &SrcElts) {
2818 return (SrcElts.popcount() == 1) ||
2820 (SrcElts & SrcUndefs).
isZero());
2822 if (!DemandedLHS.
isZero())
2823 return CheckSplatSrc(V.getOperand(0), DemandedLHS);
2824 return CheckSplatSrc(V.getOperand(1), DemandedRHS);
2828 SDValue Src = V.getOperand(0);
2830 if (Src.getValueType().isScalableVector())
2833 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2846 SDValue Src = V.getOperand(0);
2848 if (Src.getValueType().isScalableVector())
2850 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2852 APInt DemandedSrcElts = DemandedElts.
zext(NumSrcElts);
2854 UndefElts = UndefSrcElts.
trunc(NumElts);
2860 SDValue Src = V.getOperand(0);
2861 EVT SrcVT = Src.getValueType();
2871 if ((
BitWidth % SrcBitWidth) == 0) {
2873 unsigned Scale =
BitWidth / SrcBitWidth;
2875 APInt ScaledDemandedElts =
2877 for (
unsigned I = 0;
I != Scale; ++
I) {
2881 SubDemandedElts &= ScaledDemandedElts;
2885 if (!SubUndefElts.
isZero())
2899 EVT VT = V.getValueType();
2909 (AllowUndefs || !UndefElts);
2915 EVT VT = V.getValueType();
2916 unsigned Opcode = V.getOpcode();
2937 SplatIdx = (UndefElts & DemandedElts).
countr_one();
2951 auto *SVN = cast<ShuffleVectorSDNode>(V);
2952 if (!SVN->isSplat())
2954 int Idx = SVN->getSplatIndex();
2955 int NumElts = V.getValueType().getVectorNumElements();
2956 SplatIdx =
Idx % NumElts;
2957 return V.getOperand(
Idx / NumElts);
2973 if (LegalSVT.
bitsLT(SVT))
2984 const APInt &DemandedElts)
const {
2987 "Unknown shift node");
2988 unsigned BitWidth = V.getScalarValueSizeInBits();
2991 const APInt &ShAmt = SA->getAPIntValue();
3002 "Unknown shift node");
3005 unsigned BitWidth = V.getScalarValueSizeInBits();
3006 auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
3009 const APInt *MinShAmt =
nullptr;
3010 for (
unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3011 if (!DemandedElts[i])
3013 auto *SA = dyn_cast<ConstantSDNode>(BV->getOperand(i));
3017 const APInt &ShAmt = SA->getAPIntValue();
3020 if (MinShAmt && MinShAmt->
ule(ShAmt))
3031 "Unknown shift node");
3034 unsigned BitWidth = V.getScalarValueSizeInBits();
3035 auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
3038 const APInt *MaxShAmt =
nullptr;
3039 for (
unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3040 if (!DemandedElts[i])
3042 auto *SA = dyn_cast<ConstantSDNode>(BV->getOperand(i));
3046 const APInt &ShAmt = SA->getAPIntValue();
3049 if (MaxShAmt && MaxShAmt->
uge(ShAmt))
3060 EVT VT =
Op.getValueType();
3075 unsigned Depth)
const {
3076 unsigned BitWidth =
Op.getScalarValueSizeInBits();
3080 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
3084 if (
auto *
C = dyn_cast<ConstantFPSDNode>(
Op)) {
3094 assert((!
Op.getValueType().isFixedLengthVector() ||
3095 NumElts ==
Op.getValueType().getVectorNumElements()) &&
3096 "Unexpected vector size");
3101 unsigned Opcode =
Op.getOpcode();
3109 "Expected SPLAT_VECTOR implicit truncation");
3116 unsigned ScalarSize =
Op.getOperand(0).getScalarValueSizeInBits();
3118 "Expected SPLAT_VECTOR_PARTS scalars to cover element width");
3125 const APInt &Step =
Op.getConstantOperandAPInt(0);
3134 const APInt MinNumElts =
3140 .
umul_ov(MinNumElts, Overflow);
3144 const APInt MaxValue = (MaxNumElts - 1).
umul_ov(Step, Overflow);
3152 assert(!
Op.getValueType().isScalableVector());
3156 if (!DemandedElts[i])
3165 "Expected BUILD_VECTOR implicit truncation");
3178 assert(!
Op.getValueType().isScalableVector());
3181 APInt DemandedLHS, DemandedRHS;
3185 DemandedLHS, DemandedRHS))
3190 if (!!DemandedLHS) {
3198 if (!!DemandedRHS) {
3207 const APInt &Multiplier =
Op.getConstantOperandAPInt(0);
3212 if (
Op.getValueType().isScalableVector())
3216 EVT SubVectorVT =
Op.getOperand(0).getValueType();
3219 for (
unsigned i = 0; i != NumSubVectors; ++i) {
3221 DemandedElts.
extractBits(NumSubVectorElts, i * NumSubVectorElts);
3222 if (!!DemandedSub) {
3234 if (
Op.getValueType().isScalableVector())
3243 APInt DemandedSrcElts = DemandedElts;
3248 if (!!DemandedSubElts) {
3253 if (!!DemandedSrcElts) {
3263 if (
Op.getValueType().isScalableVector() || Src.getValueType().isScalableVector())
3266 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
3272 if (
Op.getValueType().isScalableVector())
3276 if (DemandedElts != 1)
3287 if (
Op.getValueType().isScalableVector())
3307 if ((
BitWidth % SubBitWidth) == 0) {
3314 unsigned SubScale =
BitWidth / SubBitWidth;
3315 APInt SubDemandedElts(NumElts * SubScale, 0);
3316 for (
unsigned i = 0; i != NumElts; ++i)
3317 if (DemandedElts[i])
3318 SubDemandedElts.
setBit(i * SubScale);
3320 for (
unsigned i = 0; i != SubScale; ++i) {
3323 unsigned Shifts = IsLE ? i : SubScale - 1 - i;
3324 Known.
insertBits(Known2, SubBitWidth * Shifts);
3329 if ((SubBitWidth %
BitWidth) == 0) {
3330 assert(
Op.getValueType().isVector() &&
"Expected bitcast to vector");
3335 unsigned SubScale = SubBitWidth /
BitWidth;
3336 APInt SubDemandedElts =
3341 for (
unsigned i = 0; i != NumElts; ++i)
3342 if (DemandedElts[i]) {
3343 unsigned Shifts = IsLE ? i : NumElts - 1 - i;
3374 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3378 Op.getOperand(0), DemandedElts,
false,
Depth + 1);
3384 if (
Op->getFlags().hasNoSignedWrap() &&
3385 Op.getOperand(0) ==
Op.getOperand(1) &&
3415 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3418 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3419 if (
Op.getResNo() == 0)
3426 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3429 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3430 if (
Op.getResNo() == 0)
3474 if (
Op.getResNo() != 1)
3489 unsigned OpNo =
Op->isStrictFPOpcode() ? 1 : 0;
3503 if (
const APInt *ShMinAmt =
3511 Op->getFlags().hasExact());
3514 if (
const APInt *ShMinAmt =
3522 Op->getFlags().hasExact());
3527 unsigned Amt =
C->getAPIntValue().urem(
BitWidth);
3533 DemandedElts,
Depth + 1);
3558 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3561 unsigned LoBits =
Op.getOperand(0).getScalarValueSizeInBits();
3562 unsigned HiBits =
Op.getOperand(1).getScalarValueSizeInBits();
3565 Known = Known2.
concat(Known);
3579 if (
Op.getResNo() == 0)
3587 EVT EVT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
3628 !
Op.getValueType().isScalableVector()) {
3642 for (
unsigned i = 0; i != NumElts; ++i) {
3643 if (!DemandedElts[i])
3646 if (
auto *CInt = dyn_cast<ConstantInt>(Elt)) {
3652 if (
auto *CFP = dyn_cast<ConstantFP>(Elt)) {
3653 APInt Value = CFP->getValueAPF().bitcastToAPInt();
3664 if (
auto *CInt = dyn_cast<ConstantInt>(Cst)) {
3666 }
else if (
auto *CFP = dyn_cast<ConstantFP>(Cst)) {
3672 }
else if (
Op.getResNo() == 0) {
3673 KnownBits Known0(!LD->getMemoryVT().isScalableVT()
3674 ? LD->getMemoryVT().getFixedSizeInBits()
3676 EVT VT =
Op.getValueType();
3683 if (
const MDNode *MD = LD->getRanges()) {
3694 if (LD->getMemoryVT().isVector())
3695 Known0 = Known0.
trunc(LD->getMemoryVT().getScalarSizeInBits());
3712 if (
Op.getValueType().isScalableVector())
3714 EVT InVT =
Op.getOperand(0).getValueType();
3726 if (
Op.getValueType().isScalableVector())
3728 EVT InVT =
Op.getOperand(0).getValueType();
3744 if (
Op.getValueType().isScalableVector())
3746 EVT InVT =
Op.getOperand(0).getValueType();
3763 EVT VT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
3766 Known.
Zero |= (~InMask);
3767 Known.
One &= (~Known.Zero);
3771 unsigned LogOfAlign =
Log2(cast<AssertAlignSDNode>(
Op)->
getAlign());
3791 Op.getOpcode() ==
ISD::ADD, Flags.hasNoSignedWrap(),
3792 Flags.hasNoUnsignedWrap(), Known, Known2);
3799 if (
Op.getResNo() == 1) {
3810 "We only compute knownbits for the difference here.");
3817 Borrow = Borrow.
trunc(1);
3831 if (
Op.getResNo() == 1) {
3842 assert(
Op.getResNo() == 0 &&
"We only compute knownbits for the sum here.");
3852 Carry = Carry.
trunc(1);
3888 const unsigned Index =
Op.getConstantOperandVal(1);
3889 const unsigned EltBitWidth =
Op.getValueSizeInBits();
3896 Known = Known.
trunc(EltBitWidth);
3912 Known = Known.
trunc(EltBitWidth);
3917 auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
3918 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
3928 if (
Op.getValueType().isScalableVector())
3937 bool DemandedVal =
true;
3938 APInt DemandedVecElts = DemandedElts;
3939 auto *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
3940 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
3941 unsigned EltIdx = CEltNo->getZExtValue();
3942 DemandedVal = !!DemandedElts[EltIdx];
3951 if (!!DemandedVecElts) {
3969 Known = Known2.
abs();
4000 if (CstLow && CstHigh) {
4005 const APInt &ValueHigh = CstHigh->getAPIntValue();
4006 if (ValueLow.
sle(ValueHigh)) {
4009 unsigned MinSignBits = std::min(LowSignBits, HighSignBits);
4032 if (IsMax && CstLow) {
4056 EVT VT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
4061 if (
Op.getResNo() == 1) {
4088 cast<AtomicSDNode>(
Op)->getMemoryVT().getScalarSizeInBits();
4090 if (
Op.getResNo() == 0) {
4114 if (
Op.getValueType().isScalableVector())
4261 return C->getAPIntValue().zextOrTrunc(
BitWidth).isPowerOf2();
4269 if (
C &&
C->getAPIntValue() == 1)
4279 if (
C &&
C->getAPIntValue().isSignMask())
4291 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(E))
4292 return C->getAPIntValue().zextOrTrunc(BitWidth).isPowerOf2();
4300 if (
C->getAPIntValue().zextOrTrunc(
BitWidth).isPowerOf2())
4337 EVT VT =
Op.getValueType();
4349 unsigned Depth)
const {
4350 EVT VT =
Op.getValueType();
4355 unsigned FirstAnswer = 1;
4357 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
4358 const APInt &Val =
C->getAPIntValue();
4368 unsigned Opcode =
Op.getOpcode();
4372 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getSizeInBits();
4373 return VTBits-Tmp+1;
4375 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getSizeInBits();
4382 unsigned NumSrcBits =
Op.getOperand(0).getValueSizeInBits();
4384 if (NumSrcSignBits > (NumSrcBits - VTBits))
4385 return NumSrcSignBits - (NumSrcBits - VTBits);
4392 if (!DemandedElts[i])
4399 APInt T =
C->getAPIntValue().trunc(VTBits);
4400 Tmp2 =
T.getNumSignBits();
4404 if (
SrcOp.getValueSizeInBits() != VTBits) {
4406 "Expected BUILD_VECTOR implicit truncation");
4407 unsigned ExtraBits =
SrcOp.getValueSizeInBits() - VTBits;
4408 Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1);
4411 Tmp = std::min(Tmp, Tmp2);
4418 APInt DemandedLHS, DemandedRHS;
4422 DemandedLHS, DemandedRHS))
4425 Tmp = std::numeric_limits<unsigned>::max();
4428 if (!!DemandedRHS) {
4430 Tmp = std::min(Tmp, Tmp2);
4435 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4451 if (VTBits == SrcBits)
4457 if ((SrcBits % VTBits) == 0) {
4460 unsigned Scale = SrcBits / VTBits;
4461 APInt SrcDemandedElts =
4471 for (
unsigned i = 0; i != NumElts; ++i)
4472 if (DemandedElts[i]) {
4473 unsigned SubOffset = i % Scale;
4474 SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset);
4475 SubOffset = SubOffset * VTBits;
4476 if (Tmp <= SubOffset)
4478 Tmp2 = std::min(Tmp2, Tmp - SubOffset);
4487 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getScalarSizeInBits();
4488 return VTBits - Tmp + 1;
4490 Tmp = VTBits -
Op.getOperand(0).getScalarValueSizeInBits();
4494 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getScalarSizeInBits();
4497 return std::max(Tmp, Tmp2);
4502 EVT SrcVT = Src.getValueType();
4510 if (
const APInt *ShAmt =
4512 Tmp = std::min<uint64_t>(Tmp + ShAmt->getZExtValue(), VTBits);
4515 if (
const APInt *ShAmt =
4519 if (ShAmt->ult(Tmp))
4520 return Tmp - ShAmt->getZExtValue();
4530 FirstAnswer = std::min(Tmp, Tmp2);
4540 if (Tmp == 1)
return 1;
4542 return std::min(Tmp, Tmp2);
4545 if (Tmp == 1)
return 1;
4547 return std::min(Tmp, Tmp2);
4559 if (CstLow && CstHigh) {
4564 Tmp2 = CstHigh->getAPIntValue().getNumSignBits();
4565 return std::min(Tmp, Tmp2);
4574 return std::min(Tmp, Tmp2);
4582 return std::min(Tmp, Tmp2);
4593 if (
Op.getResNo() != 1)
4607 unsigned OpNo =
Op->isStrictFPOpcode() ? 1 : 0;
4624 unsigned RotAmt =
C->getAPIntValue().urem(VTBits);
4628 RotAmt = (VTBits - RotAmt) % VTBits;
4632 if (Tmp > (RotAmt + 1))
return (Tmp - RotAmt);
4640 if (Tmp == 1)
return 1;
4645 if (CRHS->isAllOnes()) {
4651 if ((Known.
Zero | 1).isAllOnes())
4661 if (Tmp2 == 1)
return 1;
4662 return std::min(Tmp, Tmp2) - 1;
4665 if (Tmp2 == 1)
return 1;
4670 if (CLHS->isZero()) {
4675 if ((Known.
Zero | 1).isAllOnes())
4689 if (Tmp == 1)
return 1;
4690 return std::min(Tmp, Tmp2) - 1;
4694 if (SignBitsOp0 == 1)
4697 if (SignBitsOp1 == 1)
4699 unsigned OutValidBits =
4700 (VTBits - SignBitsOp0 + 1) + (VTBits - SignBitsOp1 + 1);
4701 return OutValidBits > VTBits ? 1 : VTBits - OutValidBits + 1;
4711 unsigned NumSrcBits =
Op.getOperand(0).getScalarValueSizeInBits();
4713 if (NumSrcSignBits > (NumSrcBits - VTBits))
4714 return NumSrcSignBits - (NumSrcBits - VTBits);
4721 const int BitWidth =
Op.getValueSizeInBits();
4722 const int Items =
Op.getOperand(0).getValueSizeInBits() /
BitWidth;
4726 const int rIndex = Items - 1 -
Op.getConstantOperandVal(1);
4741 bool DemandedVal =
true;
4742 APInt DemandedVecElts = DemandedElts;
4743 auto *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
4744 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
4745 unsigned EltIdx = CEltNo->getZExtValue();
4746 DemandedVal = !!DemandedElts[EltIdx];
4749 Tmp = std::numeric_limits<unsigned>::max();
4755 Tmp = std::min(Tmp, Tmp2);
4757 if (!!DemandedVecElts) {
4759 Tmp = std::min(Tmp, Tmp2);
4761 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4772 const unsigned BitWidth =
Op.getValueSizeInBits();
4773 const unsigned EltBitWidth =
Op.getOperand(0).getScalarValueSizeInBits();
4785 auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
4786 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
4796 if (Src.getValueType().isScalableVector())
4799 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
4808 Tmp = std::numeric_limits<unsigned>::max();
4809 EVT SubVectorVT =
Op.getOperand(0).getValueType();
4812 for (
unsigned i = 0; (i < NumSubVectors) && (Tmp > 1); ++i) {
4814 DemandedElts.
extractBits(NumSubVectorElts, i * NumSubVectorElts);
4818 Tmp = std::min(Tmp, Tmp2);
4820 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4833 APInt DemandedSrcElts = DemandedElts;
4836 Tmp = std::numeric_limits<unsigned>::max();
4837 if (!!DemandedSubElts) {
4842 if (!!DemandedSrcElts) {
4844 Tmp = std::min(Tmp, Tmp2);
4846 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4851 if (
const MDNode *Ranges = LD->getRanges()) {
4852 if (DemandedElts != 1)
4857 switch (LD->getExtensionType()) {
4892 Tmp = cast<AtomicSDNode>(
Op)->getMemoryVT().getScalarSizeInBits();
4894 if (
Op.getResNo() == 0) {
4898 return VTBits - Tmp + 1;
4900 return VTBits - Tmp;
4904 return VTBits - Tmp + 1;
4906 return VTBits - Tmp;
4914 if (
Op.getResNo() == 0) {
4917 unsigned ExtType = LD->getExtensionType();
4921 Tmp = LD->getMemoryVT().getScalarSizeInBits();
4922 return VTBits - Tmp + 1;
4924 Tmp = LD->getMemoryVT().getScalarSizeInBits();
4925 return VTBits - Tmp;
4930 Type *CstTy = Cst->getType();
4935 for (
unsigned i = 0; i != NumElts; ++i) {
4936 if (!DemandedElts[i])
4939 if (
auto *CInt = dyn_cast<ConstantInt>(Elt)) {
4941 Tmp = std::min(Tmp,
Value.getNumSignBits());
4944 if (
auto *CFP = dyn_cast<ConstantFP>(Elt)) {
4945 APInt Value = CFP->getValueAPF().bitcastToAPInt();
4946 Tmp = std::min(Tmp,
Value.getNumSignBits());
4972 FirstAnswer = std::max(FirstAnswer, NumBits);
4983 unsigned Depth)
const {
4985 return Op.getScalarValueSizeInBits() - SignBits + 1;
4989 const APInt &DemandedElts,
4990 unsigned Depth)
const {
4992 return Op.getScalarValueSizeInBits() - SignBits + 1;
4996 unsigned Depth)
const {
5002 EVT VT =
Op.getValueType();
5013 const APInt &DemandedElts,
5015 unsigned Depth)
const {
5016 unsigned Opcode =
Op.getOpcode();
5042 if (!DemandedElts[i])
5071 return isGuaranteedNotToBeUndefOrPoison(V, PoisonOnly, Depth + 1);
5077 unsigned Depth)
const {
5079 EVT VT =
Op.getValueType();
5092 unsigned Depth)
const {
5094 EVT VT =
Op.getValueType();
5098 unsigned Opcode =
Op.getOpcode();
5125 if (
Op.getOperand(0).getValueType().isInteger())
5133 if (((
unsigned)CCCode & 0x10U))
5139 (
Op->getFlags().hasNoNaNs() ||
Op->getFlags().hasNoInfs()));
5144 return ConsiderFlags &&
Op->getFlags().hasNonNeg();
5150 return ConsiderFlags && (
Op->getFlags().hasNoSignedWrap() ||
5151 Op->getFlags().hasNoUnsignedWrap());
5159 return ConsiderFlags && (
Op->getFlags().hasNoSignedWrap() ||
5160 Op->getFlags().hasNoUnsignedWrap());
5164 return ConsiderFlags &&
Op->getFlags().hasDisjoint();
5172 EVT VecVT =
Op.getOperand(0).getValueType();
5179 EVT VecVT =
Op.getOperand(0).getValueType();
5198 unsigned Opcode =
Op.getOpcode();
5200 return Op->getFlags().hasDisjoint() ||
5222 return !
C->getValueAPF().isNaN() ||
5223 (SNaN && !
C->getValueAPF().isSignaling());
5226 unsigned Opcode =
Op.getOpcode();
5334 assert(
Op.getValueType().isFloatingPoint() &&
5335 "Floating point type expected");
5346 assert(!
Op.getValueType().isFloatingPoint() &&
5347 "Floating point types unsupported - use isKnownNeverZeroFloat");
5356 switch (
Op.getOpcode()) {
5370 if (
Op->getFlags().hasNoSignedWrap() ||
Op->getFlags().hasNoUnsignedWrap())
5374 if (ValKnown.
One[0])
5434 if (
Op->getFlags().hasExact())
5450 if (
Op->getFlags().hasExact())
5455 if (
Op->getFlags().hasNoUnsignedWrap())
5466 std::optional<bool> ne =
5473 if (
Op->getFlags().hasNoSignedWrap() ||
Op->getFlags().hasNoUnsignedWrap())
5489 if (
A ==
B)
return true;
5494 if (CA->isZero() && CB->isZero())
return true;
5503 return V.getOperand(0);
5510 SDValue ExtArg = V.getOperand(0);
5529 NotOperand = NotOperand->getOperand(0);
5531 if (
Other == NotOperand)
5534 return NotOperand ==
Other->getOperand(0) ||
5535 NotOperand ==
Other->getOperand(1);
5541 A =
A->getOperand(0);
5544 B =
B->getOperand(0);
5547 return MatchNoCommonBitsPattern(
A->getOperand(0),
A->getOperand(1),
B) ||
5548 MatchNoCommonBitsPattern(
A->getOperand(1),
A->getOperand(0),
B);
5554 assert(
A.getValueType() ==
B.getValueType() &&
5555 "Values must have the same type");
5565 if (cast<ConstantSDNode>(Step)->
isZero())
5574 int NumOps = Ops.
size();
5575 assert(NumOps != 0 &&
"Can't build an empty vector!");
5577 "BUILD_VECTOR cannot be used with scalable types");
5579 "Incorrect element count in BUILD_VECTOR!");
5587 bool IsIdentity =
true;
5588 for (
int i = 0; i != NumOps; ++i) {
5590 Ops[i].getOperand(0).getValueType() != VT ||
5591 (IdentitySrc && Ops[i].getOperand(0) != IdentitySrc) ||
5592 !isa<ConstantSDNode>(Ops[i].getOperand(1)) ||
5593 Ops[i].getConstantOperandAPInt(1) != i) {
5597 IdentitySrc = Ops[i].getOperand(0);
5610 assert(!Ops.
empty() &&
"Can't concatenate an empty list of vectors!");
5613 return Ops[0].getValueType() ==
Op.getValueType();
5615 "Concatenation of vectors with inconsistent value types!");
5616 assert((Ops[0].getValueType().getVectorElementCount() * Ops.
size()) ==
5618 "Incorrect element count in vector concatenation!");
5620 if (Ops.
size() == 1)
5631 bool IsIdentity =
true;
5632 for (
unsigned i = 0, e = Ops.
size(); i != e; ++i) {
5634 unsigned IdentityIndex = i *
Op.getValueType().getVectorMinNumElements();
5636 Op.getOperand(0).getValueType() != VT ||
5637 (IdentitySrc &&
Op.getOperand(0) != IdentitySrc) ||
5638 Op.getConstantOperandVal(1) != IdentityIndex) {
5642 assert((!IdentitySrc || IdentitySrc ==
Op.getOperand(0)) &&
5643 "Unexpected identity source vector for concat of extracts");
5644 IdentitySrc =
Op.getOperand(0);
5647 assert(IdentitySrc &&
"Failed to set source vector of extracts");
5662 EVT OpVT =
Op.getValueType();
5674 SVT = (SVT.
bitsLT(
Op.getValueType()) ?
Op.getValueType() : SVT);
5697 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
5700 auto *
N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(),
5702 CSEMap.InsertNode(
N, IP);
5715 return getNode(Opcode,
DL, VT, N1, Flags);
5766 "STEP_VECTOR can only be used with scalable types");
5769 "Unexpected step operand");
5791 "Invalid FP cast!");
5795 "Vector element count mismatch!");
5813 "Invalid SIGN_EXTEND!");
5815 "SIGN_EXTEND result type type should be vector iff the operand "
5820 "Vector element count mismatch!");
5834 "Invalid ZERO_EXTEND!");
5836 "ZERO_EXTEND result type type should be vector iff the operand "
5841 "Vector element count mismatch!");
5872 "Invalid ANY_EXTEND!");
5874 "ANY_EXTEND result type type should be vector iff the operand "
5879 "Vector element count mismatch!");
5904 "Invalid TRUNCATE!");
5906 "TRUNCATE result type type should be vector iff the operand "
5911 "Vector element count mismatch!");
5934 assert(VT.
isVector() &&
"This DAG node is restricted to vector types.");
5936 "The input must be the same size or smaller than the result.");
5939 "The destination vector type must have fewer lanes than the input.");
5949 "BSWAP types must be a multiple of 16 bits!");
5963 "Cannot BITCAST between types of different sizes!");
5976 "Illegal SCALAR_TO_VECTOR node!");
6033 "Wrong operand type!");
6040 if (VT != MVT::Glue) {
6044 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
6045 E->intersectFlagsWith(Flags);
6049 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
6051 createOperands(
N, Ops);
6052 CSEMap.InsertNode(
N, IP);
6054 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
6055 createOperands(
N, Ops);
6089 if (!C2.getBoolValue())
6093 if (!C2.getBoolValue())
6097 if (!C2.getBoolValue())
6101 if (!C2.getBoolValue())
6121 return std::nullopt;
6126 bool IsUndef1,
const APInt &C2,
6128 if (!(IsUndef1 || IsUndef2))
6136 return std::nullopt;
6146 auto *C2 = dyn_cast<ConstantSDNode>(N2);
6149 int64_t
Offset = C2->getSExtValue();
6167 assert(Ops.
size() == 2 &&
"Div/rem should have 2 operands");
6174 [](
SDValue V) { return V.isUndef() ||
6175 isNullConstant(V); });
6195 unsigned NumOps = Ops.
size();
6211 if (
auto *
C = dyn_cast<ConstantSDNode>(N1)) {
6212 const APInt &Val =
C->getAPIntValue();
6216 C->isTargetOpcode(),
C->isOpaque());
6223 C->isTargetOpcode(),
C->isOpaque());
6228 C->isTargetOpcode(),
C->isOpaque());
6230 C->isTargetOpcode(),
C->isOpaque());
6277 if (VT == MVT::f16 &&
C->getValueType(0) == MVT::i16)
6279 if (VT == MVT::f32 &&
C->getValueType(0) == MVT::i32)
6281 if (VT == MVT::f64 &&
C->getValueType(0) == MVT::i64)
6283 if (VT == MVT::f128 &&
C->getValueType(0) == MVT::i128)
6290 if (
auto *
C = dyn_cast<ConstantFPSDNode>(N1)) {
6344 return getConstant(V.bitcastToAPInt().getZExtValue(),
DL, VT);
6347 if (VT == MVT::i16 &&
C->getValueType(0) == MVT::f16)
6350 if (VT == MVT::i16 &&
C->getValueType(0) == MVT::bf16)
6353 if (VT == MVT::i32 &&
C->getValueType(0) == MVT::f32)
6356 if (VT == MVT::i64 &&
C->getValueType(0) == MVT::f64)
6357 return getConstant(V.bitcastToAPInt().getZExtValue(),
DL, VT);
6372 if (
auto *C1 = dyn_cast<ConstantSDNode>(Ops[0])) {
6373 if (
auto *C2 = dyn_cast<ConstantSDNode>(Ops[1])) {
6374 if (C1->isOpaque() || C2->isOpaque())
6377 std::optional<APInt> FoldAttempt =
6378 FoldValue(Opcode, C1->getAPIntValue(), C2->getAPIntValue());
6384 "Can't fold vectors ops with scalar operands");
6405 Ops[0].getValueType() == VT && Ops[1].getValueType() == VT &&
6410 auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
6411 auto *BV2 = dyn_cast<BuildVectorSDNode>(N2);
6418 if (BV1->getConstantRawBits(IsLE, EltBits, RawBits1, UndefElts1) &&
6419 BV2->getConstantRawBits(IsLE, EltBits, RawBits2, UndefElts2)) {
6423 Opcode, RawBits1[
I], UndefElts1[
I], RawBits2[
I], UndefElts2[
I]);
6434 DstBits, RawBits, DstUndefs,
6436 EVT BVEltVT = BV1->getOperand(0).getValueType();
6439 for (
unsigned I = 0, E = DstBits.
size();
I != E; ++
I) {
6457 ? Ops[0].getConstantOperandAPInt(0) * RHSVal
6458 : Ops[0].getConstantOperandAPInt(0) << RHSVal;
6463 auto IsScalarOrSameVectorSize = [NumElts](
const SDValue &
Op) {
6464 return !
Op.getValueType().isVector() ||
6465 Op.getValueType().getVectorElementCount() == NumElts;
6468 auto IsBuildVectorSplatVectorOrUndef = [](
const SDValue &
Op) {
6477 if (!
llvm::all_of(Ops, IsBuildVectorSplatVectorOrUndef) ||
6506 for (
unsigned I = 0;
I != NumVectorElts;
I++) {
6509 EVT InSVT =
Op.getValueType().getScalarType();
6531 !isa<ConstantSDNode>(ScalarOp) &&
6545 if (LegalSVT != SVT)
6546 ScalarResult =
getNode(ExtendCode,
DL, LegalSVT, ScalarResult);
6564 if (Ops.
size() != 2)
6575 if (N1CFP && N2CFP) {
6622 if (N1C && N1C->getValueAPF().isNegZero() && N2.
isUndef())
6650 ID.AddInteger(
A.value());
6653 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
6656 auto *
N = newSDNode<AssertAlignSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
6658 createOperands(
N, {Val});
6660 CSEMap.InsertNode(
N, IP);
6673 return getNode(Opcode,
DL, VT, N1, N2, Flags);
6687 if ((N1C && !N2C) || (N1CFP && !N2CFP))
6701 "Operand is DELETED_NODE!");
6705 auto *N1C = dyn_cast<ConstantSDNode>(N1);
6706 auto *N2C = dyn_cast<ConstantSDNode>(N2);
6717 N2.
getValueType() == MVT::Other &&
"Invalid token factor!");
6721 if (N1 == N2)
return N1;
6737 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6739 N1.
getValueType() == VT &&
"Binary operator types must match!");
6742 if (N2CV && N2CV->
isZero())
6751 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6753 N1.
getValueType() == VT &&
"Binary operator types must match!");
6756 if (N2CV && N2CV->
isZero())
6763 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6765 N1.
getValueType() == VT &&
"Binary operator types must match!");
6770 const APInt &N2CImm = N2C->getAPIntValue();
6784 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6786 N1.
getValueType() == VT &&
"Binary operator types must match!");
6798 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6800 N1.
getValueType() == VT &&
"Binary operator types must match!");
6804 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6806 N1.
getValueType() == VT &&
"Binary operator types must match!");
6812 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6814 N1.
getValueType() == VT &&
"Binary operator types must match!");
6825 N1.
getValueType() == VT &&
"Binary operator types must match!");
6833 "Invalid FCOPYSIGN!");
6838 const APInt &ShiftImm = N2C->getAPIntValue();
6850 "Shift operators return type must be the same as their first arg");
6852 "Shifts only work on integers");
6854 "Vector shift amounts must be in the same as their first arg");
6861 "Invalid use of small shift amount with oversized value!");
6868 if (N2CV && N2CV->
isZero())
6875 N2C && (N2C->getZExtValue() == 0 || N2C->getZExtValue() == 1) &&
6876 "Invalid FP_ROUND!");
6881 EVT EVT = cast<VTSDNode>(N2)->getVT();
6884 "Cannot *_EXTEND_INREG FP types");
6886 "AssertSExt/AssertZExt type should be the vector element type "
6887 "rather than the vector type!");
6893 EVT EVT = cast<VTSDNode>(N2)->getVT();
6896 "Cannot *_EXTEND_INREG FP types");
6898 "SIGN_EXTEND_INREG type should be vector iff the operand "
6902 "Vector element counts must match in SIGN_EXTEND_INREG");
6904 if (
EVT == VT)
return N1;
6914 const APInt &Val = N1C->getAPIntValue();
6915 return SignExtendInReg(Val, VT);
6928 APInt Val =
C->getAPIntValue();
6929 Ops.
push_back(SignExtendInReg(Val, OpVT));
6947 "FP_TO_*INT_SAT type should be vector iff the operand type is "
6951 "Vector element counts must match in FP_TO_*INT_SAT");
6952 assert(!cast<VTSDNode>(N2)->getVT().isVector() &&
6953 "Type to saturate to must be a scalar.");
6960 "The result of EXTRACT_VECTOR_ELT must be at least as wide as the \
6961 element type of the vector.");
6993 "BUILD_VECTOR used for scalable vectors");
7016 if (N1Op2C && N2C) {
7046 assert(N2C && (
unsigned)N2C->getZExtValue() < 2 &&
"Bad EXTRACT_ELEMENT!");
7050 "Wrong types for EXTRACT_ELEMENT!");
7061 unsigned Shift = ElementSize * N2C->getZExtValue();
7062 const APInt &Val = N1C->getAPIntValue();
7069 "Extract subvector VTs must be vectors!");
7071 "Extract subvector VTs must have the same element type!");
7073 "Cannot extract a scalable vector from a fixed length vector!");
7076 "Extract subvector must be from larger vector to smaller vector!");
7077 assert(N2C &&
"Extract subvector index must be a constant");
7081 "Extract subvector overflow!");
7082 assert(N2C->getAPIntValue().getBitWidth() ==
7084 "Constant index for EXTRACT_SUBVECTOR has an invalid size");
7099 return N1.
getOperand(N2C->getZExtValue() / Factor);
7167 if (VT != MVT::Glue) {
7171 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
7172 E->intersectFlagsWith(Flags);
7176 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7178 createOperands(
N, Ops);
7179 CSEMap.InsertNode(
N, IP);
7181 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7182 createOperands(
N, Ops);
7196 return getNode(Opcode,
DL, VT, N1, N2, N3, Flags);
7205 "Operand is DELETED_NODE!");
7216 if (N1CFP && N2CFP && N3CFP) {
7245 "SETCC operands must have the same type!");
7247 "SETCC type should be vector iff the operand type is vector!");
7250 "SETCC vector element counts must match!");
7270 if (cast<ConstantSDNode>(N3)->
isZero())
7300 "Dest and insert subvector source types must match!");
7302 "Insert subvector VTs must be vectors!");
7304 "Insert subvector VTs must have the same element type!");
7306 "Cannot insert a scalable vector into a fixed length vector!");
7309 "Insert subvector must be from smaller vector to larger vector!");
7310 assert(isa<ConstantSDNode>(N3) &&
7311 "Insert subvector index must be constant");
7315 "Insert subvector overflow!");
7318 "Constant index for INSERT_SUBVECTOR has an invalid size");
7336 case ISD::VP_TRUNCATE:
7337 case ISD::VP_SIGN_EXTEND:
7338 case ISD::VP_ZERO_EXTEND:
7349 if (VT != MVT::Glue) {
7353 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
7354 E->intersectFlagsWith(Flags);
7358 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7360 createOperands(
N, Ops);
7361 CSEMap.InsertNode(
N, IP);
7363 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7364 createOperands(
N, Ops);
7375 SDValue Ops[] = { N1, N2, N3, N4 };
7382 SDValue Ops[] = { N1, N2, N3, N4, N5 };
7400 if (FI->getIndex() < 0)
7415 assert(
C->getAPIntValue().getBitWidth() == 8);
7420 return DAG.
getConstant(Val, dl, VT,
false, IsOpaque);
7426 assert(
Value.getValueType() == MVT::i8 &&
"memset with non-byte fill value?");
7442 if (VT !=
Value.getValueType())
7455 if (Slice.
Array ==
nullptr) {
7458 if (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
7473 unsigned NumVTBytes = NumVTBits / 8;
7474 unsigned NumBytes = std::min(NumVTBytes,
unsigned(Slice.
Length));
7476 APInt Val(NumVTBits, 0);
7478 for (
unsigned i = 0; i != NumBytes; ++i)
7481 for (
unsigned i = 0; i != NumBytes; ++i)
7482 Val |= (
uint64_t)(
unsigned char)Slice[i] << (NumVTBytes-i-1)*8;
7501 APInt(
Base.getValueSizeInBits().getFixedValue(),
7502 Offset.getKnownMinValue()));
7513 EVT BasePtrVT =
Ptr.getValueType();
7522 G = cast<GlobalAddressSDNode>(Src);
7523 else if (Src.getOpcode() ==
ISD::ADD &&
7526 G = cast<GlobalAddressSDNode>(Src.getOperand(0));
7527 SrcDelta = Src.getConstantOperandVal(1);
7533 SrcDelta +
G->getOffset());
7549 assert(OutLoadChains.
size() &&
"Missing loads in memcpy inlining");
7550 assert(OutStoreChains.
size() &&
"Missing stores in memcpy inlining");
7552 for (
unsigned i =
From; i < To; ++i) {
7554 GluedLoadChains.
push_back(OutLoadChains[i]);
7561 for (
unsigned i =
From; i < To; ++i) {
7562 StoreSDNode *ST = dyn_cast<StoreSDNode>(OutStoreChains[i]);
7564 ST->getBasePtr(), ST->getMemoryVT(),
7565 ST->getMemOperand());
7573 bool isVol,
bool AlwaysInline,
7589 std::vector<EVT> MemOps;
7590 bool DstAlignCanChange =
false;
7596 DstAlignCanChange =
true;
7598 if (!SrcAlign || Alignment > *SrcAlign)
7599 SrcAlign = Alignment;
7600 assert(SrcAlign &&
"SrcAlign must be set");
7604 bool isZeroConstant = CopyFromConstant && Slice.
Array ==
nullptr;
7606 const MemOp Op = isZeroConstant
7610 *SrcAlign, isVol, CopyFromConstant);
7616 if (DstAlignCanChange) {
7617 Type *Ty = MemOps[0].getTypeForEVT(
C);
7618 Align NewAlign =
DL.getABITypeAlign(Ty);
7624 if (!
TRI->hasStackRealignment(MF))
7625 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7628 if (NewAlign > Alignment) {
7632 Alignment = NewAlign;
7640 const Value *SrcVal = dyn_cast_if_present<const Value *>(SrcPtrInfo.
V);
7650 unsigned NumMemOps = MemOps.
size();
7652 for (
unsigned i = 0; i != NumMemOps; ++i) {
7657 if (VTSize >
Size) {
7660 assert(i == NumMemOps-1 && i != 0);
7661 SrcOff -= VTSize -
Size;
7662 DstOff -= VTSize -
Size;
7665 if (CopyFromConstant &&
7673 if (SrcOff < Slice.
Length) {
7675 SubSlice.
move(SrcOff);
7678 SubSlice.
Array =
nullptr;
7680 SubSlice.
Length = VTSize;
7683 if (
Value.getNode()) {
7687 DstPtrInfo.
getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
7692 if (!Store.getNode()) {
7701 bool isDereferenceable =
7704 if (isDereferenceable)
7719 DstPtrInfo.
getWithOffset(DstOff), VT, Alignment, MMOFlags, NewAAInfo);
7729 unsigned NumLdStInMemcpy = OutStoreChains.
size();
7731 if (NumLdStInMemcpy) {
7737 for (
unsigned i = 0; i < NumLdStInMemcpy; ++i) {
7743 if (NumLdStInMemcpy <= GluedLdStLimit) {
7745 NumLdStInMemcpy, OutLoadChains,
7748 unsigned NumberLdChain = NumLdStInMemcpy / GluedLdStLimit;
7749 unsigned RemainingLdStInMemcpy = NumLdStInMemcpy % GluedLdStLimit;
7750 unsigned GlueIter = 0;
7752 for (
unsigned cnt = 0; cnt < NumberLdChain; ++cnt) {
7753 unsigned IndexFrom = NumLdStInMemcpy - GlueIter - GluedLdStLimit;
7754 unsigned IndexTo = NumLdStInMemcpy - GlueIter;
7757 OutLoadChains, OutStoreChains);
7758 GlueIter += GluedLdStLimit;
7762 if (RemainingLdStInMemcpy) {
7764 RemainingLdStInMemcpy, OutLoadChains,
7776 bool isVol,
bool AlwaysInline,
7790 std::vector<EVT> MemOps;
7791 bool DstAlignCanChange =
false;
7797 DstAlignCanChange =
true;
7799 if (!SrcAlign || Alignment > *SrcAlign)
7800 SrcAlign = Alignment;
7801 assert(SrcAlign &&
"SrcAlign must be set");
7811 if (DstAlignCanChange) {
7812 Type *Ty = MemOps[0].getTypeForEVT(
C);
7813 Align NewAlign =
DL.getABITypeAlign(Ty);
7819 if (!
TRI->hasStackRealignment(MF))
7820 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7823 if (NewAlign > Alignment) {
7827 Alignment = NewAlign;
7841 unsigned NumMemOps = MemOps.
size();
7842 for (
unsigned i = 0; i < NumMemOps; i++) {
7847 bool isDereferenceable =
7850 if (isDereferenceable)
7856 SrcPtrInfo.
getWithOffset(SrcOff), *SrcAlign, SrcMMOFlags, NewAAInfo);
7863 for (
unsigned i = 0; i < NumMemOps; i++) {
7869 Chain, dl, LoadValues[i],
7871 DstPtrInfo.
getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
7911 std::vector<EVT> MemOps;
7912 bool DstAlignCanChange =
false;
7918 DstAlignCanChange =
true;
7924 MemOp::Set(
Size, DstAlignCanChange, Alignment, IsZeroVal, isVol),
7928 if (DstAlignCanChange) {
7931 Align NewAlign =
DL.getABITypeAlign(Ty);
7937 if (!
TRI->hasStackRealignment(MF))
7938 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7941 if (NewAlign > Alignment) {
7945 Alignment = NewAlign;
7951 unsigned NumMemOps = MemOps.size();
7954 EVT LargestVT = MemOps[0];
7955 for (
unsigned i = 1; i < NumMemOps; i++)
7956 if (MemOps[i].bitsGT(LargestVT))
7957 LargestVT = MemOps[i];
7964 for (
unsigned i = 0; i < NumMemOps; i++) {
7967 if (VTSize >
Size) {
7970 assert(i == NumMemOps-1 && i != 0);
7971 DstOff -= VTSize -
Size;
7978 if (VT.
bitsLT(LargestVT)) {
7999 assert(
Value.getValueType() == VT &&
"Value with wrong type.");
8026 bool isVol,
bool AlwaysInline,
bool isTailCall,
8035 if (ConstantSize->
isZero())
8039 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8040 isVol,
false, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
8041 if (Result.getNode())
8049 *
this, dl, Chain, Dst, Src,
Size, Alignment, isVol, AlwaysInline,
8050 DstPtrInfo, SrcPtrInfo);
8051 if (Result.getNode())
8058 assert(ConstantSize &&
"AlwaysInline requires a constant size!");
8060 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8061 isVol,
true, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
8077 Entry.Node = Dst; Args.push_back(Entry);
8078 Entry.Node = Src; Args.push_back(Entry);
8081 Entry.Node =
Size; Args.push_back(Entry);
8087 Dst.getValueType().getTypeForEVT(*
getContext()),
8094 std::pair<SDValue,SDValue> CallResult = TLI->
LowerCallTo(CLI);
8095 return CallResult.second;
8100 Type *SizeTy,
unsigned ElemSz,
8109 Args.push_back(Entry);
8112 Args.push_back(Entry);
8116 Args.push_back(Entry);
8120 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8134 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8135 return CallResult.second;
8140 bool isVol,
bool isTailCall,
8149 if (ConstantSize->
isZero())
8153 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8154 isVol,
false, DstPtrInfo, SrcPtrInfo, AAInfo);
8155 if (Result.getNode())
8164 Alignment, isVol, DstPtrInfo, SrcPtrInfo);
8165 if (Result.getNode())
8179 Entry.Node = Dst; Args.push_back(Entry);
8180 Entry.Node = Src; Args.push_back(Entry);
8183 Entry.Node =
Size; Args.push_back(Entry);
8189 Dst.getValueType().getTypeForEVT(*
getContext()),
8196 std::pair<SDValue,SDValue> CallResult = TLI->
LowerCallTo(CLI);
8197 return CallResult.second;
8202 Type *SizeTy,
unsigned ElemSz,
8211 Args.push_back(Entry);
8214 Args.push_back(Entry);
8218 Args.push_back(Entry);
8222 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8236 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8237 return CallResult.second;
8242 bool isVol,
bool AlwaysInline,
bool isTailCall,
8250 if (ConstantSize->
isZero())
8255 isVol,
false, DstPtrInfo, AAInfo);
8257 if (Result.getNode())
8265 *
this, dl, Chain, Dst, Src,
Size, Alignment, isVol, AlwaysInline, DstPtrInfo);
8266 if (Result.getNode())
8273 assert(ConstantSize &&
"AlwaysInline requires a constant size!");
8276 isVol,
true, DstPtrInfo, AAInfo);
8278 "getMemsetStores must return a valid sequence when AlwaysInline");
8295 const auto CreateEntry = [](
SDValue Node,
Type *Ty) {
8306 Args.push_back(CreateEntry(
Size,
DL.getIntPtrType(Ctx)));
8313 Args.push_back(CreateEntry(Src, Src.getValueType().getTypeForEVT(Ctx)));
8314 Args.push_back(CreateEntry(
Size,
DL.getIntPtrType(Ctx)));
8316 Dst.getValueType().getTypeForEVT(Ctx),
8324 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8325 return CallResult.second;
8330 Type *SizeTy,
unsigned ElemSz,
8338 Args.push_back(Entry);
8342 Args.push_back(Entry);
8346 Args.push_back(Entry);
8350 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8364 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8365 return CallResult.second;
8377 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8378 cast<AtomicSDNode>(E)->refineAlignment(MMO);
8383 VTList, MemVT, MMO);
8384 createOperands(
N, Ops);
8386 CSEMap.InsertNode(
N, IP);
8400 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8425 "Invalid Atomic Op");
8432 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8442 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8447 if (Ops.
size() == 1)
8462 if (
Size.hasValue() && !
Size.getValue())
8479 (Opcode <= (
unsigned)std::numeric_limits<int>::max() &&
8481 "Opcode is not a memory-accessing opcode!");
8485 if (VTList.
VTs[VTList.
NumVTs-1] != MVT::Glue) {
8488 ID.AddInteger(getSyntheticNodeSubclassData<MemIntrinsicSDNode>(
8489 Opcode, dl.
getIROrder(), VTList, MemVT, MMO));
8494 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8495 cast<MemIntrinsicSDNode>(E)->refineAlignment(MMO);
8500 VTList, MemVT, MMO);
8501 createOperands(
N, Ops);
8503 CSEMap.InsertNode(
N, IP);
8506 VTList, MemVT, MMO);
8507 createOperands(
N, Ops);
8516 SDValue Chain,
int FrameIndex,
8528 ID.AddInteger(FrameIndex);
8532 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
8537 createOperands(
N, Ops);
8538 CSEMap.InsertNode(
N, IP);
8553 ID.AddInteger(Guid);
8556 if (
SDNode *E = FindNodeOrInsertPos(
ID, Dl, IP))
8559 auto *
N = newSDNode<PseudoProbeSDNode>(
8561 createOperands(
N, Ops);
8562 CSEMap.InsertNode(
N, IP);
8583 !isa<ConstantSDNode>(
Ptr.getOperand(1)) ||
8584 !isa<FrameIndexSDNode>(
Ptr.getOperand(0)))
8587 int FI = cast<FrameIndexSDNode>(
Ptr.getOperand(0))->getIndex();
8590 Offset + cast<ConstantSDNode>(
Ptr.getOperand(1))->getSExtValue());
8601 if (
ConstantSDNode *OffsetNode = dyn_cast<ConstantSDNode>(OffsetOp))
8616 "Invalid chain type");
8628 Alignment, AAInfo, Ranges);
8639 assert(VT == MemVT &&
"Non-extending load from different memory type!");
8643 "Should only be an extending load, not truncating!");
8645 "Cannot convert from FP to Int or Int -> FP!");
8647 "Cannot use an ext load to convert to or from a vector!");
8650 "Cannot use an ext load to change the number of vector elements!");
8662 ID.AddInteger(getSyntheticNodeSubclassData<LoadSDNode>(
8663 dl.
getIROrder(), VTs, AM, ExtType, MemVT, MMO));
8667 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8668 cast<LoadSDNode>(E)->refineAlignment(MMO);
8672 ExtType, MemVT, MMO);
8673 createOperands(
N, Ops);
8675 CSEMap.InsertNode(
N, IP);
8689 PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges);
8707 MemVT, Alignment, MMOFlags, AAInfo);
8722 assert(LD->getOffset().isUndef() &&
"Load is already a indexed load!");
8725 LD->getMemOperand()->getFlags() &
8728 LD->getChain(),
Base,
Offset, LD->getPointerInfo(),
8729 LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo());
8755 "Invalid chain type");
8763 ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
8768 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8769 cast<StoreSDNode>(E)->refineAlignment(MMO);
8774 createOperands(
N, Ops);
8776 CSEMap.InsertNode(
N, IP);
8789 "Invalid chain type");
8810 "Invalid chain type");
8815 "Should only be a truncating store, not extending!");
8817 "Can't do FP-INT conversion!");
8819 "Cannot use trunc store to convert to or from a vector!");
8822 "Cannot use trunc store to change the number of vector elements!");
8830 ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
8835 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8836 cast<StoreSDNode>(E)->refineAlignment(MMO);
8841 createOperands(
N, Ops);
8843 CSEMap.InsertNode(
N, IP);
8854 assert(ST->getOffset().isUndef() &&
"Store is already a indexed store!");
8859 ID.AddInteger(ST->getMemoryVT().getRawBits());
8860 ID.AddInteger(ST->getRawSubclassData());
8861 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
8862 ID.AddInteger(ST->getMemOperand()->getFlags());
8864 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
8868 ST->isTruncatingStore(), ST->getMemoryVT(),
8869 ST->getMemOperand());
8870 createOperands(
N, Ops);
8872 CSEMap.InsertNode(
N, IP);
8884 const MDNode *Ranges,
bool IsExpanding) {
8897 Alignment, AAInfo, Ranges);
8898 return getLoadVP(AM, ExtType, VT, dl, Chain,
Ptr,
Offset, Mask, EVL, MemVT,
8917 ID.AddInteger(getSyntheticNodeSubclassData<VPLoadSDNode>(
8918 dl.
getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
8922 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8923 cast<VPLoadSDNode>(E)->refineAlignment(MMO);
8927 ExtType, IsExpanding, MemVT, MMO);
8928 createOperands(
N, Ops);
8930 CSEMap.InsertNode(
N, IP);
8946 Mask, EVL, PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges,
8955 Mask, EVL, VT, MMO, IsExpanding);
8964 const AAMDNodes &AAInfo,
bool IsExpanding) {
8967 EVL, PtrInfo, MemVT, Alignment, MMOFlags, AAInfo,
nullptr,
8977 EVL, MemVT, MMO, IsExpanding);
8983 auto *LD = cast<VPLoadSDNode>(OrigLoad);
8984 assert(LD->getOffset().isUndef() &&
"Load is already a indexed load!");
8987 LD->getMemOperand()->getFlags() &
8991 LD->getVectorLength(), LD->getPointerInfo(),
8992 LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo(),
8993 nullptr, LD->isExpandingLoad());
9000 bool IsCompressing) {
9010 ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
9011 dl.
getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9015 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9016 cast<VPStoreSDNode>(E)->refineAlignment(MMO);
9020 IsTruncating, IsCompressing, MemVT, MMO);
9021 createOperands(
N, Ops);
9023 CSEMap.InsertNode(
N, IP);
9036 bool IsCompressing) {
9057 bool IsCompressing) {
9064 false, IsCompressing);
9067 "Should only be a truncating store, not extending!");
9070 "Cannot use trunc store to convert to or from a vector!");
9073 "Cannot use trunc store to change the number of vector elements!");
9077 SDValue Ops[] = {Chain, Val,
Ptr, Undef, Mask, EVL};
9081 ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
9086 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9087 cast<VPStoreSDNode>(E)->refineAlignment(MMO);
9093 createOperands(
N, Ops);
9095 CSEMap.InsertNode(
N, IP);
9105 auto *ST = cast<VPStoreSDNode>(OrigStore);
9106 assert(ST->getOffset().isUndef() &&
"Store is already an indexed store!");
9108 SDValue Ops[] = {ST->getChain(), ST->getValue(),
Base,
9109 Offset, ST->getMask(), ST->getVectorLength()};
9112 ID.AddInteger(ST->getMemoryVT().getRawBits());
9113 ID.AddInteger(ST->getRawSubclassData());
9114 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
9115 ID.AddInteger(ST->getMemOperand()->getFlags());
9117 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9120 auto *
N = newSDNode<VPStoreSDNode>(
9122 ST->isCompressingStore(), ST->getMemoryVT(), ST->getMemOperand());
9123 createOperands(
N, Ops);
9125 CSEMap.InsertNode(
N, IP);
9145 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedLoadSDNode>(
9146 DL.getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
9150 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9151 cast<VPStridedLoadSDNode>(E)->refineAlignment(MMO);
9156 newSDNode<VPStridedLoadSDNode>(
DL.getIROrder(),
DL.getDebugLoc(), VTs, AM,
9157 ExtType, IsExpanding, MemVT, MMO);
9158 createOperands(
N, Ops);
9159 CSEMap.InsertNode(
N, IP);
9173 Undef, Stride, Mask, EVL, VT, MMO, IsExpanding);
9182 Stride, Mask, EVL, MemVT, MMO, IsExpanding);
9191 bool IsTruncating,
bool IsCompressing) {
9201 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
9202 DL.getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9205 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9206 cast<VPStridedStoreSDNode>(E)->refineAlignment(MMO);
9209 auto *
N = newSDNode<VPStridedStoreSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
9210 VTs, AM, IsTruncating,
9211 IsCompressing, MemVT, MMO);
9212 createOperands(
N, Ops);
9214 CSEMap.InsertNode(
N, IP);
9226 bool IsCompressing) {
9233 false, IsCompressing);
9236 "Should only be a truncating store, not extending!");
9239 "Cannot use trunc store to convert to or from a vector!");
9242 "Cannot use trunc store to change the number of vector elements!");
9246 SDValue Ops[] = {Chain, Val,
Ptr, Undef, Stride, Mask, EVL};
9250 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
9254 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9255 cast<VPStridedStoreSDNode>(E)->refineAlignment(MMO);
9258 auto *
N = newSDNode<VPStridedStoreSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
9260 IsCompressing, SVT, MMO);
9261 createOperands(
N, Ops);
9263 CSEMap.InsertNode(
N, IP);
9273 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9278 ID.AddInteger(getSyntheticNodeSubclassData<VPGatherSDNode>(
9283 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9284 cast<VPGatherSDNode>(E)->refineAlignment(MMO);
9289 VT, MMO, IndexType);
9290 createOperands(
N, Ops);
9292 assert(
N->getMask().getValueType().getVectorElementCount() ==
9293 N->getValueType(0).getVectorElementCount() &&
9294 "Vector width mismatch between mask and data");
9295 assert(
N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9296 N->getValueType(0).getVectorElementCount().isScalable() &&
9297 "Scalable flags of index and data do not match");
9299 N->getIndex().getValueType().getVectorElementCount(),
9300 N->getValueType(0).getVectorElementCount()) &&
9301 "Vector width mismatch between index and data");
9302 assert(isa<ConstantSDNode>(
N->getScale()) &&
9303 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9304 "Scale should be a constant power of 2");
9306 CSEMap.InsertNode(
N, IP);
9317 assert(Ops.
size() == 7 &&
"Incompatible number of operands");
9322 ID.AddInteger(getSyntheticNodeSubclassData<VPScatterSDNode>(
9327 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9328 cast<VPScatterSDNode>(E)->refineAlignment(MMO);
9332 VT, MMO, IndexType);
9333 createOperands(
N, Ops);
9335 assert(
N->getMask().getValueType().getVectorElementCount() ==
9336 N->getValue().getValueType().getVectorElementCount() &&
9337 "Vector width mismatch between mask and data");
9339 N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9340 N->getValue().getValueType().getVectorElementCount().isScalable() &&
9341 "Scalable flags of index and data do not match");
9343 N->getIndex().getValueType().getVectorElementCount(),
9344 N->getValue().getValueType().getVectorElementCount()) &&
9345 "Vector width mismatch between index and data");
9346 assert(isa<ConstantSDNode>(
N->getScale()) &&
9347 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9348 "Scale should be a constant power of 2");
9350 CSEMap.InsertNode(
N, IP);
9365 "Unindexed masked load with an offset!");
9372 ID.AddInteger(getSyntheticNodeSubclassData<MaskedLoadSDNode>(
9373 dl.
getIROrder(), VTs, AM, ExtTy, isExpanding, MemVT, MMO));
9377 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9378 cast<MaskedLoadSDNode>(E)->refineAlignment(MMO);
9382 AM, ExtTy, isExpanding, MemVT, MMO);
9383 createOperands(
N, Ops);
9385 CSEMap.InsertNode(
N, IP);
9396 assert(LD->getOffset().isUndef() &&
"Masked load is already a indexed load!");
9398 Offset, LD->getMask(), LD->getPassThru(),
9399 LD->getMemoryVT(), LD->getMemOperand(), AM,
9400 LD->getExtensionType(), LD->isExpandingLoad());
9408 bool IsCompressing) {
9410 "Invalid chain type");
9413 "Unindexed masked store with an offset!");
9420 ID.AddInteger(getSyntheticNodeSubclassData<MaskedStoreSDNode>(
9421 dl.
getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9425 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9426 cast<MaskedStoreSDNode>(E)->refineAlignment(MMO);
9431 IsTruncating, IsCompressing, MemVT, MMO);
9432 createOperands(
N, Ops);
9434 CSEMap.InsertNode(
N, IP);
9445 assert(ST->getOffset().isUndef() &&
9446 "Masked store is already a indexed store!");
9448 ST->getMask(), ST->getMemoryVT(), ST->getMemOperand(),
9449 AM, ST->isTruncatingStore(), ST->isCompressingStore());
9457 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9462 ID.AddInteger(getSyntheticNodeSubclassData<MaskedGatherSDNode>(
9463 dl.
getIROrder(), VTs, MemVT, MMO, IndexType, ExtTy));
9467 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9468 cast<MaskedGatherSDNode>(E)->refineAlignment(MMO);
9473 VTs, MemVT, MMO, IndexType, ExtTy);
9474 createOperands(
N, Ops);
9476 assert(
N->getPassThru().getValueType() ==
N->getValueType(0) &&
9477 "Incompatible type of the PassThru value in MaskedGatherSDNode");
9478 assert(
N->getMask().getValueType().getVectorElementCount() ==
9479 N->getValueType(0).getVectorElementCount() &&
9480 "Vector width mismatch between mask and data");
9481 assert(
N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9482 N->getValueType(0).getVectorElementCount().isScalable() &&
9483 "Scalable flags of index and data do not match");
9485 N->getIndex().getValueType().getVectorElementCount(),
9486 N->getValueType(0).getVectorElementCount()) &&
9487 "Vector width mismatch between index and data");
9488 assert(isa<ConstantSDNode>(
N->getScale()) &&
9489 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9490 "Scale should be a constant power of 2");
9492 CSEMap.InsertNode(
N, IP);
9504 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9509 ID.AddInteger(getSyntheticNodeSubclassData<MaskedScatterSDNode>(
9510 dl.
getIROrder(), VTs, MemVT, MMO, IndexType, IsTrunc));
9514 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9515 cast<MaskedScatterSDNode>(E)->refineAlignment(MMO);
9520 VTs, MemVT, MMO, IndexType, IsTrunc);
9521 createOperands(
N, Ops);
9523 assert(
N->getMask().getValueType().getVectorElementCount() ==
9524 N->getValue().getValueType().getVectorElementCount() &&
9525 "Vector width mismatch between mask and data");
9527 N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9528 N->getValue().getValueType().getVectorElementCount().isScalable() &&
9529 "Scalable flags of index and data do not match");
9531 N->getIndex().getValueType().getVectorElementCount(),
9532 N->getValue().getValueType().getVectorElementCount()) &&
9533 "Vector width mismatch between index and data");
9534 assert(isa<ConstantSDNode>(
N->getScale()) &&
9535 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9536 "Scale should be a constant power of 2");
9538 CSEMap.InsertNode(
N, IP);
9553 ID.AddInteger(getSyntheticNodeSubclassData<FPStateAccessSDNode>(
9558 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9563 createOperands(
N, Ops);
9565 CSEMap.InsertNode(
N, IP);
9580 ID.AddInteger(getSyntheticNodeSubclassData<FPStateAccessSDNode>(
9585 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9590 createOperands(
N, Ops);
9592 CSEMap.InsertNode(
N, IP);
9612 if (
auto *CondC = dyn_cast<ConstantSDNode>(
Cond))
9613 return CondC->isZero() ?
F :
T;
9619 if (CondC->isZero())
9645 return !Val || Val->getAPIntValue().uge(
X.getScalarValueSizeInBits());
9651 if (
X.getValueType().getScalarType() == MVT::i1)
9664 bool HasNan = (XC && XC->getValueAPF().isNaN()) ||
9666 bool HasInf = (XC && XC->getValueAPF().isInfinity()) ||
9669 if (Flags.hasNoNaNs() && (HasNan ||
X.isUndef() ||
Y.isUndef()))
9672 if (Flags.hasNoInfs() && (HasInf ||
X.isUndef() ||
Y.isUndef()))
9695 if (Opcode ==
ISD::FMUL && Flags.hasNoNaNs() && Flags.hasNoSignedZeros())
9710 switch (Ops.
size()) {
9712 case 1:
return getNode(Opcode,
DL, VT,
static_cast<const SDValue>(Ops[0]));
9713 case 2:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1]);
9714 case 3:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Ops[2]);
9729 return getNode(Opcode,
DL, VT, Ops, Flags);
9734 unsigned NumOps = Ops.
size();
9737 case 1:
return getNode(Opcode,
DL, VT, Ops[0], Flags);
9738 case 2:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Flags);
9739 case 3:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Ops[2], Flags);
9744 for (
const auto &
Op : Ops)
9746 "Operand is DELETED_NODE!");
9761 assert(NumOps == 5 &&
"SELECT_CC takes 5 operands!");
9763 "LHS and RHS of condition must have same type!");
9765 "True and False arms of SelectCC must have same type!");
9767 "select_cc node must be of same type as true and false value!");
9771 "Expected select_cc with vector result to have the same sized "
9772 "comparison type!");
9775 assert(NumOps == 5 &&
"BR_CC takes 5 operands!");
9777 "LHS/RHS of comparison should match types!");
9783 Opcode = ISD::VP_XOR;
9788 Opcode = ISD::VP_AND;
9790 case ISD::VP_REDUCE_MUL:
9793 Opcode = ISD::VP_REDUCE_AND;
9795 case ISD::VP_REDUCE_ADD:
9798 Opcode = ISD::VP_REDUCE_XOR;
9800 case ISD::VP_REDUCE_SMAX:
9801 case ISD::VP_REDUCE_UMIN:
9805 Opcode = ISD::VP_REDUCE_AND;
9807 case ISD::VP_REDUCE_SMIN:
9808 case ISD::VP_REDUCE_UMAX:
9812 Opcode = ISD::VP_REDUCE_OR;
9820 if (VT != MVT::Glue) {
9825 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
9828 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
9829 createOperands(
N, Ops);
9831 CSEMap.InsertNode(
N, IP);
9833 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
9834 createOperands(
N, Ops);
9854 return getNode(Opcode,
DL, VTList, Ops, Flags);
9863 for (
const auto &
Op : Ops)
9865 "Operand is DELETED_NODE!");
9874 "Invalid add/sub overflow op!");
9876 Ops[0].getValueType() == Ops[1].getValueType() &&
9877 Ops[0].getValueType() == VTList.
VTs[0] &&
9878 "Binary operator types must match!");
9879 SDValue N1 = Ops[0], N2 = Ops[1];
9885 if (N2CV && N2CV->
isZero()) {
9917 "Invalid add/sub overflow op!");
9919 Ops[0].getValueType() == Ops[1].getValueType() &&
9920 Ops[0].getValueType() == VTList.
VTs[0] &&
9921 Ops[2].getValueType() == VTList.
VTs[1] &&
9922 "Binary operator types must match!");
9928 VTList.
VTs[0] == Ops[0].getValueType() &&
9929 VTList.
VTs[0] == Ops[1].getValueType() &&
9930 "Binary operator types must match!");
9936 unsigned OutWidth = Width * 2;
9940 Val = Val.
sext(OutWidth);
9941 Mul =
Mul.sext(OutWidth);
9943 Val = Val.
zext(OutWidth);
9944 Mul =
Mul.zext(OutWidth);
9958 VTList.
VTs[0] == Ops[0].getValueType() &&
"frexp type mismatch");
9974 "Invalid STRICT_FP_EXTEND!");
9976 Ops[1].getValueType().isFloatingPoint() &&
"Invalid FP cast!");
9978 "STRICT_FP_EXTEND result type should be vector iff the operand "
9982 Ops[1].getValueType().getVectorElementCount()) &&
9983 "Vector element count mismatch!");
9985 "Invalid fpext node, dst <= src!");
9988 assert(VTList.
NumVTs == 2 && Ops.
size() == 3 &&
"Invalid STRICT_FP_ROUND!");
9990 "STRICT_FP_ROUND result type should be vector iff the operand "
9994 Ops[1].getValueType().getVectorElementCount()) &&
9995 "Vector element count mismatch!");
9997 Ops[1].getValueType().isFloatingPoint() &&
9998 VTList.
VTs[0].
bitsLT(Ops[1].getValueType()) &&
9999 isa<ConstantSDNode>(Ops[2]) &&
10000 (Ops[2]->getAsZExtVal() == 0 || Ops[2]->getAsZExtVal() == 1) &&
10001 "Invalid STRICT_FP_ROUND!");
10011 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
10012 return getNode(Opcode,
DL, VT, N1, N2, N3.getOperand(0));
10013 else if (N3.getOpcode() ==
ISD::AND)
10014 if (
ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
10018 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
10019 return getNode(Opcode,
DL, VT, N1, N2, N3.getOperand(0));
10027 if (VTList.
VTs[VTList.
NumVTs-1] != MVT::Glue) {
10030 void *IP =
nullptr;
10031 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
10034 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTList);
10035 createOperands(
N, Ops);
10036 CSEMap.InsertNode(
N, IP);
10038 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTList);
10039 createOperands(
N, Ops);
10042 N->setFlags(Flags);
10051 return getNode(Opcode,
DL, VTList, std::nullopt);
10057 return getNode(Opcode,
DL, VTList, Ops);
10063 return getNode(Opcode,
DL, VTList, Ops);
10068 SDValue Ops[] = { N1, N2, N3 };
10069 return getNode(Opcode,
DL, VTList, Ops);
10074 SDValue Ops[] = { N1, N2, N3, N4 };
10075 return getNode(Opcode,
DL, VTList, Ops);
10081 SDValue Ops[] = { N1, N2, N3, N4, N5 };
10082 return getNode(Opcode,
DL, VTList, Ops);
10086 return makeVTList(SDNode::getValueTypeList(VT), 1);
10095 void *IP =
nullptr;
10101 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 2);
10102 VTListMap.InsertNode(Result, IP);
10104 return Result->getSDVTList();
10114 void *IP =
nullptr;
10121 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 3);
10122 VTListMap.InsertNode(Result, IP);
10124 return Result->getSDVTList();
10135 void *IP =
nullptr;
10143 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 4);
10144 VTListMap.InsertNode(Result, IP);
10146 return Result->getSDVTList();
10150 unsigned NumVTs = VTs.
size();
10152 ID.AddInteger(NumVTs);
10153 for (
unsigned index = 0; index < NumVTs; index++) {
10154 ID.AddInteger(VTs[index].getRawBits());
10157 void *IP =
nullptr;
10162 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, NumVTs);
10163 VTListMap.InsertNode(Result, IP);
10165 return Result->getSDVTList();
10176 assert(
N->getNumOperands() == 1 &&
"Update with wrong number of operands");
10179 if (
Op ==
N->getOperand(0))
return N;
10182 void *InsertPos =
nullptr;
10183 if (
SDNode *Existing = FindModifiedNodeSlot(
N,
Op, InsertPos))
10188 if (!RemoveNodeFromCSEMaps(
N))
10189 InsertPos =
nullptr;
10192 N->OperandList[0].set(
Op);
10196 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10201 assert(
N->getNumOperands() == 2 &&
"Update with wrong number of operands");
10204 if (Op1 ==
N->getOperand(0) && Op2 ==
N->getOperand(1))
10208 void *InsertPos =
nullptr;
10209 if (
SDNode *Existing = FindModifiedNodeSlot(
N, Op1, Op2, InsertPos))
10214 if (!RemoveNodeFromCSEMaps(
N))
10215 InsertPos =
nullptr;
10218 if (
N->OperandList[0] != Op1)
10219 N->OperandList[0].set(Op1);
10220 if (
N->OperandList[1] != Op2)
10221 N->OperandList[1].set(Op2);
10225 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10231 SDValue Ops[] = { Op1, Op2, Op3 };
10238 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
10245 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
10251 unsigned NumOps = Ops.
size();
10252 assert(
N->getNumOperands() == NumOps &&
10253 "Update with wrong number of operands");
10256 if (std::equal(Ops.
begin(), Ops.
end(),
N->op_begin()))
10260 void *InsertPos =
nullptr;
10261 if (
SDNode *Existing = FindModifiedNodeSlot(
N, Ops, InsertPos))
10266 if (!RemoveNodeFromCSEMaps(
N))
10267 InsertPos =
nullptr;
10270 for (
unsigned i = 0; i != NumOps; ++i)
10271 if (
N->OperandList[i] != Ops[i])
10272 N->OperandList[i].set(Ops[i]);
10276 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10293 if (NewMemRefs.
empty()) {
10299 if (NewMemRefs.
size() == 1) {
10300 N->MemRefs = NewMemRefs[0];
10306 Allocator.template Allocate<MachineMemOperand *>(NewMemRefs.
size());
10308 N->MemRefs = MemRefsBuffer;
10309 N->NumMemRefs =
static_cast<int>(NewMemRefs.
size());
10332 SDValue Ops[] = { Op1, Op2 };
10340 SDValue Ops[] = { Op1, Op2, Op3 };
10373 SDValue Ops[] = { Op1, Op2 };
10381 New->setNodeId(-1);
10401 unsigned Order = std::min(
N->getIROrder(), OLoc.
getIROrder());
10402 N->setIROrder(Order);
10425 void *IP =
nullptr;
10426 if (VTs.
VTs[VTs.
NumVTs-1] != MVT::Glue) {
10430 return UpdateSDLocOnMergeSDNode(ON,
SDLoc(
N));
10433 if (!RemoveNodeFromCSEMaps(
N))
10438 N->ValueList = VTs.
VTs;
10448 if (Used->use_empty())
10449 DeadNodeSet.
insert(Used);
10454 MN->clearMemRefs();
10458 createOperands(
N, Ops);
10462 if (!DeadNodeSet.
empty()) {
10464 for (
SDNode *
N : DeadNodeSet)
10465 if (
N->use_empty())
10471 CSEMap.InsertNode(
N, IP);
10476 unsigned OrigOpc = Node->getOpcode();
10481#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
10482 case ISD::STRICT_##DAGN: NewOpc = ISD::DAGN; break;
10483#define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
10484 case ISD::STRICT_##DAGN: NewOpc = ISD::SETCC; break;
10485#include "llvm/IR/ConstrainedOps.def"
10488 assert(Node->getNumValues() == 2 &&
"Unexpected number of results!");
10491 SDValue InputChain = Node->getOperand(0);
10496 for (
unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
10539 SDValue Ops[] = { Op1, Op2 };
10547 SDValue Ops[] = { Op1, Op2, Op3 };
10561 SDValue Ops[] = { Op1, Op2 };
10569 SDValue Ops[] = { Op1, Op2, Op3 };
10584 SDValue Ops[] = { Op1, Op2 };
10593 SDValue Ops[] = { Op1, Op2, Op3 };
10614 bool DoCSE = VTs.
VTs[VTs.
NumVTs-1] != MVT::Glue;
10616 void *IP =
nullptr;
10622 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
10623 return cast<MachineSDNode>(UpdateSDLocOnMergeSDNode(E,
DL));
10628 N = newSDNode<MachineSDNode>(~Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
10629 createOperands(
N, Ops);
10632 CSEMap.InsertNode(
N, IP);
10645 VT, Operand, SRIdxVal);
10655 VT, Operand, Subreg, SRIdxVal);
10672 if (VTList.
VTs[VTList.
NumVTs - 1] != MVT::Glue) {
10675 void *IP =
nullptr;
10677 E->intersectFlagsWith(Flags);
10687 if (VTList.
VTs[VTList.
NumVTs - 1] != MVT::Glue) {
10690 void *IP =
nullptr;
10691 if (FindNodeOrInsertPos(
ID,
SDLoc(), IP))
10701 SDNode *
N,
unsigned R,
bool IsIndirect,
10703 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10704 "Expected inlined-at fields to agree");
10707 {}, IsIndirect,
DL, O,
10716 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10717 "Expected inlined-at fields to agree");
10730 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10731 "Expected inlined-at fields to agree");
10742 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10743 "Expected inlined-at fields to agree");
10746 Dependencies, IsIndirect,
DL, O,
10752 unsigned VReg,
bool IsIndirect,
10754 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10755 "Expected inlined-at fields to agree");
10758 {}, IsIndirect,
DL, O,
10766 unsigned O,
bool IsVariadic) {
10767 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10768 "Expected inlined-at fields to agree");
10771 DL, O, IsVariadic);
10775 unsigned OffsetInBits,
unsigned SizeInBits,
10776 bool InvalidateDbg) {
10779 assert(FromNode && ToNode &&
"Can't modify dbg values");
10784 if (
From == To || FromNode == ToNode)
10796 if (Dbg->isInvalidated())
10803 bool Changed =
false;
10804 auto NewLocOps = Dbg->copyLocationOps();
10806 NewLocOps.begin(), NewLocOps.end(),
10808 bool Match = Op == FromLocOp;
10818 auto *Expr = Dbg->getExpression();
10824 if (
auto FI = Expr->getFragmentInfo())
10825 if (OffsetInBits + SizeInBits > FI->SizeInBits)
10834 auto AdditionalDependencies = Dbg->getAdditionalDependencies();
10837 Var, Expr, NewLocOps, AdditionalDependencies, Dbg->isIndirect(),
10838 Dbg->getDebugLoc(), std::max(ToNode->
getIROrder(), Dbg->getOrder()),
10839 Dbg->isVariadic());
10842 if (InvalidateDbg) {
10844 Dbg->setIsInvalidated();
10845 Dbg->setIsEmitted();
10851 "Transferred DbgValues should depend on the new SDNode");
10857 if (!
N.getHasDebugValue())
10862 if (DV->isInvalidated())
10864 switch (
N.getOpcode()) {
10870 if (!isa<ConstantSDNode>(N0)) {
10871 bool RHSConstant = isa<ConstantSDNode>(N1);
10874 Offset =
N.getConstantOperandVal(1);
10877 if (!RHSConstant && DV->isIndirect())
10884 auto *DIExpr = DV->getExpression();
10885 auto NewLocOps = DV->copyLocationOps();
10886 bool Changed =
false;
10887 size_t OrigLocOpsSize = NewLocOps.size();
10888 for (
size_t i = 0; i < OrigLocOpsSize; ++i) {
10893 NewLocOps[i].getSDNode() != &
N)
10904 const auto *TmpDIExpr =
10912 NewLocOps.push_back(
RHS);
10918 assert(Changed &&
"Salvage target doesn't use N");
10921 DV->isVariadic() || OrigLocOpsSize != NewLocOps.size();
10923 auto AdditionalDependencies = DV->getAdditionalDependencies();
10925 DV->getVariable(), DIExpr, NewLocOps, AdditionalDependencies,
10926 DV->isIndirect(), DV->getDebugLoc(), DV->getOrder(), IsVariadic);
10928 DV->setIsInvalidated();
10929 DV->setIsEmitted();
10931 N0.
getNode()->dumprFull(
this);
10932 dbgs() <<
" into " << *DIExpr <<
'\n');
10939 TypeSize ToSize =
N.getValueSizeInBits(0);
10943 auto NewLocOps = DV->copyLocationOps();
10944 bool Changed =
false;
10945 for (
size_t i = 0; i < NewLocOps.size(); ++i) {
10947 NewLocOps[i].getSDNode() != &
N)
10954 assert(Changed &&
"Salvage target doesn't use N");
10959 DV->getAdditionalDependencies(), DV->isIndirect(),
10960 DV->getDebugLoc(), DV->getOrder(), DV->isVariadic());
10963 DV->setIsInvalidated();
10964 DV->setIsEmitted();
10966 dbgs() <<
" into " << *DbgExpression <<
'\n');
10973 assert(!Dbg->getSDNodes().empty() &&
10974 "Salvaged DbgValue should depend on a new SDNode");
10982 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) &&
10983 "Expected inlined-at fields to agree");
10999 while (UI != UE &&
N == *UI)
11007 :
SelectionDAG::DAGUpdateListener(d), UI(ui), UE(ue) {}
11020 "Cannot replace with this method!");
11036 RAUWUpdateListener Listener(*
this, UI, UE);
11041 RemoveNodeFromCSEMaps(
User);
11053 }
while (UI != UE && *UI ==
User);
11056 AddModifiedNodeToCSEMaps(
User);
11072 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i)
11075 "Cannot use this version of ReplaceAllUsesWith!");
11083 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i)
11084 if (
From->hasAnyUseOfValue(i)) {
11085 assert((i < To->getNumValues()) &&
"Invalid To location");
11094 RAUWUpdateListener Listener(*
this, UI, UE);
11099 RemoveNodeFromCSEMaps(
User);
11111 }
while (UI != UE && *UI ==
User);
11115 AddModifiedNodeToCSEMaps(
User);
11129 if (
From->getNumValues() == 1)
11132 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i) {
11142 RAUWUpdateListener Listener(*
this, UI, UE);
11147 RemoveNodeFromCSEMaps(
User);
11153 bool To_IsDivergent =
false;
11160 }
while (UI != UE && *UI ==
User);
11162 if (To_IsDivergent !=
From->isDivergent())
11167 AddModifiedNodeToCSEMaps(
User);
11180 if (
From == To)
return;
11183 if (
From.getNode()->getNumValues() == 1) {
11195 UE =
From.getNode()->use_end();
11196 RAUWUpdateListener Listener(*
this, UI, UE);
11199 bool UserRemovedFromCSEMaps =
false;
11209 if (
Use.getResNo() !=
From.getResNo()) {
11216 if (!UserRemovedFromCSEMaps) {
11217 RemoveNodeFromCSEMaps(
User);
11218 UserRemovedFromCSEMaps =
true;
11225 }
while (UI != UE && *UI ==
User);
11228 if (!UserRemovedFromCSEMaps)
11233 AddModifiedNodeToCSEMaps(
User);
11252bool operator<(
const UseMemo &L,
const UseMemo &R) {
11253 return (intptr_t)L.User < (intptr_t)R.User;
11263 for (UseMemo &Memo :
Uses)
11264 if (Memo.User ==
N)
11265 Memo.User =
nullptr;
11278 "Conflicting divergence information!");
11283 for (
const auto &
Op :
N->ops()) {
11284 if (
Op.Val.getValueType() != MVT::Other &&
Op.getNode()->isDivergent())
11295 if (
N->SDNodeBits.IsDivergent != IsDivergent) {
11296 N->SDNodeBits.IsDivergent = IsDivergent;
11299 }
while (!Worklist.
empty());
11302void SelectionDAG::CreateTopologicalOrder(std::vector<SDNode *> &Order) {
11304 Order.
reserve(AllNodes.size());
11306 unsigned NOps =
N.getNumOperands();
11309 Order.push_back(&
N);
11311 for (
size_t I = 0;
I != Order.size(); ++
I) {
11313 for (
auto *U :
N->uses()) {
11314 unsigned &UnsortedOps = Degree[U];
11315 if (0 == --UnsortedOps)
11316 Order.push_back(U);
11323 std::vector<SDNode *> TopoOrder;
11324 CreateTopologicalOrder(TopoOrder);
11325 for (
auto *
N : TopoOrder) {
11327 "Divergence bit inconsistency detected");
11350 for (
unsigned i = 0; i != Num; ++i) {
11351 unsigned FromResNo =
From[i].getResNo();
11354 E = FromNode->
use_end(); UI != E; ++UI) {
11356 if (
Use.getResNo() == FromResNo) {
11357 UseMemo Memo = { *UI, i, &
Use };
11358 Uses.push_back(Memo);
11365 RAUOVWUpdateListener Listener(*
this,
Uses);
11367 for (
unsigned UseIndex = 0, UseIndexEnd =
Uses.size();
11368 UseIndex != UseIndexEnd; ) {
11374 if (
User ==
nullptr) {
11380 RemoveNodeFromCSEMaps(
User);
11387 unsigned i =
Uses[UseIndex].Index;
11392 }
while (UseIndex != UseIndexEnd &&
Uses[UseIndex].
User ==
User);
11396 AddModifiedNodeToCSEMaps(
User);
11404 unsigned DAGSize = 0;
11420 unsigned Degree =
N.getNumOperands();
11423 N.setNodeId(DAGSize++);
11425 if (Q != SortedPos)
11426 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q));
11427 assert(SortedPos != AllNodes.end() &&
"Overran node list");
11431 N.setNodeId(Degree);
11443 unsigned Degree =
P->getNodeId();
11444 assert(Degree != 0 &&
"Invalid node degree");
11448 P->setNodeId(DAGSize++);
11449 if (
P->getIterator() != SortedPos)
11450 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(
P));
11451 assert(SortedPos != AllNodes.end() &&
"Overran node list");
11455 P->setNodeId(Degree);
11458 if (Node.getIterator() == SortedPos) {
11462 dbgs() <<
"Overran sorted position:\n";
11464 dbgs() <<
"Checking if this is due to cycles\n";
11471 assert(SortedPos == AllNodes.end() &&
11472 "Topological sort incomplete!");
11474 "First node in topological sort is not the entry token!");
11475 assert(AllNodes.front().getNodeId() == 0 &&
11476 "First node in topological sort has non-zero id!");
11477 assert(AllNodes.front().getNumOperands() == 0 &&
11478 "First node in topological sort has operands!");
11479 assert(AllNodes.back().getNodeId() == (
int)DAGSize-1 &&
11480 "Last node in topologic sort has unexpected id!");
11481 assert(AllNodes.back().use_empty() &&
11482 "Last node in topologic sort has users!");
11490 for (
SDNode *SD : DB->getSDNodes()) {
11494 SD->setHasDebugValue(
true);
11496 DbgInfo->
add(DB, isParameter);
11503 assert(isa<MemSDNode>(NewMemOpChain) &&
"Expected a memop node");
11509 if (OldChain == NewMemOpChain || OldChain.
use_empty())
11510 return NewMemOpChain;
11513 OldChain, NewMemOpChain);
11516 return TokenFactor;
11521 assert(isa<MemSDNode>(NewMemOp.
getNode()) &&
"Expected a memop node");
11529 assert(isa<ExternalSymbolSDNode>(
Op) &&
"Node should be an ExternalSymbol");
11531 auto *Symbol = cast<ExternalSymbolSDNode>(
Op)->getSymbol();
11535 if (OutFunction !=
nullptr)
11543 std::string ErrorStr;
11545 ErrorFormatter <<
"Undefined external symbol ";
11546 ErrorFormatter <<
'"' << Symbol <<
'"';
11556 return Const !=
nullptr && Const->isZero();
11561 return Const !=
nullptr && Const->isZero() && !Const->isNegative();
11566 return Const !=
nullptr && Const->isAllOnes();
11571 return Const !=
nullptr && Const->isOne();
11576 return Const !=
nullptr && Const->isMinSignedValue();
11580 unsigned OperandNo) {
11585 APInt Const = ConstV->getAPIntValue().trunc(V.getScalarValueSizeInBits());
11591 return Const.isZero();
11593 return Const.isOne();
11596 return Const.isAllOnes();
11598 return Const.isMinSignedValue();
11600 return Const.isMaxSignedValue();
11605 return OperandNo == 1 && Const.isZero();
11608 return OperandNo == 1 && Const.isOne();
11613 return ConstFP->isZero() &&
11614 (Flags.hasNoSignedZeros() || ConstFP->isNegative());
11616 return OperandNo == 1 && ConstFP->isZero() &&
11617 (Flags.hasNoSignedZeros() || !ConstFP->isNegative());
11619 return ConstFP->isExactlyValue(1.0);
11621 return OperandNo == 1 && ConstFP->isExactlyValue(1.0);
11625 EVT VT = V.getValueType();
11627 APFloat NeutralAF = !Flags.hasNoNaNs()
11629 : !Flags.hasNoInfs()
11635 return ConstFP->isExactlyValue(NeutralAF);
11644 V = V.getOperand(0);
11649 while (V.getOpcode() ==
ISD::BITCAST && V.getOperand(0).hasOneUse())
11650 V = V.getOperand(0);
11656 V = V.getOperand(0);
11662 V = V.getOperand(0);
11670 unsigned NumBits = V.getScalarValueSizeInBits();
11673 return C && (
C->getAPIntValue().countr_one() >= NumBits);
11677 bool AllowTruncation) {
11678 EVT VT =
N.getValueType();
11687 bool AllowTruncation) {
11694 EVT VecEltVT =
N->getValueType(0).getVectorElementType();
11695 if (
auto *CN = dyn_cast<ConstantSDNode>(
N->getOperand(0))) {
11696 EVT CVT = CN->getValueType(0);
11697 assert(CVT.
bitsGE(VecEltVT) &&
"Illegal splat_vector element extension");
11698 if (AllowTruncation || CVT == VecEltVT)
11705 ConstantSDNode *CN = BV->getConstantSplatNode(DemandedElts, &UndefElements);
11710 if (CN && (UndefElements.
none() || AllowUndefs)) {
11712 EVT NSVT =
N.getValueType().getScalarType();
11713 assert(CVT.
bitsGE(NSVT) &&
"Illegal build vector element extension");
11714 if (AllowTruncation || (CVT == NSVT))
11723 EVT VT =
N.getValueType();
11731 const APInt &DemandedElts,
11732 bool AllowUndefs) {
11739 BV->getConstantFPSplatNode(DemandedElts, &UndefElements);
11741 if (CN && (UndefElements.
none() || AllowUndefs))
11756 return C &&
C->isZero();
11762 return C &&
C->isOne();
11767 unsigned BitWidth =
N.getScalarValueSizeInBits();
11769 return C &&
C->isAllOnes() &&
C->getValueSizeInBits(0) ==
BitWidth;
11776GlobalAddressSDNode::GlobalAddressSDNode(
unsigned Opc,
unsigned Order,
11779 int64_t o,
unsigned TF)
11780 :
SDNode(Opc, Order,
DL, getSDVTList(VT)),
Offset(o), TargetFlags(TF) {
11785 EVT VT,
unsigned SrcAS,
11787 :
SDNode(ISD::ADDRSPACECAST, Order, dl, getSDVTList(VT)),
11788 SrcAddrSpace(SrcAS), DestAddrSpace(DestAS) {}
11792 :
SDNode(Opc, Order, dl, VTs), MemoryVT(memvt), MMO(mmo) {
11816 std::vector<EVT> VTs;
11829const EVT *SDNode::getValueTypeList(
EVT VT) {
11830 static std::set<EVT, EVT::compareRawBits> EVTs;
11831 static EVTArray SimpleVTArray;
11836 return &(*EVTs.insert(VT).first);
11850 if (UI.getUse().getResNo() ==
Value) {
11867 if (UI.getUse().getResNo() ==
Value)
11905 return any_of(
N->op_values(),
11906 [
this](
SDValue Op) { return this == Op.getNode(); });
11920 unsigned Depth)
const {
11921 if (*
this == Dest)
return true;
11925 if (
Depth == 0)
return false;
11945 return Op.reachesChainWithoutSideEffects(Dest, Depth - 1);
11950 if (
LoadSDNode *Ld = dyn_cast<LoadSDNode>(*
this)) {
11951 if (Ld->isUnordered())
11952 return Ld->getChain().reachesChainWithoutSideEffects(Dest,
Depth-1);
11971 bool AllowPartials) {
11980 return Op.getOpcode() ==
unsigned(BinOp);
11986 unsigned CandidateBinOp =
Op.getOpcode();
11987 if (
Op.getValueType().isFloatingPoint()) {
11989 switch (CandidateBinOp) {
11991 if (!Flags.hasNoSignedZeros() || !Flags.hasAllowReassociation())
12001 auto PartialReduction = [&](
SDValue Op,
unsigned NumSubElts) {
12002 if (!AllowPartials || !
Op)
12004 EVT OpVT =
Op.getValueType();
12027 unsigned Stages =
Log2_32(
Op.getValueType().getVectorNumElements());
12029 for (
unsigned i = 0; i < Stages; ++i) {
12030 unsigned MaskEnd = (1 << i);
12032 if (
Op.getOpcode() != CandidateBinOp)
12033 return PartialReduction(PrevOp, MaskEnd);
12042 Shuffle = dyn_cast<ShuffleVectorSDNode>(Op1);
12049 return PartialReduction(PrevOp, MaskEnd);
12054 return PartialReduction(PrevOp, MaskEnd);
12061 while (
Op.getOpcode() == CandidateBinOp) {
12062 unsigned NumElts =
Op.getValueType().getVectorNumElements();
12070 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
12071 if (NumSrcElts != (2 * NumElts))
12086 EVT VT =
N->getValueType(0);
12095 else if (NE > ResNE)
12098 if (
N->getNumValues() == 2) {
12101 EVT VT1 =
N->getValueType(1);
12105 for (i = 0; i != NE; ++i) {
12106 for (
unsigned j = 0, e =
N->getNumOperands(); j != e; ++j) {
12107 SDValue Operand =
N->getOperand(j);
12126 assert(
N->getNumValues() == 1 &&
12127 "Can't unroll a vector with multiple results!");
12133 for (i= 0; i != NE; ++i) {
12134 for (
unsigned j = 0, e =
N->getNumOperands(); j != e; ++j) {
12135 SDValue Operand =
N->getOperand(j);
12148 switch (
N->getOpcode()) {
12175 for (; i < ResNE; ++i)
12184 unsigned Opcode =
N->getOpcode();
12188 "Expected an overflow opcode");
12190 EVT ResVT =
N->getValueType(0);
12191 EVT OvVT =
N->getValueType(1);
12200 else if (NE > ResNE)
12212 for (
unsigned i = 0; i < NE; ++i) {
12213 SDValue Res =
getNode(Opcode, dl, VTs, LHSScalars[i], RHSScalars[i]);
12236 if (LD->isVolatile() ||
Base->isVolatile())
12239 if (!LD->isSimple())
12241 if (LD->isIndexed() ||
Base->isIndexed())
12243 if (LD->getChain() !=
Base->getChain())
12245 EVT VT = LD->getMemoryVT();
12253 if (BaseLocDecomp.equalBaseIndex(LocDecomp, *
this,
Offset))
12254 return (Dist * (int64_t)Bytes ==
Offset);
12263 int64_t GVOffset = 0;
12275 int FrameIdx = INT_MIN;
12276 int64_t FrameOffset = 0;
12278 FrameIdx = FI->getIndex();
12280 isa<FrameIndexSDNode>(
Ptr.getOperand(0))) {
12282 FrameIdx = cast<FrameIndexSDNode>(
Ptr.getOperand(0))->getIndex();
12283 FrameOffset =
Ptr.getConstantOperandVal(1);
12286 if (FrameIdx != INT_MIN) {
12291 return std::nullopt;
12301 "Split node must be a scalar type");
12306 return std::make_pair(
Lo,
Hi);
12319 return std::make_pair(LoVT, HiVT);
12327 bool *HiIsEmpty)
const {
12337 "Mixing fixed width and scalable vectors when enveloping a type");
12342 *HiIsEmpty =
false;
12350 return std::make_pair(LoVT, HiVT);
12355std::pair<SDValue, SDValue>
12360 "Splitting vector with an invalid mixture of fixed and scalable "
12363 N.getValueType().getVectorMinNumElements() &&
12364 "More vector elements requested than available!");
12374 return std::make_pair(
Lo,
Hi);
12381 EVT VT =
N.getValueType();
12383 "Expecting the mask to be an evenly-sized vector");
12391 return std::make_pair(
Lo,
Hi);
12396 EVT VT =
N.getValueType();
12405 unsigned Start,
unsigned Count,
12407 EVT VT =
Op.getValueType();
12410 if (EltVT ==
EVT())
12413 for (
unsigned i = Start, e = Start + Count; i != e; ++i) {
12426 return Val.MachineCPVal->getType();
12427 return Val.ConstVal->getType();
12431 unsigned &SplatBitSize,
12432 bool &HasAnyUndefs,
12433 unsigned MinSplatBits,
12434 bool IsBigEndian)
const {
12438 if (MinSplatBits > VecWidth)
12443 SplatValue =
APInt(VecWidth, 0);
12444 SplatUndef =
APInt(VecWidth, 0);
12451 assert(NumOps > 0 &&
"isConstantSplat has 0-size build vector");
12454 for (
unsigned j = 0; j < NumOps; ++j) {
12455 unsigned i = IsBigEndian ? NumOps - 1 - j : j;
12457 unsigned BitPos = j * EltWidth;
12460 SplatUndef.
setBits(BitPos, BitPos + EltWidth);
12461 else if (
auto *CN = dyn_cast<ConstantSDNode>(OpVal))
12462 SplatValue.
insertBits(CN->getAPIntValue().zextOrTrunc(EltWidth), BitPos);
12463 else if (
auto *CN = dyn_cast<ConstantFPSDNode>(OpVal))
12464 SplatValue.
insertBits(CN->getValueAPF().bitcastToAPInt(), BitPos);
12471 HasAnyUndefs = (SplatUndef != 0);
12474 while (VecWidth > 8) {
12479 unsigned HalfSize = VecWidth / 2;
12486 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) ||
12487 MinSplatBits > HalfSize)
12490 SplatValue = HighValue | LowValue;
12491 SplatUndef = HighUndef & LowUndef;
12493 VecWidth = HalfSize;
12502 SplatBitSize = VecWidth;
12509 if (UndefElements) {
12510 UndefElements->
clear();
12511 UndefElements->
resize(NumOps);
12517 for (
unsigned i = 0; i != NumOps; ++i) {
12518 if (!DemandedElts[i])
12521 if (
Op.isUndef()) {
12523 (*UndefElements)[i] =
true;
12524 }
else if (!Splatted) {
12526 }
else if (Splatted !=
Op) {
12532 unsigned FirstDemandedIdx = DemandedElts.
countr_zero();
12534 "Can only have a splat without a constant for all undefs.");
12551 if (UndefElements) {
12552 UndefElements->
clear();
12553 UndefElements->
resize(NumOps);
12561 for (
unsigned I = 0;
I != NumOps; ++
I)
12563 (*UndefElements)[
I] =
true;
12566 for (
unsigned SeqLen = 1; SeqLen < NumOps; SeqLen *= 2) {
12567 Sequence.append(SeqLen,
SDValue());
12568 for (
unsigned I = 0;
I != NumOps; ++
I) {
12569 if (!DemandedElts[
I])
12571 SDValue &SeqOp = Sequence[
I % SeqLen];
12573 if (
Op.isUndef()) {
12578 if (SeqOp && !SeqOp.
isUndef() && SeqOp !=
Op) {
12584 if (!Sequence.empty())
12588 assert(Sequence.empty() &&
"Failed to empty non-repeating sequence pattern");
12601 return dyn_cast_or_null<ConstantSDNode>(
12607 return dyn_cast_or_null<ConstantSDNode>(
getSplatValue(UndefElements));
12613 return dyn_cast_or_null<ConstantFPSDNode>(
12619 return dyn_cast_or_null<ConstantFPSDNode>(
getSplatValue(UndefElements));
12626 dyn_cast_or_null<ConstantFPSDNode>(
getSplatValue(UndefElements))) {
12629 const APFloat &APF = CN->getValueAPF();
12635 return IntVal.exactLogBase2();
12641 bool IsLittleEndian,
unsigned DstEltSizeInBits,
12649 assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
12650 "Invalid bitcast scale");
12655 BitVector SrcUndeElements(NumSrcOps,
false);
12657 for (
unsigned I = 0;
I != NumSrcOps; ++
I) {
12659 if (
Op.isUndef()) {
12660 SrcUndeElements.
set(
I);
12663 auto *CInt = dyn_cast<ConstantSDNode>(
Op);
12664 auto *CFP = dyn_cast<ConstantFPSDNode>(
Op);
12665 assert((CInt || CFP) &&
"Unknown constant");
12666 SrcBitElements[
I] = CInt ? CInt->getAPIntValue().trunc(SrcEltSizeInBits)
12667 : CFP->getValueAPF().bitcastToAPInt();
12671 recastRawBits(IsLittleEndian, DstEltSizeInBits, RawBitElements,
12672 SrcBitElements, UndefElements, SrcUndeElements);
12677 unsigned DstEltSizeInBits,
12682 unsigned NumSrcOps = SrcBitElements.
size();
12683 unsigned SrcEltSizeInBits = SrcBitElements[0].getBitWidth();
12684 assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
12685 "Invalid bitcast scale");
12686 assert(NumSrcOps == SrcUndefElements.
size() &&
12687 "Vector size mismatch");
12689 unsigned NumDstOps = (NumSrcOps * SrcEltSizeInBits) / DstEltSizeInBits;
12690 DstUndefElements.
clear();
12691 DstUndefElements.
resize(NumDstOps,
false);
12695 if (SrcEltSizeInBits <= DstEltSizeInBits) {
12696 unsigned Scale = DstEltSizeInBits / SrcEltSizeInBits;
12697 for (
unsigned I = 0;
I != NumDstOps; ++
I) {
12698 DstUndefElements.
set(
I);
12699 APInt &DstBits = DstBitElements[
I];
12700 for (
unsigned J = 0; J != Scale; ++J) {
12701 unsigned Idx = (
I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
12702 if (SrcUndefElements[
Idx])
12704 DstUndefElements.
reset(
I);
12705 const APInt &SrcBits = SrcBitElements[
Idx];
12707 "Illegal constant bitwidths");
12708 DstBits.
insertBits(SrcBits, J * SrcEltSizeInBits);
12715 unsigned Scale = SrcEltSizeInBits / DstEltSizeInBits;
12716 for (
unsigned I = 0;
I != NumSrcOps; ++
I) {
12717 if (SrcUndefElements[
I]) {
12718 DstUndefElements.
set(
I * Scale, (
I + 1) * Scale);
12721 const APInt &SrcBits = SrcBitElements[
I];
12722 for (
unsigned J = 0; J != Scale; ++J) {
12723 unsigned Idx = (
I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
12724 APInt &DstBits = DstBitElements[
Idx];
12725 DstBits = SrcBits.
extractBits(DstEltSizeInBits, J * DstEltSizeInBits);
12732 unsigned Opc =
Op.getOpcode();
12739std::optional<std::pair<APInt, APInt>>
12743 return std::nullopt;
12747 return std::nullopt;
12754 return std::nullopt;
12756 for (
unsigned i = 2; i < NumOps; ++i) {
12758 return std::nullopt;
12761 if (Val != (Start + (Stride * i)))
12762 return std::nullopt;
12765 return std::make_pair(Start, Stride);
12781 for (
int Idx = Mask[i]; i != e; ++i)
12782 if (Mask[i] >= 0 && Mask[i] !=
Idx)
12790 if (isa<ConstantSDNode>(
N))
12791 return N.getNode();
12793 return N.getNode();
12801 isa<ConstantSDNode>(
N.getOperand(0)))
12802 return N.getNode();
12809 if (isa<ConstantFPSDNode>(
N))
12810 return N.getNode();
12813 return N.getNode();
12816 isa<ConstantFPSDNode>(
N.getOperand(0)))
12817 return N.getNode();
12823 assert(!Node->OperandList &&
"Node already has operands");
12825 "too many operands to fit into SDNode");
12826 SDUse *Ops = OperandRecycler.allocate(
12829 bool IsDivergent =
false;
12830 for (
unsigned I = 0;
I != Vals.
size(); ++
I) {
12831 Ops[
I].setUser(Node);
12832 Ops[
I].setInitial(Vals[
I]);
12833 if (Ops[
I].Val.getValueType() != MVT::Other)
12837 Node->OperandList = Ops;
12840 Node->SDNodeBits.IsDivergent = IsDivergent;
12848 while (Vals.
size() > Limit) {
12849 unsigned SliceIdx = Vals.
size() - Limit;
12923 const SDLoc &DLoc) {
12928 Entry.Ty =
Ptr.getValueType().getTypeForEVT(*
getContext());
12929 Args.push_back(Entry);
12941 assert(
From && To &&
"Invalid SDNode; empty source SDValue?");
12942 auto I = SDEI.find(
From);
12943 if (
I == SDEI.end())
12948 NodeExtraInfo NEI =
I->second;
12957 SDEI[To] = std::move(NEI);
12976 Leafs.emplace_back(
N);
12979 if (!FromReach.
insert(
N).second)
12987 auto DeepCopyTo = [&](
auto &&Self,
const SDNode *
N) {
12990 if (!Visited.
insert(
N).second)
12995 if (!Self(Self,
Op.getNode()))
13015 for (
const SDNode *
N : StartFrom)
13016 VisitFrom(VisitFrom,
N,
MaxDepth - PrevDepth);
13028 errs() <<
"warning: incomplete propagation of SelectionDAG::NodeExtraInfo\n";
13029 assert(
false &&
"From subgraph too complex - increase max. MaxDepth?");
13031 SDEI[To] = std::move(NEI);
13045 if (!Visited.
insert(
N).second) {
13046 errs() <<
"Detected cycle in SelectionDAG\n";
13047 dbgs() <<
"Offending node:\n";
13048 N->dumprFull(DAG);
dbgs() <<
"\n";
13064 bool check = force;
13065#ifdef EXPENSIVE_CHECKS
13069 assert(
N &&
"Checking nonexistent SDNode");
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static bool isConstant(const MachineInstr &MI)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
This file implements the BitVector class.
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
static std::optional< bool > isBigEndian(const SmallDenseMap< int64_t, int64_t, 8 > &MemOffset2Idx, int64_t LowestIdx)
Given a map from byte offsets in memory to indices in a load/store, determine if that map corresponds...
#define __asan_unpoison_memory_region(p, size)
#define LLVM_LIKELY(EXPR)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Looks at all the uses of the given value Returns the Liveness deduced from the uses of this value Adds all uses that cause the result to be MaybeLive to MaybeLiveRetUses If the result is MaybeLiveUses might be modified but its content should be ignored(since it might not be complete). DeadArgumentEliminationPass
Given that RA is a live propagate it s liveness to any other values it uses(according to Uses). void DeadArgumentEliminationPass
Given that RA is a live value
This file defines the DenseSet and SmallDenseSet classes.
This file contains constants used for implementing Dwarf debug support.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file defines a hash set that can be used to remove duplication of nodes in a graph.
Rewrite Partial Register Uses
static const unsigned MaxDepth
static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB)
static bool shouldLowerMemFuncForSize(const MachineFunction &MF)
static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)
static Align getPrefTypeAlign(EVT VT, SelectionDAG &DAG)
mir Rename Register Operands
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
PowerPC Reduce CR logical Operation
const SmallVectorImpl< MachineOperand > & Cond
Contains matchers for matching SelectionDAG nodes and values.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static uint64_t umul_ov(uint64_t i, uint64_t j, bool &Overflow)
static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo)
Lower the call to 'memset' intrinsic function into a series of store operations.
static std::optional< APInt > FoldValueWithUndef(unsigned Opcode, const APInt &C1, bool IsUndef1, const APInt &C2, bool IsUndef2)
static SDValue FoldSTEP_VECTOR(const SDLoc &DL, EVT VT, SDValue Step, SelectionDAG &DAG)
static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned OpC, SDVTList VTList, ArrayRef< SDValue > OpList)
static SDValue getMemsetStringVal(EVT VT, const SDLoc &dl, SelectionDAG &DAG, const TargetLowering &TLI, const ConstantDataArraySlice &Slice)
getMemsetStringVal - Similar to getMemsetValue.
static cl::opt< bool > EnableMemCpyDAGOpt("enable-memcpy-dag-opt", cl::Hidden, cl::init(true), cl::desc("Gang up loads and stores generated by inlining of memcpy"))
static bool haveNoCommonBitsSetCommutative(SDValue A, SDValue B)
static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList)
AddNodeIDValueTypes - Value type lists are intern'd so we can represent them solely with their pointe...
static void commuteShuffle(SDValue &N1, SDValue &N2, MutableArrayRef< int > M)
Swaps the values of N1 and N2.
static bool isMemSrcFromConstant(SDValue Src, ConstantDataArraySlice &Slice)
Returns true if memcpy source is constant data.
static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo)
static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo, AAResults *AA)
static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC)
AddNodeIDOpcode - Add the node opcode to the NodeID data.
static ISD::CondCode getSetCCInverseImpl(ISD::CondCode Op, bool isIntegerLike)
static bool doNotCSE(SDNode *N)
doNotCSE - Return true if CSE should not be performed for this node.
static cl::opt< int > MaxLdStGlue("ldstmemcpy-glue-max", cl::desc("Number limit for gluing ld/st of memcpy."), cl::Hidden, cl::init(0))
static void AddNodeIDOperands(FoldingSetNodeID &ID, ArrayRef< SDValue > Ops)
AddNodeIDOperands - Various routines for adding operands to the NodeID data.
static SDValue foldCONCAT_VECTORS(const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG)
Try to simplify vector concatenation to an input value, undef, or build vector.
static MachinePointerInfo InferPointerInfo(const MachinePointerInfo &Info, SelectionDAG &DAG, SDValue Ptr, int64_t Offset=0)
InferPointerInfo - If the specified ptr/offset is a frame index, infer a MachinePointerInfo record fr...
static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N)
If this is an SDNode with special info, add this info to the NodeID data.
static void NewSDValueDbgMsg(SDValue V, StringRef Msg, SelectionDAG *G)
static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs)
makeVTList - Return an instance of the SDVTList struct initialized with the specified members.
static void VerifySDNode(SDNode *N, const TargetLowering *TLI)
VerifySDNode - Check the given SDNode. Aborts if it is invalid.
static void checkForCyclesHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallPtrSetImpl< const SDNode * > &Checked, const llvm::SelectionDAG *DAG)
static void chainLoadsAndStoresForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SmallVector< SDValue, 32 > &OutChains, unsigned From, unsigned To, SmallVector< SDValue, 16 > &OutLoadChains, SmallVector< SDValue, 16 > &OutStoreChains)
static int isSignedOp(ISD::CondCode Opcode)
For an integer comparison, return 1 if the comparison is a signed operation and 2 if the result is an...
static std::optional< APInt > FoldValue(unsigned Opcode, const APInt &C1, const APInt &C2)
static SDValue FoldBUILD_VECTOR(const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG)
static void checkAddrSpaceIsValidForLibcall(const TargetLowering *TLI, unsigned AS)
static Constant * ConstantFold(Instruction *I, const DataLayout &DL, const SmallDenseMap< Value *, Constant * > &ConstantPool)
Try to fold instruction I into a constant.
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file describes how to lower LLVM code to machine code.
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
static OverflowResult mapOverflowResult(ConstantRange::OverflowResult OR)
Convert ConstantRange OverflowResult into ValueTracking OverflowResult.
static unsigned getSize(unsigned Kind)
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
static APFloat getQNaN(const fltSemantics &Sem, bool Negative=false, const APInt *payload=nullptr)
Factory for QNaN values.
opStatus divide(const APFloat &RHS, roundingMode RM)
void copySign(const APFloat &RHS)
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
opStatus subtract(const APFloat &RHS, roundingMode RM)
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
opStatus add(const APFloat &RHS, roundingMode RM)
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
opStatus multiply(const APFloat &RHS, roundingMode RM)
opStatus fusedMultiplyAdd(const APFloat &Multiplicand, const APFloat &Addend, roundingMode RM)
static APFloat getLargest(const fltSemantics &Sem, bool Negative=false)
Returns the largest finite number in the given semantics.
opStatus convertToInteger(MutableArrayRef< integerPart > Input, unsigned int Width, bool IsSigned, roundingMode RM, bool *IsExact) const
static APFloat getInf(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Infinity.
opStatus mod(const APFloat &RHS)
static APFloat getNaN(const fltSemantics &Sem, bool Negative=false, uint64_t payload=0)
Factory for NaN values.
Class for arbitrary precision integers.
APInt umul_ov(const APInt &RHS, bool &Overflow) const
APInt usub_sat(const APInt &RHS) const
APInt udiv(const APInt &RHS) const
Unsigned division operation.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
void clearBit(unsigned BitPosition)
Set a given bit to 0.
APInt zext(unsigned width) const
Zero extend to a new width.
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
uint64_t getZExtValue() const
Get zero extended value.
void setHighBits(unsigned hiBits)
Set the top hiBits bits.
unsigned popcount() const
Count the number of bits set.
void setBitsFrom(unsigned loBit)
Set the top bits starting from loBit.
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
unsigned getActiveBits() const
Compute the number of active bits in the value.
APInt trunc(unsigned width) const
Truncate to new width.
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
APInt abs() const
Get the absolute value.
APInt sadd_sat(const APInt &RHS) const
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
bool ugt(const APInt &RHS) const
Unsigned greater than comparison.
bool isZero() const
Determine if this value is zero, i.e. all bits are clear.
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool ult(const APInt &RHS) const
Unsigned less than comparison.
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
bool isNegative() const
Determine sign of this APInt.
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
void clearAllBits()
Set every bit to 0.
APInt rotr(unsigned rotateAmt) const
Rotate right by rotateAmt.
APInt reverseBits() const
void ashrInPlace(unsigned ShiftAmt)
Arithmetic right-shift this APInt by ShiftAmt in place.
bool sle(const APInt &RHS) const
Signed less or equal comparison.
unsigned countr_zero() const
Count the number of trailing zero bits.
unsigned getNumSignBits() const
Computes the number of leading bits of this APInt that are equal to its sign bit.
unsigned countl_zero() const
The APInt version of std::countl_zero.
static APInt getSplat(unsigned NewLen, const APInt &V)
Return a value containing V broadcasted over NewLen bits.
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
APInt sshl_sat(const APInt &RHS) const
APInt ushl_sat(const APInt &RHS) const
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
void insertBits(const APInt &SubBits, unsigned bitPosition)
Insert the bits from a smaller APInt starting at bitPosition.
void clearLowBits(unsigned loBits)
Set bottom loBits bits to 0.
unsigned logBase2() const
APInt uadd_sat(const APInt &RHS) const
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
void setAllBits()
Set every bit to 1.
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
bool isNonNegative() const
Determine if this APInt Value is non-negative (>= 0)
bool ule(const APInt &RHS) const
Unsigned less or equal comparison.
APInt sext(unsigned width) const
Sign extend to a new width.
void setBits(unsigned loBit, unsigned hiBit)
Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
APInt shl(unsigned shiftAmt) const
Left-shift function.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getZero(unsigned numBits)
Get the '0' value for the specified bit-width.
void setLowBits(unsigned loBits)
Set the bottom loBits bits.
APInt extractBits(unsigned numBits, unsigned bitPosition) const
Return an APInt with the extracted bits [bitPosition,bitPosition+numBits).
bool sge(const APInt &RHS) const
Signed greater or equal comparison.
static APInt getBitsSetFrom(unsigned numBits, unsigned loBit)
Constructs an APInt value that has a contiguous range of bits set.
static APInt getOneBitSet(unsigned numBits, unsigned BitNo)
Return an APInt with exactly one bit set in the result.
void lshrInPlace(unsigned ShiftAmt)
Logical right-shift this APInt by ShiftAmt in place.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
APInt ssub_sat(const APInt &RHS) const
An arbitrary precision integer that knows its signedness.
AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT, unsigned SrcAS, unsigned DestAS)
Recycle small arrays allocated from a BumpPtrAllocator.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
This is an SDNode representing atomic operations.
static BaseIndexOffset match(const SDNode *N, const SelectionDAG &DAG)
Parses tree in N for base, index, offset addresses.
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void clear()
clear - Removes all bits from the bitvector.
bool none() const
none - Returns true if none of the bits are set.
size_type size() const
size - Returns the number of bits in this bitvector.
int64_t getOffset() const
unsigned getTargetFlags() const
const BlockAddress * getBlockAddress() const
The address of a basic block.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
A "pseudo-class" with methods for operating on BUILD_VECTORs.
bool getConstantRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, SmallVectorImpl< APInt > &RawBitElements, BitVector &UndefElements) const
Extract the raw bit data from a build vector of Undef, Constant or ConstantFP node elements.
static void recastRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, SmallVectorImpl< APInt > &DstBitElements, ArrayRef< APInt > SrcBitElements, BitVector &DstUndefElements, const BitVector &SrcUndefElements)
Recast bit data SrcBitElements to DstEltSizeInBits wide elements.
bool getRepeatedSequence(const APInt &DemandedElts, SmallVectorImpl< SDValue > &Sequence, BitVector *UndefElements=nullptr) const
Find the shortest repeating sequence of values in the build vector.
ConstantFPSDNode * getConstantFPSplatNode(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted constant FP or null if this is not a constant FP splat.
std::optional< std::pair< APInt, APInt > > isConstantSequence() const
If this BuildVector is constant and represents the numerical series "<a, a+n, a+2n,...
SDValue getSplatValue(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted value or a null value if this is not a splat.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector.
ConstantSDNode * getConstantSplatNode(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted constant or null if this is not a constant splat.
int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements, uint32_t BitWidth) const
If this is a constant FP splat and the splatted constant FP is an exact power or 2,...
LLVM_ATTRIBUTE_RETURNS_NONNULL void * Allocate(size_t Size, Align Alignment)
Allocate space at the specified alignment.
void Reset()
Deallocate all but the current slab and reset the current pointer to the beginning of it,...
static bool isValueValidForType(EVT VT, const APFloat &Val)
const APFloat & getValueAPF() const
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
ConstantFP - Floating Point Values [float, double].
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
const APInt & getValue() const
Return the constant as an APInt value reference.
bool isMachineConstantPoolEntry() const
This class represents a range of values.
ConstantRange multiply(const ConstantRange &Other) const
Return a new range representing the possible values resulting from a multiplication of a value in thi...
const APInt * getSingleElement() const
If this set contains a single element, return it, otherwise return null.
static ConstantRange fromKnownBits(const KnownBits &Known, bool IsSigned)
Initialize a range based on a known bits constraint.
OverflowResult unsignedSubMayOverflow(const ConstantRange &Other) const
Return whether unsigned sub of the two ranges always/never overflows.
OverflowResult unsignedAddMayOverflow(const ConstantRange &Other) const
Return whether unsigned add of the two ranges always/never overflows.
KnownBits toKnownBits() const
Return known bits for values in this range.
ConstantRange zeroExtend(uint32_t BitWidth) const
Return a new range in the specified integer type, which must be strictly larger than the current type...
APInt getSignedMin() const
Return the smallest signed value contained in the ConstantRange.
OverflowResult unsignedMulMayOverflow(const ConstantRange &Other) const
Return whether unsigned mul of the two ranges always/never overflows.
ConstantRange signExtend(uint32_t BitWidth) const
Return a new range in the specified integer type, which must be strictly larger than the current type...
APInt getUnsignedMax() const
Return the largest unsigned value contained in the ConstantRange.
APInt getSignedMax() const
Return the largest signed value contained in the ConstantRange.
OverflowResult
Represents whether an operation on the given constant range is known to always or never overflow.
@ NeverOverflows
Never overflows.
@ AlwaysOverflowsHigh
Always overflows in the direction of signed/unsigned max value.
@ AlwaysOverflowsLow
Always overflows in the direction of signed/unsigned min value.
@ MayOverflow
May or may not overflow.
uint32_t getBitWidth() const
Get the bit width of this ConstantRange.
OverflowResult signedSubMayOverflow(const ConstantRange &Other) const
Return whether signed sub of the two ranges always/never overflows.
uint64_t getZExtValue() const
const APInt & getAPIntValue() const
This is an important base class in LLVM.
Constant * getSplatValue(bool AllowPoison=false) const
If all elements of the vector constant have the same value, return that value.
Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
static ExtOps getExtOps(unsigned FromSize, unsigned ToSize, bool Signed)
Returns the ops for a zero- or sign-extension in a DIExpression.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static const DIExpression * convertToVariadicExpression(const DIExpression *Expr)
If Expr is a non-variadic expression (i.e.
static std::optional< DIExpression * > createFragmentExpression(const DIExpression *Expr, unsigned OffsetInBits, unsigned SizeInBits)
Create a DIExpression to describe one part of an aggregate variable that is fragmented across multipl...
Base class for variables.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
bool isLittleEndian() const
Layout endianness...
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
unsigned getPointerTypeSizeInBits(Type *) const
Layout pointer size, in bits, based on the type.
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
void reserve(size_type NumEntries)
Grow the densemap so that it can contain at least NumEntries items before resizing again.
Implements a dense probed hash-table based set.
const char * getSymbol() const
unsigned getTargetFlags() const
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
MachineBasicBlock * MBB
MBB - The current block.
Data structure describing the variable locations in a function.
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
AttributeList getAttributes() const
Return the attribute list for this Function.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
int64_t getOffset() const
unsigned getAddressSpace() const
unsigned getTargetFlags() const
const GlobalValue * getGlobal() const
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
unsigned getAddressSpace() const
Module * getParent()
Get the module that this global value is contained inside of...
PointerType * getType() const
Global values are always pointers.
This class is used to form a handle around another node that is persistent and is updated across invo...
static bool compare(const APInt &LHS, const APInt &RHS, ICmpInst::Predicate Pred)
Return result of LHS Pred RHS comparison.
constexpr bool isValid() const
This is an important class for using LLVM in a threaded context.
This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate the offet and size that ar...
This class is used to represent ISD::LOAD nodes.
static LocationSize precise(uint64_t Value)
TypeSize getValue() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MVT getIntegerVT(unsigned BitWidth)
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Abstract base class for all machine specific constantpool value subclasses.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
bool isNonTemporal() const
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
const MachinePointerInfo & getPointerInfo() const
Flags getFlags() const
Return the raw flags of the source value,.
bool isDereferenceable() const
An SDNode that represents everything that will be needed to construct a MachineInstr.
This class is used to represent an MGATHER node.
This class is used to represent an MLOAD node.
This class is used to represent an MSCATTER node.
This class is used to represent an MSTORE node.
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT memvt, MachineMemOperand *MMO)
MachineMemOperand * MMO
Memory reference information.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
unsigned getRawSubclassData() const
Return the SubclassData value, without HasDebugValue.
EVT getMemoryVT() const
Return the type of the in-memory value.
Representation for a specific memory location.
A Module instance is used to store all the information related to an LLVM module.
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Pass interface - Implemented by all 'passes'.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
unsigned getAddressSpace() const
Return the address space of the Pointer type.
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Analysis providing profile information.
void Deallocate(SubClass *E)
Deallocate - Release storage for the pointed-to object.
Keeps track of dbg_value information through SDISel.
BumpPtrAllocator & getAlloc()
void add(SDDbgValue *V, bool isParameter)
void erase(const SDNode *Node)
Invalidate all DbgValues attached to the node and remove it from the Node-to-DbgValues map.
ArrayRef< SDDbgValue * > getSDDbgValues(const SDNode *Node) const
Holds the information from a dbg_label node through SDISel.
Holds the information for a single machine location through SDISel; either an SDNode,...
static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo)
static SDDbgOperand fromFrameIdx(unsigned FrameIdx)
static SDDbgOperand fromVReg(unsigned VReg)
static SDDbgOperand fromConst(const Value *Const)
@ SDNODE
Value is the result of an expression.
Holds the information from a dbg_value node through SDISel.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
const DebugLoc & getDebugLoc() const
unsigned getIROrder() const
This class provides iterator support for SDUse operands that use a specific SDNode.
Represents one node in the SelectionDAG.
ArrayRef< SDUse > ops() const
const APInt & getAsAPIntVal() const
Helper method returns the APInt value of a ConstantSDNode.
void dumprFull(const SelectionDAG *G=nullptr) const
printrFull to dbgs().
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isOnlyUserOf(const SDNode *N) const
Return true if this node is the only use of N.
iterator_range< value_op_iterator > op_values() const
unsigned getIROrder() const
Return the node ordering.
static constexpr size_t getMaxNumOperands()
Return the maximum number of operands that a SDNode can hold.
MemSDNodeBitfields MemSDNodeBits
void Profile(FoldingSetNodeID &ID) const
Gather unique data for the node.
bool getHasDebugValue() const
SDNodeFlags getFlags() const
void setNodeId(int Id)
Set unique node id.
void intersectFlagsWith(const SDNodeFlags Flags)
Clear any flags in this node that aren't also set in Flags.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallVectorImpl< const SDNode * > &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
bool use_empty() const
Return true if there are no uses of this node.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
unsigned getNumOperands() const
Return the number of values used by this operation.
const SDValue & getOperand(unsigned Num) const
static bool areOnlyUsersOf(ArrayRef< const SDNode * > Nodes, const SDNode *N)
Return true if all the users of N are contained in Nodes.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
bool isOperandOf(const SDNode *N) const
Return true if this node is an operand of N.
const APInt & getConstantOperandAPInt(unsigned Num) const
Helper method returns the APInt of a ConstantSDNode operand.
bool hasPredecessor(const SDNode *N) const
Return true if N is a predecessor of this node.
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool isUndef() const
Return true if the type of the node type undefined.
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const
Return true if there are exactly NUSES uses of the indicated value.
op_iterator op_end() const
op_iterator op_begin() const
static use_iterator use_end()
void DropOperands()
Release the operands and set this node to have zero operands.
Represents a use of a SDNode.
SDNode * getNode() const
Convenience function for get().getNode().
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool isOperandOf(const SDNode *N) const
Return true if this node is an operand of N.
bool reachesChainWithoutSideEffects(SDValue Dest, unsigned Depth=2) const
Return true if this operand (which must be a chain) reaches the specified operand without crossing an...
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
bool use_empty() const
Return true if there are no nodes using value ResNo of Node.
const APInt & getConstantOperandAPInt(unsigned i) const
uint64_t getScalarValueSizeInBits() const
unsigned getResNo() const
get the index which selects a specific result in the SDNode
uint64_t getConstantOperandVal(unsigned i) const
unsigned getOpcode() const
virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo) const
Emit target-specific code that performs a memset.
virtual SDValue EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memmove.
virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memcpy.
SDNodeFlags getFlags() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Align getReducedAlign(EVT VT, bool UseABI)
In most cases this function returns the ABI alignment for a given type, except for illegal vector typ...
SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op)
Return the specified value casted to the target's desired shift amount type.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getExtLoadVP(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsExpanding=false)
SDValue getSplatSourceVector(SDValue V, int &SplatIndex)
If V is a splatted value, return the source vector and its splat index.
SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label)
OverflowKind computeOverflowForUnsignedSub(SDValue N0, SDValue N1) const
Determine if the result of the unsigned sub of 2 nodes can overflow.
unsigned ComputeMaxSignificantBits(SDValue Op, unsigned Depth=0) const
Get the upper bound on bit size for this Value Op as a signed integer.
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy)
bool isKnownNeverSNaN(SDValue Op, unsigned Depth=0) const
SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
Return an AddrSpaceCastSDNode.
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
SDValue getStackArgumentTokenFactor(SDValue Chain)
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
const TargetSubtargetInfo & getSubtarget() const
const APInt * getValidMaximumShiftAmountConstant(SDValue V, const APInt &DemandedElts) const
If a SHL/SRA/SRL node V has constant shift amounts that are all less than the element bit-width of th...
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
void updateDivergence(SDNode *N)
SDValue getSplatValue(SDValue V, bool LegalTypes=false)
If V is a splat vector, return its scalar source operand by extracting that element from the source v...
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl)
Constant fold a setcc to true or false.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
Append the extracted elements from Start to Count out of the vector Op in Args.
SDValue getNeutralElement(unsigned Opcode, const SDLoc &DL, EVT VT, SDNodeFlags Flags)
Get the (commutative) neutral element for the given opcode, if it exists.
SDValue getAtomicMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo)
SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm, bool ConstantFold=true)
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
SDValue getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr)
Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing,...
SDValue getFreeze(SDValue V)
Return a freeze using the SDLoc of the value operand.
SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type,...
SelectionDAG(const TargetMachine &TM, CodeGenOptLevel)
SDValue getBitcastedSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDValue getStridedLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDNode * isConstantIntBuildVectorOrConstantInt(SDValue N) const
Test whether the given value is a constant int or similar node.
SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
Gets a node for an atomic cmpxchg op.
SDValue makeEquivalentMemoryOrdering(SDValue OldChain, SDValue NewMemOpChain)
If an existing load has uses of its chain, create a token factor node with that chain and the new mem...
SDDbgValue * getVRegDbgValue(DIVariable *Var, DIExpression *Expr, unsigned VReg, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a VReg SDDbgValue node.
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
SDValue getJumpTableDebugInfo(int JTI, SDValue Chain, const SDLoc &DL)
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getSymbolFunctionGlobalAddress(SDValue Op, Function **TargetFunction=nullptr)
Return a GlobalAddress of the function from the current module with name matching the given ExternalS...
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
OverflowKind
Used to represent the possible overflow behavior of an operation.
bool isADDLike(SDValue Op) const
Return true if the specified operand is an ISD::OR or ISD::XOR node that can be treated as an ISD::AD...
bool haveNoCommonBitsSet(SDValue A, SDValue B) const
Return true if A and B have no common bits set.
bool calculateDivergence(SDNode *N)
SDValue getElementCount(const SDLoc &DL, EVT VT, ElementCount EC, bool ConstantFold=true)
SDValue getGetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getAssertAlign(const SDLoc &DL, SDValue V, Align A)
Return an AssertAlignSDNode.
SDNode * mutateStrictFPToFP(SDNode *Node)
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain a...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getBitcastedZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
SDValue getStepVector(const SDLoc &DL, EVT ResVT, const APInt &StepVal)
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step,...
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Align getEVTAlign(EVT MemoryVT) const
Compute the default alignment value for the given type.
void VerifyDAGDivergence()
bool shouldOptForSize() const
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
SDValue getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT,...
const TargetLowering & getTargetLoweringInfo() const
bool isEqualTo(SDValue A, SDValue B) const
Test whether two SDValues are known to compare equal.
static constexpr unsigned MaxRecursionDepth
SDValue getStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
SDValue expandVACopy(SDNode *Node)
Expand the specified ISD::VACOPY node as the Legalize pass would.
SDValue getIndexedMaskedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
APInt computeVectorKnownZeroElements(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
For each demanded element of a vector, see if it is known to be zero.
void AddDbgValue(SDDbgValue *DB, bool isParameter)
Add a dbg_value SDNode.
bool NewNodesMustHaveLegalTypes
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG n...
std::pair< EVT, EVT > GetSplitDestVTs(const EVT &VT) const
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not neces...
void salvageDebugInfo(SDNode &N)
To be invoked on an SDNode that is slated to be erased.
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
std::pair< SDValue, SDValue > UnrollVectorOverflowOp(SDNode *N, unsigned ResNE=0)
Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes.
allnodes_const_iterator allnodes_begin() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getBitcastedAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const
Test whether V has a splatted value for all the demanded elements.
void DeleteNode(SDNode *N)
Remove the specified node from the system.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
SDDbgValue * getDbgValueList(DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic)
Creates a SDDbgValue node from a list of locations.
SDValue getNegative(SDValue Val, const SDLoc &DL, EVT VT)
Create negative operation as (SUB 0, Val).
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
SDValue simplifySelect(SDValue Cond, SDValue TVal, SDValue FVal)
Try to simplify a select/vselect into 1 of its operands or a constant.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
const DataLayout & getDataLayout() const
SDNode * isConstantFPBuildVectorOrConstantFP(SDValue N) const
Test whether the given value is a constant FP or similar node.
SDValue expandVAArg(SDNode *Node)
Expand the specified ISD::VAARG node as the Legalize pass would.
SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
Creates a new TokenFactor containing Vals.
bool doesNodeExist(unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops)
Check if a node exists without modifying its flags.
bool areNonVolatileConsecutiveLoads(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const
Return true if loads are next to each other and can be merged.
SDDbgLabel * getDbgLabel(DILabel *Label, const DebugLoc &DL, unsigned O)
Creates a SDDbgLabel node.
SDValue getStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
OverflowKind computeOverflowForUnsignedMul(SDValue N0, SDValue N1) const
Determine if the result of the unsigned mul of 2 nodes can overflow.
void copyExtraInfo(SDNode *From, SDNode *To)
Copy extra info associated with one node to another.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
void clear()
Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV)
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swa...
std::pair< SDValue, SDValue > SplitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the vector with EXTRACT_SUBVECTOR using the provided VTs and return the low/high part.
const APInt * getValidShiftAmountConstant(SDValue V, const APInt &DemandedElts) const
If a SHL/SRA/SRL node V has a constant or splat constant shift amount that is less than the element b...
SDValue makeStateFunctionCall(unsigned LibFunc, SDValue Ptr, SDValue InChain, const SDLoc &DLoc)
Helper used to make a call to a library function that has one argument of pointer type.
bool isGuaranteedNotToBeUndefOrPoison(SDValue Op, bool PoisonOnly=false, unsigned Depth=0) const
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getIndexedLoadVP(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getSrcValue(const Value *v)
Construct a node to track a Value* through the backend.
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op)
SDValue getAtomicMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
OverflowKind computeOverflowForSignedMul(SDValue N0, SDValue N1) const
Determine if the result of the signed mul of 2 nodes can overflow.
MaybeAlign InferPtrAlign(SDValue Ptr) const
Infer alignment of a load / store address.
bool MaskedValueIsAllOnes(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if '(Op & Mask) == Mask'.
bool SignBitIsZero(SDValue Op, unsigned Depth=0) const
Return true if the sign bit of Op is known to be zero.
SDValue getRegister(unsigned Reg, EVT VT)
void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, FunctionVarLocs const *FnVarLocs)
Prepare this SelectionDAG to process code in the given MachineFunction.
void RemoveDeadNodes()
This method deletes all unreachable nodes in the SelectionDAG.
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
void AddDbgLabel(SDDbgLabel *DB)
Add a dbg_label SDNode.
bool isConstantValueOfAnyType(SDValue N) const
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue getBasicBlock(MachineBasicBlock *MBB)
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
bool isKnownToBeAPowerOfTwo(SDValue Val, unsigned Depth=0) const
Test if the given value is known to have exactly one bit set.
SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label)
SDValue getIndexedStoreVP(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
bool isKnownNeverZero(SDValue Op, unsigned Depth=0) const
Test whether the given SDValue is known to contain non-zero value(s).
SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getSetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT)
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate ...
SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
std::pair< SDValue, SDValue > getStrictFPExtendOrRound(SDValue Op, SDValue Chain, const SDLoc &DL, EVT VT)
Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending...
std::pair< SDValue, SDValue > SplitEVL(SDValue N, EVT VecVT, const SDLoc &DL)
Split the explicit vector length parameter of a VP operation.
SDValue getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or perform...
SDValue getVPLogicalNOT(const SDLoc &DL, SDValue Val, SDValue Mask, SDValue EVL, EVT VT)
Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask,...
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
iterator_range< allnodes_iterator > allnodes()
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
SDValue WidenVector(const SDValue &N, const SDLoc &DL)
Widen the vector up to the next power of two using INSERT_SUBVECTOR.
bool isKnownNeverZeroFloat(SDValue Op) const
Test whether the given floating point SDValue is known to never be positive or negative zero.
SDValue getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDDbgValue * getConstantDbgValue(DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O)
Creates a constant SDDbgValue node.
SDValue getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getValueType(EVT)
ArrayRef< SDDbgValue * > GetDbgValues(const SDNode *SD) const
Get the debug values which reference the given SDNode.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
OverflowKind computeOverflowForSignedAdd(SDValue N0, SDValue N1) const
Determine if the result of the signed addition of 2 nodes can overflow.
SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by tr...
unsigned AssignTopologicalOrder()
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on th...
ilist< SDNode >::size_type allnodes_size() const
SDValue getAtomicMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
bool isKnownNeverNaN(SDValue Op, bool SNaN=false, unsigned Depth=0) const
Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN.
SDValue getIndexedMaskedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getTruncStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsCompressing=false)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
bool MaskedVectorIsZero(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
Return true if 'Op' is known to be zero in DemandedElts.
SDValue getBoolConstant(bool V, const SDLoc &DL, EVT VT, EVT OpVT)
Create a true or false constant of type VT using the target's BooleanContent for type OpVT.
SDDbgValue * getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a FrameIndex SDDbgValue node.
SDValue getExtStridedLoadVP(ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDValue getJumpTable(int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0)
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...
SDValue getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT,...
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy ...
bool canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, bool ConsiderFlags=true, unsigned Depth=0) const
Return true if Op can create undef or poison from non-undef & non-poison operands.
OverflowKind computeOverflowForUnsignedAdd(SDValue N0, SDValue N1) const
Determine if the result of the unsigned addition of 2 nodes can overflow.
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op)
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getTruncStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false)
void canonicalizeCommutativeBinop(unsigned Opcode, SDValue &N1, SDValue &N2) const
Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite o...
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue getCondCode(ISD::CondCode Cond)
SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex, int64_t Size, int64_t Offset=-1)
Creates a LifetimeSDNode that starts (IsStart==true) or ends (IsStart==false) the lifetime of the por...
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
OverflowKind computeOverflowForSignedSub(SDValue N0, SDValue N1) const
Determine if the result of the signed sub of 2 nodes can overflow.
LLVMContext * getContext() const
SDValue simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y, SDNodeFlags Flags)
Try to simplify a floating-point binary operation into 1 of its operands or a constant.
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
const APInt * getValidMinimumShiftAmountConstant(SDValue V, const APInt &DemandedElts) const
If a SHL/SRA/SRL node V has constant shift amounts that are all less than the element bit-width of th...
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL, bool LegalTypes=true)
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
bool isUndef(unsigned Opcode, ArrayRef< SDValue > Ops)
Return true if the result of this operation is always undefined.
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
std::pair< EVT, EVT > GetDependentSplitDestVTs(const EVT &VT, const EVT &EnvVT, bool *HiIsEmpty) const
Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been sp...
SDValue foldConstantFPMath(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
Fold floating-point operations when all operands are constants and/or undefined.
SDNode * getNodeIfExists(unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags)
Get the specified node if it's already available, or else return NULL.
SDValue FoldSymbolOffset(unsigned Opcode, EVT VT, const GlobalAddressSDNode *GA, const SDNode *N2)
SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDDbgValue * getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a SDDbgValue node.
SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false)
SDValue getSplat(EVT VT, const SDLoc &DL, SDValue Op)
Returns a node representing a splat of one value into all lanes of the provided vector type.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
SDValue matchBinOpReduction(SDNode *Extract, ISD::NodeType &BinOp, ArrayRef< ISD::NodeType > CandidateBinOps, bool AllowPartials=false)
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector ...
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
SDValue simplifyShift(SDValue X, SDValue Y)
Try to simplify a shift into 1 of its operands or a constant.
void transferDbgValues(SDValue From, SDValue To, unsigned OffsetInBits=0, unsigned SizeInBits=0, bool InvalidateDbg=true)
Transfer debug values from one node to another, while optionally generating fragment expressions for ...
SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a logical NOT operation as (XOR Val, BooleanOne).
SDValue getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false)
ilist< SDNode >::iterator allnodes_iterator
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
static bool isSplatMask(const int *Mask, EVT VT)
int getMaskElt(unsigned Idx) const
ArrayRef< int > getMask() const
static void commuteMask(MutableArrayRef< int > Mask)
Change values in a shuffle permute mask assuming the two vector operands have swapped position.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void assign(size_type NumElts, ValueParamT Elt)
reference emplace_back(ArgTypes &&... Args)
void reserve(size_type N)
iterator erase(const_iterator CI)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
Information about stack frame layout on the target.
virtual TargetStackID::Value getStackIDForScalableVectors() const
Returns the StackID that scalable vectors should be associated with.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Completely target-dependent object reference.
int64_t getOffset() const
unsigned getTargetFlags() const
Provides information about what library functions are available for the current target.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself.
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
const TargetMachine & getTargetMachine() const
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
virtual bool shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const
Return true if the target shall perform extract vector element and store given that the vector is kno...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it's free to truncate a value of type FromTy to type ToTy.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
BooleanContent
Enum that describes how the target represents true/false values.
@ ZeroOrOneBooleanContent
@ UndefinedBooleanContent
@ ZeroOrNegativeOneBooleanContent
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
virtual unsigned getMaxGluedStoresPerMemcpy() const
Get maximum # of store operations to be glued together.
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
std::vector< ArgListEntry > ArgListTy
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
virtual bool isLegalStoreImmediate(int64_t Value) const
Return true if the specified immediate is legal for the value input of a store instruction.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
static ISD::NodeType getExtendForContent(BooleanContent Content)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual void computeKnownBitsForFrameIndex(int FIOp, KnownBits &Known, const MachineFunction &MF) const
Determine which of the bits of FrameIndex FIOp are known to be 0.
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
This method can be implemented by targets that want to expose additional information about sign bits ...
virtual void verifyTargetSDNode(const SDNode *N) const
Check the given SDNode. Aborts if it is invalid.
virtual bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const
Determines the optimal series of memory ops to replace the memset / memcpy.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const
If SNaN is false,.
virtual void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
virtual bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const
virtual bool isSDNodeAlwaysUniform(const SDNode *N) const
virtual bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth=0) const
Return true if vector Op has the same value across all DemandedElts, indicating any elements which ma...
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
Return true if folding a constant offset with the given GlobalAddress is legal.
virtual const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const
This method returns the constant pool value that will be loaded by LD.
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
virtual bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
virtual bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const
Return true if Op can create undef or poison from non-undef & non-poison operands.
Primary interface to the complete machine description for the target machine.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetLowering * getTargetLowering() const
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
static Type * getVoidTy(LLVMContext &C)
static IntegerType * getInt8Ty(LLVMContext &C)
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
A Use represents the edge between a Value definition and its users.
This class is used to represent an VP_GATHER node.
This class is used to represent a VP_LOAD node.
This class is used to represent an VP_SCATTER node.
This class is used to represent a VP_STORE node.
This class is used to represent an EXPERIMENTAL_VP_STRIDED_LOAD node.
This class is used to represent an EXPERIMENTAL_VP_STRIDED_STORE node.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
std::pair< iterator, bool > insert(const ValueT &V)
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
constexpr ScalarTy getFixedValue() const
static constexpr bool isKnownLE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr bool isKnownEven() const
A return value of true indicates we know at compile time that the number of elements (vscale * Min) i...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
static constexpr bool isKnownGE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
SmartMutex - A mutex with a compile time constant parameter that indicates whether this mutex should ...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
APInt mulhu(const APInt &C1, const APInt &C2)
Performs (2*N)-bit multiplication on zero-extended operands.
const APInt abdu(const APInt &A, const APInt &B)
Determine the absolute difference of two APInts considered to be unsigned.
APInt avgCeilU(const APInt &C1, const APInt &C2)
Compute the ceil of the unsigned average of C1 and C2.
APInt avgFloorU(const APInt &C1, const APInt &C2)
Compute the floor of the unsigned average of C1 and C2.
const APInt abds(const APInt &A, const APInt &B)
Determine the absolute difference of two APInts considered to be signed.
APInt mulhs(const APInt &C1, const APInt &C2)
Performs (2*N)-bit multiplication on sign-extended operands.
APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth, bool MatchAllBits=false)
Splat/Merge neighboring bits to widen/narrow the bitmask represented by.
APInt avgFloorS(const APInt &C1, const APInt &C2)
Compute the floor of the signed average of C1 and C2.
APInt avgCeilS(const APInt &C1, const APInt &C2)
Compute the ceil of the signed average of C1 and C2.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X...
bool isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are ~0 ...
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ JUMP_TABLE_DEBUG_INFO
JUMP_TABLE_DEBUG_INFO - Jumptable debug info.
@ BSWAP
Byte Swap and Counting operators.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
@ FADD
Simple binary floating point operators.
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SRCVALUE
SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the L...
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
@ SIGN_EXTEND
Conversion operators.
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ TargetIndex
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ SSUBO
Same for subtraction.
@ STEP_VECTOR
STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ UNDEF
UNDEF - An undefined node.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
@ BasicBlock
Various leaf nodes.
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
@ SMULO
Same for multiplication.
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ LIFETIME_START
This corresponds to the llvm.lifetime.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
@ BF16_TO_FP
BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions and truncation for bfloat16.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ GET_FPENV_MEM
Gets the current floating-point environment.
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ SET_FPENV_MEM
Sets the current floating point environment.
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
unsigned getVPForBaseOpcode(unsigned Opcode)
Translate this non-VP Opcode to its corresponding VP Opcode.
bool isBuildVectorOfConstantSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantSDNode or undef.
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
bool matchUnaryPredicate(SDValue Op, std::function< bool(ConstantSDNode *)> Match, bool AllowUndefs=false)
Hook for matching ConstantSDNode predicate.
bool isZEXTLoad(const SDNode *N)
Returns true if the specified node is a ZEXTLOAD.
bool matchUnaryFpPredicate(SDValue Op, std::function< bool(ConstantFPSDNode *)> Match, bool AllowUndefs=false)
Hook for matching ConstantFPSDNode predicate.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
bool isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are 0 o...
bool isVectorShrinkable(const SDNode *N, unsigned NewEltSize, bool Signed)
Returns true if the specified node is a vector where all elements can be truncated to the specified e...
bool matchUnaryPredicateImpl(SDValue Op, std::function< bool(ConstNodeType *)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant BUI...
bool isVPBinaryOp(unsigned Opcode)
Whether this is a vector-predicated binary operation opcode.
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
std::optional< unsigned > getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept)
Translate this VP Opcode to its corresponding non-VP Opcode.
bool isTrueWhenEqual(CondCode Cond)
Return true if the specified condition returns true if the two operands to the condition are equal.
std::optional< unsigned > getVPMaskIdx(unsigned Opcode)
The operand position of the vector mask.
unsigned getUnorderedFlavor(CondCode Cond)
This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition i...
std::optional< unsigned > getVPExplicitVectorLengthIdx(unsigned Opcode)
The operand position of the explicit vector length parameter.
bool isEXTLoad(const SDNode *N)
Returns true if the specified node is a EXTLOAD.
bool allOperandsUndef(const SDNode *N)
Return true if the node has at least one operand and all operands of the specified node are ISD::UNDE...
bool isFreezeUndef(const SDNode *N)
Return true if the specified node is FREEZE(UNDEF).
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
MemIndexType
MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calcula...
bool isBuildVectorAllZeros(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.
bool isConstantSplatVector(const SDNode *N, APInt &SplatValue)
Node predicates.
bool matchBinaryPredicate(SDValue LHS, SDValue RHS, std::function< bool(ConstantSDNode *, ConstantSDNode *)> Match, bool AllowUndefs=false, bool AllowTypeMismatch=false)
Attempt to match a binary predicate against a pair of scalar/splat constants or every element of a pa...
bool isVPReduction(unsigned Opcode)
Whether this is a vector-predicated reduction opcode.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
bool isBuildVectorOfConstantFPSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantFPSDNode or undef.
bool isSEXTLoad(const SDNode *N)
Returns true if the specified node is a SEXTLOAD.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
bool isBuildVectorAllOnes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef.
NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode)
Get underlying scalar opcode for VECREDUCE opcode.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X ...
BinaryOp_match< LHS, RHS, Instruction::And > m_And(const LHS &L, const RHS &R)
deferredval_ty< Value > m_Deferred(Value *const &V)
Like m_Specific(), but works if the specific value to match is determined as part of the same match()...
BinaryOp_match< cst_pred_ty< is_zero_int >, ValTy, Instruction::Sub > m_Neg(const ValTy &V)
Matches a 'Neg' as 'sub 0, V'.
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
bool sd_match(SDNode *N, const SelectionDAG *DAG, Pattern &&P)
initializer< Ty > init(const Ty &Val)
@ DW_OP_LLVM_arg
Only used in LLVM metadata.
std::lock_guard< SmartMutex< mt_only > > SmartScopedLock
This is an optimization pass for GlobalISel generic memory operations.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
bool operator<(int64_t V1, const APSInt &V2)
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred)
getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition ...
SDValue peekThroughExtractSubvectors(SDValue V)
Return the non-extracted vector source operand of V if it exists.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
SDValue getBitwiseNotOperand(SDValue V, SDValue Mask, bool AllowUndefs)
If V is a bitwise not, returns the inverted operand.
SDValue peekThroughBitcasts(SDValue V)
Return the non-bitcasted source operand of V if it exists.
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
bool isIntOrFPConstant(SDValue V)
Return true if V is either a integer or FP constant.
bool getAlign(const Function &F, unsigned index, unsigned &align)
bool getConstantDataArrayInfo(const Value *V, ConstantDataArraySlice &Slice, unsigned ElementSize, uint64_t Offset=0)
Returns true if the value V is a pointer into a ConstantDataArray.
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 maximum semantics.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
bool isMinSignedConstant(SDValue V)
Returns true if V is a constant min signed integer value.
ConstantFPSDNode * isConstOrConstSplatFP(SDValue N, bool AllowUndefs=false)
Returns the SDNode if it is a constant splat BuildVector or constant float.
ConstantRange getConstantRangeFromMetadata(const MDNode &RangeMD)
Parse out a conservative ConstantRange from !range metadata.
APFloat frexp(const APFloat &X, int &Exp, APFloat::roundingMode RM)
Equivalent of C standard library function.
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
bool getShuffleDemandedElts(int SrcWidth, ArrayRef< int > Mask, const APInt &DemandedElts, APInt &DemandedLHS, APInt &DemandedRHS, bool AllowUndefElts=false)
Transform a shuffle mask's output demanded element mask into demanded element masks for the 2 operand...
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 maximumNumber semantics.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
bool isBitwiseNot(SDValue V, bool AllowUndefs=false)
Returns true if V is a bitwise not operation.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void checkForCycles(const SelectionDAG *DAG, bool force=false)
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
SDValue peekThroughTruncates(SDValue V)
Return the non-truncated source operand of V if it exists.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)
Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...
SDValue peekThroughOneUseBitcasts(SDValue V)
Return the non-bitcasted and one-use source operand of V if it exists.
CodeGenOptLevel
Code generation optimization level.
bool isOneOrOneSplat(SDValue V, bool AllowUndefs=false)
Return true if the value is a constant 1 integer or a splatted vector of a constant 1 integer (with n...
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 minimumNumber semantics.
@ Mul
Product of integers.
void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
DWARFExpression::Operation Op
ConstantSDNode * isConstOrConstSplat(SDValue N, bool AllowUndefs=false, bool AllowTruncation=false)
Returns the SDNode if it is a constant splat BuildVector or constant int.
OutputIt copy(R &&Range, OutputIt Out)
constexpr unsigned BitWidth
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
bool isNullFPConstant(SDValue V)
Returns true if V is an FP constant with a value of positive zero.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
unsigned Log2(Align A)
Returns the log2 of the alignment.
void computeKnownBitsFromRangeMetadata(const MDNode &Ranges, KnownBits &Known)
Compute known bits from the range metadata.
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 minimum semantics.
bool isNeutralConstant(unsigned Opc, SDNodeFlags Flags, SDValue V, unsigned OperandNo)
Returns true if V is a neutral element of Opc with Flags.
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
constexpr uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * TBAAStruct
The tag for type-based alias analysis (tbaa struct).
MDNode * TBAA
The tag for type-based alias analysis.
static const fltSemantics & IEEEsingle() LLVM_READNONE
cmpResult
IEEE-754R 5.11: Floating Point Comparison Relations.
static constexpr roundingMode rmTowardNegative
static constexpr roundingMode rmNearestTiesToEven
static constexpr roundingMode rmTowardZero
static const fltSemantics & IEEEquad() LLVM_READNONE
static const fltSemantics & IEEEdouble() LLVM_READNONE
static const fltSemantics & IEEEhalf() LLVM_READNONE
static constexpr roundingMode rmTowardPositive
static const fltSemantics & BFloat() LLVM_READNONE
opStatus
IEEE-754R 7: Default exception handling.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Represents offset+length into a ConstantDataArray.
uint64_t Length
Length of the slice.
uint64_t Offset
Slice starts at this Offset.
void move(uint64_t Delta)
Moves the Offset and adjusts Length accordingly.
const ConstantDataArray * Array
ConstantDataArray pointer.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
intptr_t getRawBits() const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
ElementCount getVectorElementCount() const
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
unsigned getVectorMinNumElements() const
Given a vector type, return the minimum number of elements it contains.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
bool isFixedLengthVector() const
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
bool bitsEq(EVT VT) const
Return true if this has the same number of bits as VT.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isScalableVector() const
Return true if this is a vector type where the runtime length is machine dependent.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isExtended() const
Test if the given EVT is extended (as opposed to being simple).
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
bool isInteger() const
Return true if this is an integer or a vector integer type.
static KnownBits makeConstant(const APInt &C)
Create known bits from a known constant.
KnownBits sextInReg(unsigned SrcBitWidth) const
Return known bits for a in-register sign extension of the value we're tracking.
static KnownBits mulhu(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits from zero-extended multiply-hi.
unsigned countMinSignBits() const
Returns the number of times the sign bit is replicated into the other bits.
static KnownBits smax(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for smax(LHS, RHS).
bool isNonNegative() const
Returns true if this value is known to be non-negative.
bool isZero() const
Returns true if value is all zero.
void makeNonNegative()
Make this value non-negative.
static KnownBits usub_sat(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from llvm.usub.sat(LHS, RHS)
unsigned countMinTrailingZeros() const
Returns the minimum number of trailing zero bits.
static KnownBits ashr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for ashr(LHS, RHS).
static KnownBits urem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for urem(LHS, RHS).
bool isUnknown() const
Returns true if we don't know any bits.
unsigned countMaxTrailingZeros() const
Returns the maximum number of trailing zero bits possible.
static std::optional< bool > ne(const KnownBits &LHS, const KnownBits &RHS)
Determine if these known bits always give the same ICMP_NE result.
void makeNegative()
Make this value negative.
KnownBits trunc(unsigned BitWidth) const
Return known bits for a truncation of the value we're tracking.
KnownBits byteSwap() const
bool hasConflict() const
Returns true if there is conflicting information.
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
void setAllZero()
Make all bits known to be zero and discard any previous information.
KnownBits reverseBits() const
KnownBits concat(const KnownBits &Lo) const
Concatenate the bits from Lo onto the bottom of *this.
unsigned getBitWidth() const
Get the bit width of this value.
static KnownBits umax(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for umax(LHS, RHS).
KnownBits zext(unsigned BitWidth) const
Return known bits for a zero extension of the value we're tracking.
void resetAll()
Resets the known state of all bits.
KnownBits unionWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for either this or RHS or both.
static KnownBits lshr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for lshr(LHS, RHS).
bool isNonZero() const
Returns true if this value is known to be non-zero.
static KnownBits abdu(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for abdu(LHS, RHS).
KnownBits extractBits(unsigned NumBits, unsigned BitPosition) const
Return a subset of the known bits from [bitPosition,bitPosition+numBits).
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
KnownBits sext(unsigned BitWidth) const
Return known bits for a sign extension of the value we're tracking.
static KnownBits computeForSubBorrow(const KnownBits &LHS, KnownBits RHS, const KnownBits &Borrow)
Compute known bits results from subtracting RHS from LHS with 1-bit Borrow.
KnownBits zextOrTrunc(unsigned BitWidth) const
Return known bits for a zero extension or truncation of the value we're tracking.
APInt getMaxValue() const
Return the maximal unsigned value possible given these KnownBits.
static KnownBits abds(KnownBits LHS, KnownBits RHS)
Compute known bits for abds(LHS, RHS).
static KnownBits smin(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for smin(LHS, RHS).
static KnownBits mulhs(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits from sign-extended multiply-hi.
static KnownBits srem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for srem(LHS, RHS).
static KnownBits udiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for udiv(LHS, RHS).
static KnownBits computeForAddSub(bool Add, bool NSW, bool NUW, const KnownBits &LHS, const KnownBits &RHS)
Compute known bits resulting from adding LHS and RHS.
bool isStrictlyPositive() const
Returns true if this value is known to be positive.
static KnownBits sdiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for sdiv(LHS, RHS).
static bool haveNoCommonBitsSet(const KnownBits &LHS, const KnownBits &RHS)
Return true if LHS and RHS have no common bits set.
bool isNegative() const
Returns true if this value is known to be negative.
static KnownBits computeForAddCarry(const KnownBits &LHS, const KnownBits &RHS, const KnownBits &Carry)
Compute known bits resulting from adding LHS, RHS and a 1-bit Carry.
unsigned countMaxLeadingZeros() const
Returns the maximum number of leading zero bits possible.
void insertBits(const KnownBits &SubBits, unsigned BitPosition)
Insert the bits from a smaller known bits starting at bitPosition.
static KnownBits mul(const KnownBits &LHS, const KnownBits &RHS, bool NoUndefSelfMultiply=false)
Compute known bits resulting from multiplying LHS and RHS.
KnownBits anyext(unsigned BitWidth) const
Return known bits for an "any" extension of the value we're tracking, where we don't know anything ab...
KnownBits abs(bool IntMinIsPoison=false) const
Compute known bits for the absolute value.
static KnownBits shl(const KnownBits &LHS, const KnownBits &RHS, bool NUW=false, bool NSW=false, bool ShAmtNonZero=false)
Compute known bits for shl(LHS, RHS).
static KnownBits umin(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for umin(LHS, RHS).
This class contains a discriminated union of information about pointers in memory operands,...
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
MachinePointerInfo getWithOffset(int64_t O) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
static MemOp Set(uint64_t Size, bool DstAlignCanChange, Align DstAlign, bool IsZeroMemset, bool IsVolatile)
static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign, Align SrcAlign, bool IsVolatile, bool MemcpyStrSrc=false)
These are IR-level optimization flags that may be propagated to SDNodes.
void intersectWith(const SDNodeFlags Flags)
Clear any flags in this flag set that aren't also set in Flags.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Clients of various APIs that cause global effects on the DAG can optionally implement this interface.
DAGUpdateListener *const Next
virtual void NodeDeleted(SDNode *N, SDNode *E)
The node N that was deleted and, if E is not null, an equivalent node E that replaced it.
virtual void NodeInserted(SDNode *N)
The node N that was inserted.
virtual void NodeUpdated(SDNode *N)
The node N that was updated.
This structure contains all information that is necessary for lowering calls.
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
CallLoweringInfo & setDiscardResult(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
CallLoweringInfo & setTailCall(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)