LLVM 20.0.0git
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This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representation suitable for instruction selection. More...
#include "llvm/CodeGen/SelectionDAG.h"
Classes | |
struct | DAGNodeDeletedListener |
struct | DAGNodeInsertedListener |
struct | DAGUpdateListener |
Clients of various APIs that cause global effects on the DAG can optionally implement this interface. More... | |
class | FlagInserter |
Help to insert SDNodeFlags automatically in transforming. More... | |
Public Types | |
enum | OverflowKind { OFK_Never , OFK_Sometime , OFK_Always } |
Used to represent the possible overflow behavior of an operation. More... | |
using | allnodes_const_iterator = ilist< SDNode >::const_iterator |
using | allnodes_iterator = ilist< SDNode >::iterator |
Public Member Functions | |
SelectionDAG (const TargetMachine &TM, CodeGenOptLevel) | |
SelectionDAG (const SelectionDAG &)=delete | |
SelectionDAG & | operator= (const SelectionDAG &)=delete |
~SelectionDAG () | |
void | init (MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, MachineModuleInfo &MMI, FunctionVarLocs const *FnVarLocs) |
Prepare this SelectionDAG to process code in the given MachineFunction. | |
void | init (MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, MachineFunctionAnalysisManager &AM, const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, MachineModuleInfo &MMI, FunctionVarLocs const *FnVarLocs) |
void | setFunctionLoweringInfo (FunctionLoweringInfo *FuncInfo) |
void | clear () |
Clear state and free memory necessary to make this SelectionDAG ready to process a new block. | |
MachineFunction & | getMachineFunction () const |
const Pass * | getPass () const |
MachineFunctionAnalysisManager * | getMFAM () |
CodeGenOptLevel | getOptLevel () const |
const DataLayout & | getDataLayout () const |
const TargetMachine & | getTarget () const |
const TargetSubtargetInfo & | getSubtarget () const |
template<typename STC > | |
const STC & | getSubtarget () const |
const TargetLowering & | getTargetLoweringInfo () const |
const TargetLibraryInfo & | getLibInfo () const |
const SelectionDAGTargetInfo & | getSelectionDAGInfo () const |
const UniformityInfo * | getUniformityInfo () const |
const FunctionVarLocs * | getFunctionVarLocs () const |
Returns the result of the AssignmentTrackingAnalysis pass if it's available, otherwise return nullptr. | |
LLVMContext * | getContext () const |
OptimizationRemarkEmitter & | getORE () const |
ProfileSummaryInfo * | getPSI () const |
BlockFrequencyInfo * | getBFI () const |
MachineModuleInfo * | getMMI () const |
FlagInserter * | getFlagInserter () |
void | setFlagInserter (FlagInserter *FI) |
LLVM_DUMP_METHOD void | dumpDotGraph (const Twine &FileName, const Twine &Title) |
Just dump dot graph to a user-provided path and title. | |
void | viewGraph (const std::string &Title) |
Pop up a GraphViz/gv window with the DAG rendered using 'dot'. | |
void | viewGraph () |
void | clearGraphAttrs () |
Clear all previously defined node graph attributes. | |
void | setGraphAttrs (const SDNode *N, const char *Attrs) |
Set graph attributes for a node. (eg. "color=red".) | |
std::string | getGraphAttrs (const SDNode *N) const |
Get graph attributes for a node. | |
void | setGraphColor (const SDNode *N, const char *Color) |
Convenience for setting node color attribute. | |
void | setSubgraphColor (SDNode *N, const char *Color) |
Convenience for setting subgraph color attribute. | |
allnodes_const_iterator | allnodes_begin () const |
allnodes_const_iterator | allnodes_end () const |
allnodes_iterator | allnodes_begin () |
allnodes_iterator | allnodes_end () |
ilist< SDNode >::size_type | allnodes_size () const |
iterator_range< allnodes_iterator > | allnodes () |
iterator_range< allnodes_const_iterator > | allnodes () const |
const SDValue & | getRoot () const |
Return the root tag of the SelectionDAG. | |
SDValue | getEntryNode () const |
Return the token chain corresponding to the entry of the function. | |
const SDValue & | setRoot (SDValue N) |
Set the current root tag of the SelectionDAG. | |
void | VerifyDAGDivergence () |
void | Combine (CombineLevel Level, AAResults *AA, CodeGenOptLevel OptLevel) |
This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes. | |
bool | LegalizeTypes () |
This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the target. | |
void | Legalize () |
This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction selector, as indicated by the TargetLowering object. | |
bool | LegalizeOp (SDNode *N, SmallSetVector< SDNode *, 16 > &UpdatedNodes) |
Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target instruction selector, as indicated by the TargetLowering object. | |
bool | LegalizeVectors () |
This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported by the target. | |
void | RemoveDeadNodes () |
This method deletes all unreachable nodes in the SelectionDAG. | |
void | DeleteNode (SDNode *N) |
Remove the specified node from the system. | |
SDVTList | getVTList (EVT VT) |
Return an SDVTList that represents the list of values specified. | |
SDVTList | getVTList (EVT VT1, EVT VT2) |
SDVTList | getVTList (EVT VT1, EVT VT2, EVT VT3) |
SDVTList | getVTList (EVT VT1, EVT VT2, EVT VT3, EVT VT4) |
SDVTList | getVTList (ArrayRef< EVT > VTs) |
SDValue | getGlobalAddress (const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0) |
SDValue | getTargetGlobalAddress (const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0) |
SDValue | getFrameIndex (int FI, EVT VT, bool isTarget=false) |
SDValue | getTargetFrameIndex (int FI, EVT VT) |
SDValue | getJumpTable (int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0) |
SDValue | getTargetJumpTable (int JTI, EVT VT, unsigned TargetFlags=0) |
SDValue | getJumpTableDebugInfo (int JTI, SDValue Chain, const SDLoc &DL) |
SDValue | getConstantPool (const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0) |
SDValue | getTargetConstantPool (const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0) |
SDValue | getConstantPool (MachineConstantPoolValue *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0) |
SDValue | getTargetConstantPool (MachineConstantPoolValue *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0) |
SDValue | getBasicBlock (MachineBasicBlock *MBB) |
SDValue | getExternalSymbol (const char *Sym, EVT VT) |
SDValue | getTargetExternalSymbol (const char *Sym, EVT VT, unsigned TargetFlags=0) |
SDValue | getMCSymbol (MCSymbol *Sym, EVT VT) |
SDValue | getValueType (EVT) |
SDValue | getRegister (unsigned Reg, EVT VT) |
SDValue | getRegisterMask (const uint32_t *RegMask) |
SDValue | getEHLabel (const SDLoc &dl, SDValue Root, MCSymbol *Label) |
SDValue | getLabelNode (unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label) |
SDValue | getBlockAddress (const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0) |
SDValue | getTargetBlockAddress (const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0) |
SDValue | getCopyToReg (SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N) |
SDValue | getCopyToReg (SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N, SDValue Glue) |
SDValue | getCopyToReg (SDValue Chain, const SDLoc &dl, SDValue Reg, SDValue N, SDValue Glue) |
SDValue | getCopyFromReg (SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT) |
SDValue | getCopyFromReg (SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT, SDValue Glue) |
SDValue | getCondCode (ISD::CondCode Cond) |
SDValue | getVectorShuffle (EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask) |
Return an ISD::VECTOR_SHUFFLE node. | |
SDValue | getBuildVector (EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops) |
Return an ISD::BUILD_VECTOR node. | |
SDValue | getBuildVector (EVT VT, const SDLoc &DL, ArrayRef< SDUse > Ops) |
Return an ISD::BUILD_VECTOR node. | |
SDValue | getSplatBuildVector (EVT VT, const SDLoc &DL, SDValue Op) |
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements. | |
SDValue | getSplatVector (EVT VT, const SDLoc &DL, SDValue Op) |
SDValue | getSplat (EVT VT, const SDLoc &DL, SDValue Op) |
Returns a node representing a splat of one value into all lanes of the provided vector type. | |
SDValue | getStepVector (const SDLoc &DL, EVT ResVT, const APInt &StepVal) |
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step, Step * 2, Step * 3, ...> | |
SDValue | getStepVector (const SDLoc &DL, EVT ResVT) |
Returns a vector of type ResVT whose elements contain the linear sequence <0, 1, 2, 3, ...> | |
SDValue | getCommutedVectorShuffle (const ShuffleVectorSDNode &SV) |
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands. | |
SDValue | getFPExtendOrRound (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation). | |
std::pair< SDValue, SDValue > | getStrictFPExtendOrRound (SDValue Op, SDValue Chain, const SDLoc &DL, EVT VT) |
Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending or rounding (by truncation). | |
SDValue | getAnyExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncating it. | |
SDValue | getSExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or truncating it. | |
SDValue | getZExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or truncating it. | |
SDValue | getExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT, unsigned Opcode) |
Convert Op, which must be of integer type, to the integer type VT, by either any/sign/zero-extending (depending on IsAny / IsSigned) or truncating it. | |
SDValue | getExtOrTrunc (bool IsSigned, SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either sign/zero-extending (depending on IsSigned) or truncating it. | |
SDValue | getBitcastedAnyExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either any-extending or truncating it. | |
SDValue | getBitcastedSExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either sign-extending or truncating it. | |
SDValue | getBitcastedZExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either zero-extending or truncating it. | |
SDValue | getZeroExtendInReg (SDValue Op, const SDLoc &DL, EVT VT) |
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value. | |
SDValue | getVPZeroExtendInReg (SDValue Op, SDValue Mask, SDValue EVL, const SDLoc &DL, EVT VT) |
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value. | |
SDValue | getPtrExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or performing either zero or sign extension as appropriate extension for the pointer's semantics. | |
SDValue | getPtrExtendInReg (SDValue Op, const SDLoc &DL, EVT VT) |
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy value. | |
SDValue | getBoolExtOrTrunc (SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT) |
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it. | |
SDValue | getNegative (SDValue Val, const SDLoc &DL, EVT VT) |
Create negative operation as (SUB 0, Val). | |
SDValue | getNOT (const SDLoc &DL, SDValue Val, EVT VT) |
Create a bitwise NOT operation as (XOR Val, -1). | |
SDValue | getLogicalNOT (const SDLoc &DL, SDValue Val, EVT VT) |
Create a logical NOT operation as (XOR Val, BooleanOne). | |
SDValue | getVPLogicalNOT (const SDLoc &DL, SDValue Val, SDValue Mask, SDValue EVL, EVT VT) |
Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask, EVL). | |
SDValue | getVPZExtOrTrunc (const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL) |
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT, by performing either vector-predicated zext or truncating it. | |
SDValue | getVPPtrExtOrTrunc (const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL) |
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT, by either truncating it or performing either vector-predicated zero or sign extension as appropriate extension for the pointer's semantics. | |
SDValue | getMemBasePlusOffset (SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags()) |
Returns sum of the base pointer and offset. | |
SDValue | getMemBasePlusOffset (SDValue Base, SDValue Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags()) |
SDValue | getObjectPtrOffset (const SDLoc &SL, SDValue Ptr, TypeSize Offset) |
Create an add instruction with appropriate flags when used for addressing some offset of an object. | |
SDValue | getObjectPtrOffset (const SDLoc &SL, SDValue Ptr, SDValue Offset) |
SDValue | getCALLSEQ_START (SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL) |
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and OutSize specifies part of the frame set up prior to the sequence. | |
SDValue | getCALLSEQ_END (SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL) |
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd). | |
SDValue | getCALLSEQ_END (SDValue Chain, uint64_t Size1, uint64_t Size2, SDValue Glue, const SDLoc &DL) |
bool | isUndef (unsigned Opcode, ArrayRef< SDValue > Ops) |
Return true if the result of this operation is always undefined. | |
SDValue | getUNDEF (EVT VT) |
Return an UNDEF node. UNDEF does not have a useful SDLoc. | |
SDValue | getVScale (const SDLoc &DL, EVT VT, APInt MulImm, bool ConstantFold=true) |
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'. | |
SDValue | getElementCount (const SDLoc &DL, EVT VT, ElementCount EC, bool ConstantFold=true) |
SDValue | getGLOBAL_OFFSET_TABLE (EVT VT) |
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc. | |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops) |
Gets or creates the specified node. | |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, const SDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, ArrayRef< SDValue > Ops) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT) |
Gets or creates the specified node. | |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand, const SDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, const SDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, const SDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, const SDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5, const SDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) |
SDValue | getStackArgumentTokenFactor (SDValue Chain) |
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack. | |
SDValue | getMemcpy (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr) |
SDValue | getMemmove (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr) |
SDValue | getMemset (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getAtomicMemcpy (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
SDValue | getAtomicMemmove (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
SDValue | getAtomicMemset (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo) |
SDValue | getSetCC (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false) |
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SDValue. | |
SDValue | getSetCCVP (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Mask, SDValue EVL) |
Helper function to make it easier to build VP_SETCCs if you just have an ISD::CondCode instead of an SDValue. | |
SDValue | getSelect (const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS, SDNodeFlags Flags=SDNodeFlags()) |
Helper function to make it easier to build Select's if you just have operands and don't want to check for vector. | |
SDValue | getSelectCC (const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond) |
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an SDValue. | |
SDValue | simplifySelect (SDValue Cond, SDValue TVal, SDValue FVal) |
Try to simplify a select/vselect into 1 of its operands or a constant. | |
SDValue | simplifyShift (SDValue X, SDValue Y) |
Try to simplify a shift into 1 of its operands or a constant. | |
SDValue | simplifyFPBinop (unsigned Opcode, SDValue X, SDValue Y, SDNodeFlags Flags) |
Try to simplify a floating-point binary operation into 1 of its operands or a constant. | |
SDValue | getVAArg (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align) |
VAArg produces a result and token chain, and takes a pointer and a source value as input. | |
SDValue | getAtomicCmpSwap (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO) |
Gets a node for an atomic cmpxchg op. | |
SDValue | getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO) |
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands. | |
SDValue | getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO) |
Gets a node for an atomic op, produces result and chain and takes 1 operand. | |
SDValue | getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTList, ArrayRef< SDValue > Ops, MachineMemOperand *MMO) |
Gets a node for an atomic op, produces result and chain and takes N operands. | |
SDValue | getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes()) |
Creates a MemIntrinsicNode that may produce a result and takes a list of operands. | |
SDValue | getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, MaybeAlign Alignment=std::nullopt, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachineMemOperand *MMO) |
SDValue | getLifetimeNode (bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex, int64_t Size, int64_t Offset=-1) |
Creates a LifetimeSDNode that starts (IsStart==true ) or ends (IsStart==false ) the lifetime of the portion of FrameIndex between offsets Offset and Offset + Size . | |
SDValue | getPseudoProbeNode (const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr) |
Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing, as well as the attributes attr of the probe. | |
SDValue | getMergeValues (ArrayRef< SDValue > Ops, const SDLoc &dl) |
Create a MERGE_VALUES node from the given operands. | |
SDValue | getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr) |
Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain. | |
SDValue | getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO) |
SDValue | getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO) |
SDValue | getIndexedLoad (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr) |
SDValue | getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr) |
SDValue | getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, EVT MemVT, MachineMemOperand *MMO) |
SDValue | getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
Helper function to build ISD::STORE nodes. | |
SDValue | getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachineMemOperand *MMO) |
SDValue | getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, EVT SVT, MachineMemOperand *MMO) |
SDValue | getIndexedStore (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false) |
SDValue | getLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, bool IsExpanding=false) |
SDValue | getLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false) |
SDValue | getLoadVP (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false) |
SDValue | getLoadVP (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachineMemOperand *MMO, bool IsExpanding=false) |
SDValue | getExtLoadVP (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsExpanding=false) |
SDValue | getExtLoadVP (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false) |
SDValue | getIndexedLoadVP (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getStoreVP (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false) |
SDValue | getTruncStoreVP (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsCompressing=false) |
SDValue | getTruncStoreVP (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false) |
SDValue | getIndexedStoreVP (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getStridedLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false) |
SDValue | getStridedLoadVP (EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, MachineMemOperand *MMO, bool IsExpanding=false) |
SDValue | getExtStridedLoadVP (ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false) |
SDValue | getStridedStoreVP (SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false) |
SDValue | getTruncStridedStoreVP (SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false) |
SDValue | getGatherVP (SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType) |
SDValue | getScatterVP (SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType) |
SDValue | getMaskedLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false) |
SDValue | getIndexedMaskedLoad (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getMaskedStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false) |
SDValue | getIndexedMaskedStore (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getMaskedGather (SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy) |
SDValue | getMaskedScatter (SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false) |
SDValue | getMaskedHistogram (SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType) |
SDValue | getGetFPEnv (SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO) |
SDValue | getSetFPEnv (SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO) |
SDValue | getSrcValue (const Value *v) |
Construct a node to track a Value* through the backend. | |
SDValue | getMDNode (const MDNode *MD) |
Return an MDNodeSDNode which holds an MDNode. | |
SDValue | getBitcast (EVT VT, SDValue V) |
Return a bitcast using the SDLoc of the value operand, and casting to the provided type. | |
SDValue | getAddrSpaceCast (const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS) |
Return an AddrSpaceCastSDNode. | |
SDValue | getFreeze (SDValue V) |
Return a freeze using the SDLoc of the value operand. | |
SDValue | getAssertAlign (const SDLoc &DL, SDValue V, Align A) |
Return an AssertAlignSDNode. | |
void | canonicalizeCommutativeBinop (unsigned Opcode, SDValue &N1, SDValue &N2) const |
Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite order. | |
SDValue | getShiftAmountOperand (EVT LHSTy, SDValue Op) |
Return the specified value casted to the target's desired shift amount type. | |
SDValue | expandVAArg (SDNode *Node) |
Expand the specified ISD::VAARG node as the Legalize pass would. | |
SDValue | expandVACopy (SDNode *Node) |
Expand the specified ISD::VACOPY node as the Legalize pass would. | |
SDValue | getSymbolFunctionGlobalAddress (SDValue Op, Function **TargetFunction=nullptr) |
Return a GlobalAddress of the function from the current module with name matching the given ExternalSymbol. | |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op) |
Mutate the specified node in-place to have the specified operands. | |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2) |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) |
SDNode * | UpdateNodeOperands (SDNode *N, ArrayRef< SDValue > Ops) |
SDValue | getTokenFactor (const SDLoc &DL, SmallVectorImpl< SDValue > &Vals) |
Creates a new TokenFactor containing Vals . | |
void | setNodeMemRefs (MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs) |
Mutate the specified machine node's memory references to the provided list. | |
bool | calculateDivergence (SDNode *N) |
void | updateDivergence (SDNode *N) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT) |
These are used for target selectors to mutate the specified node to have the specified return type, Target opcode, and operands. | |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, ArrayRef< SDValue > Ops) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, ArrayRef< SDValue > Ops) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, ArrayRef< SDValue > Ops) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, SDVTList VTs, ArrayRef< SDValue > Ops) |
SDNode * | MorphNodeTo (SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops) |
This mutates the specified node to have the specified return type, opcode, and operands. | |
SDNode * | mutateStrictFPToFP (SDNode *Node) |
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain and dropping the metadata arguments. | |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT) |
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands. | |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, ArrayRef< SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, ArrayRef< SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, ArrayRef< SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, SDVTList VTs, ArrayRef< SDValue > Ops) |
SDValue | getTargetExtractSubreg (int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand) |
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes. | |
SDValue | getTargetInsertSubreg (int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg) |
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes. | |
SDNode * | getNodeIfExists (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags) |
Get the specified node if it's already available, or else return NULL. | |
SDNode * | getNodeIfExists (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops) |
getNodeIfExists - Get the specified node if it's already available, or else return NULL. | |
bool | doesNodeExist (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops) |
Check if a node exists without modifying its flags. | |
SDDbgValue * | getDbgValue (DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O) |
Creates a SDDbgValue node. | |
SDDbgValue * | getConstantDbgValue (DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O) |
Creates a constant SDDbgValue node. | |
SDDbgValue * | getFrameIndexDbgValue (DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O) |
Creates a FrameIndex SDDbgValue node. | |
SDDbgValue * | getFrameIndexDbgValue (DIVariable *Var, DIExpression *Expr, unsigned FI, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O) |
Creates a FrameIndex SDDbgValue node. | |
SDDbgValue * | getVRegDbgValue (DIVariable *Var, DIExpression *Expr, unsigned VReg, bool IsIndirect, const DebugLoc &DL, unsigned O) |
Creates a VReg SDDbgValue node. | |
SDDbgValue * | getDbgValueList (DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic) |
Creates a SDDbgValue node from a list of locations. | |
SDDbgLabel * | getDbgLabel (DILabel *Label, const DebugLoc &DL, unsigned O) |
Creates a SDDbgLabel node. | |
void | transferDbgValues (SDValue From, SDValue To, unsigned OffsetInBits=0, unsigned SizeInBits=0, bool InvalidateDbg=true) |
Transfer debug values from one node to another, while optionally generating fragment expressions for split-up values. | |
void | RemoveDeadNode (SDNode *N) |
Remove the specified node from the system. | |
void | RemoveDeadNodes (SmallVectorImpl< SDNode * > &DeadNodes) |
This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result. | |
void | ReplaceAllUsesWith (SDValue From, SDValue To) |
Modify anything using 'From' to use 'To' instead. | |
void | ReplaceAllUsesWith (SDNode *From, SDNode *To) |
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. | |
void | ReplaceAllUsesWith (SDNode *From, const SDValue *To) |
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. | |
void | ReplaceAllUsesOfValueWith (SDValue From, SDValue To) |
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone. | |
void | ReplaceAllUsesOfValuesWith (const SDValue *From, const SDValue *To, unsigned Num) |
Like ReplaceAllUsesOfValueWith, but for multiple values at once. | |
SDValue | makeEquivalentMemoryOrdering (SDValue OldChain, SDValue NewMemOpChain) |
If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor. | |
SDValue | makeEquivalentMemoryOrdering (LoadSDNode *OldLoad, SDValue NewMemOp) |
If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor. | |
unsigned | AssignTopologicalOrder () |
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order. | |
void | RepositionNode (allnodes_iterator Position, SDNode *N) |
Move node N in the AllNodes list to be immediately before the given iterator Position. | |
void | AddDbgValue (SDDbgValue *DB, bool isParameter) |
Add a dbg_value SDNode. | |
void | AddDbgLabel (SDDbgLabel *DB) |
Add a dbg_label SDNode. | |
ArrayRef< SDDbgValue * > | GetDbgValues (const SDNode *SD) const |
Get the debug values which reference the given SDNode. | |
bool | hasDebugValues () const |
Return true if there are any SDDbgValue nodes associated with this SelectionDAG. | |
SDDbgInfo::DbgIterator | DbgBegin () const |
SDDbgInfo::DbgIterator | DbgEnd () const |
SDDbgInfo::DbgIterator | ByvalParmDbgBegin () const |
SDDbgInfo::DbgIterator | ByvalParmDbgEnd () const |
SDDbgInfo::DbgLabelIterator | DbgLabelBegin () const |
SDDbgInfo::DbgLabelIterator | DbgLabelEnd () const |
void | salvageDebugInfo (SDNode &N) |
To be invoked on an SDNode that is slated to be erased. | |
void | dump () const |
Align | getReducedAlign (EVT VT, bool UseABI) |
In most cases this function returns the ABI alignment for a given type, except for illegal vector types where the alignment exceeds that of the stack. | |
SDValue | CreateStackTemporary (TypeSize Bytes, Align Alignment) |
Create a stack temporary based on the size in bytes and the alignment. | |
SDValue | CreateStackTemporary (EVT VT, unsigned minAlign=1) |
Create a stack temporary, suitable for holding the specified value type. | |
SDValue | CreateStackTemporary (EVT VT1, EVT VT2) |
Create a stack temporary suitable for holding either of the specified value types. | |
SDValue | FoldSymbolOffset (unsigned Opcode, EVT VT, const GlobalAddressSDNode *GA, const SDNode *N2) |
SDValue | FoldConstantArithmetic (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SDNodeFlags Flags=SDNodeFlags()) |
SDValue | foldConstantFPMath (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops) |
Fold floating-point operations when all operands are constants and/or undefined. | |
SDValue | FoldSetCC (EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl) |
Constant fold a setcc to true or false. | |
bool | SignBitIsZero (SDValue Op, unsigned Depth=0) const |
Return true if the sign bit of Op is known to be zero. | |
bool | MaskedValueIsZero (SDValue Op, const APInt &Mask, unsigned Depth=0) const |
Return true if 'Op & Mask' is known to be zero. | |
bool | MaskedValueIsZero (SDValue Op, const APInt &Mask, const APInt &DemandedElts, unsigned Depth=0) const |
Return true if 'Op & Mask' is known to be zero in DemandedElts. | |
bool | MaskedVectorIsZero (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const |
Return true if 'Op' is known to be zero in DemandedElts. | |
bool | MaskedValueIsAllOnes (SDValue Op, const APInt &Mask, unsigned Depth=0) const |
Return true if '(Op & Mask) == Mask'. | |
APInt | computeVectorKnownZeroElements (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const |
For each demanded element of a vector, see if it is known to be zero. | |
KnownBits | computeKnownBits (SDValue Op, unsigned Depth=0) const |
Determine which bits of Op are known to be either zero or one and return them in Known. | |
KnownBits | computeKnownBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const |
Determine which bits of Op are known to be either zero or one and return them in Known. | |
OverflowKind | computeOverflowForSignedAdd (SDValue N0, SDValue N1) const |
Determine if the result of the signed addition of 2 nodes can overflow. | |
OverflowKind | computeOverflowForUnsignedAdd (SDValue N0, SDValue N1) const |
Determine if the result of the unsigned addition of 2 nodes can overflow. | |
OverflowKind | computeOverflowForAdd (bool IsSigned, SDValue N0, SDValue N1) const |
Determine if the result of the addition of 2 nodes can overflow. | |
bool | willNotOverflowAdd (bool IsSigned, SDValue N0, SDValue N1) const |
Determine if the result of the addition of 2 nodes can never overflow. | |
OverflowKind | computeOverflowForSignedSub (SDValue N0, SDValue N1) const |
Determine if the result of the signed sub of 2 nodes can overflow. | |
OverflowKind | computeOverflowForUnsignedSub (SDValue N0, SDValue N1) const |
Determine if the result of the unsigned sub of 2 nodes can overflow. | |
OverflowKind | computeOverflowForSub (bool IsSigned, SDValue N0, SDValue N1) const |
Determine if the result of the sub of 2 nodes can overflow. | |
bool | willNotOverflowSub (bool IsSigned, SDValue N0, SDValue N1) const |
Determine if the result of the sub of 2 nodes can never overflow. | |
OverflowKind | computeOverflowForSignedMul (SDValue N0, SDValue N1) const |
Determine if the result of the signed mul of 2 nodes can overflow. | |
OverflowKind | computeOverflowForUnsignedMul (SDValue N0, SDValue N1) const |
Determine if the result of the unsigned mul of 2 nodes can overflow. | |
OverflowKind | computeOverflowForMul (bool IsSigned, SDValue N0, SDValue N1) const |
Determine if the result of the mul of 2 nodes can overflow. | |
bool | willNotOverflowMul (bool IsSigned, SDValue N0, SDValue N1) const |
Determine if the result of the mul of 2 nodes can never overflow. | |
bool | isKnownToBeAPowerOfTwo (SDValue Val, unsigned Depth=0) const |
Test if the given value is known to have exactly one bit set. | |
bool | isKnownToBeAPowerOfTwoFP (SDValue Val, unsigned Depth=0) const |
Test if the given fp value is known to be an integer power-of-2, either positive or negative. | |
unsigned | ComputeNumSignBits (SDValue Op, unsigned Depth=0) const |
Return the number of times the sign bit of the register is replicated into the other bits. | |
unsigned | ComputeNumSignBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const |
Return the number of times the sign bit of the register is replicated into the other bits. | |
unsigned | ComputeMaxSignificantBits (SDValue Op, unsigned Depth=0) const |
Get the upper bound on bit size for this Value Op as a signed integer. | |
unsigned | ComputeMaxSignificantBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const |
Get the upper bound on bit size for this Value Op as a signed integer. | |
bool | isGuaranteedNotToBeUndefOrPoison (SDValue Op, bool PoisonOnly=false, unsigned Depth=0) const |
Return true if this function can prove that Op is never poison and, if PoisonOnly is false, does not have undef bits. | |
bool | isGuaranteedNotToBeUndefOrPoison (SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, unsigned Depth=0) const |
Return true if this function can prove that Op is never poison and, if PoisonOnly is false, does not have undef bits. | |
bool | isGuaranteedNotToBePoison (SDValue Op, unsigned Depth=0) const |
Return true if this function can prove that Op is never poison. | |
bool | isGuaranteedNotToBePoison (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const |
Return true if this function can prove that Op is never poison. | |
bool | canCreateUndefOrPoison (SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, bool ConsiderFlags=true, unsigned Depth=0) const |
Return true if Op can create undef or poison from non-undef & non-poison operands. | |
bool | canCreateUndefOrPoison (SDValue Op, bool PoisonOnly=false, bool ConsiderFlags=true, unsigned Depth=0) const |
Return true if Op can create undef or poison from non-undef & non-poison operands. | |
bool | isADDLike (SDValue Op, bool NoWrap=false) const |
Return true if the specified operand is an ISD::OR or ISD::XOR node that can be treated as an ISD::ADD node. | |
bool | isBaseWithConstantOffset (SDValue Op) const |
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that is guaranteed to have the same semantics as an ADD. | |
bool | isKnownNeverNaN (SDValue Op, bool SNaN=false, unsigned Depth=0) const |
Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN. | |
bool | isKnownNeverSNaN (SDValue Op, unsigned Depth=0) const |
bool | isKnownNeverZeroFloat (SDValue Op) const |
Test whether the given floating point SDValue is known to never be positive or negative zero. | |
bool | isKnownNeverZero (SDValue Op, unsigned Depth=0) const |
Test whether the given SDValue is known to contain non-zero value(s). | |
bool | cannotBeOrderedNegativeFP (SDValue Op) const |
Test whether the given float value is known to be positive. | |
bool | isEqualTo (SDValue A, SDValue B) const |
Test whether two SDValues are known to compare equal. | |
bool | haveNoCommonBitsSet (SDValue A, SDValue B) const |
Return true if A and B have no common bits set. | |
bool | isSplatValue (SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const |
Test whether V has a splatted value for all the demanded elements. | |
bool | isSplatValue (SDValue V, bool AllowUndefs=false) const |
Test whether V has a splatted value. | |
SDValue | getSplatSourceVector (SDValue V, int &SplatIndex) |
If V is a splatted value, return the source vector and its splat index. | |
SDValue | getSplatValue (SDValue V, bool LegalTypes=false) |
If V is a splat vector, return its scalar source operand by extracting that element from the source vector. | |
std::optional< ConstantRange > | getValidShiftAmountRange (SDValue V, const APInt &DemandedElts, unsigned Depth) const |
If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the valid constant range. | |
std::optional< uint64_t > | getValidShiftAmount (SDValue V, const APInt &DemandedElts, unsigned Depth=0) const |
If a SHL/SRA/SRL node V has a uniform shift amount that is less than the element bit-width of the shift node, return it. | |
std::optional< uint64_t > | getValidShiftAmount (SDValue V, unsigned Depth=0) const |
If a SHL/SRA/SRL node V has a uniform shift amount that is less than the element bit-width of the shift node, return it. | |
std::optional< uint64_t > | getValidMinimumShiftAmount (SDValue V, const APInt &DemandedElts, unsigned Depth=0) const |
If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value. | |
std::optional< uint64_t > | getValidMinimumShiftAmount (SDValue V, unsigned Depth=0) const |
If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value. | |
std::optional< uint64_t > | getValidMaximumShiftAmount (SDValue V, const APInt &DemandedElts, unsigned Depth=0) const |
If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value. | |
std::optional< uint64_t > | getValidMaximumShiftAmount (SDValue V, unsigned Depth=0) const |
If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value. | |
SDValue | matchBinOpReduction (SDNode *Extract, ISD::NodeType &BinOp, ArrayRef< ISD::NodeType > CandidateBinOps, bool AllowPartials=false) |
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract. | |
SDValue | UnrollVectorOp (SDNode *N, unsigned ResNE=0) |
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the scalars and operating on each element individually. | |
std::pair< SDValue, SDValue > | UnrollVectorOverflowOp (SDNode *N, unsigned ResNE=0) |
Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes. | |
bool | areNonVolatileConsecutiveLoads (LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const |
Return true if loads are next to each other and can be merged. | |
MaybeAlign | InferPtrAlign (SDValue Ptr) const |
Infer alignment of a load / store address. | |
std::pair< SDValue, SDValue > | SplitScalar (const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT) |
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part. | |
std::pair< EVT, EVT > | GetSplitDestVTs (const EVT &VT) const |
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces. | |
std::pair< EVT, EVT > | GetDependentSplitDestVTs (const EVT &VT, const EVT &EnvVT, bool *HiIsEmpty) const |
Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces. | |
std::pair< SDValue, SDValue > | SplitVector (const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT) |
Split the vector with EXTRACT_SUBVECTOR using the provided VTs and return the low/high part. | |
std::pair< SDValue, SDValue > | SplitVector (const SDValue &N, const SDLoc &DL) |
Split the vector with EXTRACT_SUBVECTOR and return the low/high part. | |
std::pair< SDValue, SDValue > | SplitEVL (SDValue N, EVT VecVT, const SDLoc &DL) |
Split the explicit vector length parameter of a VP operation. | |
std::pair< SDValue, SDValue > | SplitVectorOperand (const SDNode *N, unsigned OpNo) |
Split the node's operand with EXTRACT_SUBVECTOR and return the low/high part. | |
SDValue | WidenVector (const SDValue &N, const SDLoc &DL) |
Widen the vector up to the next power of two using INSERT_SUBVECTOR. | |
void | ExtractVectorElements (SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT()) |
Append the extracted elements from Start to Count out of the vector Op in Args. | |
Align | getEVTAlign (EVT MemoryVT) const |
Compute the default alignment value for the given type. | |
SDNode * | isConstantIntBuildVectorOrConstantInt (SDValue N) const |
Test whether the given value is a constant int or similar node. | |
SDNode * | isConstantFPBuildVectorOrConstantFP (SDValue N) const |
Test whether the given value is a constant FP or similar node. | |
bool | isConstantValueOfAnyType (SDValue N) const |
std::optional< bool > | isBoolConstant (SDValue N, bool AllowTruncation=false) const |
Check if a value \op N is a constant using the target's BooleanContent for its type. | |
void | addCallSiteInfo (const SDNode *Node, CallSiteInfo &&CallInfo) |
Set CallSiteInfo to be associated with Node. | |
CallSiteInfo | getCallSiteInfo (const SDNode *Node) |
Return CallSiteInfo associated with Node, or a default if none exists. | |
void | addHeapAllocSite (const SDNode *Node, MDNode *MD) |
Set HeapAllocSite to be associated with Node. | |
MDNode * | getHeapAllocSite (const SDNode *Node) const |
Return HeapAllocSite associated with Node, or nullptr if none exists. | |
void | addPCSections (const SDNode *Node, MDNode *MD) |
Set PCSections to be associated with Node. | |
void | addMMRAMetadata (const SDNode *Node, MDNode *MMRA) |
Set MMRAMetadata to be associated with Node. | |
MDNode * | getPCSections (const SDNode *Node) const |
Return PCSections associated with Node, or nullptr if none exists. | |
MDNode * | getMMRAMetadata (const SDNode *Node) const |
Return the MMRA MDNode associated with Node, or nullptr if none exists. | |
void | addNoMergeSiteInfo (const SDNode *Node, bool NoMerge) |
Set NoMergeSiteInfo to be associated with Node if NoMerge is true. | |
bool | getNoMergeSiteInfo (const SDNode *Node) const |
Return NoMerge info associated with Node. | |
void | copyExtraInfo (SDNode *From, SDNode *To) |
Copy extra info associated with one node to another. | |
DenormalMode | getDenormalMode (EVT VT) const |
Return the current function's default denormal handling kind for the given floating point type. | |
bool | shouldOptForSize () const |
SDValue | getNeutralElement (unsigned Opcode, const SDLoc &DL, EVT VT, SDNodeFlags Flags) |
Get the (commutative) neutral element for the given opcode, if it exists. | |
bool | isSafeToSpeculativelyExecute (unsigned Opcode) const |
Some opcodes may create immediate undefined behavior when used with some values (integer division-by-zero for example). | |
bool | isSafeToSpeculativelyExecuteNode (const SDNode *N) const |
Check if the provided node is save to speculatively executed given its current arguments. | |
SDValue | makeStateFunctionCall (unsigned LibFunc, SDValue Ptr, SDValue InChain, const SDLoc &DLoc) |
Helper used to make a call to a library function that has one argument of pointer type. | |
SDValue | getConstant (uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false) |
Create a ConstantSDNode wrapping a constant value. | |
SDValue | getConstant (const APInt &Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false) |
SDValue | getSignedConstant (int64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false) |
SDValue | getAllOnesConstant (const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false) |
SDValue | getConstant (const ConstantInt &Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false) |
SDValue | getIntPtrConstant (uint64_t Val, const SDLoc &DL, bool isTarget=false) |
SDValue | getShiftAmountConstant (uint64_t Val, EVT VT, const SDLoc &DL) |
SDValue | getShiftAmountConstant (const APInt &Val, EVT VT, const SDLoc &DL) |
SDValue | getVectorIdxConstant (uint64_t Val, const SDLoc &DL, bool isTarget=false) |
SDValue | getTargetConstant (uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false) |
SDValue | getTargetConstant (const APInt &Val, const SDLoc &DL, EVT VT, bool isOpaque=false) |
SDValue | getTargetConstant (const ConstantInt &Val, const SDLoc &DL, EVT VT, bool isOpaque=false) |
SDValue | getBoolConstant (bool V, const SDLoc &DL, EVT VT, EVT OpVT) |
Create a true or false constant of type VT using the target's BooleanContent for type OpVT . | |
SDValue | getConstantFP (double Val, const SDLoc &DL, EVT VT, bool isTarget=false) |
Create a ConstantFPSDNode wrapping a constant value. | |
SDValue | getConstantFP (const APFloat &Val, const SDLoc &DL, EVT VT, bool isTarget=false) |
SDValue | getConstantFP (const ConstantFP &V, const SDLoc &DL, EVT VT, bool isTarget=false) |
SDValue | getTargetConstantFP (double Val, const SDLoc &DL, EVT VT) |
SDValue | getTargetConstantFP (const APFloat &Val, const SDLoc &DL, EVT VT) |
SDValue | getTargetConstantFP (const ConstantFP &Val, const SDLoc &DL, EVT VT) |
Static Public Member Functions | |
static unsigned | getOpcode_EXTEND (unsigned Opcode) |
Convert *_EXTEND_VECTOR_INREG to *_EXTEND opcode. | |
static unsigned | getOpcode_EXTEND_VECTOR_INREG (unsigned Opcode) |
Convert *_EXTEND to *_EXTEND_VECTOR_INREG opcode. | |
Public Attributes | |
bool | NewNodesMustHaveLegalTypes = false |
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG nodes that have legal types. | |
Static Public Attributes | |
static constexpr unsigned | MaxRecursionDepth = 6 |
Friends | |
struct | DAGUpdateListener |
DAGUpdateListener is a friend so it can manipulate the listener stack. | |
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representation suitable for instruction selection.
This DAG is constructed as the first step of instruction selection in order to allow implementation of machine specific optimizations and code simplifications.
The representation used by the SelectionDAG is a target-independent representation, which has some similarities to the GCC RTL representation, but is significantly more simple, powerful, and is a graph form instead of a linear form.
Definition at line 226 of file SelectionDAG.h.
Definition at line 545 of file SelectionDAG.h.
using llvm::SelectionDAG::allnodes_iterator = ilist<SDNode>::iterator |
Definition at line 550 of file SelectionDAG.h.
Used to represent the possible overflow behavior of an operation.
Never: the operation cannot overflow. Always: the operation will always overflow. Sometime: the operation may or may not overflow.
Enumerator | |
---|---|
OFK_Never | |
OFK_Sometime | |
OFK_Always |
Definition at line 1953 of file SelectionDAG.h.
|
explicit |
Definition at line 1323 of file SelectionDAG.cpp.
|
delete |
SelectionDAG::~SelectionDAG | ( | ) |
Definition at line 1351 of file SelectionDAG.cpp.
References assert().
|
inline |
Set CallSiteInfo to be associated with Node.
Definition at line 2317 of file SelectionDAG.h.
void SelectionDAG::AddDbgLabel | ( | SDDbgLabel * | DB | ) |
Add a dbg_label SDNode.
Definition at line 11854 of file SelectionDAG.cpp.
References llvm::SDDbgInfo::add().
Referenced by llvm::SelectionDAGBuilder::visitDbgInfo().
void SelectionDAG::AddDbgValue | ( | SDDbgValue * | DB, |
bool | isParameter | ||
) |
Add a dbg_value SDNode.
AddDbgValue - Add a dbg_value SDNode.
If SD is non-null that means the value is produced by SD.
Definition at line 11844 of file SelectionDAG.cpp.
References llvm::SDDbgInfo::add(), assert(), and llvm::SDDbgInfo::getSDDbgValues().
Referenced by handleDanglingVariadicDebugInfo(), llvm::SelectionDAGBuilder::handleDebugDeclare(), llvm::SelectionDAGBuilder::handleDebugValue(), llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), salvageDebugInfo(), llvm::SelectionDAGBuilder::salvageUnresolvedDbgValue(), and transferDbgValues().
Set HeapAllocSite to be associated with Node.
Definition at line 2326 of file SelectionDAG.h.
Set MMRAMetadata to be associated with Node.
Definition at line 2339 of file SelectionDAG.h.
Referenced by llvm::SelectionDAGBuilder::visit().
Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
Definition at line 2354 of file SelectionDAG.h.
Referenced by llvm::SystemZTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerCall().
Set PCSections to be associated with Node.
Definition at line 2335 of file SelectionDAG.h.
Referenced by llvm::SelectionDAGBuilder::visit().
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inline |
Definition at line 559 of file SelectionDAG.h.
References allnodes_begin(), allnodes_end(), and llvm::make_range().
Referenced by AssignTopologicalOrder(), dump(), llvm::HexagonDAGToDAGISel::PreprocessISelDAG(), RemoveDeadNodes(), and llvm::DAGTypeLegalizer::run().
|
inline |
Definition at line 562 of file SelectionDAG.h.
References allnodes_begin(), allnodes_end(), and llvm::make_range().
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inline |
Definition at line 552 of file SelectionDAG.h.
|
inline |
Definition at line 547 of file SelectionDAG.h.
Referenced by allnodes(), AssignTopologicalOrder(), Legalize(), llvm::AMDGPUDAGToDAGISel::PostprocessISelDAG(), llvm::RISCVDAGToDAGISel::PostprocessISelDAG(), llvm::AMDGPUDAGToDAGISel::PreprocessISelDAG(), and llvm::RISCVDAGToDAGISel::PreprocessISelDAG().
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inline |
Definition at line 553 of file SelectionDAG.h.
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inline |
Definition at line 548 of file SelectionDAG.h.
Referenced by allnodes(), Legalize(), llvm::AMDGPUDAGToDAGISel::PostprocessISelDAG(), llvm::RISCVDAGToDAGISel::PostprocessISelDAG(), llvm::AMDGPUDAGToDAGISel::PreprocessISelDAG(), and llvm::RISCVDAGToDAGISel::PreprocessISelDAG().
Definition at line 555 of file SelectionDAG.h.
Referenced by AssignTopologicalOrder(), and llvm::HexagonDAGToDAGISel::PreprocessISelDAG().
bool SelectionDAG::areNonVolatileConsecutiveLoads | ( | LoadSDNode * | LD, |
LoadSDNode * | Base, | ||
unsigned | Bytes, | ||
int | Dist | ||
) | const |
Return true if loads are next to each other and can be merged.
Check that both are nonvolatile and if LD is loading 'Bytes' bytes from a location that is 'Dist' units away from the location that the 'Base' load is loading from.
Definition at line 12577 of file SelectionDAG.cpp.
References llvm::sampleprof::Base, llvm::EVT::getSizeInBits(), llvm::BaseIndexOffset::match(), and llvm::Offset.
Referenced by areLoadedOffsetButOtherwiseSame(), combineBVOfConsecutiveLoads(), combineINSERT_SUBVECTOR(), EltsFromConsecutiveLoads(), and lowerShuffleAsVTRUNC().
unsigned SelectionDAG::AssignTopologicalOrder | ( | ) |
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order.
AssignTopologicalOrder - Assign a unique node id for each node in the DAG based on their topological order.
Returns the number of nodes.
It returns the maximum id and a vector of the SDNodes* in assigned order by reference.
Definition at line 11758 of file SelectionDAG.cpp.
References allnodes(), allnodes_begin(), allnodes_size(), assert(), llvm::checkForCycles(), llvm::dbgs(), llvm::SDNode::dumprFull(), llvm::ISD::EntryToken, I, llvm_unreachable, llvm::make_early_inc_range(), N, and P.
Referenced by Legalize().
|
inline |
Definition at line 1850 of file SelectionDAG.h.
References llvm::SDDbgInfo::ByvalParmDbgBegin().
Referenced by dump(), and llvm::ScheduleDAGSDNodes::EmitSchedule().
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inline |
Definition at line 1853 of file SelectionDAG.h.
References llvm::SDDbgInfo::ByvalParmDbgEnd().
Referenced by dump(), and llvm::ScheduleDAGSDNodes::EmitSchedule().
Definition at line 11626 of file SelectionDAG.cpp.
References assert(), gluePropagatesDivergence(), llvm::TargetLowering::isSDNodeAlwaysUniform(), llvm::TargetLowering::isSDNodeSourceOfDivergence(), and N.
Referenced by updateDivergence(), and VerifyDAGDivergence().
bool SelectionDAG::canCreateUndefOrPoison | ( | SDValue | Op, |
bool | PoisonOnly = false , |
||
bool | ConsiderFlags = true , |
||
unsigned | Depth = 0 |
||
) | const |
Return true if Op can create undef or poison from non-undef & non-poison operands.
ConsiderFlags
controls whether poison producing flags on the instruction are considered. This can be used to see if the instruction could still introduce undef or poison even without poison generating flags which might be on the instruction. (i.e. could the result of Op->dropPoisonGeneratingFlags() still create poison or undef)
Definition at line 5250 of file SelectionDAG.cpp.
References canCreateUndefOrPoison(), llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), llvm::EVT::isFixedLengthVector(), and PoisonOnly.
bool SelectionDAG::canCreateUndefOrPoison | ( | SDValue | Op, |
const APInt & | DemandedElts, | ||
bool | PoisonOnly = false , |
||
bool | ConsiderFlags = true , |
||
unsigned | Depth = 0 |
||
) | const |
Return true if Op can create undef or poison from non-undef & non-poison operands.
The DemandedElts argument limits the check to the requested vector elements.
ConsiderFlags
controls whether poison producing flags on the instruction are considered. This can be used to see if the instruction could still introduce undef or poison even without poison generating flags which might be on the instruction. (i.e. could the result of Op->dropPoisonGeneratingFlags() still create poison or undef)
Definition at line 5261 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::ISD::BSWAP, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::TargetLowering::canCreateUndefOrPoisonForTargetNode(), computeKnownBits(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::CTPOP, llvm::Depth, llvm::enumerate(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FREEZE, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::KnownBits::getMaxValue(), getTarget(), getValidMaximumShiftAmount(), llvm::EVT::getVectorMinNumElements(), Idx, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, isGuaranteedNotToBeUndefOrPoison(), llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::TargetMachine::Options, Options, llvm::ISD::OR, llvm::ISD::PARITY, PoisonOnly, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDSAT, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UADDSAT, llvm::APInt::uge(), llvm::APInt::ugt(), llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::USUBSAT, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.
Referenced by canCreateUndefOrPoison(), and isGuaranteedNotToBeUndefOrPoison().
Test whether the given float value is known to be positive.
+0.0, +inf and +nan are considered positive, -0.0, -inf and -nan are not.
Definition at line 5686 of file SelectionDAG.cpp.
References llvm::ISD::FABS, and llvm::isConstOrConstSplatFP().
void SelectionDAG::canonicalizeCommutativeBinop | ( | unsigned | Opcode, |
SDValue & | N1, | ||
SDValue & | N2 | ||
) | const |
Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite order.
Definition at line 6894 of file SelectionDAG.cpp.
References llvm::SDValue::getOpcode(), llvm::TargetLoweringBase::isCommutativeBinOp(), isConstantFPBuildVectorOrConstantFP(), isConstantIntBuildVectorOrConstantInt(), llvm::ISD::SPLAT_VECTOR, llvm::ISD::STEP_VECTOR, and std::swap().
Referenced by getNode().
void SelectionDAG::clear | ( | ) |
Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
Definition at line 1413 of file SelectionDAG.cpp.
References llvm::SDDbgInfo::clear(), getEntryNode(), and llvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Reset().
void SelectionDAG::clearGraphAttrs | ( | ) |
Clear all previously defined node graph attributes.
clearGraphAttrs - Clear all previously defined node graph attributes.
Intended to be used from a debugging tool (eg. gdb).
Definition at line 179 of file SelectionDAGPrinter.cpp.
References llvm::errs().
void SelectionDAG::Combine | ( | CombineLevel | Level, |
AAResults * | AA, | ||
CodeGenOptLevel | OptLevel | ||
) |
This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes.
This is the entry point for the file.
The Level argument controls whether Combine is allowed to produce nodes and types that are illegal on the target.
This is the main entry point to this class.
Definition at line 28806 of file DAGCombiner.cpp.
KnownBits SelectionDAG::computeKnownBits | ( | SDValue | Op, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
Determine which bits of Op are known to be either zero or one and return them in Known.
The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements. Targets can implement the computeKnownBitsForTargetNode method in the TargetLowering class to allow target nodes to be understood.
The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements.
Definition at line 3164 of file SelectionDAG.cpp.
References llvm::ISD::ABDS, llvm::KnownBits::abds(), llvm::ISD::ABDU, llvm::KnownBits::abdu(), llvm::ISD::ABS, llvm::KnownBits::abs(), llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm::KnownBits::anyext(), llvm::KnownBits::ashr(), assert(), llvm::ISD::AssertAlign, llvm::ISD::AssertZext, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_CLR, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_SWAP, llvm::ISD::AVGCEILS, llvm::KnownBits::avgCeilS(), llvm::ISD::AVGCEILU, llvm::KnownBits::avgCeilU(), llvm::ISD::AVGFLOORS, llvm::KnownBits::avgFloorS(), llvm::ISD::AVGFLOORU, llvm::KnownBits::avgFloorU(), llvm::bit_width(), llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::BitWidth, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::KnownBits::byteSwap(), llvm::CallingConv::C, llvm::APInt::clearAllBits(), llvm::APInt::clearBit(), llvm::APInt::clearLowBits(), llvm::KnownBits::computeForAddCarry(), llvm::KnownBits::computeForAddSub(), llvm::KnownBits::computeForSubBorrow(), computeKnownBits(), llvm::TargetLowering::computeKnownBitsForFrameIndex(), llvm::TargetLowering::computeKnownBitsForTargetNode(), llvm::computeKnownBitsFromRangeMetadata(), ComputeNumSignBits(), llvm::KnownBits::concat(), llvm::ISD::CONCAT_VECTORS, llvm::APInt::countl_zero(), llvm::KnownBits::countMaxLeadingZeros(), llvm::KnownBits::countMaxPopulation(), llvm::KnownBits::countMaxTrailingZeros(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::Depth, llvm::enumerate(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::KnownBits::extractBits(), F, llvm::ISD::FGETSIGN, llvm::ISD::FP_TO_UINT_SAT, llvm::ISD::FrameIndex, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::Constant::getAggregateElement(), llvm::getAlign(), llvm::APInt::getAllOnes(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitsSetFrom(), llvm::APInt::getBitWidth(), llvm::KnownBits::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), getDataLayout(), llvm::TargetLoweringBase::getExtendForAtomicOps(), llvm::MachineFunction::getFunction(), llvm::APInt::getHiBits(), llvm::APInt::getLowBitsSet(), getMachineFunction(), llvm::ShuffleVectorSDNode::getMask(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::APInt::getNumSignBits(), llvm::APInt::getOneBitSet(), llvm::Type::getPrimitiveSizeInBits(), llvm::EVT::getScalarSizeInBits(), llvm::Type::getScalarSizeInBits(), llvm::getShuffleDemandedElts(), llvm::EVT::getSizeInBits(), llvm::Constant::getSplatValue(), llvm::TargetLowering::getTargetConstantFromLoad(), llvm::Value::getType(), llvm::ConstantRange::getUnsignedMax(), getValidMinimumShiftAmount(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::getVScaleRange(), llvm::APInt::getZero(), I, Idx, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::APInt::insertBits(), llvm::KnownBits::insertBits(), llvm::KnownBits::intersectWith(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isConstOrConstSplat(), llvm::ISD::isEXTLoad(), llvm::EVT::isFloatingPoint(), isGuaranteedNotToBeUndefOrPoison(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::APInt::isNegative(), llvm::KnownBits::isNegative(), llvm::ISD::isNON_EXTLoad(), llvm::APInt::isNonNegative(), llvm::KnownBits::isNonNegative(), llvm::KnownBits::isNonZero(), llvm::APInt::isPowerOf2(), llvm::EVT::isScalableVector(), llvm::ISD::isSEXTLoad(), llvm::isUIntN(), llvm::KnownBits::isUnknown(), llvm::EVT::isVector(), llvm::Type::isVectorTy(), llvm::ISD::isZEXTLoad(), LHS, llvm::ISD::LOAD, llvm::Log2(), llvm::APInt::logBase2(), llvm::KnownBits::lshr(), llvm::APInt::lshrInPlace(), llvm::KnownBits::makeConstant(), llvm::KnownBits::makeNegative(), llvm::KnownBits::makeNonNegative(), MaxRecursionDepth, llvm::ISD::MERGE_VALUES, llvm::ISD::MUL, llvm::KnownBits::mul(), llvm::ISD::MULHS, llvm::KnownBits::mulhs(), llvm::ISD::MULHU, llvm::KnownBits::mulhu(), llvm::ConstantRange::multiply(), llvm::Offset, llvm::KnownBits::One, llvm::ISD::OR, llvm::ISD::PARITY, llvm::KnownBits::resetAll(), llvm::KnownBits::reverseBits(), RHS, llvm::ISD::SADDO, llvm::ISD::SADDO_CARRY, llvm::ISD::SCALAR_TO_VECTOR, llvm::APIntOps::ScaleBitMask(), llvm::ISD::SDIV, llvm::KnownBits::sdiv(), llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::APInt::setAllBits(), llvm::KnownBits::setAllZero(), llvm::APInt::setBit(), llvm::APInt::setBitsFrom(), llvm::ISD::SETCC, llvm::ISD::SETCCCARRY, llvm::APInt::setHighBits(), llvm::APInt::setLowBits(), llvm::KnownBits::sext(), llvm::KnownBits::sextInReg(), llvm::APInt::shl(), llvm::ISD::SHL, llvm::KnownBits::shl(), llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SINT_TO_FP, llvm::ArrayRef< T >::size(), llvm::APInt::sle(), llvm::ISD::SMAX, llvm::KnownBits::smax(), llvm::ISD::SMIN, llvm::KnownBits::smin(), llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::Splat, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SPLAT_VECTOR_PARTS, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::KnownBits::srem(), llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SSUBO_CARRY, llvm::ISD::STEP_VECTOR, llvm::ISD::STRICT_FSETCC, llvm::ISD::STRICT_FSETCCS, llvm::ISD::SUB, llvm::ISD::SUBC, std::swap(), llvm::ISD::TargetFrameIndex, llvm::ConstantRange::toKnownBits(), llvm::KnownBits::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::UDIV, llvm::KnownBits::udiv(), llvm::ISD::UINT_TO_FP, llvm::ISD::UMAX, llvm::KnownBits::umax(), llvm::ISD::UMIN, llvm::KnownBits::umin(), llvm::ISD::UMUL_LOHI, llvm::APInt::umul_ov(), umul_ov(), llvm::ISD::UMULO, llvm::KnownBits::unionWith(), llvm::ISD::UREM, llvm::KnownBits::urem(), llvm::KnownBits::usub_sat(), llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::USUBSAT, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSCALE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, llvm::KnownBits::zext(), llvm::APInt::zext(), llvm::ISD::ZEXTLOAD, and llvm::KnownBits::zextOrTrunc().
Determine which bits of Op are known to be either zero or one and return them in Known.
For vectors, the known bits are those that are shared by every vector element. Targets can implement the computeKnownBitsForTargetNode method in the TargetLowering class to allow target nodes to be understood.
For vectors, the known bits are those that are shared by every vector element.
Definition at line 3149 of file SelectionDAG.cpp.
References computeKnownBits(), llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().
Referenced by adjustForRedundantAnd(), llvm::TargetLowering::BuildUDIV(), canCreateUndefOrPoison(), cannotBeIntMin(), checkDot4MulSignedness(), llvm::SelectionDAGISel::CheckOrMask(), checkZExtBool(), combineArithReduction(), combineFaddCFmul(), combineFMulcFCMulc(), combineMOVMSK(), combinePMULH(), combineScalarToVector(), combineSetCC(), combineShiftToAVG(), computeKnownBits(), computeKnownBitsBinOp(), computeKnownBitsForHorizontalOperation(), computeKnownBitsForPMADDUBSW(), computeKnownBitsForPMADDWD(), computeKnownBitsForPSADBW(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::SITargetLowering::computeKnownBitsForTargetNode(), llvm::LanaiTargetLowering::computeKnownBitsForTargetNode(), llvm::SparcTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), ComputeNumSignBits(), computeOverflowForSignedMul(), computeOverflowForSignedSub(), computeOverflowForUnsignedAdd(), computeOverflowForUnsignedMul(), computeOverflowForUnsignedSub(), detectExtMul(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandFixedPointDiv(), getPack(), getValidShiftAmountRange(), haveNoCommonBitsSet(), isBitfieldPositioningOp(), isKnownNeverZero(), isTruncateOf(), isWordAligned(), LowerAndToBT(), LowerAndToBTST(), LowerCTPOP(), LowerMUL(), llvm::SITargetLowering::lowerSET_ROUNDING(), lowerShuffleWithVPMOV(), LowerVectorAllEqual(), MaskedValueIsAllOnes(), MaskedValueIsZero(), MaskedVectorIsZero(), matchBinaryShuffle(), matchTruncateWithPACK(), narrowIndex(), llvm::AMDGPUTargetLowering::numBitsUnsigned(), performANDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performORCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), provablyDisjointOr(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegImm34(), llvm::PPCTargetLowering::SelectAddressRegReg(), llvm::LoongArchDAGToDAGISel::selectShiftMask(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), tryBitfieldInsertOpFromOr(), and tryBitfieldInsertOpFromOrAndImm().
unsigned SelectionDAG::ComputeMaxSignificantBits | ( | SDValue | Op, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
Get the upper bound on bit size for this Value Op
as a signed integer.
i.e. x == sext(trunc(x to MaxSignedBits) to bitwidth(x)). Similar to the APInt::getSignificantBits function. Helper wrapper to ComputeNumSignBits.
Definition at line 5144 of file SelectionDAG.cpp.
References ComputeNumSignBits(), and llvm::Depth.
Get the upper bound on bit size for this Value Op
as a signed integer.
i.e. x == sext(trunc(x to MaxSignedBits) to bitwidth(x)). Similar to the APInt::getSignificantBits function. Helper wrapper to ComputeNumSignBits.
Definition at line 5138 of file SelectionDAG.cpp.
References ComputeNumSignBits(), and llvm::Depth.
Referenced by combineConcatVectorOps(), combineMulToPMADDWD(), combinePMULH(), detectExtMul(), EmitCmp(), llvm::TargetLowering::expandMUL_LOHI(), getPack(), lowerBuildVectorOfConstants(), llvm::AMDGPUTargetLowering::numBitsSigned(), and llvm::TargetLowering::SimplifyDemandedBits().
unsigned SelectionDAG::ComputeNumSignBits | ( | SDValue | Op, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
Return the number of times the sign bit of the register is replicated into the other bits.
We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. The DemandedElts argument allows us to only collect the minimum sign bits of the requested vector elements. Targets can implement the ComputeNumSignBitsForTarget method in the TargetLowering class to allow target nodes to be understood.
Definition at line 4472 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::AND, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_CLR, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_SWAP, llvm::ISD::AVGCEILS, llvm::ISD::AVGFLOORS, llvm::ISD::BITCAST, llvm::BitWidth, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::CallingConv::C, llvm::APInt::clearBit(), computeKnownBits(), ComputeNumSignBits(), llvm::TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::ISD::CONCAT_VECTORS, llvm::KnownBits::countMinSignBits(), llvm::Depth, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::ISD::FP_TO_SINT_SAT, llvm::Constant::getAggregateElement(), llvm::APInt::getAllOnes(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::ConstantRange::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::getConstantRangeFromMetadata(), getDataLayout(), llvm::TargetLoweringBase::getExtendForAtomicOps(), llvm::ShuffleVectorSDNode::getMask(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::APInt::getNumSignBits(), llvm::APInt::getOneBitSet(), llvm::Type::getPrimitiveSizeInBits(), llvm::EVT::getScalarSizeInBits(), llvm::Type::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::getShuffleDemandedElts(), llvm::ConstantRange::getSignedMax(), llvm::ConstantRange::getSignedMin(), llvm::TargetLowering::getTargetConstantFromLoad(), getValidMinimumShiftAmount(), getValidShiftAmountRange(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZero(), Idx, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::APInt::insertBits(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isConstOrConstSplat(), llvm::ISD::isExtOpcode(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::KnownBits::isNonNegative(), llvm::EVT::isScalableVector(), llvm::EVT::isVector(), llvm::Type::isVectorTy(), llvm::ISD::LOAD, MaxRecursionDepth, llvm::ISD::MERGE_VALUES, llvm::ISD::MUL, llvm::ISD::NON_EXTLOAD, llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SADDO_CARRY, llvm::APIntOps::ScaleBitMask(), llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETCCCARRY, llvm::ISD::SEXTLOAD, llvm::APInt::shl(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ConstantRange::signExtend(), llvm::ArrayRef< T >::size(), llvm::APInt::sle(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULO, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SSUBO, llvm::ISD::SSUBO_CARRY, llvm::ISD::STRICT_FSETCC, llvm::ISD::STRICT_FSETCCS, llvm::ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, llvm::ConstantRange::zeroExtend(), llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::APInt::zext(), and llvm::ISD::ZEXTLOAD.
Return the number of times the sign bit of the register is replicated into the other bits.
We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. Targets can implement the ComputeNumSignBitsForTarget method in the TargetLowering class to allow target nodes to be understood.
Definition at line 4460 of file SelectionDAG.cpp.
References ComputeNumSignBits(), llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().
Referenced by canReduceVMulWidth(), combineAnd(), combineAndMaskToShift(), combineAndnp(), combineBitOpWithPACK(), combineGatherScatter(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMulToPMULDQ(), combinePredicateReduction(), combinePTESTCC(), combineSelect(), combineSetCCMOVMSK(), combineShiftToAVG(), combineSIntToFP(), combineVectorCompareAndMaskUnaryOp(), combineVectorPack(), combineVSelectWithAllOnesOrZeros(), computeKnownBits(), ComputeMaxSignificantBits(), ComputeNumSignBits(), computeNumSignBitsBinOp(), llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(), computeOverflowForSignedAdd(), computeOverflowForSignedMul(), computeOverflowForSignedSub(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandFixedPointDiv(), foldAddSubMasked1(), getFauxShuffleMask(), isS16(), LowerADDSAT_SUBSAT(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), LowerEXTEND_VECTOR_INREG(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerShiftByScalarImmediate(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), lowerVectorIntrinsicScalars(), LowerVSETCC(), matchBinaryShuffle(), matchShuffleWithPACK(), matchTruncateWithPACK(), matchUnaryShuffle(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), performVectorShiftCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::LoongArchDAGToDAGISel::selectSExti32(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), and llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode().
|
inline |
Determine if the result of the addition of 2 nodes can overflow.
Definition at line 1966 of file SelectionDAG.h.
References computeOverflowForSignedAdd(), and computeOverflowForUnsignedAdd().
Referenced by willNotOverflowAdd().
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inline |
Determine if the result of the mul of 2 nodes can overflow.
Definition at line 2002 of file SelectionDAG.h.
References computeOverflowForSignedMul(), and computeOverflowForUnsignedMul().
Referenced by willNotOverflowMul().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowForSignedAdd | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the signed addition of 2 nodes can overflow.
Definition at line 4255 of file SelectionDAG.cpp.
References ComputeNumSignBits(), llvm::isNullConstant(), OFK_Never, and OFK_Sometime.
Referenced by computeOverflowForAdd().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowForSignedMul | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the signed mul of 2 nodes can overflow.
Definition at line 4337 of file SelectionDAG.cpp.
References llvm::BitWidth, computeKnownBits(), ComputeNumSignBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::KnownBits::isNonNegative(), llvm::isNullConstant(), llvm::isOneConstant(), OFK_Never, and OFK_Sometime.
Referenced by computeOverflowForMul().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowForSignedSub | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the signed sub of 2 nodes can overflow.
Definition at line 4293 of file SelectionDAG.cpp.
References computeKnownBits(), ComputeNumSignBits(), llvm::ConstantRange::fromKnownBits(), llvm::isNullConstant(), mapOverflowResult(), OFK_Never, and llvm::ConstantRange::signedSubMayOverflow().
Referenced by computeOverflowForSub().
|
inline |
Determine if the result of the sub of 2 nodes can overflow.
Definition at line 1984 of file SelectionDAG.h.
References computeOverflowForSignedSub(), and computeOverflowForUnsignedSub().
Referenced by willNotOverflowSub().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowForUnsignedAdd | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the unsigned addition of 2 nodes can overflow.
Definition at line 4270 of file SelectionDAG.cpp.
References computeKnownBits(), llvm::ConstantRange::fromKnownBits(), llvm::KnownBits::getMaxValue(), llvm::SDValue::getOpcode(), llvm::SDValue::getResNo(), llvm::isNullConstant(), mapOverflowResult(), OFK_Never, llvm::APInt::ult(), llvm::ISD::UMUL_LOHI, and llvm::ConstantRange::unsignedAddMayOverflow().
Referenced by computeOverflowForAdd().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowForUnsignedMul | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the unsigned mul of 2 nodes can overflow.
Definition at line 4324 of file SelectionDAG.cpp.
References computeKnownBits(), llvm::ConstantRange::fromKnownBits(), llvm::isNullConstant(), llvm::isOneConstant(), mapOverflowResult(), OFK_Never, and llvm::ConstantRange::unsignedMulMayOverflow().
Referenced by computeOverflowForMul().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowForUnsignedSub | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the unsigned sub of 2 nodes can overflow.
Definition at line 4311 of file SelectionDAG.cpp.
References computeKnownBits(), llvm::ConstantRange::fromKnownBits(), llvm::isNullConstant(), mapOverflowResult(), OFK_Never, and llvm::ConstantRange::unsignedSubMayOverflow().
Referenced by computeOverflowForSub().
APInt SelectionDAG::computeVectorKnownZeroElements | ( | SDValue | Op, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
For each demanded element of a vector, see if it is known to be zero.
Definition at line 2738 of file SelectionDAG.cpp.
References assert(), llvm::Depth, llvm::APInt::getBitWidth(), llvm::APInt::getOneBitSet(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZero(), llvm::EVT::isScalableVector(), llvm::EVT::isVector(), MaskedVectorIsZero(), and llvm::APInt::setBit().
Referenced by combineShuffleToZeroExtendVectorInReg().
Copy extra info associated with one node to another.
Definition at line 13317 of file SelectionDAG.cpp.
References assert(), llvm::SmallPtrSetImplBase::clear(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::contains(), llvm::dbgs(), llvm::errs(), From, getEntryNode(), llvm::SDValue::getNode(), I, llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::SmallPtrSetImpl< PtrType >::insert(), LLVM_DEBUG, LLVM_LIKELY, MaxDepth, N, and std::swap().
Referenced by ReplaceAllUsesOfValuesWith(), ReplaceAllUsesOfValueWith(), and ReplaceAllUsesWith().
Create a stack temporary, suitable for holding the specified value type.
If minAlign is specified, the slot size will have at least that alignment.
Definition at line 2523 of file SelectionDAG.cpp.
References CreateStackTemporary(), getContext(), getDataLayout(), getPrefTypeAlign(), llvm::EVT::getStoreSize(), and llvm::EVT::getTypeForEVT().
Create a stack temporary suitable for holding either of the specified value types.
Definition at line 2530 of file SelectionDAG.cpp.
References assert(), CreateStackTemporary(), DL, getContext(), getDataLayout(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::EVT::getStoreSize(), llvm::EVT::getTypeForEVT(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().
Create a stack temporary based on the size in bytes and the alignment.
Definition at line 2510 of file SelectionDAG.cpp.
References llvm::MachineFrameInfo::CreateStackObject(), getDataLayout(), getFrameIndex(), llvm::TargetLoweringBase::getFrameIndexTy(), llvm::MachineFunction::getFrameInfo(), llvm::TargetSubtargetInfo::getFrameLowering(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::TargetFrameLowering::getStackIDForScalableVectors(), llvm::MachineFunction::getSubtarget(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().
Referenced by llvm::StatepointLoweringState::allocateStackSlot(), CreateStackTemporary(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), LowerATOMIC_STORE(), llvm::SystemZTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), and llvm::X86TargetLowering::ReplaceNodeResults().
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inline |
Definition at line 1847 of file SelectionDAG.h.
References llvm::SDDbgInfo::DbgBegin().
Referenced by dump(), and llvm::ScheduleDAGSDNodes::EmitSchedule().
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inline |
Definition at line 1848 of file SelectionDAG.h.
References llvm::SDDbgInfo::DbgEnd().
Referenced by dump(), and llvm::ScheduleDAGSDNodes::EmitSchedule().
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inline |
Definition at line 1857 of file SelectionDAG.h.
References llvm::SDDbgInfo::DbgLabelBegin().
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
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inline |
Definition at line 1860 of file SelectionDAG.h.
References llvm::SDDbgInfo::DbgLabelEnd().
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
void SelectionDAG::DeleteNode | ( | SDNode * | N | ) |
Remove the specified node from the system.
This node must have no referrers.
Definition at line 1052 of file SelectionDAG.cpp.
References N.
Referenced by Legalize(), and llvm::SelectionDAGBuilder::LowerAsSTATEPOINT().
Check if a node exists without modifying its flags.
doesNodeExist - Check if a node exists without modifying its flags.
Definition at line 11023 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::SDVTList::NumVTs, and llvm::SDVTList::VTs.
Referenced by llvm::TargetLowering::expandIntMINMAX(), foldAndOrOfSETCC(), and llvm::TargetLowering::SimplifySetCC().
LLVM_DUMP_METHOD void SelectionDAG::dump | ( | ) | const |
Definition at line 1023 of file SelectionDAGDumper.cpp.
References allnodes(), ByvalParmDbgBegin(), ByvalParmDbgEnd(), DbgBegin(), DbgEnd(), llvm::dbgs(), DumpNodes(), getNode(), getRoot(), llvm::make_range(), N, shouldPrintInline(), and VerboseDAGDumping.
Referenced by NewSDValueDbgMsg(), llvm::AMDGPUDAGToDAGISel::PreprocessISelDAG(), and llvm::HexagonDAGToDAGISel::PreprocessISelDAG().
LLVM_DUMP_METHOD void SelectionDAG::dumpDotGraph | ( | const Twine & | FileName, |
const Twine & | Title | ||
) |
Just dump dot graph to a user-provided path and title.
This doesn't open the dot viewer program and helps visualization when outside debugging session. FileName expects absolute path. If provided without any path separators then the file will be created in the current directory. Error will be emitted if the path is insane.
Definition at line 171 of file SelectionDAGPrinter.cpp.
References llvm::dumpDotGraphToFile().
Expand the specified ISD::VAARG
node as the Legalize pass would.
Definition at line 2429 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, getConstant(), getContext(), getDataLayout(), getLoad(), llvm::TargetLoweringBase::getMinStackArgumentAlignment(), getNode(), llvm::TargetLoweringBase::getPointerTy(), getSignedConstant(), getStore(), getTargetLoweringInfo(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValue(), and llvm::SDValue::getValueType().
Expand the specified ISD::VACOPY
node as the Legalize pass would.
Definition at line 2463 of file SelectionDAG.cpp.
References getDataLayout(), getLoad(), llvm::TargetLoweringBase::getPointerTy(), getStore(), getTargetLoweringInfo(), and llvm::SDValue::getValue().
Referenced by LowerVACOPY().
void SelectionDAG::ExtractVectorElements | ( | SDValue | Op, |
SmallVectorImpl< SDValue > & | Args, | ||
unsigned | Start = 0 , |
||
unsigned | Count = 0 , |
||
EVT | EltVT = EVT() |
||
) |
Append the extracted elements from Start to Count out of the vector Op in Args.
If Count is 0, all of the elements will be extracted. The extracted elements will have type EVT if it is provided, and otherwise their type will be Op's element type.
Definition at line 12748 of file SelectionDAG.cpp.
References llvm::ISD::EXTRACT_VECTOR_ELT, getNode(), llvm::EVT::getVectorElementType(), getVectorIdxConstant(), and llvm::EVT::getVectorNumElements().
Referenced by adjustLoadValueTypeImpl(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVecReduceSeq(), getDWordFromOffset(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), padEltsToUndef(), UnrollVectorOverflowOp(), unrollVectorShift(), and widenVectorToPartType().
SDValue SelectionDAG::FoldConstantArithmetic | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
ArrayRef< SDValue > | Ops, | ||
SDNodeFlags | Flags = SDNodeFlags() |
||
) |
Definition at line 6390 of file SelectionDAG.cpp.
References llvm::APInt::abs(), llvm::ISD::ABS, llvm::all_of(), llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BF16_TO_FP, llvm::APFloatBase::BFloat(), llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::APInt::byteSwap(), llvm::CallingConv::C, llvm::ISD::CONCAT_VECTORS, llvm::ISD::CONDCODE, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::APFloat::convert(), llvm::APFloat::convertFromAPInt(), llvm::APInt::countl_zero(), llvm::APInt::countr_zero(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, DL, llvm::ISD::FABS, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FNEG, foldConstantFPMath(), FoldSTEP_VECTOR(), FoldSymbolOffset(), FoldValue(), FoldValueWithUndef(), llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_BF16, llvm::ISD::FP_TO_FP16, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FTRUNC, getBitcast(), llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), getBuildVector(), getConstant(), getConstantFP(), getContext(), getDataLayout(), llvm::TargetLoweringBase::getExtendForContent(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::EVT::getFltSemantics(), getNode(), llvm::SDValue::getOpcode(), getOpcode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), getSplatVector(), getStepVector(), llvm::TargetLoweringBase::getTypeAction(), llvm::TargetLoweringBase::getTypeToTransformTo(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::APInt::getZero(), I, llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEEEquad(), llvm::APFloatBase::IEEEsingle(), ignored(), llvm::TargetLoweringBase::isCommutativeBinOp(), llvm::ISD::isConstantSplatVector(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::TargetLoweringBase::isSExtCheaperThanZExt(), llvm::SDValue::isUndef(), isUndef(), llvm::EVT::isVector(), llvm::ISD::MUL, NewNodesMustHaveLegalTypes, NewSDValueDbgMsg(), llvm::APFloatBase::opInexact, llvm::APFloatBase::opInvalidOp, llvm::APFloatBase::opOK, llvm::peekThroughBitcasts(), llvm::APInt::popcount(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::BuildVectorSDNode::recastRawBits(), llvm::APInt::reverseBits(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::rmTowardNegative, llvm::APFloatBase::rmTowardPositive, llvm::APFloatBase::rmTowardZero, llvm::ISD::SETCC, llvm::APInt::sextOrTrunc(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ArrayRef< T >::size(), llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::SPLAT_VECTOR, llvm::ISD::STEP_VECTOR, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::TargetLoweringBase::TypeLegal, llvm::ISD::UINT_TO_FP, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zextOrTrunc().
Referenced by foldAddSubOfSignBit(), foldBinOpIntoSelectIfProfitable(), getNode(), getTargetVShiftByConstNode(), getTargetVShiftNode(), LowerRotate(), PromoteMaskArithmetic(), llvm::TargetLowering::SimplifyDemandedBits(), and llvm::TargetLowering::SimplifyDemandedVectorElts().
SDValue SelectionDAG::foldConstantFPMath | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
ArrayRef< SDValue > | Ops | ||
) |
Fold floating-point operations when all operands are constants and/or undefined.
Definition at line 6774 of file SelectionDAG.cpp.
References llvm::APFloat::add(), llvm::APFloat::convert(), llvm::APFloat::copySign(), llvm::APFloat::divide(), DL, llvm::ISD::FADD, llvm::ISD::FCOPYSIGN, llvm::ISD::FDIV, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXIMUMNUM, llvm::ISD::FMAXNUM, llvm::ISD::FMINIMUM, llvm::ISD::FMINIMUMNUM, llvm::ISD::FMINNUM, llvm::ISD::FMUL, llvm::ISD::FP_ROUND, llvm::ISD::FREM, llvm::ISD::FSUB, getConstantFP(), llvm::EVT::getFltSemantics(), llvm::APFloat::getNaN(), getUNDEF(), llvm::ConstantFPSDNode::getValueAPF(), llvm::isConstOrConstSplatFP(), llvm::SDValue::isUndef(), llvm::maximum(), llvm::maximumnum(), llvm::maxnum(), llvm::minimum(), llvm::minimumnum(), llvm::minnum(), llvm::APFloat::mod(), llvm::APFloat::multiply(), llvm::APFloatBase::rmNearestTiesToEven, llvm::ArrayRef< T >::size(), and llvm::APFloat::subtract().
Referenced by FoldConstantArithmetic().
SDValue SelectionDAG::FoldSetCC | ( | EVT | VT, |
SDValue | N1, | ||
SDValue | N2, | ||
ISD::CondCode | Cond, | ||
const SDLoc & | dl | ||
) |
Constant fold a setcc to true or false.
Definition at line 2547 of file SelectionDAG.cpp.
References assert(), llvm::APFloatBase::cmpEqual, llvm::APFloatBase::cmpGreaterThan, llvm::APFloatBase::cmpLessThan, llvm::APFloatBase::cmpUnordered, llvm::ICmpInst::compare(), Cond, getBoolConstant(), llvm::TargetLoweringBase::getBooleanContents(), getConstant(), llvm::getICmpCondCode(), llvm::EVT::getScalarType(), getSetCC(), llvm::ISD::getSetCCSwappedOperands(), llvm::EVT::getSimpleVT(), getUNDEF(), llvm::ISD::getUnorderedFlavor(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::isCondCodeLegal(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::ISD::isTrueWhenEqual(), llvm::SDValue::isUndef(), llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETFALSE, llvm::ISD::SETFALSE2, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETTRUE, llvm::ISD::SETTRUE2, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, and llvm::TargetLoweringBase::UndefinedBooleanContent.
Referenced by getNode(), and llvm::TargetLowering::SimplifySetCC().
SDValue SelectionDAG::FoldSymbolOffset | ( | unsigned | Opcode, |
EVT | VT, | ||
const GlobalAddressSDNode * | GA, | ||
const SDNode * | N2 | ||
) |
Definition at line 6345 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::GlobalAddressSDNode::getGlobal(), getGlobalAddress(), llvm::GlobalAddressSDNode::getOffset(), llvm::SDNode::getOpcode(), llvm::ISD::GlobalAddress, llvm::TargetLowering::isOffsetFoldingLegal(), llvm::Offset, and llvm::ISD::SUB.
Referenced by FoldConstantArithmetic().
SDValue SelectionDAG::getAddrSpaceCast | ( | const SDLoc & | dl, |
EVT | VT, | ||
SDValue | Ptr, | ||
unsigned | SrcAS, | ||
unsigned | DestAS | ||
) |
Return an AddrSpaceCastSDNode.
Definition at line 2393 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::ISD::ADDRSPACECAST, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), N, and Ptr.
Referenced by combineLoad(), combineStore(), and llvm::SITargetLowering::LowerFormalArguments().
SDValue SelectionDAG::getAllOnesConstant | ( | const SDLoc & | DL, |
EVT | VT, | ||
bool | IsTarget = false , |
||
bool | IsOpaque = false |
||
) |
Definition at line 1759 of file SelectionDAG.cpp.
References DL, llvm::APInt::getAllOnes(), getConstant(), and llvm::EVT::getScalarSizeInBits().
Referenced by combineAddOrSubToADCOrSBB(), combineAndLoadToBZHI(), combineBitcastToBoolVector(), combineMinMaxReduction(), combinePTESTCC(), combineSelectToBinOp(), combineSetCC(), combineSetCCMOVMSK(), combineVectorCompare(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTTZ(), expandVPFunnelShift(), foldBoolSelectToLogic(), foldXorTruncShiftIntoCmp(), getBoolConstant(), llvm::VECustomDAG::getConstantMask(), getNeutralElement(), getNode(), getNOT(), getOnesVector(), getTargetVShiftNode(), getWideningInterleave(), isConditionalZeroOrAllOnes(), LowerADDSUBO_CARRY(), LowerBUILD_VECTORvXi1(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), LowerSIGN_EXTEND_Mask(), LowerVectorAllEqual(), LowerVSETCC(), MatchVectorAllEqualTest(), performAddCSelIntoCSinc(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), and llvm::VPMatchContext::VPMatchContext().
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncating it.
Definition at line 1454 of file SelectionDAG.cpp.
References llvm::ISD::ANY_EXTEND, llvm::EVT::bitsGT(), DL, getNode(), and llvm::ISD::TRUNCATE.
Referenced by combineBitcast(), combineExtractVectorElt(), combineScalarToVector(), combineToExtendBoolVectorInReg(), createMMXBuildVector(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), getBitcastedAnyExtOrTrunc(), getCopyFromPartsVector(), getCopyToPartsVector(), getExtOrTrunc(), getNode(), getVectorBitwiseReduce(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerFunnelShift(), lowerLaneOp(), LowerMUL(), LowervXi8MulWithUNPCK(), performBuildShuffleExtendCombine(), PerformVSELECTCombine(), and llvm::HexagonTargetLowering::ReplaceNodeResults().
Return an AssertAlignSDNode.
Definition at line 6857 of file SelectionDAG.cpp.
References A, AddNodeIDNode(), assert(), llvm::ISD::AssertAlign, DL, llvm::SDValue::getValueType(), getVTList(), llvm::EVT::isInteger(), N, and NewSDValueDbgMsg().
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic op, produces result and chain and takes 1 operand.
Definition at line 8742 of file SelectionDAG.cpp.
References assert(), llvm::ISD::ATOMIC_LOAD, getAtomic(), getVTList(), and Ptr.
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Val, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Definition at line 8710 of file SelectionDAG.cpp.
References assert(), llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_CLR, llvm::ISD::ATOMIC_LOAD_FADD, llvm::ISD::ATOMIC_LOAD_FMAX, llvm::ISD::ATOMIC_LOAD_FMIN, llvm::ISD::ATOMIC_LOAD_FSUB, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UDEC_WRAP, llvm::ISD::ATOMIC_LOAD_UINC_WRAP, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::ATOMIC_SWAP, getAtomic(), llvm::SDValue::getValueType(), getVTList(), and Ptr.
Referenced by combineSetCCAtomicArith(), getAtomic(), getAtomicCmpSwap(), LowerATOMIC_STORE(), llvm::VETargetLowering::lowerATOMIC_SWAP(), lowerAtomicArith(), and tryToFoldExtOfAtomicLoad().
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic op, produces result and chain and takes N operands.
Definition at line 8675 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), and N.
SDValue SelectionDAG::getAtomicCmpSwap | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
SDVTList | VTs, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Cmp, | ||
SDValue | Swp, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic cmpxchg op.
There are two valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a chain result. ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value loaded, a success flag (initially i1), and a chain.
Definition at line 8698 of file SelectionDAG.cpp.
References assert(), llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, getAtomic(), llvm::SDValue::getValueType(), and Ptr.
SDValue SelectionDAG::getAtomicMemcpy | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
Type * | SizeTy, | ||
unsigned | ElemSz, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo | ||
) |
Definition at line 8381 of file SelectionDAG.cpp.
References getContext(), getDataLayout(), getExternalSymbol(), llvm::DataLayout::getIntPtrType(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), llvm::RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(), llvm::TargetLoweringBase::getPointerTy(), llvm::Type::getVoidTy(), llvm::TargetLowering::LowerCallTo(), llvm::report_fatal_error(), llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setDiscardResult(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), and Size.
SDValue SelectionDAG::getAtomicMemmove | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
Type * | SizeTy, | ||
unsigned | ElemSz, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo | ||
) |
Definition at line 8497 of file SelectionDAG.cpp.
References getContext(), getDataLayout(), getExternalSymbol(), llvm::DataLayout::getIntPtrType(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), llvm::RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(), llvm::TargetLoweringBase::getPointerTy(), llvm::Type::getVoidTy(), llvm::TargetLowering::LowerCallTo(), llvm::report_fatal_error(), llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setDiscardResult(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), and Size.
SDValue SelectionDAG::getAtomicMemset | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Value, | ||
SDValue | Size, | ||
Type * | SizeTy, | ||
unsigned | ElemSz, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo | ||
) |
Definition at line 8635 of file SelectionDAG.cpp.
References getContext(), getDataLayout(), getExternalSymbol(), llvm::Type::getInt8Ty(), llvm::DataLayout::getIntPtrType(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), llvm::RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(), llvm::TargetLoweringBase::getPointerTy(), llvm::Type::getVoidTy(), llvm::TargetLowering::LowerCallTo(), llvm::report_fatal_error(), llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setDiscardResult(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), and Size.
SDValue SelectionDAG::getBasicBlock | ( | MachineBasicBlock * | MBB | ) |
Definition at line 1977 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::ISD::BasicBlock, getVTList(), MBB, and N.
Referenced by AddNodeIDCustom(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), and llvm::SelectionDAGBuilder::visitSwitchCase().
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inline |
Definition at line 503 of file SelectionDAG.h.
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
Use getNode to set a custom SDLoc.
Definition at line 2386 of file SelectionDAG.cpp.
References llvm::ISD::BITCAST, and getNode().
Referenced by addShuffleForVecExtend(), adjustBitcastSrcVectorSSE1(), canonicalizeBitSelect(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleVectorByLane(), canonicalizeShuffleWithOp(), combineAnd(), combineAndMaskToShift(), combineAndNotIntoANDNP(), combineAndnp(), combineAndShuffleNot(), combineArithReduction(), combineBasicSADPattern(), combineBitcast(), combineBitcastToBoolVector(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBitOpWithPACK(), combineBitOpWithShift(), combineBITREVERSE(), combineBlendOfPermutes(), combineBROADCAST_LOAD(), combineCastedMaskArithmetic(), combineCMP(), combineCompareEqual(), combineCONCAT_VECTORS(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineConstantPoolLoads(), combineCVTP2I_CVTTP2I(), combineCVTPH2PS(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineFMulcFCMulc(), combineFneg(), combineFP_EXTEND(), combineFP_ROUND(), combineHorizOpWithShuffle(), combineLoad(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMinMaxReduction(), combineMOVMSK(), combineMulToPMADDWD(), combineOr(), combinePMULDQ(), combinePMULH(), combinePredicateReduction(), combinePTESTCC(), combineRedundantDWordShuffle(), combineScalarAndWithMaskSetcc(), combineScalarToVector(), combineSelect(), combineSetCCMOVMSK(), combineShuffleOfBitcast(), combineShuffleToAnyExtendVectorInreg(), combineShuffleToZeroExtendVectorInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToFPTruncExtElt(), combineTruncationShuffle(), combineVectorCompareAndMaskUnaryOp(), combineVectorHADDSUB(), combineVectorPack(), combineVectorShiftImm(), combineVectorSizedSetCCEquality(), combineVPDPBUSDPattern(), combineVSelectWithAllOnesOrZeros(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), combineXor(), constructDup(), convertIntLogicToFPLogic(), convertShiftLeftToScale(), createMMXBuildVector(), EltsFromConsecutiveLoads(), expandBitCastF128ToI128(), expandBitCastI128ToF128(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandUINT_TO_FP(), ExtractBitFromMaskVector(), FixupMMXIntrinsicTypes(), FoldConstantArithmetic(), FoldIntToFPToInt(), GeneratePerfectShuffle(), getAVX2GatherNode(), getBitcastedAnyExtOrTrunc(), getBitcastedSExtOrTrunc(), getBitcastedZExtOrTrunc(), getBuildDwordsVector(), getCanonicalConstSplat(), getConstVector(), getCopyFromPartsVector(), getCopyToPartsVector(), getDataClassTest(), getDeinterleaveViaVNSRL(), getFlagsOfCmpZeroFori1(), getMaskNode(), getMemsetValue(), llvm::X86TargetLowering::getNegatedExpression(), getOnesVector(), getPack(), getScalarMaskingNode(), getScalarValueForVectorElement(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getv64i1Argument(), getVCIXISDNodeWCHAIN(), getVectorBitwiseReduce(), getVShift(), getWideningInterleave(), getZeroVector(), llvm::TargetLowering::IncrementMemoryAddress(), isHorizontalBinOp(), IsNOT(), llvm::SystemZTargetLowering::joinRegisterPartsIntoValue(), lower128BitShuffle(), lower256BitShuffle(), lower512BitShuffle(), LowerATOMIC_STORE(), LowerAVXExtend(), LowerBITCAST(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), LowerBUILD_VECTORvXbf16(), lowerBUILD_VECTORvXf16(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorOfConstants(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::HexagonTargetLowering::LowerCall(), LowerCTPOP(), LowerEXTEND_VECTOR_INREG(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerFMINIMUM_FMAXIMUM(), llvm::SITargetLowering::LowerFormalArguments(), LowerFunnelShift(), LowerHorizontalByteSum(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), lowerLaneOp(), LowerLoad(), lowerMasksToReg(), LowerMUL(), LowerMULH(), llvm::RISCVTargetLowering::LowerOperation(), lowerRegToMasks(), llvm::HexagonTargetLowering::LowerReturn(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBitMask(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithUNPCK256(), lowerShuffleWithVPMOV(), LowerStore(), LowerTruncateVecI1(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), lowerV16F32Shuffle(), lowerV16I32Shuffle(), lowerV16I8Shuffle(), lowerV2I64Shuffle(), lowerV4F32Shuffle(), lowerV4I32Shuffle(), lowerV4I64Shuffle(), lowerV8F16Shuffle(), lowerV8F32Shuffle(), lowerV8I16GeneralSingleInputShuffle(), lowerV8I16Shuffle(), lowerV8I32Shuffle(), lowerV8I64Shuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsRotate(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVectorAllEqual(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), lowerVectorIntrinsicScalars(), LowerVSETCC(), LowervXi8MulWithUNPCK(), lowerX86FPLogicOp(), matchPERM(), narrowExtractedVectorBinOp(), narrowExtractedVectorSelect(), packImage16bitOpsToDwords(), Passv64i1ArgInRegs(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformLOADCombine(), performUzpCombine(), performVECTOR_SHUFFLECombine(), processVCIXOperands(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceBuildVecToShuffleWithZero(), reduceMaskedLoadToScalarLoad(), reduceMaskedStoreToScalarStore(), reduceVMULWidth(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), splitAndLowerShuffle(), llvm::SystemZTargetLowering::splitValueIntoRegisterParts(), takeInexpensiveLog2(), truncateVectorWithNARROW(), truncateVectorWithPACK(), tryWidenMaskForShuffle(), llvm::X86TargetLowering::visitMaskedLoad(), and llvm::X86TargetLowering::visitMaskedStore().
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either any-extending or truncating it.
Definition at line 1472 of file SelectionDAG.cpp.
References assert(), DL, getAnyExtOrTrunc(), getBitcast(), llvm::EVT::getIntegerVT(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), and Size.
Referenced by getDWordFromOffset(), and matchPERM().
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either sign-extending or truncating it.
Definition at line 1487 of file SelectionDAG.cpp.
References assert(), DL, getBitcast(), llvm::MVT::getIntegerVT(), getSExtOrTrunc(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), and Size.
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either zero-extending or truncating it.
Definition at line 1502 of file SelectionDAG.cpp.
References assert(), DL, getBitcast(), llvm::MVT::getIntegerVT(), llvm::SDValue::getValueType(), getZExtOrTrunc(), llvm::EVT::isVector(), and Size.
SDValue SelectionDAG::getBlockAddress | ( | const BlockAddress * | BA, |
EVT | VT, | ||
int64_t | Offset = 0 , |
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bool | isTarget = false , |
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unsigned | TargetFlags = 0 |
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) |
Definition at line 2335 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::ISD::BlockAddress, getVTList(), N, llvm::Offset, and llvm::ISD::TargetBlockAddress.
Referenced by getTargetBlockAddress(), llvm::SelectionDAGBuilder::getValueImpl(), and llvm::LanaiTargetLowering::LowerBlockAddress().
Create a true or false constant of type VT
using the target's BooleanContent for type OpVT
.
Definition at line 1609 of file SelectionDAG.cpp.
References DL, getAllOnesConstant(), llvm::TargetLoweringBase::getBooleanContents(), getConstant(), llvm_unreachable, llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
Referenced by llvm::TargetLowering::expandIS_FPCLASS(), FoldSetCC(), getDataClassTest(), getLogicalNOT(), getVPLogicalNOT(), performSETCCCombine(), llvm::TargetLowering::SimplifySetCC(), and UnrollVectorOverflowOp().
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it.
Definition at line 1517 of file SelectionDAG.cpp.
References llvm::EVT::bitsLE(), llvm::TargetLoweringBase::getBooleanContents(), llvm::TargetLoweringBase::getExtendForContent(), getNode(), and llvm::ISD::TRUNCATE.
Referenced by combineCarryDiamond(), combineSelectAsExtAnd(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandUADDSUBO(), and llvm::TargetLowering::SimplifySetCC().
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Return an ISD::BUILD_VECTOR node.
The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.
Definition at line 851 of file SelectionDAG.h.
References llvm::ISD::BUILD_VECTOR, DL, and getNode().
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Return an ISD::BUILD_VECTOR node.
The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.
Definition at line 842 of file SelectionDAG.h.
References llvm::ISD::BUILD_VECTOR, DL, and getNode().
Referenced by adjustLoadValueTypeImpl(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), BuildExactSDIV(), BuildExactUDIV(), buildScalarToVector(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), combineConcatVectorOfScalars(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineShuffleOfScalars(), combineStore(), combineToExtendBoolVectorInReg(), combineX86ShuffleChain(), CompactSwizzlableVector(), convertLocVTToValVT(), convertShiftLeftToScale(), ExtendToType(), extractSubVector(), foldCONCAT_VECTORS(), FoldConstantArithmetic(), GenerateFixedLengthSVETBL(), GenerateTBL(), getBuildDwordsVector(), getBuildVectorSplat(), getConstant(), getConstVector(), getCopyFromPartsVector(), getDWordFromOffset(), getGeneralPermuteNode(), getGFNICtrlMask(), llvm::TargetLowering::getNegatedExpression(), getNode(), getStepVector(), getTargetVShiftNode(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorShuffle(), incDecVectorConstant(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorToBitOp(), LowerBuildVectorv4x32(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), lowerINT_TO_FP_vXi64(), lowerLaneOp(), lowerMSABinaryBitImmIntr(), lowerMSASplatZExt(), LowerMUL(), LowerShift(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleWithPSHUFB(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerTruncateVectorStore(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerV16I8Shuffle(), lowerV8I16Shuffle(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_VSHF(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_XVSHUF(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPInRegLUT(), LowervXi8MulWithUNPCK(), NormalizeBuildVector(), packImage16bitOpsToDwords(), padEltsToUndef(), performBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), performConcatVectorsCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performINTRINSIC_WO_CHAINCombine(), PerformLOADCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performVSelectCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), ReorganizeVector(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeBinOpOfSplats(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::SimplifyDemandedVectorElts(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), takeInexpensiveLog2(), tryBuildVectorShuffle(), tryToConvertShuffleOfTbl2ToTbl4(), tryToFoldExtendOfConstant(), UnrollVectorOp(), UnrollVectorOverflowOp(), unrollVectorShift(), and widenVectorToPartType().
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Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
CALLSEQ_END does not have a useful SDLoc.
Definition at line 1095 of file SelectionDAG.h.
References llvm::ISD::CALLSEQ_END, DL, llvm::SDValue::getNode(), getNode(), getVTList(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by getCALLSEQ_END(), llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), and PrepareTailCall().
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Definition at line 1107 of file SelectionDAG.h.
References DL, getCALLSEQ_END(), and getIntPtrConstant().
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Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and OutSize specifies part of the frame set up prior to the sequence.
Definition at line 1083 of file SelectionDAG.h.
References llvm::ISD::CALLSEQ_START, DL, getIntPtrConstant(), getNode(), and getVTList().
Referenced by llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), and llvm::VETargetLowering::lowerToTLSGeneralDynamicModel().
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Return CallSiteInfo associated with Node, or a default if none exists.
Definition at line 2321 of file SelectionDAG.h.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), and I.
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
SDValue SelectionDAG::getCommutedVectorShuffle | ( | const ShuffleVectorSDNode & | SV | ) |
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands.
Example: shuffle A, B, <0,5,2,7> -> shuffle B, A, <4,1,6,3>
Definition at line 2271 of file SelectionDAG.cpp.
References llvm::ShuffleVectorSDNode::commuteMask(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and getVectorShuffle().
Referenced by lowerVECTOR_SHUFFLE().
SDValue SelectionDAG::getCondCode | ( | ISD::CondCode | Cond | ) |
Definition at line 2032 of file SelectionDAG.cpp.
Referenced by combine_CC(), llvm::TargetLowering::expandVPCTTZElements(), getSelectCC(), getSetCC(), getSetCCVP(), llvm::TargetLowering::LegalizeSetCCCondCode(), lowerBALLOTIntrinsic(), lowerFCMPIntrinsic(), lowerICMPIntrinsic(), LowerTruncatei1(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), LowerVSETCC(), performIntrinsicCombine(), performVSelectCombine(), splitIntVSETCC(), and tryConvertSVEWideCompare().
SDValue SelectionDAG::getConstant | ( | const APInt & | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false , |
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bool | isOpaque = false |
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) |
Definition at line 1633 of file SelectionDAG.cpp.
References DL, and getConstant().
SDValue SelectionDAG::getConstant | ( | const ConstantInt & | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false , |
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bool | isOpaque = false |
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) |
Definition at line 1638 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::append_range(), assert(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::ISD::BITCAST, llvm::ISD::Constant, DL, llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::APInt::extractBits(), llvm::ConstantInt::getBitWidth(), getBuildVector(), getConstant(), getContext(), getDataLayout(), getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), getSplat(), llvm::TargetLoweringBase::getTypeAction(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::ConstantInt::getValue(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), getVTList(), isBigEndian(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isOperationLegal(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isSExtCheaperThanZExt(), llvm::EVT::isVector(), N, NewNodesMustHaveLegalTypes, NewSDValueDbgMsg(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::APInt::sextOrTrunc(), llvm::ISD::SPLAT_VECTOR, llvm::ISD::SPLAT_VECTOR_PARTS, llvm::ISD::TargetConstant, llvm::TargetLoweringBase::TypeExpandInteger, llvm::TargetLoweringBase::TypePromoteInteger, and llvm::APInt::zextOrTrunc().
SDValue SelectionDAG::getConstant | ( | uint64_t | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false , |
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bool | isOpaque = false |
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) |
Create a ConstantSDNode wrapping a constant value.
If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal).
Definition at line 1624 of file SelectionDAG.cpp.
References assert(), DL, getConstant(), llvm::EVT::getScalarType(), and llvm::EVT::getSizeInBits().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addIPMSequence(), adjustForSubtraction(), adjustForTestUnderMask(), adjustICmpTruncate(), adjustSubwordCmp(), adjustZeroCmp(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), bitcastf32Toi32(), buildCallOperands(), BuildExactSDIV(), BuildExactUDIV(), BuildIntrinsicOp(), llvm::SITargetLowering::buildRSRC(), llvm::TargetLowering::BuildSDIV(), llvm::PPCTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), canonicalizeShuffleVectorByLane(), carryFlagToValue(), checkSignTestSetCCCombine(), clampDynamicVectorIndex(), combine_CC(), combineAcrossLanesIntrinsic(), combineADC(), combineAddOfBooleanXor(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAnd(), combineAndLoadToBZHI(), combineAndnp(), CombineANDShift(), combineArithReduction(), combineAVG(), CombineBaseUpdate(), combineBitcast(), combineBitcastToBoolVector(), combineCarryDiamond(), combineCarryThroughADD(), combineCMov(), combineCMP(), combineCompareEqual(), combineCONCAT_VECTORS(), combineConcatVectorOps(), combineDeMorganOfBoolean(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFP_EXTEND(), combineGatherScatter(), combineI8TruncStore(), combineKSHIFT(), combineM68kBrCond(), combineMinMaxReduction(), combineMOVMSK(), combineMul(), combineMulSpecial(), combineMulToPMADDWD(), combineOr(), combinePMULDQ(), combinePredicateReduction(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), llvm::VETargetLowering::combineSelect(), combineSelect(), llvm::VETargetLowering::combineSelectCC(), combineSelectOfTwoConstants(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToMULH(), combineStore(), combineSub(), combineSubOfBoolean(), combineSubSetcc(), combineSVEPrefetchVecBaseImmOff(), combineSVEReductionFP(), combineSVEReductionInt(), combineSVEReductionOrderedFP(), combineToExtendBoolVectorInReg(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineUADDO_CARRYDiamond(), combineV3I8LoadExt(), combineVectorCompare(), combineVectorMulToSraBitcast(), combineVectorShiftImm(), combineVectorShiftVar(), combineVectorSizedSetCCEquality(), CombineVMOVDRRCandidateWithVecOp(), combineVPMADD(), combineVSelectWithAllOnesOrZeros(), combinevXi1ConstantToInteger(), combineX86AddSub(), combineX86ShuffleChain(), constantFoldBFE(), constructDup(), constructRetValue(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), convertFixedMaskToScalableVector(), convertFromScalableVector(), convertShiftLeftToScale(), convertToScalableVector(), convertValVTToLocVT(), CreateCopyOfByValArgument(), createFPCmp(), createLoadLR(), createPSADBW(), createSetFPEnvNodes(), createStoreLR(), createVariablePermute(), createVPDPBUSD(), llvm::TargetLowering::CTTZTableLookup(), customLegalizeToWOp(), EltsFromConsecutiveLoads(), EmitCMP(), emitConditionalComparison(), emitConstantSizeRepmov(), emitMemMemImm(), emitMemMemReg(), emitSETCC(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrlen(), EmitTest(), Expand64BitShift(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), expandf64Toi32(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandFunnelShift(), llvm::TargetLowering::expandIntMINMAX(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandIS_FPCLASS(), expandMul(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), llvm::TargetLowering::expandVPBITREVERSE(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTPOP(), llvm::TargetLowering::expandVPCTTZ(), llvm::TargetLowering::expandVPCTTZElements(), expandVPFunnelShift(), ExtendToType(), extractF64Exponent(), extractShiftForRotate(), finalizeTS1AM(), foldADCToCINC(), foldAddSubBoolOfMaskedVal(), foldAndOrOfSETCC(), foldAndToUsubsat(), FoldConstantArithmetic(), foldCSELOfCSEL(), foldCSELofCTTZ(), foldExtendedSignBitTest(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldSelectOfConstantsUsingSra(), foldSelectOfCTTZOrCTLZ(), FoldSetCC(), foldSetCCWithFunnelShift(), FoldSTEP_VECTOR(), foldVSelectToSignBitSplatMask(), llvm::TargetLowering::forceExpandWideMUL(), genConstMult(), generateEquivalentSub(), GenerateFixedLengthSVETBL(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), llvm::MipsTargetLowering::getAddrNonPICSym64(), getAllOnesConstant(), getARMIndexedAddressParts(), getAVX512Node(), getBitTestCondition(), getBoolConstant(), getBoundedStrlen(), getBuildVectorSplat(), getCanonicalConstSplat(), getCCResult(), getConstant(), llvm::VECustomDAG::getConstant(), getConstVector(), getCopyFromParts(), llvm::RegsForValue::getCopyFromRegs(), getCSAddressAndShifts(), getDataClassTest(), getDefaultVLOps(), getDeinterleaveViaVNSRL(), getDWordFromOffset(), getElementCount(), GetExponent(), getFlagsOfCmpZeroFori1(), getGeneralPermuteNode(), getGFNICtrlMask(), llvm::AMDGPUTargetLowering::getHiHalf64(), getIntPtrConstant(), getLimitedPrecisionExp2(), llvm::AMDGPUTargetLowering::getLoHalf64(), llvm::VECustomDAG::getMaskBroadcast(), getMaskNode(), getMemBasePlusOffset(), getMemsetStringVal(), getMemsetValue(), getMVEIndexedAddressParts(), getNegatedInteger(), getNegative(), getNeutralElement(), getNode(), getPack(), getPMOVMSKB(), llvm::AVRTargetLowering::getPostIndexedAddressParts(), llvm::AVRTargetLowering::getPreIndexedAddressParts(), getPTest(), getPTrue(), getReductionSDNode(), getScaledOffsetForBitWidth(), getSETCC(), getShiftAmountConstant(), getShuffleScalarElt(), getSignedConstant(), GetSignificand(), llvm::NVPTXTargetLowering::getSqrtEstimate(), getStepVector(), getSVEPredicateBitCast(), getT2IndexedAddressParts(), getTargetConstant(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getTruncatedUSUBSAT(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorBitwiseReduce(), getVectorIdxConstant(), llvm::TargetLowering::getVectorSubVecPointer(), getVPZeroExtendInReg(), getVScale(), getWideningInterleave(), getZeroExtendInReg(), getZeroVector(), getzOSCalleeAndADA(), incDecVectorConstant(), llvm::TargetLowering::IncrementMemoryAddress(), insert1BitVector(), IntCondCCodeToICC(), isBLACompatibleAddress(), isConditionalZeroOrAllOnes(), IsSingleInstrConstant(), legalizeIntrinsicImmArg(), llvm::AMDGPUTargetLowering::loadInputValue(), lower1BitShuffle(), LowerABS(), lowerAddrSpaceCast(), LowerADDSAT_SUBSAT(), LowerAndToBT(), LowerAndToBTST(), LowerAsSplatVectorLoad(), LowerATOMIC_FENCE(), LowerAVXExtend(), lowerBALLOTIntrinsic(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), llvm::LanaiTargetLowering::LowerBR_CC(), LowerBR_CC(), LowerBRCOND(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTOR_i1(), LowerBUILD_VECTORToVIDUP(), LowerBUILD_VECTORvXi1(), lowerBuildVectorOfConstants(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv16i8(), lowerBuildVectorViaPacking(), llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::lowerCTLZResults(), LowerCTPOP(), LowerCTTZ(), lowerCttzElts(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_i1(), llvm::SparcTargetLowering::LowerF128Compare(), LowerF128Load(), LowerF128Store(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::lowerFEXP(), LowerFGETSIGN(), LowerFLDEXP(), llvm::AMDGPUTargetLowering::LowerFLOGCommon(), LowerFMINIMUM_FMAXIMUM(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFP16_TO_FP(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), LowerFP_TO_INT_SAT(), lowerFP_TO_INT_SAT(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), LowerFunnelShift(), llvm::SITargetLowering::lowerGET_ROUNDING(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), lowerGR128ToI128(), LowerHorizontalByteSum(), lowerI128ToGR128(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), LowerINSERT_VECTOR_ELT_i1(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), lowerINT_TO_FP_vXi64(), LowerInterruptReturn(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), LowerLabelRef(), lowerLaneOp(), llvm::MipsTargetLowering::lowerLOAD(), lowerLoadF128(), lowerLoadI1(), LowerMemOpCallTo(), lowerMSABinaryBitImmIntr(), lowerMSABitClear(), lowerMSABitClearImm(), lowerMSASplatImm(), lowerMSASplatZExt(), LowerMUL(), llvm::LanaiTargetLowering::LowerMUL(), lowerMUL_LOHI32(), LowerMULH(), LowerMULO(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), lowerOverflowArithmetic(), LowerPARITY(), LowerPredicateLoad(), LowerPredicateStore(), llvm::HexagonTargetLowering::LowerPREFETCH(), LowerPREFETCH(), lowerReductionSeq(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), lowerRETURNADDR(), LowerRotate(), LowerSaturatingConditional(), lowerScalarInsert(), lowerScalarSplat(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::SITargetLowering::lowerSET_FPENV(), llvm::SITargetLowering::lowerSET_ROUNDING(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsTruncBroadcast(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleToEXPAND(), lowerShuffleWithPSHUFB(), LowerSIGN_EXTEND_Mask(), LowerSMELdrStr(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), lowerStoreF128(), lowerStoreI1(), LowerSVEIntrinsicEXT(), LowerTruncatei1(), LowerTruncateVecI1(), LowerTruncateVectorStore(), llvm::HexagonTargetLowering::LowerUAddSubO(), LowerUADDSUBO_CARRY(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerUnalignedLoadRetParam(), LowerUnalignedStoreParam(), LowerUnalignedStoreRet(), lowerV16I8Shuffle(), lowerV8I16Shuffle(), llvm::VETargetLowering::lowerVAARG(), LowerVecReduce(), LowerVecReduceMinMax(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), lowerVECTOR_SHUFFLE_VREPLVEI(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_VSHUF4I(), lowerVECTOR_SHUFFLE_XVREPLVEI(), lowerVECTOR_SHUFFLEAsRotate(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVectorAllEqual(), lowerVectorBitClear(), lowerVectorBitClearImm(), lowerVectorBitRevImm(), lowerVectorBitSetImm(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPInRegLUT(), lowerVectorIntrinsicScalars(), lowerVectorSplatImm(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowervXi8MulWithUNPCK(), lowerX86CmpEqZeroToCtlzSrl(), LowerXALUO(), LowerZERO_EXTEND_Mask(), llvm::SparcTargetLowering::makeAddress(), matchPERM(), MatchVectorAllEqualTest(), memsetStore(), narrowIndex(), NormalizeBuildVector(), optimizeLogicalImm(), overflowFlagToValue(), llvm::SITargetLowering::passSpecialInputs(), performAddCSelIntoCSinc(), PerformAddcSubcCombine(), PerformAddeSubeCombine(), performAddSubIntoVectorOp(), performAddUADDVCombine(), performANDCombine(), performANDORCSELCombine(), performANDSETCCCombine(), PerformARMBUILD_VECTORCombine(), PerformBFICombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), PerformCSETCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDSPShiftCombine(), performDUPCombine(), performExtBinopLoadFold(), PerformEXTRACTCombine(), PerformExtractEltCombine(), PerformExtractEltToVMOVRRD(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFlagSettingCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFP_TO_INT_SATCombine(), performFpToIntCombine(), performGlobalAddressCombine(), performINTRINSIC_WO_CHAINCombine(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), performLDNT1Combine(), PerformLongShiftCombine(), PerformMinMaxCombine(), PerformMinMaxToSatCombine(), performMulCombine(), PerformMULCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performORCombine(), PerformORCombineToBFI(), PerformPREDICATE_CASTCombine(), performScalarToVectorCombine(), performSetccAddFolding(), performSETCCCombine(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), performSHLCombine(), PerformSHLSimplify(), PerformShuffleVMOVNCombine(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performSraCombine(), performSRACombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performSRLCombine(), PerformSTORECombine(), performSUBCombine(), PerformSUBCombine(), performSubsToAndsCombine(), performSVEAndCombine(), performTBZCombine(), performTruncateCombine(), PerformTruncatingStoreCombine(), performUnpackCombine(), performUzpCombine(), PerformVCMPCombine(), PerformVCVTCombine(), PerformVDUPCombine(), performVecReduceAddCombine(), performVecReduceAddCombineWithUADDLP(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), PerformVMulVCTPCombine(), performVSelectCombine(), PerformVSELECTCombine(), PerformVSetCCToVCTPCombine(), performXORCombine(), PerformXORCombine(), prepareTS1AM(), promoteExtBeforeAdd(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), refineUniformBase(), ReplaceATOMIC_LOAD_128Results(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), replaceVPICKVE2GRResults(), resolveSources(), SaturateWidenedDIVFIX(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), simplifyShift(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), llvm::AMDGPUTargetLowering::split64BitValue(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), SplitEVL(), splitStores(), splitStoreSplat(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::AMDGPUTargetLowering::storeStackInputValue(), takeInexpensiveLog2(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::RISCVTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), transformAddShlImm(), TranslateM68kCC(), translateSetCCForBranch(), TranslateX86CC(), truncateVecElts(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), TryCombineBaseUpdate(), tryCombineMULLWithUZP1(), tryCombineShiftImm(), tryConvertSVEWideCompare(), tryDemorganOfBooleanCondition(), tryExtendDUPToExtractHigh(), tryFoldSelectIntoOp(), tryFoldToZero(), tryFormConcatFromShuffle(), tryMemPairCombine(), TryMULWIDECombine(), tryToConvertShuffleOfTbl2ToTbl4(), tryToFoldExtendOfConstant(), tryWhileWRFromOR(), UnpackFromArgumentSlot(), UnrollVectorOverflowOp(), unrollVectorShift(), valueToCarryFlag(), vectorToScalarBitmask(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::X86TargetLowering::visitMaskedLoad(), llvm::SelectionDAGBuilder::visitSwitchCase(), WidenVector(), and widenVectorOpsToi8().
SDDbgValue * SelectionDAG::getConstantDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
const Value * | C, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a constant SDDbgValue node.
Definition at line 11050 of file SelectionDAG.cpp.
References assert(), llvm::CallingConv::C, DL, llvm::SDDbgOperand::fromConst(), and llvm::SDDbgInfo::getAlloc().
Referenced by llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), and llvm::SelectionDAGBuilder::salvageUnresolvedDbgValue().
SDValue SelectionDAG::getConstantFP | ( | const APFloat & | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false |
||
) |
Definition at line 1788 of file SelectionDAG.cpp.
References DL, getConstantFP(), and getContext().
SDValue SelectionDAG::getConstantFP | ( | const ConstantFP & | V, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false |
||
) |
Definition at line 1793 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::ISD::ConstantFP, DL, llvm::EVT::getScalarType(), getSplat(), getVTList(), llvm::EVT::isFloatingPoint(), llvm::EVT::isVector(), N, NewSDValueDbgMsg(), and llvm::ISD::TargetConstantFP.
Create a ConstantFPSDNode wrapping a constant value.
If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal). The forms that take a double should only be used for simple constants that can be exactly represented in VT. No checks are made.
Definition at line 1826 of file SelectionDAG.cpp.
References llvm::APFloat::convert(), DL, getConstantFP(), llvm::EVT::getFltSemantics(), llvm::EVT::getScalarType(), llvm_unreachable, and llvm::APFloatBase::rmNearestTiesToEven.
Referenced by combineBitcast(), combineExtractWithShuffle(), combineFneg(), combineFP_ROUND(), combineVSelectWithAllOnesOrZeros(), EltsFromConsecutiveLoads(), expandExp(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_UINT(), expandFP_TO_UINT_SSE(), llvm::TargetLowering::expandIS_FPCLASS(), expandLog(), ExpandPowI(), llvm::TargetLowering::expandUINT_TO_FP(), FoldConstantArithmetic(), foldConstantFPMath(), getConstantFP(), getConstVector(), getF32Constant(), getInvertedVectorForFMA(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), getMemsetStringVal(), getMemsetValue(), llvm::TargetLowering::getNegatedExpression(), getNeutralElement(), getNode(), getRVVFPReductionOpAndOperands(), llvm::AMDGPUTargetLowering::getScaledLogInput(), getShuffleScalarElt(), llvm::TargetLowering::getSqrtInputTest(), llvm::TargetLowering::getSqrtResultForDenormInput(), getTargetConstantFP(), llvm::SelectionDAGBuilder::getValueImpl(), getZeroVector(), LowerFABSorFNEG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), LowerFCOPYSIGN(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::AMDGPUTargetLowering::LowerFLOG2(), llvm::AMDGPUTargetLowering::LowerFLOGCommon(), llvm::AMDGPUTargetLowering::LowerFLOGUnsafe(), LowerFMINIMUM_FMAXIMUM(), LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerShuffleAsBitMask(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i32(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performRcpCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyFPBinop(), and strictFPExtFromF16().
SDValue SelectionDAG::getConstantPool | ( | const Constant * | C, |
EVT | VT, | ||
MaybeAlign | Align = std::nullopt , |
||
int | Offs = 0 , |
||
bool | isT = false , |
||
unsigned | TargetFlags = 0 |
||
) |
Definition at line 1921 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::CallingConv::C, llvm::ISD::ConstantPool, llvm::DataLayout::getABITypeAlign(), getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), getVTList(), N, NewSDValueDbgMsg(), llvm::Offset, shouldOptForSize(), and llvm::ISD::TargetConstantPool.
Referenced by combineConcatVectorOps(), combineTargetShuffle(), llvm::TargetLowering::CTTZTableLookup(), getAddressForMemoryInput(), getTargetConstantPool(), lowerBuildVectorAsBroadcast(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle().
SDValue SelectionDAG::getConstantPool | ( | MachineConstantPoolValue * | C, |
EVT | VT, | ||
MaybeAlign | Align = std::nullopt , |
||
int | Offs = 0 , |
||
bool | isT = false , |
||
unsigned | TargetFlags = 0 |
||
) |
Definition at line 1951 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::CallingConv::C, llvm::ISD::ConstantPool, getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), getVTList(), N, llvm::Offset, and llvm::ISD::TargetConstantPool.
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inline |
Definition at line 500 of file SelectionDAG.h.
Referenced by AddCombineVUZPToVPADDL(), llvm::RegsForValue::AddInlineAsmOperands(), addShuffleForVecExtend(), adjustLoadValueTypeImpl(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), BuildVectorFromScalar(), canCombineShuffleToExtendVectorInreg(), canFoldInAddressingMode(), checkIntrinsicImmArg(), CollectOpsToWiden(), combineAnd(), combineAndShuffleNot(), combineArithReduction(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBitcastToBoolVector(), combineBitcastvxi1(), combineBoolVectorAndTruncateStore(), combineCMP(), combineCONCAT_VECTORS(), combineConcatVectorOfCasts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFMinNumFMaxNum(), combineFP_EXTEND(), combineFP_ROUND(), combineI8TruncStore(), combineLoad(), combineMinNumMaxNumImpl(), combineOr(), combinePMULH(), combinePredicateReduction(), combineScalarAndWithMaskSetcc(), combineSelect(), combineShiftAnd1ToBitTest(), combineShiftToAVG(), combineShiftToMULH(), combineShuffleToZeroExtendVectorInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToFPTruncExtElt(), combineTruncateWithSat(), combineUIntToFP(), combineV3I8LoadExt(), combineVectorMulToSraBitcast(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), combineVSelectWithAllOnesOrZeros(), combinevXi1ConstantToInteger(), concatSubVectors(), constructRetValue(), convertIntLogicToFPLogic(), CreateStackTemporary(), llvm::TargetLowering::CTTZTableLookup(), detectPMADDUBSW(), earlyExpandDIVFIX(), EltsFromConsecutiveLoads(), llvm::SelectionDAGBuilder::EmitBranchForMergedCondition(), emitErrorAndReplaceIntrinsicResults(), emitIntrinsicErrorMessage(), emitIntrinsicWithChainErrorMessage(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), errorUnsupported(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVectorSplice(), llvm::TargetLowering::expandVPCTPOP(), llvm::TargetLowering::expandVPCTTZElements(), extractSubVector(), fail(), findMemType(), FoldConstantArithmetic(), foldExtendVectorInregToExtendOfSubvector(), foldShuffleOfConcatUndefs(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::forceExpandWideMUL(), GenerateFixedLengthSVETBL(), getAtomicMemcpy(), getAtomicMemmove(), getAtomicMemset(), getConstant(), getConstantFP(), getCopyFromParts(), getCopyFromPartsVector(), llvm::SelectionDAGBuilder::getCopyFromRegs(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::RegsForValue::getCopyToRegs(), GetDependentSplitDestVTs(), getEVTAlign(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), getMemcpy(), getMemcpyLoadsAndStores(), getMemmove(), getMemmoveLoadsAndStores(), getMemset(), getMemsetStores(), getMemsetStringVal(), getMemsetValue(), getPrefTypeAlign(), getPTest(), getReducedAlign(), getRegistersForValue(), llvm::AMDGPUTargetLowering::getScaledLogInput(), getSplatValue(), GetSplitDestVTs(), llvm::AMDGPUTargetLowering::getSplitDestVTs(), llvm::TargetLowering::getSqrtInputTest(), GetTLSADDR(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorBitwiseReduce(), llvm::TargetLowering::getVectorElementPointer(), llvm::VECustomDAG::getVectorVT(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::SelectionDAGBuilder::init(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), isSaturatingMinMax(), isUpperSubvectorUndef(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), legalizeIntrinsicImmArg(), LowerADDSAT_SUBSAT(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), LowerAsSplatVectorLoad(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), lowerBitreverseShuffle(), lowerBuildVectorAsBroadcast(), llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SITargetLowering::LowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallSiteWithDeoptBundleImpl(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), llvm::AMDGPUTargetLowering::LowerFCEIL(), lowerFCMPIntrinsic(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFMINIMUM_FMAXIMUM(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), lowerICMPIntrinsic(), lowerLaneOp(), LowerMSCATTER(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), LowerPredicateLoad(), LowerPredicateStore(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::SelectionDAGBuilder::LowerStatepoint(), LowerStore(), LowerSVEIntrinsicEXT(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::VETargetLowering::lowerToVVP(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), lowerVectorBitClearImm(), lowerVectorBitRevImm(), lowerVectorBitSetImm(), LowerVectorExtend(), lowerVectorSplatImm(), LowerVSETCC(), llvm::VETargetLowering::lowerVVP_LOAD_STORE(), llvm::SystemZTargetLowering::makeExternalCall(), llvm::TargetLowering::makeLibCall(), makeStateFunctionCall(), matchBinOpReduction(), matchPMADDWD(), matchPMADDWD_2(), narrowExtractedVectorBinOp(), narrowIndex(), PerformARMBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), performConcatVectorsCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performExtBinopLoadFold(), PerformExtractFpToIntStores(), PerformInsertEltCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performLOADCombine(), PerformMinMaxFpToSatCombine(), performMSTORECombine(), performMulVectorCmpZeroCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performSelectCombine(), performSignExtendInRegCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), performSunpkloCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), performUADDVZextCombine(), PerformUMinFpToSatCombine(), performUzpCombine(), performVecReduceAddCombine(), performVectorExtCombine(), llvm::TargetLoweringBase::promoteTargetBoolean(), promoteToConstantPool(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceVMULWidth(), ReplaceLoadVector(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeBinOpOfSplats(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), shouldTransformMulToShiftsAddsSubs(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), llvm::TargetLowering::softenSetCCOperands(), splitStores(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVectorWithNARROW(), truncateVectorWithPACK(), tryCombineMULLWithUZP1(), tryFormConcatFromShuffle(), UnrollVectorOp(), UnrollVectorOverflowOp(), llvm::TargetLowering::verifyReturnAddressArgumentIsConstant(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), widenAbs(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), widenVec(), and WidenVector().
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Definition at line 813 of file SelectionDAG.h.
References llvm::ISD::CopyFromReg, getNode(), getRegister(), getVTList(), and Reg.
Referenced by llvm::AMDGPUTargetLowering::CreateLiveInRegister(), expandIntrinsicWChainHelper(), llvm::RegsForValue::getCopyFromRegs(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getFRAMEADDR(), getReadTimeStampCounter(), GetTLSADDR(), getv64i1Argument(), getzOSCalleeAndADA(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), lowerBALLOTIntrinsic(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::SITargetLowering::LowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), LowerCallResult(), LowerCMP_SWAP(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINTRINSIC_W_CHAIN(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::SITargetLowering::LowerSTACKSAVE(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), performDivRemCombine(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceZeroVectorStore(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), llvm::LoongArchDAGToDAGISel::selectShiftMask(), llvm::AMDGPUTargetLowering::storeStackInputValue(), unpack64(), unpackF64OnRV32DSoftABI(), unpackFromRegLoc(), llvm::SelectionDAGBuilder::visitBitTestCase(), and llvm::SelectionDAGBuilder::visitJumpTable().
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Definition at line 822 of file SelectionDAG.h.
References llvm::ISD::CopyFromReg, llvm::SDValue::getNode(), getNode(), getRegister(), getVTList(), and Reg.
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Definition at line 805 of file SelectionDAG.h.
References llvm::ISD::CopyToReg, llvm::SDValue::getNode(), getNode(), getVTList(), N, and Reg.
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Definition at line 787 of file SelectionDAG.h.
References llvm::ISD::CopyToReg, getNode(), getRegister(), N, and Reg.
Referenced by llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(), emitRepmovs(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), expandIntrinsicWChainHelper(), llvm::RegsForValue::getCopyToRegs(), llvm::MipsTargetLowering::getOpndList(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallTo(), LowerCMP_SWAP(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerSETCCCARRY(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSLocalDynamicModel(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::SITargetLowering::PostISelFolding(), prepareDescriptorIndirectCall(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::SelectionDAGBuilder::visitBitTestHeader(), and llvm::SelectionDAGBuilder::visitJumpTableHeader().
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Definition at line 796 of file SelectionDAG.h.
References llvm::ISD::CopyToReg, llvm::SDValue::getNode(), getNode(), getRegister(), getVTList(), N, and Reg.
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Definition at line 487 of file SelectionDAG.h.
References llvm::MachineFunction::getDataLayout().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), analyzeCallOperands(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), BuildExactSDIV(), BuildExactUDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), canCombineShuffleToExtendVectorInreg(), canFoldInAddressingMode(), combineBVOfVecSExt(), combineConcatVectorOps(), combineFMinNumFMaxNum(), combineGatherScatter(), combineLoad(), combinePredicateReduction(), combineShiftAnd1ToBitTest(), combineShuffleToAnyExtendVectorInreg(), combineShuffleToZeroExtendVectorInReg(), combineStore(), combineTargetShuffle(), combineTruncationShuffle(), combineVSelectWithAllOnesOrZeros(), computeKnownBits(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), ComputeNumSignBits(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), createGPRPairNode(), createMMXBuildVector(), createSetFPEnvNodes(), CreateStackTemporary(), llvm::TargetLowering::CTTZTableLookup(), EltsFromConsecutiveLoads(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::X86TargetLowering::emitStackGuardXorFP(), llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), expandVACopy(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVPBITREVERSE(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTPOP(), FoldConstantArithmetic(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::forceExpandWideMUL(), getADAEntry(), getAddressForMemoryInput(), getAtomicMemcpy(), getAtomicMemmove(), getAtomicMemset(), getAVX2GatherNode(), getConstant(), getConstantPool(), getCopyFromParts(), llvm::SelectionDAGBuilder::getCopyFromRegs(), getCopyToParts(), getEVTAlign(), GetExponent(), llvm::SelectionDAGBuilder::getFrameIndexTy(), getGatherNode(), getGlobalAddress(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), getIntPtrConstant(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), getJumpTableDebugInfo(), getLifetimeNode(), getLimitedPrecisionExp2(), getLoadStackGuard(), getMemCmpLoad(), getMemcpy(), getMemcpyLoadsAndStores(), getMemmove(), getMemmoveLoadsAndStores(), getMemset(), getMemsetStores(), getMemsetStringVal(), getNode(), llvm::TargetLowering::getPICJumpTableRelocBase(), llvm::M68kTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::VETargetLowering::getPICJumpTableRelocBase(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), getPPCf128HiElementSelector(), getPrefetchNode(), getPrefTypeAlign(), getReducedAlign(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), llvm::AMDGPUTargetLowering::getScaledLogInput(), getScatterNode(), getShiftAmountConstant(), getShiftAmountOperand(), llvm::PPC::getSplatIdxForPPCMnemonics(), llvm::TargetLowering::getSqrtInputTest(), getSymbolFunctionGlobalAddress(), getTagSymNode(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorIdxConstant(), getzOSCalleeAndADA(), llvm::SelectionDAGBuilder::handleDebugValue(), InferPtrAlign(), llvm::SelectionDAGBuilder::init(), isBLACompatibleAddress(), isExtendedBUILD_VECTOR(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), IsPredicateKnownToFail(), isVMOVModifiedImm(), llvm::PPC::isVMRGEOShuffleMask(), llvm::PPC::isVMRGHShuffleMask(), llvm::PPC::isVMRGLShuffleMask(), llvm::PPC::isVPKUDUMShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), llvm::PPC::isVSLDOIShuffleMask(), LowerADDSAT_SUBSAT(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), llvm::HexagonTargetLowering::LowerBlockAddress(), lowerBuildVectorAsBroadcast(), llvm::NVPTXTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SelectionDAGBuilder::LowerCallSiteWithPtrAuthBundle(), llvm::TargetLowering::LowerCallTo(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::LanaiTargetLowering::LowerConstantPool(), LowerCTPOP(), llvm::SelectionDAGBuilder::LowerDeoptimizeCall(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), LowerF64Op(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFMINIMUM_FMAXIMUM(), LowerFNEGorFABS(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), LowerMemOpCallTo(), LowerMULO(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), LowerPredicateLoad(), LowerPredicateStore(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), LowerRETURNADDR(), llvm::SelectionDAGBuilder::LowerStatepoint(), LowerSTORE(), llvm::TargetLowering::LowerToTLSEmulatedModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), llvm::SparcTargetLowering::makeAddress(), llvm::SystemZTargetLowering::makeExternalCall(), llvm::TargetLowering::makeLibCall(), makeStateFunctionCall(), matchPERM(), narrowExtractedVectorLoad(), PerformBITCASTCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMULCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), performUzpCombine(), PerformVMOVRRDCombine(), llvm::TargetLoweringBase::promoteTargetBoolean(), promoteToConstantPool(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), ReplaceATOMIC_LOAD_128Results(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), ReplaceLoadVector(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::RISCVDAGToDAGISel::SelectAddrRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), transformCallee(), unpackFromMemLoc(), UnrollVectorOverflowOp(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), and llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad().
SDDbgLabel * SelectionDAG::getDbgLabel | ( | DILabel * | Label, |
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a SDDbgLabel node.
Definition at line 11318 of file SelectionDAG.cpp.
References assert(), DL, and llvm::SDDbgInfo::getAlloc().
Referenced by llvm::SelectionDAGBuilder::visitDbgInfo().
SDDbgValue * SelectionDAG::getDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
SDNode * | N, | ||
unsigned | R, | ||
bool | IsIndirect, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a SDDbgValue node.
getDbgValue - Creates a SDDbgValue node.
Definition at line 11038 of file SelectionDAG.cpp.
References assert(), DL, llvm::SDDbgOperand::fromNode(), llvm::SDDbgInfo::getAlloc(), and N.
Referenced by llvm::SelectionDAGBuilder::handleDebugDeclare().
SDDbgValue * SelectionDAG::getDbgValueList | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
ArrayRef< SDDbgOperand > | Locs, | ||
ArrayRef< SDNode * > | Dependencies, | ||
bool | IsIndirect, | ||
const DebugLoc & | DL, | ||
unsigned | O, | ||
bool | IsVariadic | ||
) |
Creates a SDDbgValue node from a list of locations.
Definition at line 11100 of file SelectionDAG.cpp.
References assert(), DL, and llvm::SDDbgInfo::getAlloc().
Referenced by handleDanglingVariadicDebugInfo(), llvm::SelectionDAGBuilder::handleDebugValue(), salvageDebugInfo(), and transferDbgValues().
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Get the debug values which reference the given SDNode.
Definition at line 1838 of file SelectionDAG.h.
References llvm::SDDbgInfo::getSDDbgValues().
Referenced by ProcessSDDbgValues(), salvageDebugInfo(), and transferDbgValues().
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Return the current function's default denormal handling kind for the given floating point type.
Definition at line 2369 of file SelectionDAG.h.
References llvm::MachineFunction::getDenormalMode(), and llvm::EVT::getFltSemantics().
std::pair< EVT, EVT > SelectionDAG::GetDependentSplitDestVTs | ( | const EVT & | VT, |
const EVT & | EnvVT, | ||
bool * | HiIsEmpty | ||
) | const |
Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces.
GetDependentSplitDestVTs - Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces.
Sets the HisIsEmpty flag when hi type has zero storage size.
Sets the HiIsEmpty flag when hi type has zero storage size.
Definition at line 12671 of file SelectionDAG.cpp.
References assert(), getContext(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().
Definition at line 2311 of file SelectionDAG.cpp.
References llvm::ISD::EH_LABEL, and getLabelNode().
SDValue SelectionDAG::getElementCount | ( | const SDLoc & | DL, |
EVT | VT, | ||
ElementCount | EC, | ||
bool | ConstantFold = true |
||
) |
Definition at line 2064 of file SelectionDAG.cpp.
References DL, getConstant(), llvm::EVT::getSizeInBits(), and getVScale().
Referenced by llvm::RISCVTargetLowering::computeVLMax(), lowerCttzElts(), and llvm::RISCVTargetLowering::PerformDAGCombine().
|
inline |
Return the token chain corresponding to the entry of the function.
Definition at line 570 of file SelectionDAG.h.
Referenced by llvm::AMDGPUTargetLowering::addTokenForArgument(), clear(), combineConcatVectorOps(), combineTargetShuffle(), copyExtraInfo(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegisterRaw(), llvm::TargetLowering::CTTZTableLookup(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), getADAEntry(), llvm::MipsTargetLowering::getAddrLocal(), llvm::SelectionDAGBuilder::getCopyFromRegs(), getFLUSHW(), getFRAMEADDR(), getMemCmpLoad(), getStackArgumentTokenFactor(), GetTLSADDR(), llvm::SelectionDAGBuilder::getValueImpl(), getzOSCalleeAndADA(), HandleMergeInputChains(), llvm::AMDGPUTargetLowering::loadStackInputValue(), lowerBALLOTIntrinsic(), lowerBuildVectorAsBroadcast(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), lowerRETURNADDR(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), llvm::SelectionDAGBuilder::LowerStatepoint(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSGeneralDynamicModel64(), LowerToTLSGeneralDynamicModelX32(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerToTLSLocalDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), llvm::TargetLowering::makeLibCall(), llvm::ARMTargetLowering::PerformCMOVCombine(), performDivRemCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), llvm::SITargetLowering::PostISelFolding(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), promoteXINT_TO_FP(), llvm::SITargetLowering::ReplaceNodeResults(), replaceZeroVectorStore(), llvm::RISCVDAGToDAGISel::Select(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), llvm::LoongArchDAGToDAGISel::selectShiftMask(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
Compute the default alignment value for the given type.
Definition at line 1315 of file SelectionDAG.cpp.
References llvm::PointerType::get(), llvm::DataLayout::getABITypeAlign(), getContext(), getDataLayout(), and llvm::EVT::getTypeForEVT().
Referenced by getLoad(), getLoadStackGuard(), getLoadVP(), getMemIntrinsicNode(), getStore(), and getTruncStore().
Definition at line 2005 of file SelectionDAG.cpp.
References getVTList(), N, and Sym.
Referenced by llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), getAtomicMemcpy(), getAtomicMemmove(), getAtomicMemset(), getMemcpy(), getMemmove(), getMemset(), llvm::SelectionDAGBuilder::LowerDeoptimizeCall(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), LowerFSINCOS(), llvm::TargetLowering::LowerToTLSEmulatedModel(), llvm::SystemZTargetLowering::makeExternalCall(), llvm::TargetLowering::makeLibCall(), and makeStateFunctionCall().
SDValue SelectionDAG::getExtLoad | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 9017 of file SelectionDAG.cpp.
References getLoad(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getExtLoad | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
MaybeAlign | Alignment = MaybeAlign() , |
||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
||
const AAMDNodes & | AAInfo = AAMDNodes() |
||
) |
Definition at line 9006 of file SelectionDAG.cpp.
References getLoad(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.
Referenced by adjustSubwordCmp(), combineEXTEND_VECTOR_INREG(), combineLoad(), llvm::TargetLowering::CTTZTableLookup(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), getMemcpyLoadsAndStores(), LowerPredicateLoad(), lowerVECTOR_SHUFFLE(), performFPExtendCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), PerformVMOVrhCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorLoad(), SkipLoadExtensionForVMULL(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), unpackFromMemLoc(), and llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad().
SDValue SelectionDAG::getExtLoadVP | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding = false |
||
) |
Definition at line 9278 of file SelectionDAG.cpp.
References getLoadVP(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getExtLoadVP | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
MaybeAlign | Alignment, | ||
MachineMemOperand::Flags | MMOFlags, | ||
const AAMDNodes & | AAInfo, | ||
bool | IsExpanding = false |
||
) |
Definition at line 9265 of file SelectionDAG.cpp.
References getLoadVP(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.
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inline |
Convert Op, which must be of integer type, to the integer type VT, by either sign/zero-extending (depending on IsSigned) or truncating it.
Definition at line 984 of file SelectionDAG.h.
References DL, getSExtOrTrunc(), and getZExtOrTrunc().
|
inline |
Convert Op, which must be of integer type, to the integer type VT, by either any/sign/zero-extending (depending on IsAny / IsSigned) or truncating it.
Definition at line 968 of file SelectionDAG.h.
References llvm::ISD::ANY_EXTEND, DL, getAnyExtOrTrunc(), getSExtOrTrunc(), getZExtOrTrunc(), llvm_unreachable, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.
Referenced by combineShiftToAVG(), combineShiftToMULH(), earlyExpandDIVFIX(), expandDivFix(), LowerShift(), and PerformMinMaxFpToSatCombine().
SDValue SelectionDAG::getExtStridedLoadVP | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Stride, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding = false |
||
) |
Definition at line 9483 of file SelectionDAG.cpp.
References DL, getStridedLoadVP(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.
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inline |
Definition at line 506 of file SelectionDAG.h.
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation).
Definition at line 1433 of file SelectionDAG.cpp.
References llvm::EVT::bitsGT(), DL, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, getIntPtrConstant(), and getNode().
Referenced by llvm::TargetLowering::expandRoundInexactToOdd(), getCopyFromPartsVector(), getNode(), llvm::RISCVTargetLowering::LowerOperation(), LowerUINT_TO_FP_i32(), and llvm::RISCVTargetLowering::PerformDAGCombine().
Definition at line 1878 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::ISD::FrameIndex, getVTList(), N, and llvm::ISD::TargetFrameIndex.
Referenced by llvm::StatepointLoweringState::allocateStackSlot(), llvm::X86TargetLowering::BuildFILD(), CalculateTailCallArgDest(), CreateStackTemporary(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), getAddressForMemoryInput(), getLifetimeNode(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), getTargetFrameIndex(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::AMDGPUTargetLowering::loadStackInputValue(), llvm::SITargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::TargetLowering::LowerCallTo(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Op(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerINTRINSIC_W_CHAIN(), lowerStatepointMetaArgs(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), unpack64(), unpackF64OnRV32DSoftABI(), unpackFromMemLoc(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
SDDbgValue * SelectionDAG::getFrameIndexDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
unsigned | FI, | ||
ArrayRef< SDNode * > | Dependencies, | ||
bool | IsIndirect, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a FrameIndex SDDbgValue node.
FrameIndex with dependencies.
Definition at line 11074 of file SelectionDAG.cpp.
References assert(), DL, llvm::SDDbgOperand::fromFrameIdx(), and llvm::SDDbgInfo::getAlloc().
SDDbgValue * SelectionDAG::getFrameIndexDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
unsigned | FI, | ||
bool | IsIndirect, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a FrameIndex SDDbgValue node.
FrameIndex.
Definition at line 11063 of file SelectionDAG.cpp.
References assert(), DL, and getFrameIndexDbgValue().
Referenced by getFrameIndexDbgValue(), and llvm::SelectionDAGBuilder::handleDebugDeclare().
Return a freeze using the SDLoc of the value operand.
Definition at line 2415 of file SelectionDAG.cpp.
References llvm::ISD::FREEZE, and getNode().
Referenced by combinePredicateReduction(), combineSelectToBinOp(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandVECTOR_COMPRESS(), foldBoolSelectToLogic(), foldSelectWithIdentityConstant(), foldVSelectToSignBitSplatMask(), getNode(), LowerABD(), LowerAVXCONCAT_VECTORS(), llvm::RISCVTargetLowering::LowerOperation(), LowerShiftByScalarImmediate(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and llvm::TargetLowering::SimplifyDemandedVectorElts().
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inline |
Returns the result of the AssignmentTrackingAnalysis pass if it's available, otherwise return nullptr.
Definition at line 499 of file SelectionDAG.h.
Referenced by llvm::SelectionDAGBuilder::visitDbgInfo().
SDValue SelectionDAG::getGatherVP | ( | SDVTList | VTs, |
EVT | VT, | ||
const SDLoc & | dl, | ||
ArrayRef< SDValue > | Ops, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexType | IndexType | ||
) |
Definition at line 9577 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::details::FixedOrScalableQuantity< ElementCount, unsigned >::isKnownGE(), N, NewSDValueDbgMsg(), and llvm::ArrayRef< T >::size().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
SDValue SelectionDAG::getGetFPEnv | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Ptr, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 9890 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::ISD::GET_FPENV_MEM, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::SDValue::getValueType(), getVTList(), N, NewSDValueDbgMsg(), and Ptr.
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
Definition at line 1130 of file SelectionDAG.h.
References getNode(), and llvm::ISD::GLOBAL_OFFSET_TABLE.
Referenced by llvm::TargetLowering::getPICJumpTableRelocBase(), and llvm::HexagonTargetLowering::LowerGLOBALADDRESS().
SDValue SelectionDAG::getGlobalAddress | ( | const GlobalValue * | GV, |
const SDLoc & | DL, | ||
EVT | VT, | ||
int64_t | offset = 0 , |
||
bool | isTargetGA = false , |
||
unsigned | TargetFlags = 0 |
||
) |
Definition at line 1844 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::BitWidth, DL, getDataLayout(), llvm::DataLayout::getPointerTypeSizeInBits(), llvm::GlobalValue::getType(), getVTList(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::GlobalValue::isThreadLocal(), N, llvm::Offset, llvm::SignExtend64(), llvm::ISD::TargetGlobalAddress, and llvm::ISD::TargetGlobalTLSAddress.
Referenced by FoldSymbolOffset(), llvm::VETargetLowering::getPICJumpTableRelocBase(), getSymbolFunctionGlobalAddress(), getTargetGlobalAddress(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::TargetLowering::LowerToTLSEmulatedModel(), and performGlobalAddressCombine().
Get graph attributes for a node.
getGraphAttrs - Get graph attributes for a node.
(eg. "color=red".) Used from getNodeAttributes.
Definition at line 203 of file SelectionDAGPrinter.cpp.
References llvm::errs(), I, and N.
Referenced by llvm::DOTGraphTraits< SelectionDAG * >::getNodeAttributes().
Return HeapAllocSite associated with Node, or nullptr if none exists.
Definition at line 2330 of file SelectionDAG.h.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), and I.
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
SDValue SelectionDAG::getIndexedLoad | ( | SDValue | OrigLoad, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 9025 of file SelectionDAG.cpp.
References assert(), llvm::sampleprof::Base, getLoad(), llvm::SDValue::getValueType(), llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, and llvm::Offset.
SDValue SelectionDAG::getIndexedLoadVP | ( | SDValue | OrigLoad, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 9287 of file SelectionDAG.cpp.
References assert(), llvm::sampleprof::Base, getLoadVP(), llvm::SDValue::getValueType(), llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, and llvm::Offset.
SDValue SelectionDAG::getIndexedMaskedLoad | ( | SDValue | OrigLoad, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 9699 of file SelectionDAG.cpp.
References assert(), llvm::sampleprof::Base, getMaskedLoad(), llvm::SDValue::getValueType(), and llvm::Offset.
SDValue SelectionDAG::getIndexedMaskedStore | ( | SDValue | OrigStore, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 9748 of file SelectionDAG.cpp.
References assert(), llvm::sampleprof::Base, getMaskedStore(), and llvm::Offset.
SDValue SelectionDAG::getIndexedStore | ( | SDValue | OrigStore, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 9157 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::sampleprof::Base, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), N, NewSDValueDbgMsg(), llvm::Offset, and llvm::ISD::STORE.
Referenced by llvm::HexagonTargetLowering::LowerStore().
SDValue SelectionDAG::getIndexedStoreVP | ( | SDValue | OrigStore, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 9409 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::sampleprof::Base, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), N, NewSDValueDbgMsg(), and llvm::Offset.
Definition at line 1765 of file SelectionDAG.cpp.
References DL, getConstant(), getDataLayout(), and llvm::TargetLoweringBase::getPointerTy().
Referenced by buildCallOperands(), buildFromShuffleMostly(), combineArithReduction(), combineBitcast(), combineBitcastToBoolVector(), combineBVZEXTLOAD(), combineCompareEqual(), combineConcatVectorOps(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFP16_TO_FP(), combineFP_EXTEND(), combineFP_ROUND(), combineINSERT_SUBVECTOR(), combineMinMaxReduction(), combineSelect(), combineTargetShuffle(), combineTruncateWithSat(), CompactSwizzlableVector(), CreateCopyOfByValArgument(), detectPMADDUBSW(), EltsFromConsecutiveLoads(), emitConstantSizeRepmov(), emitRepmovsB(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), ExtendToType(), ExtractBitFromMaskVector(), extractSubVector(), getCALLSEQ_END(), getCALLSEQ_START(), getCopyToParts(), getFPExtendOrRound(), getFRAMEADDR(), getMaskNode(), getParamsForOneTrueMaskedElt(), getScalarMaskingNode(), getShuffleHalfVectors(), getStrictFPExtendOrRound(), GetTLSADDR(), insert1BitVector(), insertSubVector(), lower1BitShuffle(), lower1BitShuffleAsKSHIFTR(), lowerAddSubToHorizontalOp(), LowerAVXCONCAT_VECTORS(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), LowerBUILD_VECTORvXi1(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), LowerCONCAT_VECTORSvXi1(), llvm::HexagonTargetLowering::LowerEH_RETURN(), LowerEXTRACT_SUBVECTOR(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFLDEXP(), LowerFMINIMUM_FMAXIMUM(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), LowerFP16_TO_FP(), LowerFP_TO_FP16(), lowerFPToIntToFP(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), LowerFSINCOS(), LowerI64IntToFP16(), LowerI64IntToFP_AVX512DQ(), lowerINT_TO_FP_vXi64(), LowerLoad(), lowerMasksToReg(), LowerMGATHER(), LowerMLOAD(), llvm::RISCVTargetLowering::LowerOperation(), llvm::LanaiTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerSDIV(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), llvm::SelectionDAGBuilder::LowerStatepoint(), LowerStore(), LowerToTLSExecModel(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), LowerVACOPY(), llvm::HexagonTargetLowering::LowerVACOPY(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), LowerVASTART(), LowerZERO_EXTEND_Mask(), matchPMADDWD_2(), llvm::PPCTargetLowering::PerformDAGCombine(), performFPExtendCombine(), PerformLOADCombine(), PerformTruncatingStoreCombine(), prepareDescriptorIndirectCall(), promoteXINT_TO_FP(), ReorganizeVector(), ReplaceLoadVector(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), SplitAndExtendv16i1(), SplitScalar(), vectorizeExtractedCast(), and widenSubVector().
SDValue SelectionDAG::getJumpTable | ( | int | JTI, |
EVT | VT, | ||
bool | isTarget = false , |
||
unsigned | TargetFlags = 0 |
||
) |
Definition at line 1894 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), getVTList(), llvm::ISD::JumpTable, N, and llvm::ISD::TargetJumpTable.
Referenced by getTargetJumpTable(), and llvm::SelectionDAGBuilder::visitJumpTable().
Definition at line 1914 of file SelectionDAG.cpp.
References DL, getDataLayout(), getNode(), llvm::TargetLoweringBase::getPointerTy(), getTargetConstant(), getTargetLoweringInfo(), and llvm::ISD::JUMP_TABLE_DEBUG_INFO.
Referenced by llvm::TargetLowering::expandIndirectJTBranch(), llvm::RISCVTargetLowering::expandIndirectJTBranch(), and llvm::X86TargetLowering::expandIndirectJTBranch().
SDValue SelectionDAG::getLabelNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
SDValue | Root, | ||
MCSymbol * | Label | ||
) |
Definition at line 2316 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), and N.
Referenced by getEHLabel().
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inline |
Definition at line 494 of file SelectionDAG.h.
SDValue SelectionDAG::getLifetimeNode | ( | bool | IsStart, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
int | FrameIndex, | ||
int64_t | Size, | ||
int64_t | Offset = -1 |
||
) |
Creates a LifetimeSDNode that starts (IsStart==true
) or ends (IsStart==false
) the lifetime of the portion of FrameIndex
between offsets Offset
and Offset + Size
.
Definition at line 8822 of file SelectionDAG.cpp.
References AddNodeIDNode(), getDataLayout(), llvm::SDLoc::getDebugLoc(), getFrameIndex(), llvm::SDLoc::getIROrder(), getTargetLoweringInfo(), getVTList(), llvm::ISD::LIFETIME_END, llvm::ISD::LIFETIME_START, N, NewSDValueDbgMsg(), llvm::Offset, and Size.
SDValue SelectionDAG::getLoad | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 8999 of file SelectionDAG.cpp.
References getLoad(), getUNDEF(), llvm::ISD::NON_EXTLOAD, Ptr, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoad | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
MaybeAlign | Alignment = MaybeAlign() , |
||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
||
const AAMDNodes & | AAInfo = AAMDNodes() , |
||
const MDNode * | Ranges = nullptr |
||
) |
Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain.
This function will set the MOLoad flag on MMOFlags, but you can set it if you want. The MOStore flag must not be set.
Definition at line 8989 of file SelectionDAG.cpp.
References getLoad(), getUNDEF(), llvm::ISD::NON_EXTLOAD, Ptr, and llvm::ISD::UNINDEXED.
Referenced by bitcastf32Toi32(), llvm::X86TargetLowering::BuildFILD(), combineBVOfConsecutiveLoads(), combineConcatVectorOps(), combineExtractFromVectorLoad(), combineExtractWithShuffle(), combineLoad(), combineMaskedLoadConstantMask(), combineMOVDQ2Q(), combineStore(), combineTargetShuffle(), combineV3I8LoadExt(), EltsFromConsecutiveLoads(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), expandf64Toi32(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), expandVACopy(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), getADAEntry(), llvm::MipsTargetLowering::getAddrGlobal(), llvm::MipsTargetLowering::getAddrGlobalLargeGOT(), llvm::MipsTargetLowering::getAddrLocal(), getExtLoad(), getFRAMEADDR(), getIndexedLoad(), getLoad(), getMemCmpLoad(), getMemmoveLoadsAndStores(), GetTLSADDR(), getzOSCalleeAndADA(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerAsSplatVectorLoad(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::TargetLowering::LowerCallTo(), LowerF128Load(), llvm::SparcTargetLowering::LowerF128Op(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), LowerLoad(), llvm::HexagonTargetLowering::LowerLoad(), lowerLoadF128(), lowerLoadI1(), lowerMSALoadIntr(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), lowerRETURNADDR(), lowerShuffleAsBroadcast(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerUINT_TO_FP_i64(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), lowerVECTOR_SHUFFLE(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), narrowExtractedVectorLoad(), performConcatVectorsCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), performIntToFpCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performLOADCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToWideningLoad(), PerformVMOVhrCombine(), PerformVMOVRRDCombine(), prepareDescriptorIndirectCall(), reduceMaskedLoadToScalarLoad(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifySetCC(), SkipLoadExtensionForVMULL(), unpack64(), unpackF64OnRV32DSoftABI(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
SDValue SelectionDAG::getLoad | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 8939 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::EVT::bitsLT(), llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::EVT::getScalarType(), llvm::EVT::getVectorElementCount(), getVTList(), Indexed, llvm::EVT::isInteger(), llvm::EVT::isVector(), llvm::ISD::LOAD, N, NewSDValueDbgMsg(), llvm::ISD::NON_EXTLOAD, llvm::Offset, Ptr, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoad | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
||
const AAMDNodes & | AAInfo = AAMDNodes() , |
||
const MDNode * | Ranges = nullptr |
||
) |
Definition at line 8915 of file SelectionDAG.cpp.
References assert(), getLoad(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueType(), InferPointerInfo(), llvm::PointerUnion< PTs >::isNull(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::Offset, llvm::LocationSize::precise(), Ptr, Size, and llvm::MachinePointerInfo::V.
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inline |
Definition at line 1396 of file SelectionDAG.h.
References getEVTAlign(), getLoad(), llvm::Offset, and Ptr.
SDValue SelectionDAG::getLoadVP | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding = false |
||
) |
Definition at line 9257 of file SelectionDAG.cpp.
References getLoadVP(), getUNDEF(), llvm::ISD::NON_EXTLOAD, Ptr, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoadVP | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachinePointerInfo | PtrInfo, | ||
MaybeAlign | Alignment, | ||
MachineMemOperand::Flags | MMOFlags, | ||
const AAMDNodes & | AAInfo, | ||
const MDNode * | Ranges = nullptr , |
||
bool | IsExpanding = false |
||
) |
Definition at line 9244 of file SelectionDAG.cpp.
References getLoadVP(), getUNDEF(), llvm::ISD::NON_EXTLOAD, Ptr, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoadVP | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding = false |
||
) |
Definition at line 9209 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), getVTList(), Indexed, N, NewSDValueDbgMsg(), llvm::Offset, Ptr, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoadVP | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | MMOFlags, | ||
const AAMDNodes & | AAInfo, | ||
const MDNode * | Ranges = nullptr , |
||
bool | IsExpanding = false |
||
) |
Definition at line 9186 of file SelectionDAG.cpp.
References assert(), getLoadVP(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueType(), InferPointerInfo(), llvm::PointerUnion< PTs >::isNull(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::Offset, llvm::LocationSize::precise(), Ptr, Size, and llvm::MachinePointerInfo::V.
Referenced by getExtLoadVP(), getIndexedLoadVP(), and getLoadVP().
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inline |
Definition at line 1459 of file SelectionDAG.h.
References getEVTAlign(), getLoadVP(), llvm::Offset, and Ptr.
Create a logical NOT operation as (XOR Val, BooleanOne).
Definition at line 1584 of file SelectionDAG.cpp.
References DL, getBoolConstant(), getNode(), and llvm::ISD::XOR.
Referenced by extractBooleanFlip(), llvm::RISCVTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerUAddSubOCarry(), and PerformORCombine_i1().
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inline |
Definition at line 482 of file SelectionDAG.h.
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::StatepointLoweringState::allocateStackSlot(), buildCallOperands(), llvm::X86TargetLowering::BuildFILD(), llvm::TargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildSREMPow2(), CalculateTailCallSPDiff(), llvm::AArch64TargetLowering::changeStreamingMode(), combineConcatVectorOps(), combineFMA(), combineFMADDSUB(), combineFMinNumFMaxNum(), combineFneg(), combineI8TruncStore(), combineMul(), combineStore(), combineTargetShuffle(), combineV3I8LoadExt(), combineVectorSizedSetCCEquality(), llvm::BaseIndexOffset::computeAliasing(), computeKnownBits(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::SITargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::TargetLowering::CTTZTableLookup(), llvm::SITargetLowering::denormalsEnabledForType(), EmitCmp(), emitConstantSizeRepmov(), emitLockedStackOp(), llvm::AArch64SelectionDAGInfo::EmitMOPS(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemmove(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(), EmitUnrolledSetTag(), llvm::BaseIndexOffset::equalBaseIndex(), errorUnsupported(), llvm::X86TargetLowering::expandIndirectJTBranch(), llvm::TargetLowering::expandIS_FPCLASS(), expandMul(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), fail(), llvm::SelectionDAGBuilder::FindMergedConditions(), fixupFuncForFI(), getADAEntry(), getAddressForMemoryInput(), llvm::MipsTargetLowering::getAddrLocal(), getBROADCAST_LOAD(), getCopyFromParts(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getFRAMEADDR(), llvm::MipsTargetLowering::getGlobalReg(), getLoad(), getLoadStackGuard(), getLoadVP(), getMemcpyLoadsAndStores(), getMemIntrinsicNode(), getMemmoveLoadsAndStores(), getMemsetStores(), llvm::MipsTargetLowering::getOpndList(), llvm::VETargetLowering::getPICJumpTableRelocBase(), getReducedAlign(), getRegistersForValue(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), llvm::NVPTXTargetLowering::getSqrtEstimate(), getStore(), getTagSymNode(), GetTLSADDR(), getTruncStore(), getTruncStoreVP(), getv64i1Argument(), getVCIXISDNodeWCHAIN(), getVScale(), getzOSCalleeAndADA(), hasReturnsTwiceAttr(), InferPointerInfo(), InferPtrAlign(), llvm::SelectionDAGBuilder::init(), llvm::SITargetLowering::isCanonicalized(), isConsecutiveLSLoc(), llvm::HexagonTargetLowering::IsEligibleForTailCallOptimization(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), isEligibleToFoldADDIForFasterLocalAccesses(), llvm::SITargetLowering::isFMADLegal(), llvm::SITargetLowering::isFPExtFoldable(), llvm::TargetLowering::isInTailCallPosition(), llvm::SITargetLowering::isKnownNeverNaNForTargetNode(), isKnownNeverZero(), isThreadPointerAcquisitionNode(), IsWebAssemblyLocal(), legalizeScatterGatherIndexType(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerAsSplatVectorLoad(), LowerATOMIC_STORE(), lowerBuildVectorAsBroadcast(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SITargetLowering::LowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::TargetLowering::LowerCallTo(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Op(), llvm::HexagonTargetLowering::LowerFDIV(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), lowerIncomingStatepointValue(), llvm::HexagonTargetLowering::LowerINLINEASM(), LowerInterruptReturn(), LowerINTRINSIC_W_CHAIN(), llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN(), llvm::R600TargetLowering::LowerOperation(), llvm::SITargetLowering::LowerOperation(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), lowerRETURNADDR(), lowerShuffleAsBroadcast(), lowerStatepointMetaArgs(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), LowerToTLSLocalDynamicModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVACOPY(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), lowerVECTOR_SHUFFLE(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), MarkEHGuard(), MarkEHRegistrationNode(), narrowExtractedVectorLoad(), llvm::AMDGPUTargetLowering::needsDenormHandlingF32(), llvm::SITargetLowering::passSpecialInputs(), performBRCONDCombine(), performCONCAT_VECTORSCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformFADDCombineWithOperands(), performMemPairCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), llvm::SITargetLowering::PostISelFolding(), llvm::AArch64TargetLowering::preferredShiftLegalizationStrategy(), llvm::RISCVTargetLowering::preferredShiftLegalizationStrategy(), llvm::X86TargetLowering::preferredShiftLegalizationStrategy(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), processVCIXOperands(), promoteToConstantPool(), promoteVCIXScalar(), recoverFramePointer(), reduceVMULWidth(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), selectI64Imm(), setAlignFlagsForFI(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), setUsesTOCBasePtr(), shouldGenerateInlineTPLoop(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifySetCC(), spillIncomingStatepointValue(), splitStores(), llvm::AMDGPUTargetLowering::storeStackInputValue(), StoreTailCallArgumentsToStackSlot(), transformCallee(), tryMemPairCombine(), llvm::X86InstrInfo::unfoldMemoryOperand(), unpack64(), unpackF64OnRV32DSoftABI(), unpackFromMemLoc(), unpackFromRegLoc(), updateForAIXShLibTLSModelOpt(), viewGraph(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
ArrayRef< EVT > | ResultTys, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 10942 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT | ||
) |
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
getMachineNode - These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
Note that getMachineNode returns the resultant node. If there is already a node of the specified opcode and operands, it returns that node instead of the current one.
Definition at line 10861 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
Referenced by buildRegSequence16(), buildRegSequence32(), llvm::SITargetLowering::buildRSRC(), buildSMovImm32(), llvm::VETargetLowering::combineTRUNCATE(), llvm::SITargetLowering::copyToM0(), createGPRPairNode(), createTuple(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), emitLockedStackOp(), llvm::AArch64SelectionDAGInfo::EmitMOPS(), llvm::X86TargetLowering::emitStackGuardXorFP(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(), expandBitCastI128ToF128(), expandIntrinsicWChainHelper(), llvm::HexagonDAGToDAGISel::FastFDiv(), llvm::HexagonDAGToDAGISel::FDiv(), getDataClassTest(), getLeftShift(), getLoadStackGuard(), getMachineNode(), getPrefetchNode(), getTargetExtractSubreg(), getTargetInsertSubreg(), InvertCarryFlag(), isWorthFoldingIntoOrrWithShift(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), llvm::VETargetLowering::lowerATOMIC_FENCE(), lowerBuildVectorViaPacking(), llvm::SITargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerF128Load(), LowerF128Store(), LowerF64Op(), LowerFNEGorFABS(), llvm::VETargetLowering::LowerFormalArguments(), lowerI128ToGR128(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), LowerINTRINSIC_W_CHAIN(), lowerLoadF128(), lowerLoadI1(), llvm::SystemZTargetLowering::LowerOperationWrapper(), llvm::VETargetLowering::LowerReturn(), lowerStoreF128(), lowerStoreI1(), optimizeLogicalImm(), llvm::packConstantV2I16(), llvm::SITargetLowering::PostISelFolding(), ReplaceATOMIC_LOAD_128Results(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), llvm::AMDGPUDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::Select(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::RISCVDAGToDAGISel::SelectAddrRegImm(), llvm::RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(), llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale(), llvm::HexagonDAGToDAGISel::SelectAddSubCarry(), llvm::HexagonDAGToDAGISel::SelectBrevLdIntrinsic(), llvm::AMDGPUDAGToDAGISel::SelectBuildVector(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectConstant(), selectConstantAddr(), llvm::HexagonDAGToDAGISel::SelectConstantFP(), llvm::HexagonDAGToDAGISel::SelectD2P(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), llvm::HexagonDAGToDAGISel::SelectHVXDualOutput(), selectI64Imm(), selectI64ImmDirect(), selectI64ImmDirectPrefix(), selectImm(), selectImmSeq(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::HexagonDAGToDAGISel::SelectNewCircIntrinsic(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), llvm::HexagonDAGToDAGISel::SelectP2D(), llvm::HexagonDAGToDAGISel::SelectQ2V(), llvm::HvxSelector::selectRor(), SelectSAddrFI(), llvm::RISCVDAGToDAGISel::selectSETCC(), llvm::RISCVDAGToDAGISel::selectSF_VC_X_SE(), llvm::LoongArchDAGToDAGISel::selectShiftMask(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), llvm::HexagonDAGToDAGISel::SelectV2Q(), llvm::HexagonDAGToDAGISel::SelectV65Gather(), llvm::HexagonDAGToDAGISel::SelectV65GatherPred(), llvm::HexagonDAGToDAGISel::SelectVAlign(), llvm::HvxSelector::selectVAlign(), llvm::HexagonDAGToDAGISel::SelectVAlignAddr(), llvm::RISCVDAGToDAGISel::selectVLSEG(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), llvm::RISCVDAGToDAGISel::selectVSSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), llvm::RISCVDAGToDAGISel::tryIndexedLoad(), llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), llvm::X86InstrInfo::unfoldMemoryOperand(), Widen(), and llvm::SITargetLowering::wrapAddr64Rsrc().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 10889 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Op1 | ||
) |
Definition at line 10867 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line 10874 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3 | ||
) |
Definition at line 10881 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 10911 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
EVT | VT3, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 10935 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
EVT | VT3, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line 10918 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
EVT | VT3, | ||
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3 | ||
) |
Definition at line 10926 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line 10895 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3 | ||
) |
Definition at line 10903 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
SDVTList | VTs, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 10949 of file SelectionDAG.cpp.
References AddNodeIDNode(), DL, N, NewSDValueDbgMsg(), llvm::SDVTList::NumVTs, and llvm::SDVTList::VTs.
SDValue SelectionDAG::getMaskedGather | ( | SDVTList | VTs, |
EVT | MemVT, | ||
const SDLoc & | dl, | ||
ArrayRef< SDValue > | Ops, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexType | IndexType, | ||
ISD::LoadExtType | ExtTy | ||
) |
Definition at line 9759 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::details::FixedOrScalableQuantity< ElementCount, unsigned >::isKnownGE(), llvm::ISD::MGATHER, N, NewSDValueDbgMsg(), and llvm::ArrayRef< T >::size().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine(), performMaskedGatherScatterCombine(), and rebuildGatherScatter().
SDValue SelectionDAG::getMaskedHistogram | ( | SDVTList | VTs, |
EVT | MemVT, | ||
const SDLoc & | dl, | ||
ArrayRef< SDValue > | Ops, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexType | IndexType | ||
) |
Definition at line 9852 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::ISD::EXPERIMENTAL_VECTOR_HISTOGRAM, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), N, NewSDValueDbgMsg(), and llvm::ArrayRef< T >::size().
SDValue SelectionDAG::getMaskedLoad | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
SDValue | Mask, | ||
SDValue | Src0, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexedMode | AM, | ||
ISD::LoadExtType | ExtTy, | ||
bool | IsExpanding = false |
||
) |
Definition at line 9664 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::sampleprof::Base, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), getVTList(), Indexed, llvm::ISD::MLOAD, N, NewSDValueDbgMsg(), llvm::Offset, and llvm::ISD::UNINDEXED.
Referenced by combineMaskedLoad(), combineMaskedLoadConstantMask(), getIndexedMaskedLoad(), LowerMLOAD(), llvm::RISCVTargetLowering::PerformDAGCombine(), performLDNT1Combine(), performUnpackCombine(), and tryToFoldExtOfMaskedLoad().
SDValue SelectionDAG::getMaskedScatter | ( | SDVTList | VTs, |
EVT | MemVT, | ||
const SDLoc & | dl, | ||
ArrayRef< SDValue > | Ops, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexType | IndexType, | ||
bool | IsTruncating = false |
||
) |
Definition at line 9806 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::details::FixedOrScalableQuantity< ElementCount, unsigned >::isKnownGE(), llvm::ISD::MSCATTER, N, NewSDValueDbgMsg(), and llvm::ArrayRef< T >::size().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine(), performMaskedGatherScatterCombine(), and rebuildGatherScatter().
SDValue SelectionDAG::getMaskedStore | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
SDValue | Mask, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexedMode | AM, | ||
bool | IsTruncating = false , |
||
bool | IsCompressing = false |
||
) |
Definition at line 9710 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::sampleprof::Base, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::SDValue::getValueType(), getVTList(), Indexed, llvm::ISD::MSTORE, N, NewSDValueDbgMsg(), llvm::Offset, and llvm::ISD::UNINDEXED.
Referenced by combineMaskedStore(), getIndexedMaskedStore(), LowerINTRINSIC_W_CHAIN(), LowerMSTORE(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMSTORECombine(), and performSTNT1Combine().
Definition at line 2013 of file SelectionDAG.cpp.
References getVTList(), N, and Sym.
Referenced by recoverFramePointer(), and transformCallee().
Return an MDNodeSDNode which holds an MDNode.
Definition at line 2371 of file SelectionDAG.cpp.
References AddNodeIDNode(), getVTList(), llvm::ISD::MDNODE_SDNODE, and N.
Referenced by llvm::PPCTargetLowering::CollectTargetIntrinsicOperands(), and llvm::SelectionDAGBuilder::getValueImpl().
SDValue SelectionDAG::getMemBasePlusOffset | ( | SDValue | Base, |
SDValue | Offset, | ||
const SDLoc & | DL, | ||
const SDNodeFlags | Flags = SDNodeFlags() |
||
) |
Definition at line 7781 of file SelectionDAG.cpp.
References llvm::ISD::ADD, assert(), DL, getNode(), llvm::Offset, and Ptr.
SDValue SelectionDAG::getMemBasePlusOffset | ( | SDValue | Base, |
TypeSize | Offset, | ||
const SDLoc & | DL, | ||
const SDNodeFlags | Flags = SDNodeFlags() |
||
) |
Returns sum of the base pointer and offset.
Unlike getObjectPtrOffset this does not set NoUnsignedWrap by default.
Definition at line 7765 of file SelectionDAG.cpp.
References llvm::sampleprof::Base, DL, getConstant(), getMemBasePlusOffset(), getVScale(), and llvm::Offset.
Referenced by combineI8TruncStore(), combineLoad(), combineStore(), combineTargetShuffle(), combineV3I8LoadExt(), llvm::TargetLowering::CTTZTableLookup(), EmitUnrolledSetTag(), getBROADCAST_LOAD(), getMemBasePlusOffset(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), getObjectPtrOffset(), getParamsForOneTrueMaskedElt(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerShuffleAsBroadcast(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerVECTOR_SHUFFLE(), narrowExtractedVectorLoad(), performLOADCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), scalarizeVectorStore(), ShrinkLoadReplaceStoreWithStore(), and splitVectorStore().
SDValue SelectionDAG::getMemcpy | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
Align | Alignment, | ||
bool | isVol, | ||
bool | AlwaysInline, | ||
const CallInst * | CI, | ||
std::optional< bool > | OverrideTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo, | ||
const AAMDNodes & | AAInfo = AAMDNodes() , |
||
AAResults * | AA = nullptr |
||
) |
Definition at line 8296 of file SelectionDAG.cpp.
References assert(), checkAddrSpaceIsValidForLibcall(), llvm::SelectionDAGTargetInfo::EmitTargetCodeForMemcpy(), llvm::funcReturnsFirstArgOfCall(), llvm::MachinePointerInfo::getAddrSpace(), getContext(), getDataLayout(), getExternalSymbol(), llvm::DataLayout::getIntPtrType(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), getMemcpyLoadsAndStores(), llvm::TargetLoweringBase::getPointerTy(), getTarget(), llvm::PointerType::getUnqual(), llvm::ConstantSDNode::getZExtValue(), llvm::isInTailCallPosition(), llvm::CallInst::isTailCall(), llvm::ConstantSDNode::isZero(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setDiscardResult(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), and Size.
Referenced by CreateCopyOfByValArgument(), emitConstantSizeRepmov(), llvm::SITargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), LowerVACOPY(), and llvm::HexagonTargetLowering::LowerVACOPY().
SDValue SelectionDAG::getMemIntrinsicNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 8779 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::ISD::FIRST_TARGET_MEMORY_OPCODE, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, N, NewSDValueDbgMsg(), llvm::SDVTList::NumVTs, llvm::ISD::PREFETCH, and llvm::SDVTList::VTs.
SDValue SelectionDAG::getMemIntrinsicNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops, | ||
EVT | MemVT, | ||
MachinePointerInfo | PtrInfo, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore , |
||
LocationSize | Size = 0 , |
||
const AAMDNodes & | AAInfo = AAMDNodes() |
||
) |
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
Opcode may be INTRINSIC_VOID, INTRINSIC_W_CHAIN, or a target-specific opcode with a value not less than FIRST_TARGET_MEMORY_OPCODE.
Definition at line 8764 of file SelectionDAG.cpp.
References getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), getMemIntrinsicNode(), llvm::EVT::getStoreSize(), llvm::LocationSize::precise(), and Size.
Referenced by llvm::X86TargetLowering::BuildFILD(), combineBitcast(), combineBVZEXTLOAD(), combineINSERT_SUBVECTOR(), combineTargetShuffle(), CombineVLDDUP(), combineX86CloadCstore(), createLoadLR(), createSetFPEnvNodes(), createStoreLR(), EltsFromConsecutiveLoads(), EmitMaskedTruncSStore(), EmitTruncSStore(), EmitUnrolledSetTag(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), getAVX2GatherNode(), getBROADCAST_LOAD(), getGatherNode(), getMemIntrinsicNode(), getScatterNode(), LowerATOMIC_STORE(), lowerAtomicArithWithLOCK(), lowerBuildVectorAsBroadcast(), llvm::NVPTXTargetLowering::LowerCall(), LowerCMP_SWAP(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMSCATTER(), llvm::SystemZTargetLowering::LowerOperationWrapper(), llvm::NVPTXTargetLowering::LowerReturn(), lowerShuffleAsBroadcast(), LowerStore(), LowerSTORE(), lowerUINT_TO_FP_vXi32(), LowerUnalignedLoadRetParam(), LowerUnalignedStoreParam(), LowerUnalignedStoreRet(), lowerVECTOR_SHUFFLE(), llvm::AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(), narrowLoadToVZLoad(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformLOADCombine(), PerformMVEVLDCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), PerformVDUPCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), TryCombineBaseUpdate(), tryMemPairCombine(), llvm::X86TargetLowering::visitMaskedLoad(), and llvm::X86TargetLowering::visitMaskedStore().
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inline |
Definition at line 1334 of file SelectionDAG.h.
References getEVTAlign(), getMemIntrinsicNode(), and Size.
SDValue SelectionDAG::getMemmove | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
Align | Alignment, | ||
bool | isVol, | ||
const CallInst * | CI, | ||
std::optional< bool > | OverrideTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo, | ||
const AAMDNodes & | AAInfo = AAMDNodes() , |
||
AAResults * | AA = nullptr |
||
) |
Definition at line 8421 of file SelectionDAG.cpp.
References checkAddrSpaceIsValidForLibcall(), llvm::SelectionDAGTargetInfo::EmitTargetCodeForMemmove(), llvm::funcReturnsFirstArgOfCall(), llvm::MachinePointerInfo::getAddrSpace(), getContext(), getDataLayout(), getExternalSymbol(), llvm::DataLayout::getIntPtrType(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), getMemmoveLoadsAndStores(), llvm::TargetLoweringBase::getPointerTy(), getTarget(), llvm::PointerType::getUnqual(), llvm::ConstantSDNode::getZExtValue(), llvm::isInTailCallPosition(), llvm::CallInst::isTailCall(), llvm::ConstantSDNode::isZero(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setDiscardResult(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), and Size.
SDValue SelectionDAG::getMemset | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
Align | Alignment, | ||
bool | isVol, | ||
bool | AlwaysInline, | ||
const CallInst * | CI, | ||
MachinePointerInfo | DstPtrInfo, | ||
const AAMDNodes & | AAInfo = AAMDNodes() |
||
) |
Definition at line 8537 of file SelectionDAG.cpp.
References assert(), checkAddrSpaceIsValidForLibcall(), DL, llvm::SelectionDAGTargetInfo::EmitTargetCodeForMemset(), llvm::funcReturnsFirstArgOfCall(), llvm::MachinePointerInfo::getAddrSpace(), getContext(), getDataLayout(), getExternalSymbol(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), getMemsetStores(), llvm::TargetLoweringBase::getPointerTy(), getTarget(), getTargetLoweringInfo(), llvm::PointerType::getUnqual(), llvm::Type::getVoidTy(), llvm::ConstantSDNode::getZExtValue(), llvm::isInTailCallPosition(), llvm::isNullConstant(), llvm::CallInst::isTailCall(), llvm::ConstantSDNode::isZero(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::TargetLowering::CallLoweringInfo::setDiscardResult(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::TargetLowering::CallLoweringInfo::setTailCall(), and Size.
Referenced by llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset().
Create a MERGE_VALUES node from the given operands.
getMergeValues - Create a MERGE_VALUES node from the given operands.
Definition at line 8753 of file SelectionDAG.cpp.
References getNode(), getVTList(), llvm::ISD::MERGE_VALUES, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), and llvm::ArrayRef< T >::size().
Referenced by combineFP_EXTEND(), combineFP_ROUND(), combineV3I8LoadExt(), combineVectorCompareAndMaskUnaryOp(), combineX86AddSub(), combineX86SubCmpForFlags(), constructRetValue(), emitIntrinsicWithChainErrorMessage(), FixupMMXIntrinsicTypes(), getAVX2GatherNode(), getGatherNode(), llvm::VECustomDAG::getMergeValues(), llvm::SelectionDAGBuilder::getValueImpl(), getVCIXISDNodeWCHAIN(), llvm::VETargetLowering::lowerATOMIC_SWAP(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerDSPIntr(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), LowerF128Load(), llvm::SITargetLowering::LowerFormalArguments(), LowerFP16_TO_FP(), LowerFP_TO_FP16(), llvm::SITargetLowering::lowerGET_FPENV(), llvm::SITargetLowering::lowerGET_ROUNDING(), LowerI64IntToFP16(), LowerI64IntToFP_AVX512DQ(), lowerINT_TO_FP_vXi64(), LowerINTRINSIC_W_CHAIN(), LowerLoad(), llvm::HexagonTargetLowering::LowerLoad(), llvm::MipsTargetLowering::lowerLOAD(), lowerLoadF128(), lowerLoadI1(), LowerMGATHER(), LowerMLOAD(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), LowerPredicateLoad(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), LowerREADCYCLECOUNTER(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::SITargetLowering::LowerSTACKSAVE(), llvm::HexagonTargetLowering::LowerUAddSubO(), llvm::HexagonTargetLowering::LowerUAddSubOCarry(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), LowerUINT_TO_FP_i32(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), LowerVSETCC(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFlagSettingCombine(), performGatherLoadCombine(), performLD1Combine(), performLD1ReplicateCombine(), performLDNT1Combine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformLOADCombine(), performLOADCombine(), PerformLongShiftCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformVMOVRRDCombine(), SplitStrictFPVectorOp(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), tryMemPairCombine(), UnrollVectorOp(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), and widenVectorOpsToi8().
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inline |
Definition at line 484 of file SelectionDAG.h.
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inline |
Definition at line 504 of file SelectionDAG.h.
Return the MMRA MDNode associated with Node, or nullptr if none exists.
Definition at line 2349 of file SelectionDAG.h.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), and llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find().
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
Create negative operation as (SUB 0, Val).
Definition at line 1575 of file SelectionDAG.cpp.
References DL, getConstant(), getNode(), and llvm::ISD::SUB.
Referenced by combineAddOrSubToADCOrSBB(), combineAnd(), combineMul(), combinePredicateReduction(), combineSelectToBinOp(), combineSetCC(), combineX86AddSub(), LowerABS(), lowerAtomicArith(), LowerShift(), performCONCAT_VECTORSCombine(), and llvm::RISCVTargetLowering::PerformDAGCombine().
SDValue SelectionDAG::getNeutralElement | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDNodeFlags | Flags | ||
) |
Get the (commutative) neutral element for the given opcode, if it exists.
Definition at line 13235 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::APFloat::changeSign(), DL, llvm::ISD::FADD, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMUL, getAllOnesConstant(), getConstant(), getConstantFP(), llvm::EVT::getFltSemantics(), llvm::APFloat::getInf(), llvm::APFloat::getLargest(), llvm::APFloat::getQNaN(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), llvm::EVT::getSizeInBits(), llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, and llvm::ISD::XOR.
Referenced by tryFoldSelectIntoOp().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
ArrayRef< EVT > | ResultTys, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 10182 of file SelectionDAG.cpp.
References DL, getNode(), and getVTList().
Gets or creates the specified node.
Definition at line 5899 of file SelectionDAG.cpp.
References AddNodeIDNode(), DL, getVTList(), N, and NewSDValueDbgMsg().
Gets or creates the specified node.
Definition at line 10046 of file SelectionDAG.cpp.
References DL, getNode(), and llvm::ArrayRef< T >::size().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addIPMSequence(), addRequiredExtensionForVectorMULL(), AddRequiredExtensionForVMULL(), addShuffleForVecExtend(), llvm::AMDGPUTargetLowering::addTokenForArgument(), adjustBitcastSrcVectorSSE1(), adjustForTestUnderMask(), adjustICmp128(), adjustLoadValueTypeImpl(), buildCallOperands(), BuildExactSDIV(), BuildExactUDIV(), buildFromShuffleMostly(), BuildIntrinsicOp(), buildMergeScalars(), buildPCRelGlobalAddress(), buildScalarToVector(), llvm::TargetLowering::BuildSDIV(), llvm::PPCTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), BuildVectorFromScalar(), BuildVSLDOI(), canonicalizeBitSelect(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleVectorByLane(), canonicalizeShuffleWithOp(), carryFlagToValue(), chainLoadsAndStoresForMemcpy(), llvm::AArch64TargetLowering::changeStreamingMode(), checkIntrinsicImmArg(), checkSignTestSetCCCombine(), clampDynamicVectorIndex(), CollectOpsToWiden(), combine_CC(), combineAcrossLanesIntrinsic(), combineADC(), combineAdd(), combineAddOfBooleanXor(), combineAddOfPMADDWD(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineADDToMAT_PCREL_ADDR(), combineADDX(), combineAnd(), combineAndLoadToBZHI(), combineAndMaskToShift(), combineAndNotIntoANDNP(), combineAndnp(), combineAndOrForCcmpCtest(), CombineANDShift(), combineAndShuffleNot(), combineArithReduction(), combineAVG(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBinOpToReduce(), combineBitcast(), combineBitcastToBoolVector(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBitOpWithPACK(), combineBitOpWithShift(), combineBoolVectorAndTruncateStore(), combineBrCond(), combineCarryDiamond(), combineCarryThroughADD(), combineCastedMaskArithmetic(), combineCMov(), combineCMP(), combineCommutableSHUFP(), combineCompareEqual(), combineConcatVectorOfCasts(), combineConcatVectorOfConcatVectors(), combineConcatVectorOfScalars(), combineConcatVectorOfShuffleAndItsOperands(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineCVTPH2PS(), combineDeMorganOfBoolean(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineFAndFNotToFAndn(), combineFMA(), combineFMADDSUB(), combineFMinFMax(), llvm::AMDGPUTargetLowering::combineFMinMaxLegacy(), llvm::AMDGPUTargetLowering::combineFMinMaxLegacyImpl(), combineFMinNumFMaxNum(), combineFMulcFCMulc(), combineFneg(), combineFP16_TO_FP(), combineFP_EXTEND(), combineFP_ROUND(), combineGatherScatter(), combineHorizOpWithShuffle(), combineI8TruncStore(), combineINSERT_SUBVECTOR(), combineLoad(), combineLogicBlendIntoConditionalNegate(), combineLRINT_LLRINT(), combineM68kBrCond(), combineMADConstOne(), combineMinMaxReduction(), combineMinNumMaxNumImpl(), combineMOVMSK(), combineMul(), combineMulSelectConstOne(), combineMulSpecial(), combineMulToPMADDWD(), combineMulToPMULDQ(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), combineOrOfCZERO(), combineOrXorWithSETCC(), combinePMULDQ(), combinePMULH(), combinePredicateReduction(), combinePTESTCC(), combineRedundantDWordShuffle(), combineSBB(), combineScalarAndWithMaskSetcc(), combineScalarToVector(), llvm::VETargetLowering::combineSelect(), combineSelect(), combineSelectAndUse(), combineSelectAsExtAnd(), llvm::VETargetLowering::combineSelectCC(), combineSelectOfTwoConstants(), combineSelectToBinOp(), combineSetCC(), combineSetCCMOVMSK(), combineSext(), combineSextInRegCmov(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToAVG(), combineShiftToMULH(), combineShiftToPMULH(), combineShuffleOfConcatUndef(), combineShuffleToAddSubOrFMAddSub(), combineShuffleToAnyExtendVectorInreg(), combineShuffleToFMAddSub(), combineShuffleToZeroExtendVectorInReg(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineSubABS(), combineSubOfBoolean(), combineSubSetcc(), combineSubShiftToOrcB(), combineSUBX(), combineSVEPrefetchVecBaseImmOff(), combineSVEReductionFP(), combineSVEReductionInt(), combineSVEReductionOrderedFP(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToExtendCMOV(), combineToFPTruncExtElt(), combineToHorizontalAddSub(), combineToVWMACC(), combineTruncate(), combineTruncatedArithmetic(), combineTruncateWithSat(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineTruncToVnclip(), combineUADDO_CARRYDiamond(), combineUIntToFP(), combineV3I8LoadExt(), combineVectorCompareAndMaskUnaryOp(), combineVectorHADDSUB(), combineVectorInsert(), combineVectorMulToSraBitcast(), combineVectorPack(), combineVectorShiftImm(), combineVectorSizedSetCCEquality(), combineVFMADD_VLWithVFNEG_VL(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), combineVSelectToBLENDV(), combineVSelectWithAllOnesOrZeros(), combineVTRUNC(), combineVWADDSUBWSelect(), combineX86AddSub(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86SubCmpForFlags(), combineXor(), combineXorSubCTLZ(), combineZext(), CompactSwizzlableVector(), ConstantBuildVector(), constructDup(), constructRetValue(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), convertFixedMaskToScalableVector(), convertFPToInt(), convertFromScalableVector(), convertIntLogicToFPLogic(), convertIntToFP(), convertLocVTToValVT(), convertMergedOpToPredOp(), ConvertSelectToConcatVector(), convertShiftLeftToScale(), convertToScalableVector(), convertValVTToLocVT(), createCMovFP(), createFPCmp(), createLoadLR(), createMemMemNode(), createMMXBuildVector(), createPSADBW(), createSetFPEnvNodes(), createStoreLR(), createVariablePermute(), createVPDPBUSD(), llvm::TargetLowering::CTTZTableLookup(), customLegalizeToWOp(), customLegalizeToWOpWithSExt(), CustomNonLegalBITCASTResults(), detectPMADDUBSW(), detectUSatPattern(), distributeOpThroughSelect(), dump(), EltsFromConsecutiveLoads(), EmitAVX512Test(), EmitCMP(), EmitCmp(), emitCmp(), emitComparison(), emitConditionalComparison(), emitConstantSizeRepmov(), emitIntrinsicWithCC(), emitIntrinsicWithCCAndChain(), emitMemMemReg(), llvm::AArch64SelectionDAGInfo::EmitMOPS(), emitOrXorXorTree(), emitRepmovs(), emitSETCC(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), emitStrictFPComparison(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(), EmitTest(), EmitUnrolledSetTag(), EmitVectorComparison(), Expand64BitShift(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), expandBitCastF128ToI128(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandBSWAP(), ExpandBVWithShuffles(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), expandExp(), expandExp2(), expandf64Toi32(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFMINNUM_FMAXNUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandFP_TO_UINT(), expandFP_TO_UINT_SSE(), llvm::TargetLowering::expandFunnelShift(), ExpandHorizontalBinOp(), llvm::TargetLowering::expandIndirectJTBranch(), llvm::RISCVTargetLowering::expandIndirectJTBranch(), llvm::X86TargetLowering::expandIndirectJTBranch(), llvm::TargetLowering::expandIntMINMAX(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandIS_FPCLASS(), expandLog(), expandLog10(), expandLog2(), expandMul(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), expandPow(), ExpandPowI(), ExpandREAD_REGISTER(), llvm::TargetLowering::expandREM(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandV4F32ToV2F64(), expandVAArg(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVecReduceSeq(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), llvm::TargetLowering::expandVPBITREVERSE(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTPOP(), llvm::TargetLowering::expandVPCTTZ(), llvm::TargetLowering::expandVPCTTZElements(), expandVPFunnelShift(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), ExtractBitFromMaskVector(), extractF64Exponent(), extractLOHI(), extractShiftForRotate(), extractSubVector(), ExtractVectorElements(), finalizeTS1AM(), findMoreOptimalIndexType(), FixupMMXIntrinsicTypes(), foldADCToCINC(), foldAddSubBoolOfMaskedVal(), foldAddSubMasked1(), foldAddSubOfSignBit(), foldAndOrOfSETCC(), foldAndToUsubsat(), foldBinOpIntoSelectIfProfitable(), foldBitOrderCrossLogicOp(), FoldConstantArithmetic(), foldCSELOfCSEL(), foldCSELofCTTZ(), foldExtendedSignBitTest(), foldExtendVectorInregToExtendOfSubvector(), foldExtractSubvectorFromShuffleVector(), foldFPToIntToFP(), llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), foldIndexIntoBase(), FoldIntToFPToInt(), foldLogicOfShifts(), foldLogicTreeOfShifts(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedMergeImpl(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldOverflowCheck(), foldSelectOfConstantsUsingSra(), foldSelectOfCTTZOrCTLZ(), foldSelectWithIdentityConstant(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldShuffleOfConcatUndefs(), foldToSaturated(), foldVectorXorShiftIntoCmp(), foldVSelectToSignBitSplatMask(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::forceExpandWideMUL(), fpExtendHelper(), genConstMult(), generateComparison(), generateEquivalentSub(), GenerateFixedLengthSVETBL(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), getADAEntry(), llvm::MipsTargetLowering::getAddrGlobal(), llvm::MipsTargetLowering::getAddrGlobalLargeGOT(), llvm::MipsTargetLowering::getAddrGPRel(), llvm::MipsTargetLowering::getAddrLocal(), llvm::MipsTargetLowering::getAddrNonPIC(), llvm::MipsTargetLowering::getAddrNonPICSym64(), getAllOnesMask(), getAnyExtOrTrunc(), getAVX512Node(), getAVX512TruncNode(), getBitcast(), getBitSelect(), getBitTestCondition(), getBMIMatchingOp(), getBoolExtOrTrunc(), getBoundedStrlen(), getBT(), getBuildVector(), getBuildVectorSplat(), getCALLSEQ_END(), getCALLSEQ_START(), getCCResult(), getConstant(), getCopyFromParts(), getCopyFromPartsVector(), getCopyFromReg(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), getCopyToReg(), llvm::RegsForValue::getCopyToRegs(), getCSAddressAndShifts(), getDataClassTest(), getDeinterleaveViaVNSRL(), getDWordFromOffset(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getEstimate(), GetExponent(), getEXTEND_VECTOR_INREG(), getFlagsOfCmpZeroFori1(), getFLUSHW(), getFPBinOp(), getFPExtendOrRound(), getFPTernOp(), getFRAMEADDR(), getFreeze(), getGeneralPermuteNode(), getGLOBAL_OFFSET_TABLE(), llvm::AMDGPUTargetLowering::getHiHalf64(), getHopForBuildVector(), llvm::AMDGPUTargetLowering::getIsFinite(), getJumpTableDebugInfo(), getKnownUndefForVectorBinop(), getLimitedPrecisionExp2(), getLoadExtOrTrunc(), getLogicalNOT(), llvm::AMDGPUTargetLowering::getLoHalf64(), getMad(), getMad64_32(), llvm::VECustomDAG::getMaskBroadcast(), getMaskNode(), getMemBasePlusOffset(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), getMemsetStringVal(), getMemsetValue(), getMergeValues(), getMul24(), llvm::AMDGPUTargetLowering::getNegatedExpression(), llvm::X86TargetLowering::getNegatedExpression(), llvm::TargetLowering::getNegatedExpression(), llvm::PPCTargetLowering::getNegatedExpression(), getNegatedInteger(), getNegative(), llvm::EmptyMatchContext::getNode(), llvm::VECustomDAG::getNode(), getNode(), llvm::VPMatchContext::getNode(), getNOT(), llvm::VECustomDAG::getPack(), getPack(), getPermuteNode(), llvm::HexagonTargetLowering::getPICJumpTableRelocBase(), llvm::M68kTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::VETargetLowering::getPICJumpTableRelocBase(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), getPMOVMSKB(), getPTest(), getPTrue(), llvm::AMDGPUTargetLowering::getRecipEstimate(), getReductionSDNode(), getRegistersForValue(), getRVVFPReductionOpAndOperands(), getScalarMaskingNode(), llvm::AMDGPUTargetLowering::getScaledLogInput(), getScaledOffsetForBitWidth(), getSelect(), getSelectCC(), getSETCC(), getSetCC(), getSetCCVP(), getSExtOrTrunc(), getShuffleHalfVectors(), GetSignificand(), getSplatBuildVector(), getSplatValue(), getSplatVector(), llvm::NVPTXTargetLowering::getSqrtEstimate(), llvm::AMDGPUTargetLowering::getSqrtEstimate(), llvm::TargetLowering::getSqrtInputTest(), getStackArgumentTokenFactor(), getStepVector(), getSToVPermuted(), getStrictFPExtendOrRound(), getSVEPredicateBitCast(), getTargetVShiftByConstNode(), getTargetVShiftNode(), GetTLSADDR(), getTokenFactor(), getTruncatedUSUBSAT(), getUNDEF(), llvm::VECustomDAG::getUnpack(), getv64i1Argument(), getVAArg(), llvm::SelectionDAGBuilder::getValueImpl(), getVCIXISDNodeVOID(), getVCIXISDNodeWCHAIN(), getVectorBitwiseReduce(), getVectorMaskingNode(), getVectorShuffle(), llvm::TargetLowering::getVectorSubVecPointer(), getVPLogicalNOT(), getVPZeroExtendInReg(), getVPZExtOrTrunc(), getVScale(), getVShift(), getVSlidedown(), getVSlideup(), getWideningInterleave(), getX86XALUOOp(), getZeroExtendInReg(), getZeroVector(), getZExtOrTrunc(), getzOSCalleeAndADA(), handleCMSEValue(), HandleMergeInputChains(), llvm::TargetLowering::IncrementMemoryAddress(), initAccumulator(), insert1BitVector(), InsertBitToMaskVector(), insertSubVector(), isFNEG(), isFusableLoadOpStorePattern(), IsNOT(), isUpperSubvectorUndef(), joinDwords(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), Legalize(), legalizeIntrinsicImmArg(), legalizeScatterGatherIndexType(), llvm::TargetLowering::LegalizeSetCCCondCode(), legalizeSVEGatherPrefetchOffsVec(), llvm::AMDGPUTargetLowering::loadInputValue(), lower1BitShuffle(), lower1BitShuffleAsKSHIFTR(), LowerABD(), LowerABS(), lowerAddrSpaceCast(), LowerADDRSPACECAST(), LowerADDSAT_SUBSAT(), LowerADDSUBO_CARRY(), lowerADDSUBO_CARRY(), LowerADDSUBSAT(), lowerAddSubToHorizontalOp(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerAsSplatVectorLoad(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), llvm::HexagonTargetLowering::LowerATOMIC_FENCE(), llvm::VETargetLowering::lowerATOMIC_FENCE(), LowerATOMIC_FENCE(), LowerATOMIC_STORE(), llvm::VETargetLowering::lowerATOMIC_SWAP(), lowerAtomicArith(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), lowerBALLOTIntrinsic(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), llvm::HexagonTargetLowering::LowerBlockAddress(), llvm::LanaiTargetLowering::LowerBlockAddress(), llvm::MSP430TargetLowering::LowerBlockAddress(), llvm::LanaiTargetLowering::LowerBR_CC(), llvm::MSP430TargetLowering::LowerBR_CC(), LowerBR_CC(), LowerBRCOND(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTOR_i1(), LowerBUILD_VECTORToVIDUP(), LowerBUILD_VECTORvXbf16(), lowerBUILD_VECTORvXf16(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorOfConstants(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), lowerBuildVectorToBitOp(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::SITargetLowering::LowerCallResult(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), LowerCMP_SWAP(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), LowerCONCAT_VECTORSvXi1(), llvm::HexagonTargetLowering::LowerConstantPool(), llvm::LanaiTargetLowering::LowerConstantPool(), LowerConvertLow(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::lowerCTLZResults(), LowerCTPOP(), LowerCTTZ(), lowerCttzElts(), LowerCVTPS2PH(), llvm::SelectionDAGBuilder::LowerDeoptimizingReturn(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerDSPIntr(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::VETargetLowering::lowerEH_SJLJ_LONGJMP(), llvm::VETargetLowering::lowerEH_SJLJ_SETJMP(), llvm::VETargetLowering::lowerEH_SJLJ_SETUP_DISPATCH(), LowerEXTEND_VECTOR_INREG(), llvm::MSP430TargetLowering::LowerExternalSymbol(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_SUBVECTOR(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_i1(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::SparcTargetLowering::LowerF128Compare(), LowerF128Load(), LowerF128Store(), LowerF64Op(), LowerFABSorFNEG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), lowerFCMPIntrinsic(), LowerFCOPYSIGN(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFGETSIGN(), LowerFLDEXP(), llvm::AMDGPUTargetLowering::LowerFLOG2(), llvm::AMDGPUTargetLowering::LowerFLOGCommon(), llvm::AMDGPUTargetLowering::LowerFLOGUnsafe(), lowerFMAXIMUM_FMINIMUM(), LowerFMINIMUM_FMAXIMUM(), llvm::AMDGPUTargetLowering::LowerFNEARBYINT(), LowerFNEGorFABS(), llvm::SITargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFP16_TO_FP(), llvm::SITargetLowering::lowerFP_EXTEND(), LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), LowerFP_TO_INT_SAT(), lowerFP_TO_INT_SAT(), LowerFP_TO_SINT(), lowerFP_TO_SINT_STORE(), lowerFPToIntToFP(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerFREM(), llvm::AMDGPUTargetLowering::LowerFRINT(), LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), LowerFunnelShift(), llvm::SITargetLowering::lowerGET_FPENV(), llvm::SITargetLowering::lowerGET_ROUNDING(), lowerGetVectorLength(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::MSP430TargetLowering::LowerGlobalAddress(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), lowerGR128Binary(), lowerGR128ToI128(), LowerHorizontalByteSum(), lowerI128ToGR128(), LowerI64IntToFP16(), LowerI64IntToFP_AVX512DQ(), lowerICMPIntrinsic(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), LowerINSERT_VECTOR_ELT_i1(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), lowerINT_TO_FP_vXi64(), LowerInterruptReturn(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN(), llvm::HexagonTargetLowering::LowerJumpTable(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::MSP430TargetLowering::LowerJumpTable(), LowerLabelRef(), lowerLaneOp(), LowerLoad(), llvm::MipsTargetLowering::lowerLOAD(), lowerLoadF128(), lowerLoadI1(), lowerMasksToReg(), LowerMemOpCallTo(), LowerMGATHER(), LowerMLOAD(), lowerMSABinaryBitImmIntr(), lowerMSABitClear(), lowerMSABitClearImm(), lowerMSACopyIntr(), lowerMSALoadIntr(), lowerMSASplatZExt(), lowerMSAStoreIntr(), LowerMSCATTER(), LowerMUL(), llvm::LanaiTargetLowering::LowerMUL(), lowerMUL_LOHI32(), LowerMULH(), LowerMULO(), llvm::AArch64TargetLowering::LowerOperation(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), lowerOverflowArithmetic(), LowerPARITY(), LowerPredicateLoad(), LowerPredicateStore(), LowerPREFETCH(), llvm::HexagonTargetLowering::LowerPREFETCH(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::HexagonTargetLowering::LowerREADCYCLECOUNTER(), llvm::HexagonTargetLowering::LowerREADSTEADYCOUNTER(), lowerReductionSeq(), lowerRegToMasks(), llvm::AMDGPUTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), lowerRETURNADDR(), LowerReverse_VECTOR_SHUFFLE(), LowerRotate(), LowerSaturatingConditional(), LowerSCALAR_TO_VECTOR(), lowerScalarInsert(), lowerScalarSplat(), LowerSDIV(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::SITargetLowering::lowerSET_FPENV(), llvm::SITargetLowering::lowerSET_ROUNDING(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), llvm::MSP430TargetLowering::LowerShifts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), lowerShuffleAsBitMask(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsInsertPS(), lowerShuffleAsLanePermuteAndSHUFP(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsTruncBroadcast(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShufflePairAsUNPCKAndPermute(), lowerShuffleToEXPAND(), lowerShuffleViaVRegSplitting(), lowerShuffleWithPACK(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithSHUFPD(), lowerShuffleWithSHUFPS(), lowerShuffleWithSSE4A(), lowerShuffleWithUndefHalf(), lowerShuffleWithUNPCK(), lowerShuffleWithUNPCK256(), LowerSIGN_EXTEND(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerSIGN_EXTEND_Mask(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerSINT_TO_FP(), LowerSMELdrStr(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::SITargetLowering::LowerSTACKSAVE(), LowerStore(), LowerSTORE(), lowerStoreF128(), lowerStoreI1(), LowerSVEIntrinsicDUP(), LowerSVEIntrinsicEXT(), LowerSVEIntrinsicIndex(), lowerToAddSubOrFMAddSub(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerToTLSLocalDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerTruncate(), LowerTruncatei1(), LowerTruncateVecI1(), LowerTruncateVecPack(), LowerTruncateVectorStore(), llvm::HexagonTargetLowering::LowerUAddSubO(), LowerUADDSUBO_CARRY(), llvm::HexagonTargetLowering::LowerUAddSubOCarry(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerUnalignedLoadRetParam(), LowerUnalignedStoreParam(), LowerUnalignedStoreRet(), lowerV16F32Shuffle(), lowerV16I32Shuffle(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2I64Shuffle(), lowerV2X128Shuffle(), lowerV4F32Shuffle(), lowerV4F64Shuffle(), lowerV4I32Shuffle(), lowerV4I64Shuffle(), lowerV4X128Shuffle(), lowerV8F32Shuffle(), lowerV8F64Shuffle(), lowerV8I16GeneralSingleInputShuffle(), lowerV8I16Shuffle(), lowerV8I32Shuffle(), lowerV8I64Shuffle(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), LowerVASTART(), LowerVecReduce(), LowerVecReduceMinMax(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), lowerVECTOR_SHUFFLE_ILVEV(), lowerVECTOR_SHUFFLE_ILVL(), lowerVECTOR_SHUFFLE_ILVOD(), lowerVECTOR_SHUFFLE_ILVR(), lowerVECTOR_SHUFFLE_PCKEV(), lowerVECTOR_SHUFFLE_PCKOD(), lowerVECTOR_SHUFFLE_SHF(), lowerVECTOR_SHUFFLE_VILVH(), lowerVECTOR_SHUFFLE_VILVL(), lowerVECTOR_SHUFFLE_VPACKEV(), lowerVECTOR_SHUFFLE_VPACKOD(), lowerVECTOR_SHUFFLE_VPICKEV(), lowerVECTOR_SHUFFLE_VPICKOD(), lowerVECTOR_SHUFFLE_VREPLVEI(), lowerVECTOR_SHUFFLE_VSHF(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_VSHUF4I(), lowerVECTOR_SHUFFLE_XVILVH(), lowerVECTOR_SHUFFLE_XVILVL(), lowerVECTOR_SHUFFLE_XVPICKEV(), lowerVECTOR_SHUFFLE_XVPICKOD(), lowerVECTOR_SHUFFLE_XVREPLVEI(), lowerVECTOR_SHUFFLE_XVSHUF(), lowerVECTOR_SHUFFLEAsRotate(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorAllEqual(), LowerVectorArith(), lowerVectorBitClear(), lowerVectorBitClearImm(), lowerVectorBitRevImm(), lowerVectorBitSetImm(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), LowerVectorExtend(), LowerVectorFP_TO_INT(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), LowerVectorINT_TO_FP(), lowerVectorIntrinsicScalars(), lowerVectorSplatImm(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowervXi8MulWithUNPCK(), LowerWRITE_REGISTER(), lowerX86CmpEqZeroToCtlzSrl(), lowerX86FPLogicOp(), LowerXALUO(), LowerZERO_EXTEND_Mask(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), makeEquivalentMemoryOrdering(), llvm::SparcTargetLowering::makeHiLoPair(), llvm::VETargetLowering::makeHiLoPair(), matchBinOpReduction(), matchBSwapHWordOrAndAnd(), llvm::AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(), matchPERM(), matchPMADDWD(), matchPMADDWD_2(), matchSplatAsGather(), matchTruncateWithPACK(), MatchVectorAllEqualTest(), moveBelowOrigChain(), narrowExtractedVectorBinOp(), narrowIndex(), narrowInsertExtractVectorBinOp(), narrowVectorSelect(), optimizeLogicalImm(), overflowFlagToValue(), packImage16bitOpsToDwords(), partitionShuffleOfConcats(), llvm::SITargetLowering::passSpecialInputs(), performADDCombine(), performAddCombineForShiftedOperands(), performAddCombineSubShift(), PerformADDCombineWithOperands(), performAddCSelIntoCSinc(), PerformAddcSubcCombine(), performAddDotCombine(), PerformAddeSubeCombine(), performAddSubIntoVectorOp(), performAddSubLongCombine(), performAddUADDVCombine(), PerformADDVecReduce(), performANDCombine(), PerformANDCombine(), performANDORCSELCombine(), performANDSETCCCombine(), PerformARMBUILD_VECTORCombine(), llvm::AMDGPUTargetLowering::performAssertSZExtCombine(), PerformBFICombine(), performBitcastCombine(), PerformBITCASTCombine(), performBITREV_WCombine(), performBITREVERSECombine(), llvm::ARMTargetLowering::PerformBRCONDCombine(), performBRCONDCombine(), performBSPExpandForSVE(), performBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), performBuildShuffleExtendCombine(), performBuildVectorCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCMovFPCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performConcatVectorsCombine(), performCONDCombine(), PerformCSETCombine(), performCTLZCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDivRemCombine(), performDSPShiftCombine(), performDUPCombine(), performDupLane128Combine(), performExtBinopLoadFold(), PerformExtendCombine(), performExtendCombine(), PerformEXTRACTCombine(), PerformExtractEltCombine(), PerformExtractEltToVMOVRRD(), performExtractSubvectorCombine(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFADDCombine(), PerformFADDCombineWithOperands(), PerformFADDVCMLACombine(), PerformFAddVSelectCombine(), performFlagSettingCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), performFPExtendCombine(), performFpToIntCombine(), performGatherLoadCombine(), performGLD1Combine(), performGlobalAddressCombine(), PerformHWLoopCombine(), performINSERT_VECTOR_ELTCombine(), PerformInsertEltCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), performINTRINSIC_WO_CHAINCombine(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), performIntrinsicCombine(), performIntToFpCombine(), performLD1Combine(), performLD1ReplicateCombine(), performLDNT1Combine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performLOADCombine(), PerformLongShiftCombine(), performMADD_MSUBCombine(), PerformMinMaxCombine(), PerformMinMaxFpToSatCombine(), PerformMinMaxToSatCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), performMulCombine(), performMULCombine(), PerformMULCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), llvm::AMDGPUTargetLowering::performMulLoHiCombine(), performMulVectorCmpZeroCombine(), performMulVectorExtendCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), PerformMVEVMULLCombine(), performNegCSelCombine(), performNVCASTCombine(), performORCombine(), PerformORCombine(), PerformORCombine_i1(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), performOrXorChainCombine(), PerformPREDICATE_CASTCombine(), PerformReduceShuffleCombine(), PerformREMCombine(), performScalarToVectorCombine(), performScatterStoreCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), performSelectCombine(), PerformSELECTCombine(), performSetccAddFolding(), performSETCCCombine(), PerformSETCCCombine(), performSetccMergeZeroCombine(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), performSHLCombine(), PerformSHLSimplify(), PerformShuffleVMOVNCombine(), performSIGN_EXTEND_INREGCombine(), PerformSignExtendInregCombine(), performSignExtendInRegCombine(), performSignExtendSetCCCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performSraCombine(), performSRACombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performSRLCombine(), performST1Combine(), performSTNT1Combine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), performSubAddMULCombine(), performSUBCombine(), PerformSUBCombine(), PerformSubCSINCCombine(), performSubsToAndsCombine(), performSunpkloCombine(), performSVEAndCombine(), performSVEMulAddSubCombine(), performTBZCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), performTruncateCombine(), performTRUNCATECombine(), PerformTruncatingStoreCombine(), performUADDVAddCombine(), performUADDVCombine(), performUADDVZextCombine(), PerformUMinFpToSatCombine(), PerformUMLALCombine(), performUzpCombine(), PerformVCMPCombine(), PerformVCVTCombine(), PerformVDUPCombine(), PerformVDUPLANECombine(), PerformVECREDUCE_ADDCombine(), performVecReduceAddCombine(), performVecReduceAddCombineWithUADDLP(), PerformVECTOR_REG_CASTCombine(), PerformVECTOR_SHUFFLECombine(), performVectorCompareAndMaskUnaryOpCombine(), performVectorExtCombine(), performVectorExtendCombine(), performVectorExtendToFPCombine(), performVectorTruncZeroCombine(), PerformVMOVDRRCombine(), PerformVMOVhrCombine(), PerformVMOVNCombine(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), PerformVMULCombine(), PerformVMulVCTPCombine(), PerformVQDMULHCombine(), performVSelectCombine(), performVSELECTCombine(), PerformVSELECTCombine(), PerformVSetCCToVCTPCombine(), performXORCombine(), PerformXORCombine(), prepareDescriptorIndirectCall(), prepareIndirectCall(), PrepareTailCall(), prepareTS1AM(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), promoteExtBeforeAdd(), PromoteMaskArithmetic(), PromoteMVEPredVector(), llvm::TargetLoweringBase::promoteTargetBoolean(), promoteToConstantPool(), promoteVCIXScalar(), promoteXINT_TO_FP(), pushAddIntoCmovOfConsts(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), ReconstructTruncateFromBuildVector(), recoverFramePointer(), reduceMaskedLoadToScalarLoad(), reduceMaskedStoreToScalarStore(), reduceVMULWidth(), refineUniformBase(), ReorganizeVector(), ReplaceAddWithADDP(), ReplaceAllUsesWith(), ReplaceATOMIC_LOAD_128Results(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), ReplaceCopyFromReg_128(), replaceInChain(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), ReplaceLongIntrinsic(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), ReplaceReductionResults(), replaceShuffleOfInsert(), replaceVecCondBranchResults(), replaceVPICKVE2GRResults(), resolveSources(), SaturateWidenedDIVFIX(), scalarizeBinOpOfSplats(), scalarizeExtEltFP(), scalarizeExtractedBinop(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), scalarizeVectorStore(), llvm::HexagonDAGToDAGISel::SelectIntrinsicWOChain(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), signExtendBitcastSrcVector(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyMul24(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), splatPartsI64WithVL(), llvm::AMDGPUTargetLowering::split64BitValue(), SplitAndExtendv16i1(), splitAndLowerShuffle(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), llvm::SITargetLowering::splitBinaryVectorOp(), SplitEVL(), splitIntVSETCC(), SplitOpsAndApply(), SplitScalar(), splitStores(), splitStoreSplat(), SplitStrictFPVectorOp(), llvm::SITargetLowering::splitTernaryVectorOp(), llvm::SITargetLowering::splitUnaryVectorOp(), llvm::PPCTargetLowering::splitValueIntoRegisterParts(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::AMDGPUTargetLowering::splitVector(), SplitVector(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), SplitVectorOp(), splitVectorOp(), SplitVectorReductionOp(), llvm::AMDGPUTargetLowering::SplitVectorStore(), splitVectorStore(), SplitVPOp(), llvm::AMDGPUTargetLowering::storeStackInputValue(), stripModuloOnShift(), takeInexpensiveLog2(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::RISCVTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), transformAddImmMulImm(), transformAddShlImm(), translateSetCCForBranch(), truncateAVX512SetCCNoBWI(), truncateScalarIntegerArg(), truncateVecElts(), truncateVectorWithNARROW(), truncateVectorWithPACK(), truncateVectorWithPACKSS(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), TryCombineBaseUpdate(), tryCombineCRC32(), tryCombineExtendRShTrunc(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), tryCombineMULLWithUZP1(), tryCombineShiftImm(), tryCombineToBSL(), tryCombineWhileLo(), tryConvertSVEWideCompare(), tryDemorganOfBooleanCondition(), TryDistrubutionADDVecReduce(), tryExtendDUPToExtractHigh(), tryFoldSelectIntoOp(), tryFormConcatFromShuffle(), tryLowerToSLI(), TryMULWIDECombine(), trySimplifySrlAddToRshrnb(), trySwapVSelectOperands(), tryToConvertShuffleOfTbl2ToTbl4(), tryToFoldExtendOfConstant(), tryToFoldExtendSelectLoad(), tryToFoldExtOfAtomicLoad(), tryToFoldExtOfLoad(), tryToFoldExtOfMaskedLoad(), tryToWidenSetCCOperands(), tryWhileWRFromOR(), unpack64(), unpackF64OnRV32DSoftABI(), UnpackFromArgumentSlot(), UnrollVectorOp(), UnrollVectorOverflowOp(), unrollVectorShift(), valueToCarryFlag(), vectorizeExtractedCast(), vectorToScalarBitmask(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), visitORCommutative(), llvm::SelectionDAGBuilder::visitSPDescriptorFailure(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), widenAbs(), widenCtPop(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), widenSubVector(), widenVec(), WidenVector(), WidenVector(), widenVectorOpsToi8(), widenVectorToPartType(), and WinDBZCheckDenominator().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 10062 of file SelectionDAG.cpp.
References DL, llvm::SelectionDAG::FlagInserter::getFlags(), and getNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
ArrayRef< SDValue > | Ops, | ||
const SDNodeFlags | Flags | ||
) |
Definition at line 10070 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::ISD::BR_CC, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::DELETED_NODE, DL, FoldBUILD_VECTOR(), foldCONCAT_VECTORS(), getNode(), getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), getVTList(), llvm::EVT::isVector(), N, NewSDValueDbgMsg(), llvm::ISD::SELECT_CC, and llvm::ArrayRef< T >::size().
Definition at line 6886 of file SelectionDAG.cpp.
References DL, llvm::SelectionDAG::FlagInserter::getFlags(), and getNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
const SDNodeFlags | Flags | ||
) |
Definition at line 6915 of file SelectionDAG.cpp.
References llvm::ISD::ABDS, llvm::ISD::ABDU, llvm::ISD::ADD, AddNodeIDNode(), llvm::ISD::AND, llvm::APInt::ashrInPlace(), assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::EVT::bitsLE(), llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, canonicalizeCommutativeBinop(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::DELETED_NODE, DL, llvm::ISD::EntryToken, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::ISD::FADD, llvm::ISD::FCOPYSIGN, llvm::ISD::FDIV, llvm::ISD::FMUL, FoldBUILD_VECTOR(), foldCONCAT_VECTORS(), FoldConstantArithmetic(), llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT_SAT, llvm::ISD::FP_TO_UINT_SAT, llvm::ISD::FREM, llvm::ISD::FSUB, getAllOnesConstant(), getAnyExtOrTrunc(), llvm::APInt::getBitWidth(), getBuildVector(), getConstant(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDNode::getConstantOperandAPInt(), getDataLayout(), getFPExtendOrRound(), llvm::SDValue::getNode(), getNode(), getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), getSExtOrTrunc(), llvm::EVT::getSizeInBits(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), getVectorIdxConstant(), llvm::TargetLoweringBase::getVectorIdxTy(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::getVectorNumElements(), getVScale(), getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ConstantSDNode::isAllOnes(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::TargetLoweringBase::isCommutativeBinOp(), llvm::isConstOrConstSplat(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::ConstantSDNode::isZero(), llvm::Log2_32_Ceil(), llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, N, NewSDValueDbgMsg(), llvm::ISD::OR, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDSAT, llvm::ISD::SCMP, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, simplifyFPBinop(), simplifyShift(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SSUBSAT, llvm::ISD::SUB, std::swap(), llvm::ISD::TokenFactor, llvm::ISD::UADDSAT, llvm::ISD::UCMP, llvm::ISD::UDIV, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UREM, llvm::ISD::USUBSAT, llvm::ISD::VSCALE, and llvm::ISD::XOR.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3 | ||
) |
Definition at line 7430 of file SelectionDAG.cpp.
References DL, llvm::SelectionDAG::FlagInserter::getFlags(), and getNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
const SDNodeFlags | Flags | ||
) |
Definition at line 7438 of file SelectionDAG.cpp.
References llvm::APFloat::add(), AddNodeIDNode(), assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::DELETED_NODE, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FMA, llvm::ISD::FMAD, FoldBUILD_VECTOR(), foldCONCAT_VECTORS(), FoldConstantArithmetic(), FoldSetCC(), llvm::APFloat::fusedMultiplyAdd(), llvm::get(), llvm::SDNode::getAsAPIntVal(), llvm::SDNode::getAsZExtVal(), llvm::APInt::getBitWidth(), getConstantFP(), getDataLayout(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getUNDEF(), llvm::ConstantFPSDNode::getValueAPF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::TargetLoweringBase::getVectorIdxTy(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::getVectorNumElements(), getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::isFixedLengthVector(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), isZero(), llvm_unreachable, llvm::APFloat::multiply(), N, NewSDValueDbgMsg(), llvm::APFloatBase::rmNearestTiesToEven, llvm::ISD::SELECT, llvm::ISD::SETCC, simplifySelect(), llvm::ISD::VECTOR_COMPRESS, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VECTOR_SPLICE, and llvm::ISD::VSELECT.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4 | ||
) |
Definition at line 7635 of file SelectionDAG.cpp.
References DL, llvm::SelectionDAG::FlagInserter::getFlags(), and getNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4, | ||
const SDNodeFlags | Flags | ||
) |
Definition at line 7628 of file SelectionDAG.cpp.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4, | ||
SDValue | N5 | ||
) |
Definition at line 7650 of file SelectionDAG.cpp.
References DL, llvm::SelectionDAG::FlagInserter::getFlags(), and getNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4, | ||
SDValue | N5, | ||
const SDNodeFlags | Flags | ||
) |
Definition at line 7643 of file SelectionDAG.cpp.
Definition at line 5916 of file SelectionDAG.cpp.
References DL, llvm::SelectionDAG::FlagInserter::getFlags(), and getNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | Operand, | ||
const SDNodeFlags | Flags | ||
) |
Definition at line 5924 of file SelectionDAG.cpp.
References llvm::ISD::ABS, AddNodeIDNode(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, assert(), llvm::ISD::BF16_TO_FP, llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::EVT::bitsGT(), llvm::EVT::bitsLE(), llvm::EVT::bitsLT(), llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::ISD::DELETED_NODE, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FNEG, FoldBUILD_VECTOR(), FoldConstantArithmetic(), llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_BF16, llvm::ISD::FP_TO_FP16, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FREEZE, llvm::ISD::FTRUNC, llvm::APInt::getBitsSetFrom(), getConstant(), getConstantFP(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDValue::getConstantOperandVal(), llvm::SDNode::getFlags(), llvm::SDValue::getNode(), getNode(), getNOT(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::EVT::getSizeInBits(), getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), getVScale(), getVTList(), llvm::SDNodeFlags::hasNonNeg(), llvm::EVT::isFloatingPoint(), isGuaranteedNotToBeUndefOrPoison(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm_unreachable, MaskedValueIsZero(), llvm::ISD::MERGE_VALUES, N, NewNodesMustHaveLegalTypes, NewSDValueDbgMsg(), llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SPLAT_VECTOR, llvm::ISD::STEP_VECTOR, llvm::ISD::TargetConstant, llvm::ISD::TokenFactor, transferDbgValues(), llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, llvm::ISD::UNDEF, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ISD::VECREDUCE_XOR, llvm::ISD::VSCALE, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.
Definition at line 10387 of file SelectionDAG.cpp.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 10187 of file SelectionDAG.cpp.
References DL, llvm::SelectionDAG::FlagInserter::getFlags(), and getNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops, | ||
const SDNodeFlags | Flags | ||
) |
Definition at line 10195 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::ISD::AND, assert(), llvm::EVT::bitsLT(), llvm::CallingConv::C, canonicalizeCommutativeBinop(), llvm::ISD::DELETED_NODE, DL, llvm::APInt::extractBits(), llvm::ISD::FFREXP, llvm::frexp(), getConstant(), getConstantFP(), getFreeze(), getNode(), getNOT(), llvm::EVT::getScalarSizeInBits(), getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::Hi, llvm::isConstOrConstSplat(), llvm::APFloat::isFinite(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isVector(), llvm::ConstantSDNode::isZero(), LHS, llvm::Lo, llvm::ISD::MERGE_VALUES, llvm::Mul, N, NewSDValueDbgMsg(), llvm::SDVTList::NumVTs, RHS, llvm::APFloatBase::rmNearestTiesToEven, llvm::ISD::SADDO, llvm::ISD::SADDO_CARRY, llvm::APInt::sext(), llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND_INREG, llvm::ArrayRef< T >::size(), llvm::ISD::SMUL_LOHI, llvm::ISD::SRA_PARTS, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SSUBO_CARRY, llvm::ISD::STRICT_FP_EXTEND, llvm::ISD::STRICT_FP_ROUND, llvm::APInt::trunc(), llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::UMUL_LOHI, llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::SDVTList::VTs, llvm::ISD::XOR, and llvm::APInt::zext().
Definition at line 10392 of file SelectionDAG.cpp.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
SDVTList | VTList, | ||
SDValue | N1, | ||
SDValue | N2 | ||
) |
Definition at line 10398 of file SelectionDAG.cpp.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
SDVTList | VTList, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3 | ||
) |
Definition at line 10404 of file SelectionDAG.cpp.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
SDVTList | VTList, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4 | ||
) |
Definition at line 10410 of file SelectionDAG.cpp.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
SDVTList | VTList, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4, | ||
SDValue | N5 | ||
) |
Definition at line 10416 of file SelectionDAG.cpp.
SDNode * SelectionDAG::getNodeIfExists | ( | unsigned | Opcode, |
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops | ||
) |
getNodeIfExists - Get the specified node if it's already available, or else return NULL.
Definition at line 10999 of file SelectionDAG.cpp.
References llvm::SelectionDAG::FlagInserter::getFlags(), and getNodeIfExists().
SDNode * SelectionDAG::getNodeIfExists | ( | unsigned | Opcode, |
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops, | ||
const SDNodeFlags | Flags | ||
) |
Get the specified node if it's already available, or else return NULL.
Definition at line 11007 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::SDVTList::NumVTs, and llvm::SDVTList::VTs.
Referenced by combineBitcastToBoolVector(), combineSetCC(), combineX86AddSub(), getInvertedVectorForFMA(), getNodeIfExists(), performDUPCombine(), PerformExtractFpToIntStores(), performFlagSettingCombine(), and tryToWidenSetCCOperands().
Return NoMerge info associated with Node.
Definition at line 2359 of file SelectionDAG.h.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), and I.
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
Create a bitwise NOT operation as (XOR Val, -1).
getNOT - Create a bitwise NOT operation as (XOR Val, -1).
Definition at line 1580 of file SelectionDAG.cpp.
References DL, getAllOnesConstant(), getNode(), and llvm::ISD::XOR.
Referenced by combineAndnp(), combineMOVMSK(), combineSelect(), combineSelectOfTwoConstants(), combineSetCC(), combineSub(), combineVectorPack(), combineVSelectWithAllOnesOrZeros(), combineXor(), EmitVectorComparison(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTTZ(), llvm::TargetLowering::expandFunnelShift(), foldAndOrOfSETCC(), foldExtendedSignBitTest(), foldVSelectToSignBitSplatMask(), llvm::VECustomDAG::getConstantMask(), getDataClassTest(), getNode(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), lowerMSABitClear(), LowerVectorAllEqual(), lowerVectorBitClear(), LowerVSETCC(), performBSPExpandForSVE(), performConcatVectorsCombine(), performINTRINSIC_WO_CHAINCombine(), performSETCCCombine(), performXORCombine(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), and visitORCommutative().
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Definition at line 1072 of file SelectionDAG.h.
References getMemBasePlusOffset(), llvm::Offset, and Ptr.
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Create an add instruction with appropriate flags when used for addressing some offset of an object.
i.e. if a load is split into multiple components, create an add nuw from the base pointer to the offset.
Definition at line 1066 of file SelectionDAG.h.
References getMemBasePlusOffset(), llvm::Offset, and Ptr.
Referenced by llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::TargetLowering::SimplifySetCC(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), and llvm::AMDGPUTargetLowering::SplitVectorStore().
Convert *_EXTEND_VECTOR_INREG to *_EXTEND opcode.
Definition at line 922 of file SelectionDAG.h.
References llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm_unreachable, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.
Referenced by combineEXTEND_VECTOR_INREG(), and foldExtendVectorInregToExtendOfSubvector().
Convert *_EXTEND to *_EXTEND_VECTOR_INREG opcode.
Definition at line 938 of file SelectionDAG.h.
References llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm_unreachable, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.
Referenced by combineEXTRACT_SUBVECTOR(), getEXTEND_VECTOR_INREG(), LowerAVXExtend(), and matchUnaryShuffle().
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Definition at line 486 of file SelectionDAG.h.
Referenced by llvm::FunctionLoweringInfo::set().
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Definition at line 501 of file SelectionDAG.h.
Definition at line 483 of file SelectionDAG.h.
Referenced by llvm::SITargetLowering::LowerFormalArguments(), and llvm::SITargetLowering::passSpecialInputs().
Return PCSections associated with Node, or nullptr if none exists.
Definition at line 2343 of file SelectionDAG.h.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), and llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find().
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
SDValue SelectionDAG::getPseudoProbeNode | ( | const SDLoc & | Dl, |
SDValue | Chain, | ||
uint64_t | Guid, | ||
uint64_t | Index, | ||
uint32_t | Attr | ||
) |
Creates a PseudoProbeSDNode with function GUID Guid
and the index of the block Index
it is probing, as well as the attributes attr
of the probe.
Definition at line 8852 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), llvm::Guid, N, NewSDValueDbgMsg(), and llvm::ISD::PSEUDO_PROBE.
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Definition at line 502 of file SelectionDAG.h.
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy value.
This may be either a zero extend or a sign extend.
Definition at line 1569 of file SelectionDAG.cpp.
References DL, and getZeroExtendInReg().
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or performing either zero or sign extension as appropriate extension for the pointer's semantics.
Definition at line 1563 of file SelectionDAG.cpp.
References DL, and getZExtOrTrunc().
Referenced by getLoadStackGuard(), and llvm::SelectionDAGBuilder::visitSwitchCase().
In most cases this function returns the ABI alignment for a given type, except for illegal vector types where the alignment exceeds that of the stack.
In such cases we attempt to break the vector down to a legal type and return the ABI alignment for that instead.
Definition at line 2477 of file SelectionDAG.cpp.
References DL, getContext(), getDataLayout(), llvm::TargetSubtargetInfo::getFrameLowering(), getMachineFunction(), llvm::TargetFrameLowering::getStackAlign(), llvm::MachineFunction::getSubtarget(), llvm::EVT::getTypeForEVT(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::TargetLoweringBase::isTypeLegal(), and llvm::EVT::isVector().
Referenced by llvm::TargetLowering::expandVECTOR_COMPRESS(), and llvm::TargetLowering::expandVectorSplice().
Definition at line 2281 of file SelectionDAG.cpp.
References AddNodeIDNode(), getVTList(), llvm::TargetLowering::isSDNodeSourceOfDivergence(), N, and llvm::ISD::Register.
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(), buildCallOperands(), createCMovFP(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), emitLockedStackOp(), EmitUnrolledSetTag(), extractPtrauthBlendDiscriminators(), getADAEntry(), llvm::MipsTargetLowering::getAddrGPRel(), getCopyFromReg(), getCopyToReg(), getDefaultScalableVLOps(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), llvm::MipsTargetLowering::getGlobalReg(), llvm::MipsTargetLowering::getOpndList(), getPrefetchNode(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::LanaiTargetLowering::LowerConstantPool(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), LowerMemOpCallTo(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerSETCCCARRY(), llvm::VETargetLowering::lowerVASTART(), LowerVASTART(), lowerVECTOR_SHUFFLE(), lowerVectorIntrinsicScalars(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), llvm::SITargetLowering::PostISelFolding(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVDAGToDAGISel::Select(), llvm::LoongArchDAGToDAGISel::SelectAddrConstant(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegImm34(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale(), llvm::SelectionDAGISel::SelectCodeCommon(), selectConstantAddr(), llvm::PPCTargetLowering::SelectForceXFormMode(), selectImmSeq(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), llvm::RISCVDAGToDAGISel::selectShiftMask(), selectSOffset(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), and splatPartsI64WithVL().
Definition at line 2297 of file SelectionDAG.cpp.
References AddNodeIDNode(), getVTList(), N, and llvm::ISD::RegisterMask.
Referenced by buildCallOperands(), llvm::AArch64TargetLowering::changeStreamingMode(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), llvm::MipsTargetLowering::getOpndList(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), and llvm::VETargetLowering::lowerToTLSGeneralDynamicModel().
Return the root tag of the SelectionDAG.
Definition at line 567 of file SelectionDAG.h.
Referenced by llvm::checkForCycles(), dump(), llvm::ScheduleDAGSDNodes::getCustomGraphFeatures(), getMemCmpLoad(), Legalize(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), llvm::SelectionDAGBuilder::LowerDeoptimizingReturn(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::RISCVDAGToDAGISel::PostprocessISelDAG(), RemoveDeadNode(), RemoveDeadNodes(), ReplaceAllUsesOfValueWith(), ReplaceAllUsesWith(), and llvm::DAGTypeLegalizer::run().
SDValue SelectionDAG::getScatterVP | ( | SDVTList | VTs, |
EVT | VT, | ||
const SDLoc & | dl, | ||
ArrayRef< SDValue > | Ops, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexType | IndexType | ||
) |
Definition at line 9620 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::details::FixedOrScalableQuantity< ElementCount, unsigned >::isKnownGE(), N, NewSDValueDbgMsg(), and llvm::ArrayRef< T >::size().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
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Helper function to make it easier to build Select's if you just have operands and don't want to check for vector.
Definition at line 1267 of file SelectionDAG.h.
References assert(), Cond, DL, getNode(), LHS, RHS, llvm::ISD::SELECT, and llvm::ISD::VSELECT.
Referenced by llvm::TargetLowering::BuildUDIV(), combineConcatVectorOps(), combineFMinNumFMaxNum(), combineLogicBlendIntoPBLENDV(), combineMaskedLoadConstantMask(), combineSelect(), commuteSelect(), llvm::TargetLowering::CTTZTableLookup(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTTZ(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandVECTOR_COMPRESS(), foldBinOpIntoSelectIfProfitable(), foldSelectWithIdentityConstant(), llvm::TargetLowering::getNegatedExpression(), LowerADDSAT_SUBSAT(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerCttzElts(), lowerFMAXIMUM_FMINIMUM(), LowerFMINIMUM_FMAXIMUM(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), lowerINT_TO_FP_vXi64(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), LowerShift(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), lowerShuffleAsBlend(), LowerSIGN_EXTEND_Mask(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerZERO_EXTEND_Mask(), narrowExtractedVectorSelect(), PerformADDCombineWithOperands(), performSelectCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), signExtendBitcastSrcVector(), takeInexpensiveLog2(), tryFoldSelectIntoOp(), tryToFoldExtendOfConstant(), tryToFoldExtendSelectLoad(), UnrollVectorOverflowOp(), and useInversedSetcc().
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Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an SDValue.
Definition at line 1277 of file SelectionDAG.h.
References Cond, DL, getCondCode(), getNode(), llvm::SDValue::getValueType(), LHS, RHS, and llvm::ISD::SELECT_CC.
Referenced by llvm::TargetLowering::createSelectForFMINNUM_FMAXNUM(), createVariablePermute(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandMUL_LOHI(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), lowerFP_TO_INT_SAT(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::R600TargetLowering::PerformDAGCombine(), and performFP_TO_INT_SATCombine().
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Definition at line 495 of file SelectionDAG.h.
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Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SDValue.
Definition at line 1238 of file SelectionDAG.h.
References assert(), Cond, DL, getCondCode(), getNode(), llvm::EVT::isVector(), LHS, RHS, llvm::ISD::SETCC, llvm::ISD::SETCC_INVALID, llvm::ISD::STRICT_FSETCC, and llvm::ISD::STRICT_FSETCCS.
Referenced by llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), combineAnd(), combineBitcast(), combineExtractVectorElt(), combineExtSetcc(), combineFMinNumFMaxNum(), combineOr(), combinePredicateReduction(), combineSelect(), combineSetCC(), combineShiftAnd1ToBitTest(), combineSubOfBoolean(), combineToExtendBoolVectorInReg(), combineVectorSizedSetCCEquality(), combineVSelectWithAllOnesOrZeros(), commuteSelect(), convertIntLogicToFPLogic(), llvm::TargetLowering::CTTZTableLookup(), emitOrXorXorTree(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTTZ(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandVECTOR_COMPRESS(), foldAndOrOfSETCC(), FoldSetCC(), foldSetCCWithFunnelShift(), foldSetCCWithRotate(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), getDataClassTest(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), llvm::VECustomDAG::getMaskBroadcast(), llvm::AMDGPUTargetLowering::getScaledLogInput(), llvm::TargetLowering::getSqrtInputTest(), llvm::TargetLowering::LegalizeSetCCCondCode(), lower1BitShuffle(), LowerADDSAT_SUBSAT(), lowerBUILD_VECTOR(), lowerCttzElts(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), LowerEXTEND_VECTOR_INREG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), lowerFMAXIMUM_FMINIMUM(), LowerFMINIMUM_FMAXIMUM(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::SITargetLowering::lowerGET_ROUNDING(), lowerINT_TO_FP_vXi64(), LowerIntVSETCC_AVX512(), LowerMULH(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftByScalarImmediate(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUAddSubO(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), lowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), LowerVectorCTLZInRegLUT(), LowerVSETCC(), llvm::RISCVTargetLowering::PerformDAGCombine(), performOrXorChainCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), performSETCCCombine(), performSignExtendSetCCCombine(), performVSelectCombine(), performXORCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), llvm::TargetLowering::softenSetCCOperands(), truncateAVX512SetCCNoBWI(), tryDemorganOfBooleanCondition(), trySwapVSelectOperands(), useInversedSetcc(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), and widenVectorOpsToi8().
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Helper function to make it easier to build VP_SETCCs if you just have an ISD::CondCode instead of an SDValue.
Definition at line 1255 of file SelectionDAG.h.
References assert(), Cond, DL, getCondCode(), getNode(), LHS, RHS, and llvm::ISD::SETCC_INVALID.
Referenced by llvm::TargetLowering::LegalizeSetCCCondCode().
SDValue SelectionDAG::getSetFPEnv | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Ptr, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 9917 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::SDValue::getValueType(), getVTList(), N, NewSDValueDbgMsg(), Ptr, and llvm::ISD::SET_FPENV_MEM.
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or truncating it.
Definition at line 1460 of file SelectionDAG.cpp.
References llvm::EVT::bitsGT(), DL, getNode(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::TRUNCATE.
Referenced by combineGatherScatter(), combineShuffleOfScalars(), combineToExtendBoolVectorInReg(), createVPDPBUSD(), llvm::TargetLowering::CTTZTableLookup(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandFP_TO_SINT(), foldCONCAT_VECTORS(), getBitcastedSExtOrTrunc(), getExtOrTrunc(), llvm::VECustomDAG::getMaskBroadcast(), getNode(), LowerADDSUBSAT(), LowerBITCAST(), llvm::HexagonTargetLowering::LowerLoad(), LowerMULO(), llvm::HexagonTargetLowering::LowerSETCC(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVectorAllEqual(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulLoHiCombine(), selectUmullSmull(), and vectorToScalarBitmask().
Definition at line 1777 of file SelectionDAG.cpp.
References assert(), DL, llvm::EVT::getScalarSizeInBits(), getShiftAmountConstant(), llvm::APInt::getZExtValue(), and llvm::APInt::ult().
Definition at line 1770 of file SelectionDAG.cpp.
References assert(), DL, getConstant(), getDataLayout(), llvm::TargetLoweringBase::getShiftAmountTy(), and llvm::EVT::isInteger().
Referenced by llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), combineExtractWithShuffle(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::TargetLowering::expandVPCTPOP(), extractShiftForRotate(), llvm::TargetLowering::forceExpandWideMUL(), getCopyToParts(), getShiftAmountConstant(), llvm::AMDGPUTargetLowering::loadInputValue(), LowerCTPOP(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), matchBSwapHWordOrAndAnd(), llvm::SITargetLowering::passSpecialInputs(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorLoad(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), and visitORCommutative().
Return the specified value casted to the target's desired shift amount type.
getShiftAmountOperand - Return the specified value casted to the target's desired shift amount type.
Definition at line 2421 of file SelectionDAG.cpp.
References getDataLayout(), llvm::TargetLoweringBase::getShiftAmountTy(), getZExtOrTrunc(), and llvm::EVT::isVector().
Referenced by LowerCTPOP(), and UnrollVectorOp().
SDValue SelectionDAG::getSignedConstant | ( | int64_t | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false , |
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bool | isOpaque = false |
||
) |
Definition at line 1750 of file SelectionDAG.cpp.
References assert(), DL, getConstant(), llvm::EVT::getScalarSizeInBits(), llvm::isIntN(), and Size.
Referenced by llvm::TargetLowering::BuildSDIV(), expandVAArg(), foldMaskedShiftToScaledMask(), getAArch64Cmp(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::RISCVTargetLowering::LowerAsmOperandForConstraint(), lowerBuildVectorOfConstants(), llvm::RISCVTargetLowering::LowerOperation(), lowerShuffleAsBlend(), LowerVECTOR_SHUFFLEv8i8(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performSETCCCombine(), llvm::RISCVDAGToDAGISel::SelectAddrRegImm(), llvm::RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(), llvm::SelectionDAGISel::SelectCodeCommon(), selectConstantAddr(), llvm::RISCVDAGToDAGISel::SelectFrameAddrRegImm(), selectImm(), selectImmSeq(), llvm::RISCVDAGToDAGISel::selectRVVSimm5(), llvm::RISCVDAGToDAGISel::selectSETCC(), llvm::RISCVDAGToDAGISel::selectSimm5Shl2(), llvm::RISCVDAGToDAGISel::selectVLOp(), selectVSplatImmHelper(), transformAddImmMulImm(), tryConvertSVEWideCompare(), llvm::RISCVDAGToDAGISel::tryIndexedLoad(), and llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm().
Returns a node representing a splat of one value into all lanes of the provided vector type.
This is a utility which returns either a BUILD_VECTOR or SPLAT_VECTOR depending on the scalability of the desired vector type.
Definition at line 892 of file SelectionDAG.h.
References assert(), DL, getSplatBuildVector(), getSplatVector(), llvm::EVT::isScalableVector(), and llvm::EVT::isVector().
Referenced by llvm::TargetLowering::expandVPCTTZElements(), getConstant(), getConstantFP(), llvm::SelectionDAGBuilder::getValueImpl(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), refineUniformBase(), scalarizeBinOpOfSplats(), and takeInexpensiveLog2().
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
VT must be a vector type. Op's type must be the same as (or, for integers, a type wider than) VT's element type.
Definition at line 859 of file SelectionDAG.h.
References assert(), llvm::EVT::bitsLE(), llvm::ISD::BUILD_VECTOR, DL, getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::isInteger(), and llvm::ISD::UNDEF.
Referenced by combineGatherScatter(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(), getMemsetValue(), getSplat(), getVectorShuffle(), lowerBUILD_VECTOR(), and lowerBuildVectorViaDominantValues().
If V is a splatted value, return the source vector and its splat index.
Definition at line 2963 of file SelectionDAG.cpp.
References assert(), llvm::countr_one(), llvm::APInt::getAllOnes(), getUNDEF(), llvm::EVT::getVectorNumElements(), Idx, llvm::EVT::isScalableVector(), isSplatValue(), llvm::APInt::isSubsetOf(), llvm::peekThroughExtractSubvectors(), llvm::ISD::SPLAT_VECTOR, and llvm::ISD::VECTOR_SHUFFLE.
Referenced by getSplatValue(), LowerFunnelShift(), LowerRotate(), LowerShiftByScalarVariable(), and scalarizeBinOpOfSplats().
If V is a splat vector, return its scalar source operand by extracting that element from the source vector.
If LegalTypes is true, this method may only return a legally-typed splat value. If it cannot legalize the splatted value it will return SDValue().
Definition at line 3015 of file SelectionDAG.cpp.
References llvm::EVT::bitsLT(), llvm::ISD::EXTRACT_VECTOR_ELT, getContext(), getNode(), llvm::EVT::getScalarType(), getSplatSourceVector(), llvm::TargetLoweringBase::getTypeToTransformTo(), getVectorIdxConstant(), llvm::EVT::isInteger(), and llvm::TargetLoweringBase::isTypeLegal().
Referenced by canLowerSRLToRoundingShiftForVT(), findMoreOptimalIndexType(), foldIndexIntoBase(), PerformVSetCCToVCTPCombine(), and refineUniformBase().
Definition at line 876 of file SelectionDAG.h.
References assert(), llvm::EVT::bitsLE(), DL, getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::isInteger(), llvm::ISD::SPLAT_VECTOR, and llvm::ISD::UNDEF.
Referenced by BuildExactSDIV(), BuildExactUDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), FoldConstantArithmetic(), getSplat(), getWideningInterleave(), and lowerBUILD_VECTOR().
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces.
GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces.
Definition at line 12656 of file SelectionDAG.cpp.
References getContext(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::TargetLoweringBase::getTypeToTransformTo(), and llvm::EVT::isVector().
Referenced by LowerCVTPS2PH(), LowerMULO(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceReductionResults(), splitIntVSETCC(), SplitStrictFPVectorOp(), llvm::SITargetLowering::splitTernaryVectorOp(), SplitVector(), SplitVectorOp(), splitVectorOp(), and SplitVPOp().
Construct a node to track a Value* through the backend.
Definition at line 2356 of file SelectionDAG.cpp.
References AddNodeIDNode(), getVTList(), N, and llvm::ISD::SRCVALUE.
Referenced by llvm::SelectionDAGBuilder::LowerAsSTATEPOINT().
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
getStackArgumentTokenFactor - Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
This is used in tail call lowering to protect stack arguments from being clobbered.
Definition at line 7661 of file SelectionDAG.cpp.
References getEntryNode(), getNode(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::TokenFactor, and uses().
Returns a vector of type ResVT whose elements contain the linear sequence <0, 1, 2, 3, ...>
Definition at line 2073 of file SelectionDAG.cpp.
References DL, llvm::EVT::getScalarSizeInBits(), and getStepVector().
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step, Step * 2, Step * 3, ...>
Definition at line 2078 of file SelectionDAG.cpp.
References assert(), DL, llvm::APInt::getBitWidth(), getBuildVector(), getConstant(), getNode(), llvm::EVT::getScalarSizeInBits(), getTargetConstant(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::isScalableVector(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ISD::STEP_VECTOR.
Referenced by llvm::TargetLowering::expandVPCTTZElements(), findMoreOptimalIndexType(), FoldConstantArithmetic(), getStepVector(), and LowerSVEIntrinsicIndex().
SDValue SelectionDAG::getStore | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 9059 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), getUNDEF(), llvm::SDValue::getValueType(), getVTList(), N, NewSDValueDbgMsg(), Ptr, llvm::ISD::STORE, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getStore | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
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const AAMDNodes & | AAInfo = AAMDNodes() |
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) |
Helper function to build ISD::STORE nodes.
This function will set the MOStore flag on MMOFlags, but you can set it if you want. The MOLoad and MOInvariant flags must not be set.
Definition at line 9039 of file SelectionDAG.cpp.
References assert(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), getStore(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueType(), InferPointerInfo(), llvm::PointerUnion< PTs >::isNull(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::LocationSize::precise(), Ptr, Size, and llvm::MachinePointerInfo::V.
Referenced by combineBoolVectorAndTruncateStore(), combineI8TruncStore(), combineStore(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), expandVACopy(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), foldTruncStoreOfExt(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), getStore(), getTruncStore(), LowerATOMIC_STORE(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), LowerF128Store(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), lowerFP_TO_SINT_STORE(), LowerMemOpCallTo(), lowerMSAStoreIntr(), LowerStore(), LowerSTORE(), lowerStoreF128(), lowerStoreI1(), LowerTruncateVectorStore(), LowerVAARG(), llvm::VETargetLowering::lowerVAARG(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), memsetStore(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), PerformTruncatingStoreCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), reduceMaskedStoreToScalarStore(), llvm::TargetLowering::scalarizeVectorStore(), scalarizeVectorStore(), ShrinkLoadReplaceStoreWithStore(), spillIncomingStatepointValue(), splitStores(), splitStoreSplat(), splitVectorStore(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), llvm::AMDGPUTargetLowering::storeStackInputValue(), and StoreTailCallArgumentsToStackSlot().
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Definition at line 1422 of file SelectionDAG.h.
References getEVTAlign(), getStore(), llvm::SDValue::getValueType(), and Ptr.
SDValue SelectionDAG::getStoreVP | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexedMode | AM, | ||
bool | IsTruncating = false , |
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bool | IsCompressing = false |
||
) |
Definition at line 9303 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::SDValue::getValueType(), getVTList(), Indexed, N, NewSDValueDbgMsg(), llvm::Offset, Ptr, and llvm::ISD::UNINDEXED.
Referenced by getTruncStoreVP(), and llvm::RISCVTargetLowering::PerformDAGCombine().
std::pair< SDValue, SDValue > SelectionDAG::getStrictFPExtendOrRound | ( | SDValue | Op, |
SDValue | Chain, | ||
const SDLoc & | DL, | ||
EVT | VT | ||
) |
Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending or rounding (by truncation).
Definition at line 1441 of file SelectionDAG.cpp.
References assert(), llvm::EVT::bitsEq(), llvm::EVT::bitsGT(), DL, getIntPtrConstant(), llvm::SDValue::getNode(), getNode(), llvm::ISD::STRICT_FP_EXTEND, and llvm::ISD::STRICT_FP_ROUND.
Referenced by llvm::RISCVTargetLowering::LowerOperation(), and LowerUINT_TO_FP_i32().
SDValue SelectionDAG::getStridedLoadVP | ( | EVT | VT, |
const SDLoc & | DL, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Stride, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding = false |
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) |
Definition at line 9473 of file SelectionDAG.cpp.
References DL, getStridedLoadVP(), getUNDEF(), llvm::ISD::NON_EXTLOAD, Ptr, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getStridedLoadVP | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
const SDLoc & | DL, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
SDValue | Stride, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding = false |
||
) |
Definition at line 9439 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), DL, llvm::MachinePointerInfo::getAddrSpace(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), getVTList(), Indexed, N, NewSDValueDbgMsg(), llvm::Offset, Ptr, and llvm::ISD::UNINDEXED.
Referenced by getExtStridedLoadVP(), getStridedLoadVP(), performCONCAT_VECTORSCombine(), and llvm::RISCVTargetLowering::PerformDAGCombine().
SDValue SelectionDAG::getStridedStoreVP | ( | SDValue | Chain, |
const SDLoc & | DL, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
SDValue | Stride, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexedMode | AM, | ||
bool | IsTruncating = false , |
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bool | IsCompressing = false |
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) |
Definition at line 9492 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), DL, llvm::MachinePointerInfo::getAddrSpace(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::SDValue::getValueType(), getVTList(), Indexed, N, NewSDValueDbgMsg(), llvm::Offset, Ptr, and llvm::ISD::UNINDEXED.
Referenced by getTruncStridedStoreVP().
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Definition at line 489 of file SelectionDAG.h.
References llvm::MachineFunction::getSubtarget().
Referenced by combineCommutableSHUFP(), emitComparison(), emitConditionalComparison(), emitStrictFPComparison(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), findMoreOptimalIndexType(), GenerateFixedLengthSVETBL(), getPredicateForFixedLengthVector(), GetTLSADDR(), init(), isAllActivePredicate(), llvm::PPC::isVPKUDUMShuffleMask(), lowerMSASplatZExt(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), optimizeIncrementingWhile(), patchMatchingInput(), performBuildVectorCombine(), performExtractVectorEltCombine(), performSVEMulAddSubCombine(), recoverFramePointer(), llvm::AMDGPUDAGToDAGISel::SelectBuildVector(), truncateVecElts(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryCombineToBSL(), and vectorToScalarBitmask().
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Definition at line 490 of file SelectionDAG.h.
References llvm::MachineFunction::getSubtarget().
SDValue SelectionDAG::getSymbolFunctionGlobalAddress | ( | SDValue | Op, |
Function ** | TargetFunction = nullptr |
||
) |
Return a GlobalAddress of the function from the current module with name matching the given ExternalSymbol.
Additionally can provide the matched function. Panic if the function doesn't exist.
Definition at line 11882 of file SelectionDAG.cpp.
References assert(), llvm::GlobalValue::getAddressSpace(), getDataLayout(), llvm::MachineFunction::getFunction(), llvm::Module::getFunction(), getGlobalAddress(), llvm::GlobalValue::getParent(), llvm::TargetLoweringBase::getPointerTy(), and llvm::report_fatal_error().
Referenced by llvm::NVPTXTargetLowering::LowerCall().
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Definition at line 488 of file SelectionDAG.h.
Referenced by llvm::AMDGPUTargetLowering::allowApproxFunc(), canCreateUndefOrPoison(), canOptimizeTLSDFormToXForm(), combineFaddCFmul(), combineFMinFMax(), combineFMinNumFMaxNum(), combineSelect(), llvm::ScheduleDAGSDNodes::EmitSchedule(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandIndirectJTBranch(), foldFPToIntToFP(), getMemcpy(), getMemmove(), getMemset(), llvm::TargetLowering::getNegatedExpression(), GetTLSADDR(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), isEligibleToFoldADDIForFasterLocalAccesses(), isFMAddSubOrFMSubAdd(), isKnownNeverNaN(), isLegalToCombineMinNumMaxNum(), llvm::LoongArchTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::SelectionDAGBuilder::LowerDeoptimizingReturn(), LowerFMINIMUM_FMAXIMUM(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN(), and transformCallee().
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Definition at line 782 of file SelectionDAG.h.
References getBlockAddress(), and llvm::Offset.
Referenced by getTargetNode(), llvm::TargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::HexagonTargetLowering::LowerBlockAddress(), llvm::MSP430TargetLowering::LowerBlockAddress(), llvm::SparcTargetLowering::withTargetFlags(), and llvm::VETargetLowering::withTargetFlags().
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Definition at line 694 of file SelectionDAG.h.
References DL, and getConstant().
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Definition at line 698 of file SelectionDAG.h.
References DL, and getConstant().
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Definition at line 690 of file SelectionDAG.h.
References DL, and getConstant().
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(), buildPCRelGlobalAddress(), buildRegSequence16(), buildRegSequence32(), llvm::SITargetLowering::buildRSRC(), buildSMovImm32(), canonicalizeBitSelect(), llvm::AArch64TargetLowering::changeStreamingMode(), checkCVTFixedPointOperandWithFBits(), llvm::SITargetLowering::CollectTargetIntrinsicOperands(), combineADC(), combineAddOrSubToADCOrSBB(), combineAndMaskToShift(), combineAndOrForCcmpCtest(), combineBitcastToBoolVector(), combineBrCond(), combineCMov(), combineCommutableSHUFP(), combineCompareEqual(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractWithShuffle(), combineFP16_TO_FP(), combineFP_ROUND(), combineTargetShuffle(), llvm::VETargetLowering::combineTRUNCATE(), combineVectorShiftImm(), combineX86ShuffleChain(), combineX86SubCmpForFlags(), createGPRPairNode(), createMMXBuildVector(), createSetFPEnvNodes(), createTuple(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), EmitAVX512Test(), emitCmp(), emitLockedStackOp(), emitSETCC(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(), expandBitCastI128ToF128(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), expandFP_TO_UINT_SSE(), ExtractBitFromMaskVector(), extractPtrauthBlendDiscriminators(), llvm::HexagonDAGToDAGISel::FastFDiv(), llvm::HexagonDAGToDAGISel::FDiv(), llvm::PPC::get_VSPLTI_elt(), getADAEntry(), getAL(), getAVX2GatherNode(), getCopyFromParts(), getDataClassTest(), getGatherNode(), getGeneralPermuteNode(), getIntOperandsFromRegisterString(), getJumpTableDebugInfo(), getLeftShift(), getPack(), getPermuteNode(), getPrefetchNode(), getPTrue(), getScatterNode(), getSETCC(), getSPDenormModeValue(), getStepVector(), getTargetExtractSubreg(), getTargetInsertSubreg(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getUniformBase(), getV4X86ShuffleImm8ForMask(), getVAArg(), getVShift(), getVSlidedown(), getVSlideup(), getZeroVector(), insert1BitVector(), InvertCarryFlag(), isVMOVModifiedImm(), isWorthFoldingIntoOrrWithShift(), llvm::HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(), lower1BitShuffle(), lower1BitShuffleAsKSHIFTR(), LowerABD(), LowerABS(), llvm::TargetLowering::LowerAsmOperandForConstraint(), llvm::SITargetLowering::LowerAsmOperandForConstraint(), llvm::AVRTargetLowering::LowerAsmOperandForConstraint(), llvm::LanaiTargetLowering::LowerAsmOperandForConstraint(), llvm::M68kTargetLowering::LowerAsmOperandForConstraint(), llvm::PPCTargetLowering::LowerAsmOperandForConstraint(), llvm::RISCVTargetLowering::LowerAsmOperandForConstraint(), llvm::SparcTargetLowering::LowerAsmOperandForConstraint(), llvm::SystemZTargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), llvm::VETargetLowering::lowerATOMIC_FENCE(), LowerBITREVERSE(), llvm::SITargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), LowerCMP_SWAP(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), LowerCTTZ(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerF128Load(), LowerF128Store(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::LowerFLOG2(), llvm::AMDGPUTargetLowering::LowerFLOGCommon(), LowerFMINIMUM_FMAXIMUM(), llvm::VETargetLowering::LowerFormalArguments(), LowerFP_TO_FP16(), lowerFP_TO_INT_SAT(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), LowerFunnelShift(), llvm::SITargetLowering::lowerGET_FPENV(), llvm::SITargetLowering::lowerGET_ROUNDING(), lowerGetVectorLength(), LowerINTRINSIC_W_CHAIN(), lowerLaneOp(), lowerLoadF128(), lowerLoadI1(), LowerMLOAD(), LowerMUL(), LowerPREFETCH(), lowerReductionSeq(), llvm::VETargetLowering::LowerReturn(), LowerRotate(), llvm::SITargetLowering::lowerSET_FPENV(), llvm::SITargetLowering::lowerSET_ROUNDING(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsElementInsertion(), lowerShuffleAsInsertPS(), lowerShuffleAsLanePermuteAndSHUFP(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShufflePairAsUNPCKAndPermute(), lowerShuffleWithSHUFPD(), lowerShuffleWithSSE4A(), LowerSMELdrStr(), lowerStatepointMetaArgs(), LowerSTORE(), lowerStoreF128(), lowerStoreI1(), lowerUINT_TO_FP_vXi32(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2X128Shuffle(), lowerV4F64Shuffle(), lowerV8F64Shuffle(), lowerV8I16Shuffle(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_SHF(), lowerVECTOR_SHUFFLE_VSHF(), lowerVECTOR_SHUFFLE_XVSHUF(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), LowerVSETCC(), optimizeLogicalImm(), llvm::packConstantV2I16(), parseTexFail(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), PerformHWLoopCombine(), pickOpcodeForVectorStParam(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), PromoteMVEPredVector(), pushStackMapConstant(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), llvm::AMDGPUDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::Select(), llvm::LoongArchDAGToDAGISel::SelectAddrConstant(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegImm34(), llvm::RISCVDAGToDAGISel::SelectAddrFrameIndex(), llvm::RISCVDAGToDAGISel::SelectAddrRegImm(), llvm::RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(), llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale(), llvm::HexagonDAGToDAGISel::SelectAnyImmediate(), llvm::HexagonDAGToDAGISel::SelectAnyInt(), llvm::AMDGPUDAGToDAGISel::SelectBuildVector(), llvm::SelectionDAGISel::SelectCodeCommon(), selectConstantAddr(), llvm::HexagonDAGToDAGISel::SelectConstantFP(), llvm::HexagonDAGToDAGISel::SelectD2P(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), selectI64Imm(), selectI64ImmDirect(), selectI64ImmDirectPrefix(), selectImm(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::HexagonDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::LoongArchDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::SelectionDAGISel::SelectInlineAsmMemoryOperands(), llvm::HexagonDAGToDAGISel::SelectNewCircIntrinsic(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), llvm::HexagonDAGToDAGISel::SelectQ2V(), llvm::RISCVDAGToDAGISel::selectSF_VC_X_SE(), llvm::HexagonDAGToDAGISel::SelectSHL(), llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp(), llvm::RISCVDAGToDAGISel::selectSHXADDOp(), llvm::RISCVDAGToDAGISel::selectSimm5Shl2(), llvm::HexagonDAGToDAGISel::SelectV2Q(), llvm::HexagonDAGToDAGISel::SelectV65Gather(), llvm::HexagonDAGToDAGISel::SelectV65GatherPred(), llvm::HexagonDAGToDAGISel::SelectVAlign(), llvm::HexagonDAGToDAGISel::SelectVAlignAddr(), llvm::RISCVDAGToDAGISel::selectVLOp(), llvm::RISCVDAGToDAGISel::selectVSETVLI(), llvm::LoongArchDAGToDAGISel::selectVSplatImm(), llvm::LoongArchDAGToDAGISel::selectVSplatUimmInvPow2(), llvm::LoongArchDAGToDAGISel::selectVSplatUimmPow2(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), tryCombineWhileLo(), llvm::RISCVDAGToDAGISel::tryIndexedLoad(), tryLowerToSLI(), tryOrrWithShift(), llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), trySimplifySrlAddToRshrnb(), tryToConvertShuffleOfTbl2ToTbl4(), llvm::X86TargetLowering::visitMaskedLoad(), llvm::X86TargetLowering::visitMaskedStore(), and llvm::SITargetLowering::wrapAddr64Rsrc().
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Definition at line 725 of file SelectionDAG.h.
References DL, and getConstantFP().
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Definition at line 728 of file SelectionDAG.h.
References DL, and getConstantFP().
Definition at line 722 of file SelectionDAG.h.
References DL, and getConstantFP().
Referenced by pickOpcodeForVectorStParam(), and llvm::SelectionDAGISel::SelectCodeCommon().
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Definition at line 753 of file SelectionDAG.h.
References llvm::CallingConv::C, getConstantPool(), and llvm::Offset.
Referenced by getTargetNode(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerConstantPool(), llvm::LanaiTargetLowering::LowerConstantPool(), promoteToConstantPool(), llvm::SparcTargetLowering::withTargetFlags(), and llvm::VETargetLowering::withTargetFlags().
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Definition at line 761 of file SelectionDAG.h.
References llvm::CallingConv::C, getConstantPool(), and llvm::Offset.
SDValue SelectionDAG::getTargetExternalSymbol | ( | const char * | Sym, |
EVT | VT, | ||
unsigned | TargetFlags = 0 |
||
) |
Definition at line 2022 of file SelectionDAG.cpp.
References getVTList(), N, and Sym.
Referenced by llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), getTagSymNode(), GetTLSADDR(), getzOSCalleeAndADA(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), llvm::MSP430TargetLowering::LowerExternalSymbol(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN(), transformCallee(), llvm::SparcTargetLowering::withTargetFlags(), and llvm::VETargetLowering::withTargetFlags().
SDValue SelectionDAG::getTargetExtractSubreg | ( | int | SRIdx, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | Operand | ||
) |
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
getTargetExtractSubreg - A convenience function for creating TargetOpcode::EXTRACT_SUBREG nodes.
Definition at line 10979 of file SelectionDAG.cpp.
References DL, getMachineNode(), and getTargetConstant().
Referenced by llvm::SITargetLowering::buildRSRC(), expandBitCastF128ToI128(), LowerF64Op(), LowerFNEGorFABS(), lowerGR128Binary(), lowerGR128ToI128(), narrowIfNeeded(), NarrowVector(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::HexagonDAGToDAGISel::SelectVAlign(), llvm::RISCVDAGToDAGISel::selectVLSEG(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), and llvm::RISCVDAGToDAGISel::selectVLXSEG().
Definition at line 741 of file SelectionDAG.h.
References getFrameIndex().
Referenced by addStackMapLiveVars(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(), EmitUnrolledSetTag(), lowerIncomingStatepointValue(), lowerStatepointMetaArgs(), reservePreviousStackSlotForValue(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegImm34(), llvm::HexagonDAGToDAGISel::SelectAddrFI(), llvm::RISCVDAGToDAGISel::SelectAddrFrameIndex(), llvm::RISCVDAGToDAGISel::SelectAddrRegImm(), llvm::RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(), llvm::LoongArchDAGToDAGISel::SelectBaseAddr(), llvm::RISCVDAGToDAGISel::SelectFrameAddrRegImm(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), SelectSAddrFI(), and spillIncomingStatepointValue().
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Definition at line 736 of file SelectionDAG.h.
References DL, and getGlobalAddress().
Referenced by buildPCRelGlobalAddress(), combineADDToMAT_PCREL_ADDR(), foldADDIForFasterLocalAccesses(), getADAEntry(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getTargetNode(), GetTLSADDR(), getzOSCalleeAndADA(), llvm::TargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::MSP430TargetLowering::LowerGlobalAddress(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerToTLSLocalDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), llvm::RISCVDAGToDAGISel::SelectAddrRegImm(), llvm::HexagonDAGToDAGISel::SelectGlobalAddress(), transformCallee(), llvm::SparcTargetLowering::withTargetFlags(), and llvm::VETargetLowering::withTargetFlags().
SDValue SelectionDAG::getTargetInsertSubreg | ( | int | SRIdx, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | Operand, | ||
SDValue | Subreg | ||
) |
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
getTargetInsertSubreg - A convenience function for creating TargetOpcode::INSERT_SUBREG nodes.
Definition at line 10989 of file SelectionDAG.cpp.
References DL, getMachineNode(), and getTargetConstant().
Referenced by LowerF64Op(), LowerFNEGorFABS(), llvm::RISCVDAGToDAGISel::Select(), and Widen().
Definition at line 746 of file SelectionDAG.h.
References getJumpTable().
Referenced by llvm::HexagonTargetLowering::getPICJumpTableRelocBase(), getTargetNode(), llvm::HexagonTargetLowering::LowerJumpTable(), llvm::LanaiTargetLowering::LowerJumpTable(), llvm::MSP430TargetLowering::LowerJumpTable(), and llvm::VETargetLowering::withTargetFlags().
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Definition at line 493 of file SelectionDAG.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), llvm::RegsForValue::AddInlineAsmOperands(), buildFromShuffleMostly(), canonicalizeShuffleWithOp(), combineAdd(), combineAddOrSubToADCOrSBB(), combineAnd(), combineAndnp(), combineAndShuffleNot(), combineBEXTR(), combineBinOpOfZExt(), combineBitcast(), combineBitcastToBoolVector(), combineBITREVERSE(), combineBT(), combineCMP(), combineCONCAT_VECTORS(), combineConcatVectorOfCasts(), combineConcatVectorOfConcatVectors(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineCVTPH2PS(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractFromVectorLoad(), combineExtractVectorElt(), combineFMA(), combineFMADDSUB(), combineFMinNumFMaxNum(), combineFneg(), combineGatherScatter(), combineKSHIFT(), combineLoad(), combineLogicBlendIntoConditionalNegate(), combineMaskedLoad(), combineMaskedStore(), combineMOVMSK(), combineOr(), combinePDEP(), combinePMULDQ(), combinePredicateReduction(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectAsExtAnd(), combineSelectOfTwoConstants(), combineSetCC(), combineShiftAnd1ToBitTest(), combineShuffle(), combineShuffleToFMAddSub(), combineStore(), combineTargetShuffle(), combineTESTP(), combineTruncatedArithmetic(), combineTruncateWithSat(), combineTruncSelectToSMaxUSat(), combineVectorInsert(), combineVectorMulToSraBitcast(), combineVectorShiftImm(), combineVectorShiftVar(), combineVEXTRACT_STORE(), combineVPMADD(), combineVSelectToBLENDV(), combineVSelectWithAllOnesOrZeros(), combineVTRUNC(), combineX86GatherScatter(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), combineXor(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), createMMXBuildVector(), createSetFPEnvNodes(), EltsFromConsecutiveLoads(), expandBitCastF128ToI128(), expandBitCastI128ToF128(), ExpandPowI(), expandVAArg(), expandVACopy(), foldAndOrOfSETCC(), foldBoolSelectToLogic(), foldCONCAT_VECTORS(), foldExtendedSignBitTest(), foldShuffleOfConcatUndefs(), foldVSelectToSignBitSplatMask(), foldXorTruncShiftIntoCmp(), formSplatFromShuffles(), getADAEntry(), getAddressForMemoryInput(), getAVX2GatherNode(), getAVX512Node(), getAVX512TruncNode(), getBT(), getConstVector(), getContainerForFixedLengthVector(), getCopyFromParts(), getCopyFromPartsVector(), llvm::SelectionDAGBuilder::getCopyFromRegs(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::RegsForValue::getCopyToRegs(), llvm::SelectionDAGBuilder::getFrameIndexTy(), getGatherNode(), getJumpTableDebugInfo(), getKnownUndefForVectorBinop(), getLifetimeNode(), getLimitedPrecisionExp2(), getLoadStackGuard(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemset(), getMemsetStores(), getMemsetValue(), getPredicateForFixedLengthVector(), getPredicateForScalableVector(), getPrefetchNode(), getPTest(), getRegistersForValue(), getScatterNode(), getSVEPredicateBitCast(), getTagSymNode(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVCIXISDNodeWCHAIN(), getZeroVector(), getzOSCalleeAndADA(), llvm::SelectionDAGBuilder::handleDebugValue(), llvm::SelectionDAGBuilder::init(), isAddSubOrSubAdd(), isBLACompatibleAddress(), isConsecutiveLSLoc(), isKnownToBeAPowerOfTwo(), isPackedVectorType(), LowerABD(), LowerADDSAT_SUBSAT(), LowerADDSUBO_CARRY(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), LowerATOMIC_STORE(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), llvm::SelectionDAGBuilder::LowerCallTo(), LowerCTPOP(), llvm::SelectionDAGBuilder::LowerDeoptimizeCall(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFMINIMUM_FMAXIMUM(), LowerFSINCOS(), lowerGR128ToI128(), lowerI128ToGR128(), llvm::SelectionDAGBuilder::lowerInvokable(), LowerMemOpCallTo(), LowerMSCATTER(), LowerMULO(), LowerRotate(), LowerShiftParts(), lowerShuffleAsElementInsertion(), lowerShuffleAsShift(), llvm::SelectionDAGBuilder::LowerStatepoint(), lowerStatepointMetaArgs(), LowerStore(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), LowerVASTART(), lowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), LowerVSETCC(), LowerXALUO(), matchLSNode(), matchRotateSub(), narrowExtractedVectorBinOp(), narrowExtractedVectorLoad(), narrowInsertExtractVectorBinOp(), narrowShuffle(), llvm::ScheduleDAGSDNodes::newSUnit(), patchMatchingInput(), performAddCSelIntoCSinc(), performAddSubIntoVectorOp(), performANDCombine(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), performBuildVectorCombine(), performConcatVectorsCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), PerformExtendCombine(), PerformExtractEltToVMOVRRD(), PerformFADDCombineWithOperands(), performFP_TO_INT_SATCombine(), performFP_TO_INTCombine(), performFpToIntCombine(), performGatherLoadCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), PerformLOADCombine(), PerformMinMaxFpToSatCombine(), performORCombine(), PerformORCombine(), PerformPREDICATE_CASTCombine(), performScatterStoreCombine(), performSelectCombine(), PerformShiftCombine(), PerformSTORECombine(), performTBISimplification(), PerformTruncatingStoreCombine(), PerformUMinFpToSatCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), PerformVMOVhrCombine(), PerformVMOVNCombine(), PerformVQMOVNCombine(), PerformVSetCCToVCTPCombine(), performXORCombine(), PerformXORCombine(), PromoteMaskArithmetic(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), refineIndexType(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), scalarizeBinOpOfSplats(), scalarizeExtractedBinop(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::SelectionDAGBuilder::shouldKeepJumpConditionsTogether(), shouldTransformMulToShiftsAddsSubs(), ShrinkLoadReplaceStoreWithStore(), simplifyMul24(), transformCallee(), tryWidenMaskForShuffle(), vectorToScalarBitmask(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorFailure(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), widenAbs(), widenCtPop(), and widenVectorToPartType().
SDValue SelectionDAG::getTokenFactor | ( | const SDLoc & | DL, |
SmallVectorImpl< SDValue > & | Vals | ||
) |
Creates a new TokenFactor containing Vals
.
If Vals
contains 64k values or more, move values into new TokenFactors in 64k-1 blocks, until the final TokenFactor has less than 64k operands.
Definition at line 13222 of file SelectionDAG.cpp.
References llvm::SmallVectorTemplateCommon< T, typename >::begin(), DL, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::SmallVectorImpl< T >::erase(), llvm::SDNode::getMaxNumOperands(), getNode(), llvm::SmallVectorBase< Size_T >::size(), llvm::ArrayRef< T >::slice(), and llvm::ISD::TokenFactor.
Referenced by llvm::SITargetLowering::LowerCall().
SDValue SelectionDAG::getTruncStore | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
EVT | SVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 9111 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::EVT::bitsLT(), llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::EVT::getScalarType(), getStore(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), getVTList(), llvm::EVT::isInteger(), llvm::EVT::isVector(), N, NewSDValueDbgMsg(), Ptr, llvm::ISD::STORE, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getTruncStore | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | SVT, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
||
const AAMDNodes & | AAInfo = AAMDNodes() |
||
) |
Definition at line 9090 of file SelectionDAG.cpp.
References assert(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::EVT::getStoreSize(), getTruncStore(), llvm::SDValue::getValueType(), InferPointerInfo(), llvm::PointerUnion< PTs >::isNull(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::LocationSize::precise(), Ptr, and llvm::MachinePointerInfo::V.
Referenced by chainLoadsAndStoresForMemcpy(), combineStore(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), getAddressForMemoryInput(), getMemcpyLoadsAndStores(), getTruncStore(), LowerINTRINSIC_W_CHAIN(), LowerPredicateStore(), llvm::HexagonTargetLowering::LowerStore(), PerformExtractFpToIntStores(), llvm::ARMTargetLowering::PerformMVETruncCombine(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), performSTORECombine(), llvm::TargetLowering::scalarizeVectorStore(), ShrinkLoadReplaceStoreWithStore(), llvm::AMDGPUTargetLowering::SplitVectorStore(), and llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic().
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Definition at line 1438 of file SelectionDAG.h.
References getEVTAlign(), getTruncStore(), and Ptr.
SDValue SelectionDAG::getTruncStoreVP | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | SVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsCompressing = false |
||
) |
Definition at line 9360 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::EVT::bitsLT(), llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::EVT::getScalarType(), getStoreVP(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), getVTList(), llvm::EVT::isInteger(), llvm::EVT::isVector(), N, NewSDValueDbgMsg(), Ptr, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getTruncStoreVP | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | SVT, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | MMOFlags, | ||
const AAMDNodes & | AAInfo, | ||
bool | IsCompressing = false |
||
) |
Definition at line 9337 of file SelectionDAG.cpp.
References assert(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::EVT::getStoreSize(), getTruncStoreVP(), llvm::SDValue::getValueType(), InferPointerInfo(), llvm::PointerUnion< PTs >::isNull(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::LocationSize::precise(), Ptr, and llvm::MachinePointerInfo::V.
Referenced by getTruncStoreVP().
SDValue SelectionDAG::getTruncStridedStoreVP | ( | SDValue | Chain, |
const SDLoc & | DL, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
SDValue | Stride, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | SVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsCompressing = false |
||
) |
Definition at line 9528 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::EVT::bitsLT(), DL, llvm::MachinePointerInfo::getAddrSpace(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::EVT::getScalarType(), getStridedStoreVP(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), getVTList(), llvm::EVT::isInteger(), llvm::EVT::isVector(), N, NewSDValueDbgMsg(), Ptr, and llvm::ISD::UNINDEXED.
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition at line 1118 of file SelectionDAG.h.
References getNode(), and llvm::ISD::UNDEF.
Referenced by addShuffleForVecExtend(), adjustLoadValueTypeImpl(), buildFromShuffleMostly(), buildMergeScalars(), buildScalarToVector(), llvm::TargetLowering::BuildUDIV(), canonicalizeShuffleMaskWithHorizOp(), collectConcatOps(), CollectOpsToWiden(), combineArithReduction(), combineBasicSADPattern(), combineBinOpToReduce(), combineBitcast(), combineBitcastToBoolVector(), combineBlendOfPermutes(), combineBVOfConsecutiveLoads(), combineConcatVectorOfConcatVectors(), combineConcatVectorOfExtracts(), combineConcatVectorOfShuffleAndItsOperands(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFP_EXTEND(), combineI8TruncStore(), combineINSERT_SUBVECTOR(), combineLRINT_LLRINT(), combineMaskedLoadConstantMask(), combineSelect(), combineSetCCAtomicArith(), combineShuffleOfBitcast(), combineShuffleOfConcatUndef(), combineShuffleOfScalars(), combineShuffleOfSplatVal(), combineSVEReductionOrderedFP(), combineTargetShuffle(), combineToHorizontalAddSub(), combineTruncateWithSat(), combineTruncToVnclip(), combineVectorPack(), combineVPDPBUSDPattern(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), CompactSwizzlableVector(), concatSubVectors(), convertLocVTToValVT(), convertShiftLeftToScale(), convertToScalableVector(), createMMXBuildVector(), EltsFromConsecutiveLoads(), emitErrorAndReplaceIntrinsicResults(), emitIntrinsicWithChainErrorMessage(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), EmitTruncSStore(), ExpandBVWithShuffles(), ExpandHorizontalBinOp(), expandV4F32ToV2F64(), ExtendToType(), extractSubVector(), FoldBUILD_VECTOR(), foldCONCAT_VECTORS(), FoldConstantArithmetic(), foldConstantFPMath(), foldExtractSubvectorFromShuffleVector(), FoldSetCC(), getBuildDwordsVector(), getConstVector(), getCopyFromPartsVector(), getDeinterleaveViaVNSRL(), getExtLoad(), getExtLoadVP(), getExtStridedLoadVP(), getGeneralPermuteNode(), getHopForBuildVector(), getInvertedVectorForFMA(), getKnownUndefForVectorBinop(), getLoad(), getLoadVP(), getNode(), getShuffleHalfVectors(), getShuffleScalarElt(), getShuffleVectorZeroOrUndef(), getSplatSourceVector(), getStore(), getStridedLoadVP(), getTargetVShiftNode(), getTruncStore(), getTruncStoreVP(), getTruncStridedStoreVP(), llvm::VECustomDAG::getUNDEF(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorShuffle(), getVectorShuffle(), getWideningInterleave(), insert1BitVector(), isAddSubOrSubAdd(), isFNEG(), isHopBuildVector(), isHorizontalBinOpPart(), joinDwords(), lower1BitShuffle(), LowerAsSplatVectorLoad(), lowerAtomicArith(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorOfConstants(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv4x32(), lowerBuildVectorViaDominantValues(), llvm::SITargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), lowerFCMPIntrinsic(), LowerFLDEXP(), lowerFMAXIMUM_FMINIMUM(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), lowerICMPIntrinsic(), lowerINT_TO_FP_vXi64(), LowerINTRINSIC_W_CHAIN(), llvm::MipsTargetLowering::lowerLOAD(), LowerMSCATTER(), LowerMUL(), llvm::RISCVTargetLowering::LowerOperation(), LowerPredicateStore(), lowerReductionSeq(), LowerSCALAR_TO_VECTOR(), lowerScalarInsert(), lowerScalarSplat(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBlend(), lowerShuffleAsBlendAndPermute(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleOfExtractsAsVperm(), lowerShuffleViaVRegSplitting(), lowerShuffleWithPSHUFB(), lowerShuffleWithSSE4A(), lowerShuffleWithUndefHalf(), lowerShuffleWithUNPCK256(), LowerSIGN_EXTEND_Mask(), llvm::SelectionDAGBuilder::LowerStatepoint(), LowerStore(), LowerTruncateVectorStore(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), lowerV16I8Shuffle(), lowerV2F64Shuffle(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), lowerVECTOR_SHUFFLE_VREPLVEI(), lowerVECTOR_SHUFFLE_XVREPLVEI(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsInsertPS(), matchShuffleWithUNPCK(), matchSplatAsGather(), NormalizeBuildVector(), padEltsToUndef(), partitionShuffleOfConcats(), llvm::SITargetLowering::passSpecialInputs(), PerformARMBUILD_VECTORCombine(), performBuildShuffleExtendCombine(), performBuildVectorCombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDupLane128Combine(), performLDNT1Combine(), performLOADCombine(), PerformMinMaxCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), performSTNT1Combine(), PerformTruncatingStoreCombine(), performUnpackCombine(), performUzpCombine(), PerformVECTOR_REG_CASTCombine(), PerformVECTOR_SHUFFLECombine(), performVECTOR_SHUFFLECombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), ReplaceAddWithADDP(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeBinOpOfSplats(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), simplifyDivRem(), simplifyFPBinop(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), simplifyShift(), splatPartsI64WithVL(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), truncateVectorWithPACK(), tryBuildVectorShuffle(), tryCombineMULLWithUZP1(), tryToFoldExtendOfConstant(), UnrollVectorOp(), UnrollVectorOverflowOp(), vectorizeExtractedCast(), widenSubVector(), widenVec(), WidenVector(), WidenVector(), and widenVectorToPartType().
|
inline |
Definition at line 496 of file SelectionDAG.h.
Referenced by llvm::FunctionLoweringInfo::set().
SDValue SelectionDAG::getVAArg | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | SV, | ||
unsigned | Align | ||
) |
VAArg produces a result and token chain, and takes a pointer and a source value as input.
Definition at line 10040 of file SelectionDAG.cpp.
References getNode(), getTargetConstant(), getVTList(), Ptr, and llvm::ISD::VAARG.
std::optional< uint64_t > SelectionDAG::getValidMaximumShiftAmount | ( | SDValue | V, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
If a SHL/SRA/SRL node V
has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value.
Definition at line 3126 of file SelectionDAG.cpp.
References assert(), llvm::Depth, getValidShiftAmountRange(), llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.
Referenced by canCreateUndefOrPoison(), getValidMaximumShiftAmount(), llvm::TargetLowering::SimplifyDemandedBits(), and llvm::TargetLowering::SimplifyMultipleUseDemandedBits().
std::optional< uint64_t > SelectionDAG::getValidMaximumShiftAmount | ( | SDValue | V, |
unsigned | Depth = 0 |
||
) | const |
If a SHL/SRA/SRL node V
has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value.
Definition at line 3138 of file SelectionDAG.cpp.
References llvm::Depth, llvm::APInt::getAllOnes(), getValidMaximumShiftAmount(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().
std::optional< uint64_t > SelectionDAG::getValidMinimumShiftAmount | ( | SDValue | V, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
If a SHL/SRA/SRL node V
has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value.
Definition at line 3105 of file SelectionDAG.cpp.
References assert(), llvm::Depth, getValidShiftAmountRange(), llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.
Referenced by computeKnownBits(), ComputeNumSignBits(), and getValidMinimumShiftAmount().
std::optional< uint64_t > SelectionDAG::getValidMinimumShiftAmount | ( | SDValue | V, |
unsigned | Depth = 0 |
||
) | const |
If a SHL/SRA/SRL node V
has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value.
Definition at line 3117 of file SelectionDAG.cpp.
References llvm::Depth, llvm::APInt::getAllOnes(), getValidMinimumShiftAmount(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().
std::optional< uint64_t > SelectionDAG::getValidShiftAmount | ( | SDValue | V, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
If a SHL/SRA/SRL node V
has a uniform shift amount that is less than the element bit-width of the shift node, return it.
Definition at line 3083 of file SelectionDAG.cpp.
References assert(), llvm::Depth, getValidShiftAmountRange(), llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.
Referenced by checkSignTestSetCCCombine(), getValidShiftAmount(), matchTruncateWithPACK(), and llvm::TargetLowering::SimplifyDemandedBits().
If a SHL/SRA/SRL node V
has a uniform shift amount that is less than the element bit-width of the shift node, return it.
Definition at line 3096 of file SelectionDAG.cpp.
References llvm::Depth, llvm::APInt::getAllOnes(), getValidShiftAmount(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().
std::optional< ConstantRange > SelectionDAG::getValidShiftAmountRange | ( | SDValue | V, |
const APInt & | DemandedElts, | ||
unsigned | Depth | ||
) | const |
If a SHL/SRA/SRL node V
has shift amounts that are all less than the element bit-width of the shift node, return the valid constant range.
Definition at line 3034 of file SelectionDAG.cpp.
References assert(), llvm::BitWidth, computeKnownBits(), llvm::Depth, llvm::ConstantRange::fromKnownBits(), llvm::KnownBits::getMaxValue(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::APInt::uge(), llvm::APInt::ugt(), and llvm::APInt::ult().
Referenced by ComputeNumSignBits(), getValidMaximumShiftAmount(), getValidMinimumShiftAmount(), and getValidShiftAmount().
Definition at line 1991 of file SelectionDAG.cpp.
References llvm::EVT::getSimpleVT(), llvm::EVT::isExtended(), llvm::EVT::isSimple(), N, and llvm::MVT::SimpleTy.
Referenced by addShuffleForVecExtend(), combineShiftRightArithmetic(), convertLocVTToValVT(), customLegalizeToWOpWithSExt(), emitRepmovs(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), getAArch64Cmp(), getCopyFromParts(), llvm::RegsForValue::getCopyFromRegs(), getNode(), LowerBUILD_VECTOR_i1(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SITargetLowering::LowerCallResult(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::SITargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFP_TO_INT_SAT(), LowerINSERT_VECTOR_ELT_i1(), lowerMSACopyIntr(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::MSP430TargetLowering::LowerShifts(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performGatherLoadCombine(), performLD1Combine(), PerformMinMaxCombine(), PerformMinMaxFpToSatCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), performScatterStoreCombine(), performSETCCCombine(), performSignExtendInRegCombine(), performSRACombine(), performST1Combine(), PerformUMinFpToSatCombine(), PromoteMaskArithmetic(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceVPICKVE2GRResults(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateScalarIntegerArg(), truncateVectorWithPACKSS(), UnpackFromArgumentSlot(), UnrollVectorOp(), and unrollVectorShift().
SDValue SelectionDAG::getVectorIdxConstant | ( | uint64_t | Val, |
const SDLoc & | DL, | ||
bool | isTarget = false |
||
) |
Definition at line 1783 of file SelectionDAG.cpp.
References DL, getConstant(), getDataLayout(), and llvm::TargetLoweringBase::getVectorIdxTy().
Referenced by BuildVectorFromScalar(), CollectOpsToWiden(), combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineEXTRACT_SUBVECTOR(), combineExtractFromVectorLoad(), combineI8TruncStore(), combineVectorSizedSetCCEquality(), convertIntLogicToFPLogic(), convertToScalableVector(), CustomNonLegalBITCASTResults(), llvm::TargetLowering::expandVECTOR_COMPRESS(), ExtractVectorElements(), foldExtractSubvectorFromShuffleVector(), GeneratePerfectShuffle(), getCopyFromPartsVector(), getCopyToPartsVector(), getDataClassTest(), getMemsetStores(), getNode(), getRVVFPReductionOpAndOperands(), getSplatValue(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), lowerBitreverseShuffle(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerLaneOp(), llvm::RISCVTargetLowering::LowerOperation(), lowerReductionSeq(), lowerScalarInsert(), lowerShuffleViaVRegSplitting(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLEUsingOneOff(), matchBinOpReduction(), narrowExtractedVectorBinOp(), performBuildVectorCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performINSERT_VECTOR_ELTCombine(), PerformInsertSubvectorCombine(), performInsertSubvectorCombine(), performLOADCombine(), performSunpkloCombine(), PerformVQDMULHCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), replaceShuffleOfInsert(), scalarizeBinOpOfSplats(), llvm::TargetLowering::scalarizeVectorStore(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::AMDGPUTargetLowering::splitVector(), SplitVector(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), UnrollVectorOp(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), WidenVector(), and widenVectorToPartType().
SDValue SelectionDAG::getVectorShuffle | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | N1, | ||
SDValue | N2, | ||
ArrayRef< int > | Mask | ||
) |
Return an ISD::VECTOR_SHUFFLE node.
The number of elements in VT, which must be a vector type, must match the number of mask elements NumElts. An integer mask element equal to -1 is treated as undefined.
Definition at line 2100 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::all_of(), llvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Allocate(), assert(), llvm::ISD::BITCAST, commuteShuffle(), llvm::copy(), llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getNode(), llvm::SDNode::getOperand(), getSplatBuildVector(), llvm::BuildVectorSDNode::getSplatValue(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getVTList(), llvm::TargetLoweringBase::hasVectorBlend(), llvm::isNullConstant(), llvm::SDValue::isUndef(), N, NewSDValueDbgMsg(), llvm::BitVector::none(), llvm::Offset, llvm::Splat, and llvm::ISD::VECTOR_SHUFFLE.
Referenced by addShuffleForVecExtend(), buildFromShuffleMostly(), llvm::TargetLowering::buildLegalVectorShuffle(), BuildVSLDOI(), combineAddOfPMADDWD(), combineAndShuffleNot(), combineArithReduction(), combineBasicSADPattern(), combineBITREVERSE(), combineBlendOfPermutes(), combineBVOfConsecutiveLoads(), combineConcatVectorOfShuffleAndItsOperands(), combineConcatVectorOps(), combineFP_ROUND(), combineHorizOpWithShuffle(), combineINSERT_SUBVECTOR(), combineMinMaxReduction(), combinePMULDQ(), combineSelect(), combineShuffleOfBitcast(), combineShuffleOfConcatUndef(), combineShuffleOfSplatVal(), combineSIntToFP(), combineToExtendBoolVectorInReg(), combineToHorizontalAddSub(), combineVPDPBUSDPattern(), createVariablePermute(), EltsFromConsecutiveLoads(), ExpandBVWithShuffles(), expandV4F32ToV2F64(), foldExtractSubvectorFromShuffleVector(), foldShuffleOfConcatUndefs(), formSplatFromShuffles(), GeneratePerfectShuffle(), getCommutedVectorShuffle(), getPack(), getShuffleHalfVectors(), getShuffleVectorZeroOrUndef(), getSToVPermuted(), getTargetVShiftNode(), getVectorShuffle(), isFNEG(), lower128BitShuffle(), lower1BitShuffle(), lower256BitShuffle(), lower512BitShuffle(), LowerAsSplatVectorLoad(), LowerBuildVectorv4x32(), LowerConvertLow(), LowerEXTEND_VECTOR_INREG(), LowerMUL(), LowerMULH(), LowerReverse_VECTOR_SHUFFLE(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBlend(), lowerShuffleAsBlendAndPermute(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsLanePermuteAndSHUFP(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleOfExtractsAsVperm(), lowerShuffleViaVRegSplitting(), lowerShuffleWithUNPCK256(), LowerSIGN_EXTEND(), lowerToAddSubOrFMAddSub(), LowerTruncateVecI1(), LowerUINT_TO_FP_i64(), lowerV16I8Shuffle(), lowerV2I64Shuffle(), lowerV4I32Shuffle(), lowerV8F16Shuffle(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), LowerVECTOR_SHUFFLEUsingMovs(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), partitionShuffleOfConcats(), performBuildShuffleExtendCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performExtBinopLoadFold(), performSelectCombine(), PerformTruncatingStoreCombine(), PerformVECTOR_SHUFFLECombine(), performVECTOR_SHUFFLECombine(), PerformVQDMULHCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceVMULWidth(), ReplaceAddWithADDP(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::SimplifyDemandedBits(), splitAndLowerShuffle(), truncateVectorWithPACK(), tryWidenMaskForShuffle(), and vectorizeExtractedCast().
SDValue SelectionDAG::getVPLogicalNOT | ( | const SDLoc & | DL, |
SDValue | Val, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | VT | ||
) |
Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask, EVL).
Definition at line 1589 of file SelectionDAG.cpp.
References DL, getBoolConstant(), and getNode().
SDValue SelectionDAG::getVPPtrExtOrTrunc | ( | const SDLoc & | DL, |
EVT | VT, | ||
SDValue | Op, | ||
SDValue | Mask, | ||
SDValue | EVL | ||
) |
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT, by either truncating it or performing either vector-predicated zero or sign extension as appropriate extension for the pointer's semantics.
This function just redirects to getVPZExtOrTrunc right now.
Definition at line 1595 of file SelectionDAG.cpp.
References DL, and getVPZExtOrTrunc().
SDValue SelectionDAG::getVPZeroExtendInReg | ( | SDValue | Op, |
SDValue | Mask, | ||
SDValue | EVL, | ||
const SDLoc & | DL, | ||
EVT | VT | ||
) |
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
Definition at line 1544 of file SelectionDAG.cpp.
References assert(), llvm::EVT::bitsLE(), DL, getConstant(), llvm::APInt::getLowBitsSet(), getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorElementCount(), llvm::EVT::isInteger(), and llvm::EVT::isVector().
SDValue SelectionDAG::getVPZExtOrTrunc | ( | const SDLoc & | DL, |
EVT | VT, | ||
SDValue | Op, | ||
SDValue | Mask, | ||
SDValue | EVL | ||
) |
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT, by performing either vector-predicated zext or truncating it.
The Op will be returned as-is if Op and VT are vectors containing integer with same width.
Definition at line 1600 of file SelectionDAG.cpp.
References llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), DL, and getNode().
Referenced by getVPPtrExtOrTrunc().
SDDbgValue * SelectionDAG::getVRegDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
unsigned | VReg, | ||
bool | IsIndirect, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a VReg SDDbgValue node.
VReg.
Definition at line 11089 of file SelectionDAG.cpp.
References assert(), DL, llvm::SDDbgOperand::fromVReg(), and llvm::SDDbgInfo::getAlloc().
Referenced by llvm::SelectionDAGBuilder::handleDebugValue().
SDValue SelectionDAG::getVScale | ( | const SDLoc & | DL, |
EVT | VT, | ||
APInt | MulImm, | ||
bool | ConstantFold = true |
||
) |
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
Definition at line 2045 of file SelectionDAG.cpp.
References assert(), llvm::CallingConv::C, DL, F, llvm::APInt::getBitWidth(), getConstant(), llvm::MachineFunction::getFunction(), getMachineFunction(), getNode(), llvm::ConstantRange::getSingleElement(), llvm::EVT::getSizeInBits(), llvm::getVScaleRange(), and llvm::ISD::VSCALE.
Referenced by clampDynamicVectorIndex(), llvm::TargetLowering::expandVectorSplice(), GenerateFixedLengthSVETBL(), getElementCount(), getMemBasePlusOffset(), getNode(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::TargetLowering::IncrementMemoryAddress(), and SplitEVL().
Definition at line 10487 of file SelectionDAG.cpp.
References llvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Allocate(), llvm::copy(), and llvm::ArrayRef< T >::size().
Return an SDVTList that represents the list of values specified.
Definition at line 10423 of file SelectionDAG.cpp.
References makeVTList().
Referenced by AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), llvm::X86TargetLowering::BuildFILD(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), llvm::AArch64TargetLowering::changeStreamingMode(), CloneNodeWithValues(), combineADC(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineADDX(), combineBitcast(), combineBitcastToBoolVector(), combineBVZEXTLOAD(), combineCMov(), combineCMP(), combineINSERT_SUBVECTOR(), combineSBB(), combineSetCC(), combineSubSetcc(), combineSUBX(), combineSVEPrefetchVecBaseImmOff(), combineTargetShuffle(), CombineVLDDUP(), combineX86AddSub(), combineXorSubCTLZ(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), convertFPToInt(), convertIntToFP(), createLoadLR(), createMemMemNode(), createSetFPEnvNodes(), createStoreLR(), EltsFromConsecutiveLoads(), EmitCmp(), emitCmp(), emitComparison(), emitIntrinsicWithCCAndChain(), EmitMaskedTruncSStore(), emitRepmovs(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), EmitTest(), EmitTruncSStore(), EmitUnrolledSetTag(), Expand64BitShift(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandIntMINMAX(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), ExpandREAD_REGISTER(), llvm::TargetLowering::expandREM(), expandV4F32ToV2F64(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), llvm::HexagonDAGToDAGISel::FastFDiv(), llvm::HexagonDAGToDAGISel::FDiv(), FixupMMXIntrinsicTypes(), foldAndOrOfSETCC(), GeneratePerfectShuffle(), getAArch64XALUOOp(), llvm::MipsTargetLowering::getAddrGPRel(), getAddrSpaceCast(), getAssertAlign(), getAtomic(), getAVX2GatherNode(), getBasicBlock(), getBlockAddress(), getBoundedStrlen(), getBROADCAST_LOAD(), getCALLSEQ_END(), getCALLSEQ_START(), getConstant(), getConstantFP(), getConstantPool(), getCopyFromParts(), getCopyFromReg(), llvm::RegsForValue::getCopyFromRegs(), getCopyToReg(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getExternalSymbol(), getFlagsOfCmpZeroFori1(), getFPBinOp(), getFPTernOp(), getFrameIndex(), getGatherNode(), getGetFPEnv(), getGlobalAddress(), getIndexedStore(), getIndexedStoreVP(), getInvertedVectorForFMA(), getJumpTable(), getLabelNode(), getLifetimeNode(), getLoad(), getLoadVP(), getMachineNode(), getMad64_32(), getMaskedLoad(), getMaskedStore(), getMCSymbol(), getMDNode(), getMergeValues(), getNode(), getPseudoProbeNode(), getRegister(), getRegisterMask(), getScatterNode(), getSetFPEnv(), getSrcValue(), getStore(), getStoreVP(), getStridedLoadVP(), getStridedStoreVP(), getTargetExternalSymbol(), GetTLSADDR(), getTruncStore(), getTruncStoreVP(), getTruncStridedStoreVP(), getVAArg(), getVCIXISDNodeWCHAIN(), getVectorShuffle(), getX86XALUOOp(), legalizeSVEGatherPrefetchOffsVec(), LowerABD(), LowerABS(), LowerADDSAT_SUBSAT(), LowerADDSUBO_CARRY(), lowerADDSUBO_CARRY(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), LowerATOMIC_STORE(), llvm::VETargetLowering::lowerATOMIC_SWAP(), lowerAtomicArithWithLOCK(), LowerBUILD_VECTORToVIDUP(), lowerBuildVectorAsBroadcast(), llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), LowerCMP_SWAP(), LowerCTLZ(), LowerCTTZ(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::VETargetLowering::lowerEH_SJLJ_SETJMP(), LowerFSINCOS(), llvm::SITargetLowering::lowerGET_FPENV(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMSCATTER(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperationWrapper(), lowerOverflowArithmetic(), LowerPARITY(), llvm::HexagonTargetLowering::LowerREADCYCLECOUNTER(), llvm::HexagonTargetLowering::LowerREADSTEADYCOUNTER(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), LowerSETCCCARRY(), lowerShuffleAsBroadcast(), LowerStore(), LowerSTORE(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), LowerUADDSUBO_CARRY(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_vXi32(), LowerUnalignedLoadRetParam(), LowerUnalignedStoreParam(), LowerUnalignedStoreRet(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorExtend(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), LowerXALUO(), llvm::AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(), mutateStrictFPToFP(), narrowLoadToVZLoad(), PerformADDVecReduce(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCONDCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), PerformExtractFpToIntStores(), performFlagSettingCombine(), performGatherLoadCombine(), PerformHWLoopCombine(), performLD1Combine(), PerformLOADCombine(), performMaskedGatherScatterCombine(), PerformMVEVLDCombine(), performNEONPostLDSTCombine(), performPostLD1Combine(), performScatterStoreCombine(), PerformSETCCCombine(), performSignExtendInRegCombine(), PerformUMLALCombine(), PerformVDUPCombine(), PerformVECREDUCE_ADDCombine(), PerformVMOVhrCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), ReplaceATOMIC_LOAD_128Results(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), ReplaceLongIntrinsic(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), llvm::AMDGPUDAGToDAGISel::Select(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectHVXDualOutput(), SelectNodeTo(), llvm::HexagonDAGToDAGISel::SelectTypecast(), llvm::HexagonDAGToDAGISel::SelectV65Gather(), llvm::HexagonDAGToDAGISel::SelectV65GatherPred(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), SplitStrictFPVectorOp(), TryCombineBaseUpdate(), tryMemPairCombine(), tryToWidenSetCCOperands(), UnrollVectorOverflowOp(), valueToCarryFlag(), llvm::X86TargetLowering::visitMaskedLoad(), llvm::X86TargetLowering::visitMaskedStore(), and widenVectorOpsToi8().
Definition at line 10427 of file SelectionDAG.cpp.
References llvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Allocate(), and llvm::EVT::getRawBits().
Definition at line 10445 of file SelectionDAG.cpp.
References llvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Allocate(), and llvm::EVT::getRawBits().
Definition at line 10465 of file SelectionDAG.cpp.
References llvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Allocate(), and llvm::EVT::getRawBits().
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
Definition at line 1526 of file SelectionDAG.cpp.
References llvm::ISD::AND, assert(), llvm::EVT::bitsLE(), DL, getConstant(), llvm::APInt::getLowBitsSet(), getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorElementCount(), llvm::EVT::isInteger(), and llvm::EVT::isVector().
Referenced by combineExtSetcc(), combineStore(), getPtrExtendInReg(), lowerFP_TO_INT_SAT(), llvm::MSP430TargetLowering::LowerShifts(), LowerStore(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), performFP_TO_INT_SATCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), PromoteMaskArithmetic(), llvm::TargetLowering::SimplifyDemandedBits(), and truncateVectorWithPACKUS().
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or truncating it.
Definition at line 1466 of file SelectionDAG.cpp.
References llvm::EVT::bitsGT(), DL, getNode(), llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by combineAnd(), combineAndLoadToBZHI(), combineBitcast(), combineBitcastvxi1(), combineBoolVectorAndTruncateStore(), combineCompareEqual(), combineExtractVectorElt(), combineExtractWithShuffle(), combineOr(), combinePredicateReduction(), combineScalarAndWithMaskSetcc(), combineScalarToVector(), combineSelect(), combineSetCC(), combineSetCCMOVMSK(), combineShiftAnd1ToBitTest(), combineShuffleOfScalars(), combineXor(), createVariablePermute(), createVPDPBUSD(), earlyExpandDIVFIX(), emitMemMemReg(), llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(), Expand64BitShift(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandVPCTTZElements(), foldAddSubBoolOfMaskedVal(), foldCONCAT_VECTORS(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldSelectOfCTTZOrCTLZ(), getBitcastedZExtOrTrunc(), getExtOrTrunc(), getFlagsOfCmpZeroFori1(), getPTest(), getPtrExtOrTrunc(), getShiftAmountOperand(), getTargetVShiftNode(), llvm::TargetLowering::getVectorSubVecPointer(), llvm::TargetLowering::IncrementMemoryAddress(), lowerBALLOTIntrinsic(), LowerBITCAST(), llvm::HexagonTargetLowering::LowerBITCAST(), lowerBuildVectorToBitOp(), LowerBuildVectorv16i8(), LowerCTPOP(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), lowerFCMPIntrinsic(), LowerFGETSIGN(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), LowerFunnelShift(), lowerICMPIntrinsic(), LowerINTRINSIC_W_CHAIN(), llvm::HexagonTargetLowering::LowerLoad(), llvm::SystemZTargetLowering::LowerOperationWrapper(), LowerShift(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowervXi8MulWithUNPCK(), lowerX86CmpEqZeroToCtlzSrl(), performBitcastCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), llvm::AMDGPUTargetLowering::performMulLoHiCombine(), performSETCCCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformUMinFpToSatCombine(), PerformVSetCCToVCTPCombine(), replaceBoolVectorBitcast(), llvm::X86TargetLowering::ReplaceNodeResults(), takeInexpensiveLog2(), tryCombineWhileLo(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), visitORCommutative(), widenAbs(), and widenCtPop().
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inline |
Return true if there are any SDDbgValue nodes associated with this SelectionDAG.
Definition at line 1845 of file SelectionDAG.h.
References llvm::SDDbgInfo::empty().
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
Return true if A and B have no common bits set.
As an example, this can allow an 'add' to be transformed into an 'or'.
Definition at line 5759 of file SelectionDAG.cpp.
References A, assert(), B, computeKnownBits(), llvm::KnownBits::haveNoCommonBitsSet(), and haveNoCommonBitsSetCommutative().
Referenced by getPointerConstIncrement(), and isADDLike().
MaybeAlign SelectionDAG::InferPtrAlign | ( | SDValue | Ptr | ) | const |
Infer alignment of a load / store address.
InferPtrAlignment - Infer alignment of a load / store address.
Return std::nullopt if it cannot be inferred.
Definition at line 12605 of file SelectionDAG.cpp.
References llvm::commonAlignment(), llvm::computeKnownBits(), llvm::KnownBits::countMinTrailingZeros(), getDataLayout(), llvm::MachineFunction::getFrameInfo(), getMachineFunction(), llvm::MachineFrameInfo::getObjectAlign(), llvm::DataLayout::getPointerTypeSizeInBits(), llvm::GlobalValue::getType(), isBaseWithConstantOffset(), llvm::TargetLowering::isGAPlusOffset(), and Ptr.
Referenced by getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), and LowerAsSplatVectorLoad().
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inline |
Definition at line 465 of file SelectionDAG.h.
References init().
void SelectionDAG::init | ( | MachineFunction & | NewMF, |
OptimizationRemarkEmitter & | NewORE, | ||
Pass * | PassPtr, | ||
const TargetLibraryInfo * | LibraryInfo, | ||
UniformityInfo * | UA, | ||
ProfileSummaryInfo * | PSIin, | ||
BlockFrequencyInfo * | BFIin, | ||
MachineModuleInfo & | MMI, | ||
FunctionVarLocs const * | FnVarLocs | ||
) |
Prepare this SelectionDAG to process code in the given MachineFunction.
Definition at line 1331 of file SelectionDAG.cpp.
References llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::TargetSubtargetInfo::getSelectionDAGInfo(), getSubtarget(), and llvm::TargetSubtargetInfo::getTargetLowering().
Referenced by init(), and llvm::SelectionDAGISel::initializeAnalysisResults().
Return true if the specified operand is an ISD::OR or ISD::XOR node that can be treated as an ISD::ADD node.
or(x,y) == add(x,y) iff haveNoCommonBitsSet(x,y) xor(x,y) == add(x,y) iff isMinSignedConstant(y) && !NoWrap If NoWrap
is true, this will not match ISD::XOR.
Definition at line 5378 of file SelectionDAG.cpp.
References haveNoCommonBitsSet(), llvm::isMinSignedConstant(), llvm::ISD::OR, and llvm::ISD::XOR.
Referenced by isBaseWithConstantOffset().
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that is guaranteed to have the same semantics as an ADD.
This handles the equivalence: X|Cst == X+Cst iff X&Cst = 0.
Definition at line 5388 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::DWARFExpression::Operation::getNumOperands(), and isADDLike().
Referenced by getBaseWithConstantOffset(), getBaseWithOffsetUsingSplitOR(), InferPtrAlign(), llvm::SITargetLowering::isReassocProfitable(), LowerAsSplatVectorLoad(), replaceZeroVectorStore(), llvm::RISCVDAGToDAGISel::SelectAddrRegImm(), llvm::RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(), llvm::RISCVDAGToDAGISel::SelectFrameAddrRegImm(), and llvm::LoongArchDAGToDAGISel::SelectInlineAsmMemoryOperand().
std::optional< bool > SelectionDAG::isBoolConstant | ( | SDValue | N, |
bool | AllowTruncation = false |
||
) | const |
Check if a value \op N is a constant using the target's BooleanContent for its type.
Definition at line 13167 of file SelectionDAG.cpp.
References llvm::TargetLoweringBase::getBooleanContents(), llvm::APInt::isAllOnes(), llvm::isConstOrConstSplat(), llvm::APInt::isOne(), llvm::APInt::isZero(), llvm_unreachable, N, llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
Referenced by extractBooleanFlip(), and simplifySelect().
Test whether the given value is a constant FP or similar node.
Definition at line 13153 of file SelectionDAG.cpp.
References llvm::ISD::isBuildVectorOfConstantFPSDNodes(), N, and llvm::ISD::SPLAT_VECTOR.
Referenced by canonicalizeCommutativeBinop(), and isConstantValueOfAnyType().
Test whether the given value is a constant int or similar node.
Definition at line 13134 of file SelectionDAG.cpp.
References llvm::ISD::GlobalAddress, llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::TargetLowering::isOffsetFoldingLegal(), N, and llvm::ISD::SPLAT_VECTOR.
Referenced by canonicalizeCommutativeBinop(), combinePMULDQ(), combineSetCC(), combineSub(), foldAddSubOfSignBit(), isConstantValueOfAnyType(), performSubAddMULCombine(), llvm::TargetLowering::SimplifySetCC(), and stripConstantMask().
N
is any kind of constant or build_vector of constants, int or float. If a vector, it may not necessarily be a splat. Definition at line 2306 of file SelectionDAG.h.
References isConstantFPBuildVectorOrConstantFP(), isConstantIntBuildVectorOrConstantInt(), and N.
Referenced by llvm::AMDGPUTargetLowering::performSelectCombine(), and simplifySelect().
Test whether two SDValues are known to compare equal.
This is true if they are the same value, or if one is negative zero and the other positive zero.
Definition at line 5693 of file SelectionDAG.cpp.
Referenced by combineSelect().
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inline |
Return true if this function can prove that Op
is never poison.
The DemandedElts argument limits the check to the requested vector elements.
Definition at line 2074 of file SelectionDAG.h.
References llvm::Depth, and isGuaranteedNotToBeUndefOrPoison().
Return true if this function can prove that Op
is never poison.
Definition at line 2068 of file SelectionDAG.h.
References llvm::Depth, and isGuaranteedNotToBeUndefOrPoison().
bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison | ( | SDValue | Op, |
bool | PoisonOnly = false , |
||
unsigned | Depth = 0 |
||
) | const |
Return true if this function can prove that Op
is never poison and, if PoisonOnly
is false, does not have undef bits.
Definition at line 5151 of file SelectionDAG.cpp.
References llvm::Depth, llvm::ISD::FREEZE, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), llvm::EVT::isFixedLengthVector(), isGuaranteedNotToBeUndefOrPoison(), and PoisonOnly.
Referenced by canCreateUndefOrPoison(), computeKnownBits(), getNode(), isGuaranteedNotToBePoison(), isGuaranteedNotToBeUndefOrPoison(), llvm::X86TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), and llvm::TargetLowering::SimplifyMultipleUseDemandedBits().
bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison | ( | SDValue | Op, |
const APInt & | DemandedElts, | ||
bool | PoisonOnly = false , |
||
unsigned | Depth = 0 |
||
) | const |
Return true if this function can prove that Op
is never poison and, if PoisonOnly
is false, does not have undef bits.
The DemandedElts argument limits the check to the requested vector elements.
Definition at line 5164 of file SelectionDAG.cpp.
References llvm::all_of(), llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, canCreateUndefOrPoison(), llvm::ISD::CONDCODE, llvm::ISD::CopyFromReg, llvm::Depth, llvm::ISD::FrameIndex, llvm::ISD::FREEZE, llvm::APInt::getBitWidth(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::getShuffleDemandedElts(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, isGuaranteedNotToBeUndefOrPoison(), llvm::TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode(), llvm::isIntOrFPConstant(), llvm::APInt::isZero(), MaxRecursionDepth, PoisonOnly, llvm::ISD::SPLAT_VECTOR, llvm::ISD::TargetFrameIndex, llvm::ISD::UNDEF, llvm::ISD::VALUETYPE, and llvm::ISD::VECTOR_SHUFFLE.
Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN.
If SNaN
is true, returns if Op
is known to never be a signaling NaN (it may still be a qNaN).
Definition at line 5393 of file SelectionDAG.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::CallingConv::C, llvm::Depth, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::ISD::FACOS, llvm::ISD::FADD, llvm::ISD::FASIN, llvm::ISD::FATAN, llvm::ISD::FCANONICALIZE, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FCOSH, llvm::ISD::FDIV, llvm::ISD::FEXP, llvm::ISD::FEXP10, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FLDEXP, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXIMUMNUM, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINIMUM, llvm::ISD::FMINIMUMNUM, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FMUL, llvm::ISD::FNEARBYINT, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FPOW, llvm::ISD::FPOWI, llvm::ISD::FREM, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FSIN, llvm::ISD::FSINH, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::ISD::FTAN, llvm::ISD::FTANH, llvm::ISD::FTRUNC, getTarget(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, isKnownNeverNaN(), llvm::TargetLowering::isKnownNeverNaNForTargetNode(), isKnownNeverSNaN(), llvm::ISD::LLRINT, llvm::ISD::LRINT, MaxRecursionDepth, Options, llvm::ISD::SELECT, llvm::ISD::SINT_TO_FP, and llvm::ISD::UINT_TO_FP.
Referenced by arebothOperandsNotNan(), combineFMinNumFMaxNum(), combineSelect(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFMINNUM_FMAXNUM(), isKnownNeverNaN(), llvm::AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(), llvm::SITargetLowering::isKnownNeverNaNForTargetNode(), isKnownNeverSNaN(), isLegalToCombineMinNumMaxNum(), lowerFMAXIMUM_FMINIMUM(), and LowerFMINIMUM_FMAXIMUM().
Op
is known to never be a signaling NaN. Definition at line 2126 of file SelectionDAG.h.
References llvm::Depth, and isKnownNeverNaN().
Referenced by arebothOperandsNotSNan(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFMINNUM_FMAXNUM(), llvm::SITargetLowering::isCanonicalized(), and isKnownNeverNaN().
Test whether the given SDValue is known to contain non-zero value(s).
Definition at line 5532 of file SelectionDAG.cpp.
References llvm::ISD::ABS, llvm::ISD::ADD, assert(), llvm::ISD::BITREVERSE, llvm::ISD::BSWAP, llvm::CallingConv::C, computeKnownBits(), llvm::ConstantRange::contains(), llvm::ISD::CTPOP, llvm::Depth, F, llvm::ConstantRange::getBitWidth(), llvm::KnownBits::getBitWidth(), llvm::MachineFunction::getFunction(), getMachineFunction(), llvm::KnownBits::getMaxValue(), llvm::getVScaleRange(), isKnownNeverZero(), llvm::KnownBits::isNegative(), llvm::KnownBits::isNonZero(), llvm::isNullConstant(), llvm::KnownBits::isStrictlyPositive(), llvm::APInt::isZero(), llvm::APInt::lshr(), llvm::ISD::matchUnaryPredicate(), MaxRecursionDepth, llvm::ISD::MUL, llvm::ConstantRange::multiply(), llvm::KnownBits::ne(), llvm::KnownBits::One, llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SELECT, llvm::APInt::shl(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::UADDSAT, llvm::ISD::UDIV, llvm::APInt::ult(), llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::VSCALE, llvm::ISD::VSELECT, and llvm::ISD::ZERO_EXTEND.
Referenced by isCMN(), isKnownNeverZero(), isKnownToBeAPowerOfTwo(), isSafeToSpeculativelyExecuteNode(), LowerCTTZ(), LowerShift(), and simplifySetCCWithCTPOP().
Test whether the given floating point SDValue is known to never be positive or negative zero.
Definition at line 5523 of file SelectionDAG.cpp.
References assert(), llvm::CallingConv::C, and llvm::ISD::matchUnaryFpPredicate().
Referenced by combineSelect(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::TargetLowering::expandFMINNUM_FMAXNUM(), and LowerFMINIMUM_FMAXIMUM().
Test if the given value is known to have exactly one bit set.
This differs from computeKnownBits in that it doesn't necessarily determine which bit is set.
Definition at line 4366 of file SelectionDAG.cpp.
References llvm::all_of(), llvm::BitWidth, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::Depth, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::isConstOrConstSplat(), isKnownNeverZero(), isKnownToBeAPowerOfTwo(), llvm::PatternMatch::m_And(), llvm::PatternMatch::m_Deferred(), llvm::PatternMatch::m_Neg(), llvm::PatternMatch::m_Value(), llvm::ISD::matchUnaryPredicate(), MaxRecursionDepth, llvm::SDNode::ops(), llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::SDPatternMatch::sd_match(), llvm::ISD::SELECT, llvm::ISD::SHL, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SRL, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::VSCALE, llvm::ISD::VSELECT, X, and llvm::ISD::ZERO_EXTEND.
Referenced by isKnownToBeAPowerOfTwo(), and isKnownToBeAPowerOfTwoFP().
Test if the given fp value is known to be an integer power-of-2, either positive or negative.
Definition at line 4450 of file SelectionDAG.cpp.
References llvm::Depth, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::isConstOrConstSplatFP(), isKnownToBeAPowerOfTwo(), llvm::ISD::SINT_TO_FP, and llvm::ISD::UINT_TO_FP.
Some opcodes may create immediate undefined behavior when used with some values (integer division-by-zero for example).
Therefore, these operations are not generally safe to move around or change.
Definition at line 2382 of file SelectionDAG.h.
References llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SREM, llvm::ISD::UDIV, llvm::ISD::UDIVREM, and llvm::ISD::UREM.
Referenced by isSafeToSpeculativelyExecuteNode(), and performBUILD_VECTORCombine().
Check if the provided node is save to speculatively executed given its current arguments.
So, while udiv
the opcode is not safe to speculatively execute, a given udiv
node may be if the denominator is known nonzero.
Definition at line 2400 of file SelectionDAG.h.
References isKnownNeverZero(), isSafeToSpeculativelyExecute(), N, and llvm::ISD::UDIV.
Referenced by foldSelectWithIdentityConstant().
Test whether V
has a splatted value.
Helper wrapper to main isSplatValue function.
Definition at line 2949 of file SelectionDAG.cpp.
References assert(), llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), llvm::EVT::isScalableVector(), isSplatValue(), and llvm::EVT::isVector().
bool SelectionDAG::isSplatValue | ( | SDValue | V, |
const APInt & | DemandedElts, | ||
APInt & | UndefElts, | ||
unsigned | Depth = 0 |
||
) | const |
Test whether V
has a splatted value for all the demanded elements.
isSplatValue - Return true if the vector V has the same value across all DemandedElts.
On success UndefElts
will indicate the elements that have UNDEF values instead of the splat value, this is only guaranteed to be correct for DemandedElts
.
NOTE: The function will return true for a demanded splat of UNDEF values.
For scalable vectors, we don't know the number of lanes at compile time. Instead, we use a 1 bit APInt to represent a conservative value for all lanes; that is, that one bit value is implicitly splatted across all lanes.
Definition at line 2763 of file SelectionDAG.cpp.
References llvm::ISD::ABS, llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, assert(), llvm::ISD::BITCAST, llvm::BitWidth, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::Depth, llvm::ISD::EXTRACT_SUBVECTOR, llvm::APInt::extractBits(), llvm::APInt::getAllOnes(), llvm::APInt::getBitWidth(), llvm::APInt::getOneBitSet(), llvm::EVT::getScalarSizeInBits(), llvm::APInt::getSplat(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZero(), I, Idx, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), isSplatValue(), llvm::TargetLowering::isSplatValueForTargetNode(), llvm::EVT::isVector(), llvm::APInt::isZero(), isZero(), LHS, MaxRecursionDepth, llvm::ISD::OR, RHS, llvm::APIntOps::ScaleBitMask(), llvm::APInt::setBit(), llvm::APInt::shl(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SUB, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, and llvm::APInt::zext().
Referenced by canonicalizeShuffleWithOp(), combineEXTRACT_SUBVECTOR(), combineShuffleOfSplatVal(), combineX86ShuffleChain(), getSplatSourceVector(), isOnlyUsedByStores(), isSplatValue(), LowerRotate(), lowerVECTOR_SHUFFLE(), llvm::X86TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), splitVector(), and tryCombineMULLWithUZP1().
Return true if the result of this operation is always undefined.
Definition at line 6365 of file SelectionDAG.cpp.
References llvm::any_of(), assert(), llvm::SDValue::getNode(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::isNullConstant(), llvm::SDValue::isUndef(), llvm::SDNode::op_values(), llvm::ISD::SDIV, llvm::ArrayRef< T >::size(), llvm::ISD::SREM, llvm::ISD::UDIV, and llvm::ISD::UREM.
Referenced by FoldConstantArithmetic(), and simplifyDivRem().
void SelectionDAG::Legalize | ( | ) |
This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction selector, as indicated by the TargetLowering object.
This is the entry point for the file.
Note that this is an involved process that may invalidate pointers into the graph.
Definition at line 5872 of file LegalizeDAG.cpp.
References allnodes_begin(), allnodes_end(), AssignTopologicalOrder(), DeleteNode(), llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::SDValue::getNode(), getNode(), getRoot(), llvm::SmallPtrSetImpl< PtrType >::insert(), N, and RemoveDeadNodes().
bool SelectionDAG::LegalizeOp | ( | SDNode * | N, |
SmallSetVector< SDNode *, 16 > & | UpdatedNodes | ||
) |
Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target instruction selector, as indicated by the TargetLowering object.
N
is a valid, legal node after calling this.This essentially runs a single recursive walk of the Legalize
process over the given node (and its operands). This can be used to incrementally legalize the DAG. All of the nodes which are directly replaced, potentially including N, are added to the output parameter UpdatedNodes
so that the delta to the DAG can be understood by the caller.
When this returns false, N has been legalized in a way that make the pointer passed in no longer valid. It may have even been deleted from the DAG, and so it shouldn't be used further. When this returns true, the N passed in is a legal node, and can be immediately processed as such. This may still have done some work on the DAG, and will still populate UpdatedNodes with any new nodes replacing those originally in the DAG.
Definition at line 5921 of file LegalizeDAG.cpp.
References llvm::SmallPtrSetImpl< PtrType >::count(), llvm::SmallPtrSetImpl< PtrType >::insert(), and N.
bool SelectionDAG::LegalizeTypes | ( | ) |
This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the target.
Returns "true" if it made any changes.
Note that this is an involved process that may invalidate pointers into the graph.
Definition at line 1056 of file LegalizeTypes.cpp.
References llvm::DAGTypeLegalizer::run().
bool SelectionDAG::LegalizeVectors | ( | ) |
This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported by the target.
This is necessary as a separate step from Legalize because unrolling a vector operation can introduce illegal types, which requires running LegalizeTypes again.
This returns true if it made any changes; in that case, LegalizeTypes is called again before Legalize.
Note that this is an involved process that may invalidate pointers into the graph.
Definition at line 2035 of file LegalizeVectorOps.cpp.
SDValue SelectionDAG::makeEquivalentMemoryOrdering | ( | LoadSDNode * | OldLoad, |
SDValue | NewMemOp | ||
) |
If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor.
This ensures that the new memory node will have the same relative memory dependency position as the old load. Returns the new merged load chain.
Definition at line 11874 of file SelectionDAG.cpp.
References assert(), llvm::SDValue::getNode(), llvm::SDValue::getValue(), and makeEquivalentMemoryOrdering().
If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor.
This ensures that the new memory node will have the same relative memory dependency position as the old load. Returns the new merged load chain.
Definition at line 11856 of file SelectionDAG.cpp.
References assert(), getNode(), llvm::SDValue::getValueType(), ReplaceAllUsesOfValueWith(), llvm::ISD::TokenFactor, UpdateNodeOperands(), and llvm::SDValue::use_empty().
Referenced by combineBVOfConsecutiveLoads(), combineExtractFromVectorLoad(), combineStore(), EltsFromConsecutiveLoads(), getBROADCAST_LOAD(), lowerShuffleAsBroadcast(), lowerVECTOR_SHUFFLE(), makeEquivalentMemoryOrdering(), narrowExtractedVectorLoad(), performCONCAT_VECTORSCombine(), performExtBinopLoadFold(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().
SDValue SelectionDAG::makeStateFunctionCall | ( | unsigned | LibFunc, |
SDValue | Ptr, | ||
SDValue | InChain, | ||
const SDLoc & | DLoc | ||
) |
Helper used to make a call to a library function that has one argument of pointer type.
Such functions include 'fegetmode', 'fesetenv' and some others, which are used to get or set floating-point state. They have one argument of pointer type, which points to the memory region containing bits of the floating-point state. The value returned by such function is ignored in the created call.
LibFunc | Reference to library function (value of RTLIB::Libcall). |
Ptr | Pointer used to save/load state. |
InChain | Ingoing token chain. |
Definition at line 13298 of file SelectionDAG.cpp.
References assert(), getContext(), getDataLayout(), getExternalSymbol(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), llvm::TargetLoweringBase::getPointerTy(), llvm::SDValue::getValueType(), llvm::Type::getVoidTy(), llvm::TargetLowering::LowerCallTo(), Ptr, llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), and llvm::TargetLowering::CallLoweringInfo::setLibCallee().
bool SelectionDAG::MaskedValueIsAllOnes | ( | SDValue | Op, |
const APInt & | Mask, | ||
unsigned | Depth = 0 |
||
) | const |
Return true if '(Op & Mask) == Mask'.
MaskedValueIsAllOnes - Return true if '(Op & Mask) == Mask'.
Op and Mask are known to be the same type.
Definition at line 2733 of file SelectionDAG.cpp.
References computeKnownBits(), and llvm::Depth.
bool SelectionDAG::MaskedValueIsZero | ( | SDValue | V, |
const APInt & | Mask, | ||
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
Return true if 'Op & Mask' is known to be zero in DemandedElts.
MaskedValueIsZero - Return true if 'V & Mask' is known to be zero in DemandedElts.
We use this predicate to simplify operations downstream. Op and Mask are known to be the same type.
We use this predicate to simplify operations downstream. Mask is known to be zero for bits that V cannot have.
Definition at line 2719 of file SelectionDAG.cpp.
References computeKnownBits(), and llvm::Depth.
Return true if 'Op & Mask' is known to be zero.
MaskedValueIsZero - Return true if 'V & Mask' is known to be zero.
We use this predicate to simplify operations downstream. Op and Mask are known to be the same type.
We use this predicate to simplify operations downstream. Mask is known to be zero for bits that V cannot have.
Definition at line 2711 of file SelectionDAG.cpp.
References computeKnownBits(), and llvm::Depth.
Referenced by llvm::SelectionDAGISel::CheckAndMask(), combine_CC(), combineAddOfBooleanXor(), combineAddOfPMADDWD(), combineAnd(), combineCMP(), combineDeMorganOfBoolean(), combineMulToPMADDWD(), combineMulToPMULDQ(), combineSetCC(), combineSubShiftToOrcB(), combineTargetShuffle(), combineVectorPack(), combineZext(), EmitCmp(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::TargetLowering::expandMUL_LOHI(), foldMaskAndShiftToScale(), getBT(), getFauxShuffleMask(), getNode(), getTruncatedUSUBSAT(), isTruncWithZeroHighBitsInput(), LowerPARITY(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), matchLSNode(), matchShuffleWithPACK(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformORCombineToBFI(), performSETCCCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), selectUmullSmull(), llvm::RISCVDAGToDAGISel::selectZExtBits(), llvm::LoongArchDAGToDAGISel::selectZExti32(), ShrinkLoadReplaceStoreWithStore(), SignBitIsZero(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), skipExtensionForVectorMULL(), and tryDemorganOfBooleanCondition().
bool SelectionDAG::MaskedVectorIsZero | ( | SDValue | V, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
Return true if 'Op' is known to be zero in DemandedElts.
MaskedVectorIsZero - Return true if 'Op' is known to be zero in DemandedElts.
We use this predicate to simplify operations downstream.
Definition at line 2727 of file SelectionDAG.cpp.
References computeKnownBits(), llvm::Depth, and llvm::KnownBits::isZero().
Referenced by combineOr(), computeVectorKnownZeroElements(), isTargetShuffleEquivalent(), matchBinaryShuffle(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().
SDValue SelectionDAG::matchBinOpReduction | ( | SDNode * | Extract, |
ISD::NodeType & | BinOp, | ||
ArrayRef< ISD::NodeType > | CandidateBinOps, | ||
bool | AllowPartials = false |
||
) |
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract.
The reduction must use one of the opcodes listed in /p CandidateBinOps and on success /p BinOp will contain the matching opcode. Returns the vector that is being reduced on, or SDValue() if a reduction was not matched. If AllowPartials
is set then in the case of a reduction pattern that only matches the first few stages, the extracted subvector of the start of the reduction is returned.
Definition at line 12314 of file SelectionDAG.cpp.
References llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::SDValue::getConstantOperandAPInt(), getContext(), llvm::ShuffleVectorSDNode::getMaskElt(), getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), getVectorIdxConstant(), llvm::EVT::getVectorVT(), llvm::TargetLoweringBase::isExtractSubvectorCheap(), llvm::isNullConstant(), llvm_unreachable, llvm::Log2_32(), and llvm::none_of().
Referenced by combineArithReduction(), combineBasicSADPattern(), combineMinMaxReduction(), combinePredicateReduction(), combineVPDPBUSDPattern(), and MatchVectorAllEqualTest().
SDNode * SelectionDAG::MorphNodeTo | ( | SDNode * | N, |
unsigned | Opc, | ||
SDVTList | VTs, | ||
ArrayRef< SDValue > | Ops | ||
) |
This mutates the specified node to have the specified return type, opcode, and operands.
MorphNodeTo - This mutates the specified node to have the specified return type, opcode, and operands.
Note that MorphNodeTo returns the resultant node. If there is already a node of the specified opcode and operands, it returns that node instead of the current one. Note that the SDLoc need not be the same.
Using MorphNodeTo is faster than creating a new node and swapping it in with ReplaceAllUsesWith both because it often avoids allocating a new node, and because it doesn't require CSE recalculation for any of the node's users.
However, note that MorphNodeTo recursively deletes dead nodes from the DAG. As a consequence it isn't appropriate to use from within the DAG combiner or the legalizer which maintain worklists that would need to be updated when deleting things.
Definition at line 10760 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::SmallPtrSetImplBase::empty(), I, llvm::SmallPtrSetImpl< PtrType >::insert(), N, llvm::SDVTList::NumVTs, llvm::SmallVectorTemplateBase< T, bool >::push_back(), RemoveDeadNodes(), llvm::Use::set(), and llvm::SDVTList::VTs.
Referenced by CloneNodeWithValues(), llvm::NVPTXTargetLowering::LowerCall(), mutateStrictFPToFP(), llvm::AMDGPUDAGToDAGISel::Select(), SelectNodeTo(), and llvm::HexagonDAGToDAGISel::SelectTypecast().
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain and dropping the metadata arguments.
The node must be a strict FP node.
Definition at line 10813 of file SelectionDAG.cpp.
References assert(), getVTList(), llvm_unreachable, MorphNodeTo(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), RemoveDeadNode(), ReplaceAllUsesOfValueWith(), ReplaceAllUsesWith(), and llvm::SDNode::setNodeId().
|
delete |
void SelectionDAG::RemoveDeadNode | ( | SDNode * | N | ) |
Remove the specified node from the system.
If any of its operands then becomes dead, remove them as well. Inform UpdateListener for each node deleted.
Definition at line 1041 of file SelectionDAG.cpp.
References getRoot(), N, and RemoveDeadNodes().
Referenced by foldADDIForFasterLocalAccesses(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), llvm::TargetLowering::getCheaperOrNeutralNegatedExpression(), llvm::TargetLowering::getNegatedExpression(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::NVPTXTargetLowering::LowerCall(), mutateStrictFPToFP(), llvm::SelectionDAGISel::ReplaceNode(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectBrevLdIntrinsic(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectHVXDualOutput(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::HexagonDAGToDAGISel::SelectIntrinsicWChain(), llvm::HexagonDAGToDAGISel::SelectNewCircIntrinsic(), SelectNodeTo(), llvm::HvxSelector::selectVAlign(), llvm::RISCVDAGToDAGISel::selectVLSEG(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), and llvm::HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic().
void SelectionDAG::RemoveDeadNodes | ( | ) |
This method deletes all unreachable nodes in the SelectionDAG.
RemoveDeadNodes - This method deletes all unreachable nodes in the SelectionDAG.
Definition at line 987 of file SelectionDAG.cpp.
References allnodes(), getRoot(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), RemoveDeadNodes(), and setRoot().
Referenced by Legalize(), MorphNodeTo(), llvm::AMDGPUDAGToDAGISel::PostprocessISelDAG(), llvm::RISCVDAGToDAGISel::PostprocessISelDAG(), llvm::AMDGPUDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), RemoveDeadNode(), RemoveDeadNodes(), and llvm::DAGTypeLegalizer::run().
void SelectionDAG::RemoveDeadNodes | ( | SmallVectorImpl< SDNode * > & | DeadNodes | ) |
This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result.
RemoveDeadNodes - This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result.
Definition at line 1007 of file SelectionDAG.cpp.
References llvm::ISD::DELETED_NODE, llvm::SmallVectorBase< Size_T >::empty(), I, N, llvm::SelectionDAG::DAGUpdateListener::Next, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::Use::set(), and llvm::SDNode::use_empty().
void SelectionDAG::ReplaceAllUsesOfValuesWith | ( | const SDValue * | From, |
const SDValue * | To, | ||
unsigned | Num | ||
) |
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
This correctly handles the case where there is an overlap between the From values and the To values.
The same value may appear in both the From and To list. The Deleted vector is handled the same way as for ReplaceAllUsesWith.
Definition at line 11691 of file SelectionDAG.cpp.
References copyExtraInfo(), From, ReplaceAllUsesOfValueWith(), llvm::Use::set(), llvm::sort(), transferDbgValues(), llvm::SDNode::use_begin(), llvm::SDNode::use_end(), and Uses.
Referenced by llvm::SelectionDAGISel::ReplaceUses().
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
The Deleted vector is handled the same way as for ReplaceAllUsesWith.
Definition at line 11516 of file SelectionDAG.cpp.
References copyExtraInfo(), From, llvm::SDValue::getNode(), getRoot(), llvm::SDNode::use_iterator::getUse(), llvm::SDNode::isDivergent(), ReplaceAllUsesWith(), llvm::Use::set(), setRoot(), transferDbgValues(), and updateDivergence().
Referenced by AddCombineTo64bitMLAL(), AddCombineTo64BitSMLAL16(), AddCombineTo64bitUMAAL(), adjustSubwordCmp(), combineBitcast(), combineCarryDiamond(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineCVTPH2PS(), combineEXTEND_VECTOR_INREG(), combineExtractWithShuffle(), combineINSERT_SUBVECTOR(), combineMOVDQ2Q(), combineOp_VLToVWOp_VL(), combineSetCCAtomicArith(), combineSIntToFP(), combineTargetShuffle(), combineVSelectToBLENDV(), combineX86INT_TO_FP(), emitIntrinsicWithCCAndChain(), EmitTest(), lowerBuildVectorAsBroadcast(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), makeEquivalentMemoryOrdering(), llvm::AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(), mutateStrictFPToFP(), performConcatVectorsCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDivRemCombine(), performExtractVectorEltCombine(), PerformHWLoopCombine(), performIntToFpCombine(), PerformORCombineToSMULWBT(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performStoreCombine(), performUnpackCombine(), PerformVDUPCombine(), PerformVMOVhrCombine(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), reduceVSXSwap(), ReplaceAllUsesOfValuesWith(), llvm::SelectionDAGISel::ReplaceUses(), SkipExtensionForVMULL(), tryToFoldExtOfAtomicLoad(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), and tryToFoldExtOfMaskedLoad().
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
This can cause recursive merging of nodes in the DAG.
This version can replace From with any result values. To must match the number and types of values returned by From.
Definition at line 11466 of file SelectionDAG.cpp.
References copyExtraInfo(), From, getNode(), getRoot(), llvm::SDNode::use_iterator::getUse(), llvm::SDNode::isDivergent(), ReplaceAllUsesWith(), llvm::Use::set(), setRoot(), transferDbgValues(), and updateDivergence().
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
This can cause recursive merging of nodes in the DAG.
This version assumes that for each value of From, there is a corresponding value in To in the same position with the same type.
Definition at line 11408 of file SelectionDAG.cpp.
References assert(), copyExtraInfo(), From, getNode(), getRoot(), llvm::SDNode::use_iterator::getUse(), llvm::SDNode::getValueType(), llvm::SDNode::isDivergent(), setRoot(), transferDbgValues(), and updateDivergence().
Modify anything using 'From' to use 'To' instead.
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
This can cause recursive merging of nodes in the DAG. Use the first version if 'From' is known to have a single result, use the second if you have two nodes with identical results (or if 'To' has a superset of the results of 'From'), use the third otherwise.
These methods all take an optional UpdateListener, which (if not null) is informed about nodes that are deleted and modified due to recursive changes in the dag.
These functions only replace all existing uses. It's possible that as these replacements are being performed, CSE may cause the From node to be given new uses. These new uses of From are left in place, and not automatically transferred to To.
This can cause recursive merging of nodes in the DAG.
This version assumes From has a single result value.
Definition at line 11355 of file SelectionDAG.cpp.
References assert(), copyExtraInfo(), From, llvm::SDValue::getNode(), llvm::SDValue::getResNo(), getRoot(), llvm::SDNode::use_iterator::getUse(), llvm::SDNode::isDivergent(), llvm::Use::set(), setRoot(), transferDbgValues(), and updateDivergence().
Referenced by emitComparison(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), llvm::NVPTXTargetLowering::LowerCall(), lowerShufflePairAsUNPCKAndPermute(), mutateStrictFPToFP(), performCONDCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), PerformHWLoopCombine(), PerformLongShiftCombine(), performSETCCCombine(), ReplaceAllUsesOfValueWith(), ReplaceAllUsesWith(), llvm::SelectionDAGISel::ReplaceNode(), llvm::SelectionDAGISel::ReplaceUses(), SelectNodeTo(), tryCombineMULLWithUZP1(), and tryMemPairCombine().
|
inline |
Move node N in the AllNodes list to be immediately before the given iterator Position.
This may be used to update the topological ordering when the list of nodes is modified.
Definition at line 1826 of file SelectionDAG.h.
References llvm::iplist_impl< IntrusiveListT, TraitsT >::insert(), N, and llvm::iplist_impl< IntrusiveListT, TraitsT >::remove().
Referenced by insertDAGNode().
void SelectionDAG::salvageDebugInfo | ( | SDNode & | N | ) |
To be invoked on an SDNode that is slated to be erased.
This function mirrors llvm::salvageDebugInfo
.
Definition at line 11194 of file SelectionDAG.cpp.
References llvm::ISD::ADD, AddDbgValue(), llvm::DIExpression::appendOffset(), llvm::DIExpression::appendOpsToArg(), assert(), llvm::DIExpression::convertToVariadicExpression(), llvm::dbgs(), llvm::dwarf::DW_OP_LLVM_arg, llvm::SDDbgOperand::fromNode(), getDbgValueList(), GetDbgValues(), llvm::DIExpression::getExtOps(), llvm::SDValue::getNode(), llvm::SDValue::getResNo(), llvm::SDValue::getValueSizeInBits(), LLVM_DEBUG, N, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), RHS, llvm::SDDbgOperand::SDNODE, and llvm::ISD::TRUNCATE.
Referenced by llvm::SelectionDAGISel::SelectCodeCommon().
These are used for target selectors to mutate the specified node to have the specified return type, Target opcode, and operands.
SelectNodeTo - These are wrappers around MorphNodeTo that accept a machine opcode.
Note that target opcodes are stored as ~TargetOpcode in the node opcode field. The resultant node is returned.
Definition at line 10653 of file SelectionDAG.cpp.
References getVTList(), N, and SelectNodeTo().
Referenced by llvm::AMDGPUDAGToDAGISel::SelectBuildVector(), SelectNodeTo(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), and tryOrrWithShift().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 10682 of file SelectionDAG.cpp.
References getVTList(), N, and SelectNodeTo().
Definition at line 10659 of file SelectionDAG.cpp.
References getVTList(), N, and SelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line 10666 of file SelectionDAG.cpp.
References getVTList(), N, and SelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT, | ||
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3 | ||
) |
Definition at line 10674 of file SelectionDAG.cpp.
References getVTList(), N, and SelectNodeTo().
Definition at line 10694 of file SelectionDAG.cpp.
References getVTList(), N, and SelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT1, | ||
EVT | VT2, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 10688 of file SelectionDAG.cpp.
References getVTList(), N, and SelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT1, | ||
EVT | VT2, | ||
EVT | VT3, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 10700 of file SelectionDAG.cpp.
References getVTList(), N, and SelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT1, | ||
EVT | VT2, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line 10707 of file SelectionDAG.cpp.
References getVTList(), N, and SelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
SDVTList | VTs, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 10715 of file SelectionDAG.cpp.
References MorphNodeTo(), N, RemoveDeadNode(), and ReplaceAllUsesWith().
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inline |
Definition at line 507 of file SelectionDAG.h.
Referenced by llvm::SelectionDAG::FlagInserter::FlagInserter(), and llvm::SelectionDAG::FlagInserter::~FlagInserter().
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inline |
Definition at line 474 of file SelectionDAG.h.
Set graph attributes for a node. (eg. "color=red".)
setGraphAttrs - Set graph attributes for a node.
(eg. "color=red".)
Definition at line 191 of file SelectionDAGPrinter.cpp.
References llvm::errs(), and N.
Convenience for setting node color attribute.
setGraphColor - Convenience for setting node color attribute.
Definition at line 221 of file SelectionDAGPrinter.cpp.
References llvm::errs(), and N.
void SelectionDAG::setNodeMemRefs | ( | MachineSDNode * | N, |
ArrayRef< MachineMemOperand * > | NewMemRefs | ||
) |
Mutate the specified machine node's memory references to the provided list.
Definition at line 10629 of file SelectionDAG.cpp.
References llvm::copy(), llvm::ArrayRef< T >::empty(), N, and llvm::ArrayRef< T >::size().
Referenced by CloneNodeWithValues(), llvm::AArch64SelectionDAGInfo::EmitMOPS(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(), getLoadStackGuard(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), ReplaceATOMIC_LOAD_128Results(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectBrevLdIntrinsic(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::HexagonDAGToDAGISel::SelectV65Gather(), llvm::HexagonDAGToDAGISel::SelectV65GatherPred(), llvm::RISCVDAGToDAGISel::selectVLSEG(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::RISCVDAGToDAGISel::tryIndexedLoad(), and llvm::X86InstrInfo::unfoldMemoryOperand().
Set the current root tag of the SelectionDAG.
Definition at line 576 of file SelectionDAG.h.
References assert(), llvm::checkForCycles(), and N.
Referenced by llvm::TargetLowering::LowerCallTo(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::SelectionDAGBuilder::LowerDeoptimizingReturn(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), lowerIncomingStatepointValue(), llvm::SelectionDAGBuilder::lowerInvokable(), llvm::RISCVDAGToDAGISel::PostprocessISelDAG(), RemoveDeadNodes(), ReplaceAllUsesOfValueWith(), ReplaceAllUsesWith(), llvm::DAGTypeLegalizer::run(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorFailure(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), and llvm::SelectionDAGBuilder::visitSwitchCase().
Convenience for setting subgraph color attribute.
setSubgraphColor - Convenience for setting subgraph color attribute.
Definition at line 265 of file SelectionDAGPrinter.cpp.
References llvm::errs(), and N.
bool SelectionDAG::shouldOptForSize | ( | ) | const |
Definition at line 1358 of file SelectionDAG.cpp.
References llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineFunction::getFunction(), llvm::Function::hasOptSize(), llvm::FunctionLoweringInfo::MBB, and llvm::shouldOptimizeForSize().
Referenced by combineX86ShuffleChain(), combineX86ShufflesConstants(), llvm::TargetLowering::expandDIVREMByConstant(), ExpandPowI(), getConstantPool(), LowerAndToBT(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerConstant(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), LowerFunnelShift(), lowerShuffleAsBlend(), shouldLowerMemFuncForSize(), llvm::SelectionDAGISel::shouldOptForSize(), and shouldUseHorizontalOp().
Return true if the sign bit of Op is known to be zero.
SignBitIsZero - Return true if the sign bit of Op is known to be zero.
We use this predicate to simplify operations downstream.
Definition at line 2703 of file SelectionDAG.cpp.
References llvm::BitWidth, llvm::Depth, llvm::APInt::getSignMask(), and MaskedValueIsZero().
Referenced by canReduceVMulWidth(), checkSignTestSetCCCombine(), combineUIntToFP(), llvm::TargetLowering::expandABD(), getCmp(), LowerVSETCC(), and selectUmullSmull().
SDValue SelectionDAG::simplifyFPBinop | ( | unsigned | Opcode, |
SDValue | X, | ||
SDValue | Y, | ||
SDNodeFlags | Flags | ||
) |
Try to simplify a floating-point binary operation into 1 of its operands or a constant.
Definition at line 9995 of file SelectionDAG.cpp.
References llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FSUB, getConstantFP(), getUNDEF(), llvm::ConstantFPSDNode::getValueAPF(), llvm::isConstOrConstSplatFP(), llvm::APFloat::isExactlyValue(), llvm::APFloat::isInfinity(), llvm::APFloat::isNaN(), llvm::APFloat::isNegZero(), llvm::APFloat::isPosZero(), llvm::APFloat::isZero(), X, and Y.
Referenced by getNode().
Try to simplify a select/vselect into 1 of its operands or a constant.
Definition at line 9944 of file SelectionDAG.cpp.
References llvm::CallingConv::C, Cond, F, isBoolConstant(), and isConstantValueOfAnyType().
Referenced by combineSelect(), and getNode().
Try to simplify a shift into 1 of its operands or a constant.
Definition at line 9967 of file SelectionDAG.cpp.
References getConstant(), getUNDEF(), llvm::isNullOrNullSplat(), llvm::ISD::matchUnaryPredicate(), X, and Y.
Referenced by getNode().
Split the explicit vector length parameter of a VP operation.
Definition at line 12722 of file SelectionDAG.cpp.
References assert(), DL, getConstant(), getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorMinNumElements(), getVScale(), llvm::Hi, llvm::EVT::isFixedLengthVector(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownEven(), llvm::Lo, N, llvm::ISD::UMIN, and llvm::ISD::USUBSAT.
Referenced by SplitVectorReductionOp(), and SplitVPOp().
std::pair< SDValue, SDValue > SelectionDAG::SplitScalar | ( | const SDValue & | N, |
const SDLoc & | DL, | ||
const EVT & | LoVT, | ||
const EVT & | HiVT | ||
) |
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
Definition at line 12641 of file SelectionDAG.cpp.
References assert(), DL, llvm::ISD::EXTRACT_ELEMENT, getIntPtrConstant(), getNode(), llvm::Hi, llvm::EVT::isVector(), llvm::Lo, and N.
Referenced by createGPRPairNode(), Expand64BitShift(), expandBitCastI128ToF128(), llvm::TargetLowering::expandDIVREMByConstant(), getMaskNode(), initAccumulator(), LowerBITCAST(), lowerI128ToGR128(), llvm::AArch64TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerVectorAllEqual(), lowerVectorIntrinsicScalars(), LowerWRITE_REGISTER(), Passv64i1ArgInRegs(), PerformADDVecReduce(), performMADD_MSUBCombine(), ReplaceATOMIC_LOAD_128Results(), ReplaceCMP_SWAP_128Results(), ReplaceLongIntrinsic(), llvm::X86TargetLowering::ReplaceNodeResults(), splatSplitI64WithVL(), and WinDBZCheckDenominator().
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inline |
Split the vector with EXTRACT_SUBVECTOR and return the low/high part.
Definition at line 2268 of file SelectionDAG.h.
References DL, GetSplitDestVTs(), N, and SplitVector().
std::pair< SDValue, SDValue > SelectionDAG::SplitVector | ( | const SDValue & | N, |
const SDLoc & | DL, | ||
const EVT & | LoVT, | ||
const EVT & | HiVT | ||
) |
Split the vector with EXTRACT_SUBVECTOR using the provided VTs and return the low/high part.
SplitVector - Split the vector with EXTRACT_SUBVECTOR and return the low/high part.
Definition at line 12701 of file SelectionDAG.cpp.
References assert(), DL, llvm::ISD::EXTRACT_SUBVECTOR, getNode(), getVectorIdxConstant(), llvm::EVT::getVectorMinNumElements(), llvm::Hi, llvm::EVT::isScalableVector(), llvm::Lo, and N.
Referenced by combineHorizOpWithShuffle(), combinePredicateReduction(), llvm::TargetLowering::expandVecReduce(), getPMOVMSKB(), getVectorBitwiseReduce(), isHorizontalBinOp(), LowerVecReduceMinMax(), LowerVectorAllEqual(), ReplaceAddWithADDP(), llvm::X86TargetLowering::ReplaceNodeResults(), SplitStrictFPVectorOp(), SplitVector(), SplitVectorOp(), SplitVectorOperand(), SplitVectorReductionOp(), and SplitVPOp().
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inline |
Split the node's operand with EXTRACT_SUBVECTOR and return the low/high part.
Definition at line 2279 of file SelectionDAG.h.
References N, and SplitVector().
Referenced by LowerCVTPS2PH(), LowerTruncate(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceReductionResults(), llvm::SITargetLowering::splitBinaryVectorOp(), llvm::SITargetLowering::splitTernaryVectorOp(), and llvm::SITargetLowering::splitUnaryVectorOp().
void SelectionDAG::transferDbgValues | ( | SDValue | From, |
SDValue | To, | ||
unsigned | OffsetInBits = 0 , |
||
unsigned | SizeInBits = 0 , |
||
bool | InvalidateDbg = true |
||
) |
Transfer debug values from one node to another, while optionally generating fragment expressions for split-up values.
If InvalidateDbg
is set, debug values are invalidated after they are transferred.
Definition at line 11112 of file SelectionDAG.cpp.
References AddDbgValue(), assert(), llvm::DIExpression::createFragmentExpression(), From, llvm::SDDbgOperand::fromNode(), getDbgValueList(), GetDbgValues(), llvm::SDNode::getHasDebugValue(), llvm::SDNode::getIROrder(), llvm::SDValue::getNode(), llvm::SDValue::getResNo(), llvm::is_contained(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by getNode(), ReplaceAllUsesOfValuesWith(), ReplaceAllUsesOfValueWith(), and ReplaceAllUsesWith().
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the scalars and operating on each element individually.
If the ResNE is 0, fully unroll the vector op. If ResNE is less than the width of the vector op, unroll up to ResNE. If the ResNE is greater than the width of the vector op, unroll the vector op and fill the end of the resulting vector with UNDEFS.
Definition at line 12430 of file SelectionDAG.cpp.
References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, getBuildVector(), getContext(), getMergeValues(), getNode(), getShiftAmountOperand(), getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), getValueType(), llvm::EVT::getVectorElementType(), getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::EVT::isVector(), N, Operands, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SELECT, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::VSELECT.
Referenced by llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandShlSat(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), and unrollVectorShift().
std::pair< SDValue, SDValue > SelectionDAG::UnrollVectorOverflowOp | ( | SDNode * | N, |
unsigned | ResNE = 0 |
||
) |
Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes.
This is a separate function because those opcodes have two results.
Definition at line 12527 of file SelectionDAG.cpp.
References llvm::SmallVectorImpl< T >::append(), assert(), ExtractVectorElements(), getBoolConstant(), getBuildVector(), getConstant(), getContext(), getDataLayout(), getNode(), getSelect(), llvm::TargetLoweringBase::getSetCCResultType(), getUNDEF(), llvm::SDValue::getValue(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), getVTList(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SADDO, llvm::ISD::SMULO, llvm::ISD::SSUBO, llvm::ISD::UADDO, llvm::ISD::UMULO, and llvm::ISD::USUBO.
void SelectionDAG::updateDivergence | ( | SDNode * | N | ) |
Definition at line 11645 of file SelectionDAG.cpp.
References llvm::append_range(), calculateDivergence(), llvm::SmallVectorBase< Size_T >::empty(), N, and llvm::SmallVectorImpl< T >::pop_back_val().
Referenced by ReplaceAllUsesOfValueWith(), ReplaceAllUsesWith(), and UpdateNodeOperands().
Definition at line 10587 of file SelectionDAG.cpp.
References assert(), llvm::ArrayRef< T >::begin(), llvm::ArrayRef< T >::end(), N, llvm::ArrayRef< T >::size(), and updateDivergence().
Mutate the specified node in-place to have the specified operands.
UpdateNodeOperands - Mutate the specified node in-place to have the specified operands.
If the resultant node already exists in the DAG, this does not modify the specified node, instead it returns the node that already exists. If the resultant node does not exist in the DAG, the input node is returned. As a degenerate case, if you specify the same input operands as the node already has, the input node is returned.
Definition at line 10513 of file SelectionDAG.cpp.
References assert(), N, and updateDivergence().
Referenced by foldADDIForFasterLocalAccesses(), llvm::SITargetLowering::legalizeTargetIndependentNode(), makeEquivalentMemoryOrdering(), moveBelowOrigChain(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performIntrinsicWOChainCombine(), and UpdateNodeOperands().
Definition at line 10538 of file SelectionDAG.cpp.
References assert(), N, and updateDivergence().
Definition at line 10567 of file SelectionDAG.cpp.
References N, and UpdateNodeOperands().
SDNode * SelectionDAG::UpdateNodeOperands | ( | SDNode * | N, |
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3, | ||
SDValue | Op4 | ||
) |
Definition at line 10573 of file SelectionDAG.cpp.
References N, and UpdateNodeOperands().
SDNode * SelectionDAG::UpdateNodeOperands | ( | SDNode * | N, |
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3, | ||
SDValue | Op4, | ||
SDValue | Op5 | ||
) |
Definition at line 10580 of file SelectionDAG.cpp.
References N, and UpdateNodeOperands().
void SelectionDAG::VerifyDAGDivergence | ( | ) |
Definition at line 11677 of file SelectionDAG.cpp.
References assert(), calculateDivergence(), and N.
void SelectionDAG::viewGraph | ( | ) |
Definition at line 159 of file SelectionDAGPrinter.cpp.
References viewGraph().
Referenced by viewGraph().
void SelectionDAG::viewGraph | ( | const std::string & | Title | ) |
Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'.
Definition at line 146 of file SelectionDAGPrinter.cpp.
References llvm::errs(), getMachineFunction(), getName(), and llvm::ViewGraph().
Widen the vector up to the next power of two using INSERT_SUBVECTOR.
Definition at line 12740 of file SelectionDAG.cpp.
References DL, getContext(), getNode(), getUNDEF(), llvm::EVT::getVectorElementType(), getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INSERT_SUBVECTOR, N, and llvm::NextPowerOf2().
Determine if the result of the addition of 2 nodes can never overflow.
Definition at line 1973 of file SelectionDAG.h.
References computeOverflowForAdd(), and OFK_Never.
Referenced by combineAdd(), combineShiftToAVG(), and promoteExtBeforeAdd().
Determine if the result of the mul of 2 nodes can never overflow.
Definition at line 2009 of file SelectionDAG.h.
References computeOverflowForMul(), and OFK_Never.
Determine if the result of the sub of 2 nodes can never overflow.
Definition at line 1991 of file SelectionDAG.h.
References computeOverflowForSub(), and OFK_Never.
Referenced by llvm::TargetLowering::expandABD().
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friend |
DAGUpdateListener is a friend so it can manipulate the listener stack.
Definition at line 394 of file SelectionDAG.h.
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staticconstexpr |
Definition at line 451 of file SelectionDAG.h.
Referenced by collectInstructionDeps(), combineBitcastToBoolVector(), computeKnownBits(), ComputeNumSignBits(), llvm::TargetLowering::getNegatedExpression(), llvm::PPCTargetLowering::getNegatedExpression(), getShuffleScalarElt(), getTargetShuffleInputs(), getUsefulBits(), llvm::RISCVDAGToDAGISel::hasAllNBitUsers(), isFNEG(), isGuaranteedNotToBeUndefOrPoison(), isKnownNeverNaN(), isKnownNeverZero(), isKnownToBeAPowerOfTwo(), isSplatValue(), PromoteMaskArithmetic(), llvm::SelectionDAGBuilder::shouldKeepJumpConditionsTogether(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), and takeInexpensiveLog2().
bool llvm::SelectionDAG::NewNodesMustHaveLegalTypes = false |
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG nodes that have legal types.
This is important after type legalization since any illegally typed nodes generated after this point will not experience type legalization.
Definition at line 390 of file SelectionDAG.h.
Referenced by combineBinOpOfExtractToReduceTree(), FoldConstantArithmetic(), getConstant(), and getNode().