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FunctionLoweringInfo.cpp
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00001 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This implements routines for translating functions from LLVM IR into
00011 // Machine IR.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "llvm/CodeGen/FunctionLoweringInfo.h"
00016 #include "llvm/ADT/PostOrderIterator.h"
00017 #include "llvm/CodeGen/Analysis.h"
00018 #include "llvm/CodeGen/MachineFrameInfo.h"
00019 #include "llvm/CodeGen/MachineFunction.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/MachineModuleInfo.h"
00022 #include "llvm/CodeGen/MachineRegisterInfo.h"
00023 #include "llvm/CodeGen/WinEHFuncInfo.h"
00024 #include "llvm/IR/DataLayout.h"
00025 #include "llvm/IR/DebugInfo.h"
00026 #include "llvm/IR/DerivedTypes.h"
00027 #include "llvm/IR/Function.h"
00028 #include "llvm/IR/Instructions.h"
00029 #include "llvm/IR/IntrinsicInst.h"
00030 #include "llvm/IR/LLVMContext.h"
00031 #include "llvm/IR/Module.h"
00032 #include "llvm/Support/Debug.h"
00033 #include "llvm/Support/ErrorHandling.h"
00034 #include "llvm/Support/MathExtras.h"
00035 #include "llvm/Support/raw_ostream.h"
00036 #include "llvm/Target/TargetFrameLowering.h"
00037 #include "llvm/Target/TargetInstrInfo.h"
00038 #include "llvm/Target/TargetLowering.h"
00039 #include "llvm/Target/TargetOptions.h"
00040 #include "llvm/Target/TargetRegisterInfo.h"
00041 #include "llvm/Target/TargetSubtargetInfo.h"
00042 #include <algorithm>
00043 using namespace llvm;
00044 
00045 #define DEBUG_TYPE "function-lowering-info"
00046 
00047 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
00048 /// PHI nodes or outside of the basic block that defines it, or used by a
00049 /// switch or atomic instruction, which may expand to multiple basic blocks.
00050 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
00051   if (I->use_empty()) return false;
00052   if (isa<PHINode>(I)) return true;
00053   const BasicBlock *BB = I->getParent();
00054   for (const User *U : I->users())
00055     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
00056       return true;
00057 
00058   return false;
00059 }
00060 
00061 static ISD::NodeType getPreferredExtendForValue(const Value *V) {
00062   // For the users of the source value being used for compare instruction, if
00063   // the number of signed predicate is greater than unsigned predicate, we
00064   // prefer to use SIGN_EXTEND.
00065   //
00066   // With this optimization, we would be able to reduce some redundant sign or
00067   // zero extension instruction, and eventually more machine CSE opportunities
00068   // can be exposed.
00069   ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
00070   unsigned NumOfSigned = 0, NumOfUnsigned = 0;
00071   for (const User *U : V->users()) {
00072     if (const auto *CI = dyn_cast<CmpInst>(U)) {
00073       NumOfSigned += CI->isSigned();
00074       NumOfUnsigned += CI->isUnsigned();
00075     }
00076   }
00077   if (NumOfSigned > NumOfUnsigned)
00078     ExtendKind = ISD::SIGN_EXTEND;
00079 
00080   return ExtendKind;
00081 }
00082 
00083 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
00084                                SelectionDAG *DAG) {
00085   Fn = &fn;
00086   MF = &mf;
00087   TLI = MF->getSubtarget().getTargetLowering();
00088   RegInfo = &MF->getRegInfo();
00089   MachineModuleInfo &MMI = MF->getMMI();
00090 
00091   // Check whether the function can return without sret-demotion.
00092   SmallVector<ISD::OutputArg, 4> Outs;
00093   GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
00094   CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
00095                                        Fn->isVarArg(), Outs, Fn->getContext());
00096 
00097   // Initialize the mapping of values to registers.  This is only set up for
00098   // instruction values that are used outside of the block that defines
00099   // them.
00100   Function::const_iterator BB = Fn->begin(), EB = Fn->end();
00101   for (; BB != EB; ++BB)
00102     for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
00103          I != E; ++I) {
00104       if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
00105         // Static allocas can be folded into the initial stack frame adjustment.
00106         if (AI->isStaticAlloca()) {
00107           const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
00108           Type *Ty = AI->getAllocatedType();
00109           uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
00110           unsigned Align =
00111               std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
00112                        AI->getAlignment());
00113 
00114           TySize *= CUI->getZExtValue();   // Get total allocated size.
00115           if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
00116 
00117           StaticAllocaMap[AI] =
00118             MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
00119 
00120         } else {
00121           unsigned Align = std::max(
00122               (unsigned)TLI->getDataLayout()->getPrefTypeAlignment(
00123                 AI->getAllocatedType()),
00124               AI->getAlignment());
00125           unsigned StackAlign =
00126               MF->getSubtarget().getFrameLowering()->getStackAlignment();
00127           if (Align <= StackAlign)
00128             Align = 0;
00129           // Inform the Frame Information that we have variable-sized objects.
00130           MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
00131         }
00132       }
00133 
00134       // Look for inline asm that clobbers the SP register.
00135       if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
00136         ImmutableCallSite CS(I);
00137         if (isa<InlineAsm>(CS.getCalledValue())) {
00138           unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
00139           const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00140           std::vector<TargetLowering::AsmOperandInfo> Ops =
00141               TLI->ParseConstraints(TRI, CS);
00142           for (size_t I = 0, E = Ops.size(); I != E; ++I) {
00143             TargetLowering::AsmOperandInfo &Op = Ops[I];
00144             if (Op.Type == InlineAsm::isClobber) {
00145               // Clobbers don't have SDValue operands, hence SDValue().
00146               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
00147               std::pair<unsigned, const TargetRegisterClass *> PhysReg =
00148                   TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
00149                                                     Op.ConstraintVT);
00150               if (PhysReg.first == SP)
00151                 MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
00152             }
00153           }
00154         }
00155       }
00156 
00157       // Look for calls to the @llvm.va_start intrinsic. We can omit some
00158       // prologue boilerplate for variadic functions that don't examine their
00159       // arguments.
00160       if (const auto *II = dyn_cast<IntrinsicInst>(I)) {
00161         if (II->getIntrinsicID() == Intrinsic::vastart)
00162           MF->getFrameInfo()->setHasVAStart(true);
00163       }
00164 
00165       // If we have a musttail call in a variadic funciton, we need to ensure we
00166       // forward implicit register parameters.
00167       if (const auto *CI = dyn_cast<CallInst>(I)) {
00168         if (CI->isMustTailCall() && Fn->isVarArg())
00169           MF->getFrameInfo()->setHasMustTailInVarArgFunc(true);
00170       }
00171 
00172       // Mark values used outside their block as exported, by allocating
00173       // a virtual register for them.
00174       if (isUsedOutsideOfDefiningBlock(I))
00175         if (!isa<AllocaInst>(I) ||
00176             !StaticAllocaMap.count(cast<AllocaInst>(I)))
00177           InitializeRegForValue(I);
00178 
00179       // Collect llvm.dbg.declare information. This is done now instead of
00180       // during the initial isel pass through the IR so that it is done
00181       // in a predictable order.
00182       if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
00183         assert(DI->getVariable() && "Missing variable");
00184         assert(DI->getDebugLoc() && "Missing location");
00185         if (MMI.hasDebugInfo()) {
00186           // Don't handle byval struct arguments or VLAs, for example.
00187           // Non-byval arguments are handled here (they refer to the stack
00188           // temporary alloca at this point).
00189           const Value *Address = DI->getAddress();
00190           if (Address) {
00191             if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
00192               Address = BCI->getOperand(0);
00193             if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
00194               DenseMap<const AllocaInst *, int>::iterator SI =
00195                 StaticAllocaMap.find(AI);
00196               if (SI != StaticAllocaMap.end()) { // Check for VLAs.
00197                 int FI = SI->second;
00198                 MMI.setVariableDbgInfo(DI->getVariable(), DI->getExpression(),
00199                                        FI, DI->getDebugLoc());
00200               }
00201             }
00202           }
00203         }
00204       }
00205 
00206       // Decide the preferred extend type for a value.
00207       PreferredExtendType[I] = getPreferredExtendForValue(I);
00208     }
00209 
00210   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
00211   // also creates the initial PHI MachineInstrs, though none of the input
00212   // operands are populated.
00213   for (BB = Fn->begin(); BB != EB; ++BB) {
00214     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
00215     MBBMap[BB] = MBB;
00216     MF->push_back(MBB);
00217 
00218     // Transfer the address-taken flag. This is necessary because there could
00219     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
00220     // the first one should be marked.
00221     if (BB->hasAddressTaken())
00222       MBB->setHasAddressTaken();
00223 
00224     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
00225     // appropriate.
00226     for (BasicBlock::const_iterator I = BB->begin();
00227          const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
00228       if (PN->use_empty()) continue;
00229 
00230       // Skip empty types
00231       if (PN->getType()->isEmptyTy())
00232         continue;
00233 
00234       DebugLoc DL = PN->getDebugLoc();
00235       unsigned PHIReg = ValueMap[PN];
00236       assert(PHIReg && "PHI node does not have an assigned virtual register!");
00237 
00238       SmallVector<EVT, 4> ValueVTs;
00239       ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
00240       for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
00241         EVT VT = ValueVTs[vti];
00242         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
00243         const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
00244         for (unsigned i = 0; i != NumRegisters; ++i)
00245           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
00246         PHIReg += NumRegisters;
00247       }
00248     }
00249   }
00250 
00251   // Mark landing pad blocks.
00252   SmallVector<const LandingPadInst *, 4> LPads;
00253   for (BB = Fn->begin(); BB != EB; ++BB) {
00254     if (const auto *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
00255       MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
00256     if (BB->isLandingPad())
00257       LPads.push_back(BB->getLandingPadInst());
00258   }
00259 
00260   // If this is an MSVC EH personality, we need to do a bit more work.
00261   EHPersonality Personality = EHPersonality::Unknown;
00262   if (Fn->hasPersonalityFn())
00263     Personality = classifyEHPersonality(Fn->getPersonalityFn());
00264   if (!isMSVCEHPersonality(Personality))
00265     return;
00266 
00267   if (Personality == EHPersonality::MSVC_Win64SEH ||
00268       Personality == EHPersonality::MSVC_X86SEH) {
00269     addSEHHandlersForLPads(LPads);
00270   }
00271 
00272   WinEHFuncInfo &EHInfo = MMI.getWinEHFuncInfo(&fn);
00273   if (Personality == EHPersonality::MSVC_CXX) {
00274     const Function *WinEHParentFn = MMI.getWinEHParent(&fn);
00275     calculateWinCXXEHStateNumbers(WinEHParentFn, EHInfo);
00276   }
00277 
00278   // Copy the state numbers to LandingPadInfo for the current function, which
00279   // could be a handler or the parent. This should happen for 32-bit SEH and
00280   // C++ EH.
00281   if (Personality == EHPersonality::MSVC_CXX ||
00282       Personality == EHPersonality::MSVC_X86SEH) {
00283     for (const LandingPadInst *LP : LPads) {
00284       MachineBasicBlock *LPadMBB = MBBMap[LP->getParent()];
00285       MMI.addWinEHState(LPadMBB, EHInfo.LandingPadStateMap[LP]);
00286     }
00287   }
00288 }
00289 
00290 void FunctionLoweringInfo::addSEHHandlersForLPads(
00291     ArrayRef<const LandingPadInst *> LPads) {
00292   MachineModuleInfo &MMI = MF->getMMI();
00293 
00294   // Iterate over all landing pads with llvm.eh.actions calls.
00295   for (const LandingPadInst *LP : LPads) {
00296     const IntrinsicInst *ActionsCall =
00297         dyn_cast<IntrinsicInst>(LP->getNextNode());
00298     if (!ActionsCall ||
00299         ActionsCall->getIntrinsicID() != Intrinsic::eh_actions)
00300       continue;
00301 
00302     // Parse the llvm.eh.actions call we found.
00303     MachineBasicBlock *LPadMBB = MBBMap[LP->getParent()];
00304     SmallVector<std::unique_ptr<ActionHandler>, 4> Actions;
00305     parseEHActions(ActionsCall, Actions);
00306 
00307     // Iterate EH actions from most to least precedence, which means
00308     // iterating in reverse.
00309     for (auto I = Actions.rbegin(), E = Actions.rend(); I != E; ++I) {
00310       ActionHandler *Action = I->get();
00311       if (auto *CH = dyn_cast<CatchHandler>(Action)) {
00312         const auto *Filter =
00313             dyn_cast<Function>(CH->getSelector()->stripPointerCasts());
00314         assert((Filter || CH->getSelector()->isNullValue()) &&
00315                "expected function or catch-all");
00316         const auto *RecoverBA =
00317             cast<BlockAddress>(CH->getHandlerBlockOrFunc());
00318         MMI.addSEHCatchHandler(LPadMBB, Filter, RecoverBA);
00319       } else {
00320         assert(isa<CleanupHandler>(Action));
00321         const auto *Fini = cast<Function>(Action->getHandlerBlockOrFunc());
00322         MMI.addSEHCleanupHandler(LPadMBB, Fini);
00323       }
00324     }
00325   }
00326 }
00327 
00328 /// clear - Clear out all the function-specific state. This returns this
00329 /// FunctionLoweringInfo to an empty state, ready to be used for a
00330 /// different function.
00331 void FunctionLoweringInfo::clear() {
00332   assert(CatchInfoFound.size() == CatchInfoLost.size() &&
00333          "Not all catch info was assigned to a landing pad!");
00334 
00335   MBBMap.clear();
00336   ValueMap.clear();
00337   StaticAllocaMap.clear();
00338 #ifndef NDEBUG
00339   CatchInfoLost.clear();
00340   CatchInfoFound.clear();
00341 #endif
00342   LiveOutRegInfo.clear();
00343   VisitedBBs.clear();
00344   ArgDbgValues.clear();
00345   ByValArgFrameIndexMap.clear();
00346   RegFixups.clear();
00347   StatepointStackSlots.clear();
00348   StatepointRelocatedValues.clear();
00349   PreferredExtendType.clear();
00350 }
00351 
00352 /// CreateReg - Allocate a single virtual register for the given type.
00353 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
00354   return RegInfo->createVirtualRegister(
00355       MF->getSubtarget().getTargetLowering()->getRegClassFor(VT));
00356 }
00357 
00358 /// CreateRegs - Allocate the appropriate number of virtual registers of
00359 /// the correctly promoted or expanded types.  Assign these registers
00360 /// consecutive vreg numbers and return the first assigned number.
00361 ///
00362 /// In the case that the given value has struct or array type, this function
00363 /// will assign registers for each member or element.
00364 ///
00365 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
00366   const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
00367 
00368   SmallVector<EVT, 4> ValueVTs;
00369   ComputeValueVTs(*TLI, Ty, ValueVTs);
00370 
00371   unsigned FirstReg = 0;
00372   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
00373     EVT ValueVT = ValueVTs[Value];
00374     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
00375 
00376     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
00377     for (unsigned i = 0; i != NumRegs; ++i) {
00378       unsigned R = CreateReg(RegisterVT);
00379       if (!FirstReg) FirstReg = R;
00380     }
00381   }
00382   return FirstReg;
00383 }
00384 
00385 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
00386 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
00387 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
00388 /// the larger bit width by zero extension. The bit width must be no smaller
00389 /// than the LiveOutInfo's existing bit width.
00390 const FunctionLoweringInfo::LiveOutInfo *
00391 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
00392   if (!LiveOutRegInfo.inBounds(Reg))
00393     return nullptr;
00394 
00395   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
00396   if (!LOI->IsValid)
00397     return nullptr;
00398 
00399   if (BitWidth > LOI->KnownZero.getBitWidth()) {
00400     LOI->NumSignBits = 1;
00401     LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
00402     LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
00403   }
00404 
00405   return LOI;
00406 }
00407 
00408 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
00409 /// register based on the LiveOutInfo of its operands.
00410 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
00411   Type *Ty = PN->getType();
00412   if (!Ty->isIntegerTy() || Ty->isVectorTy())
00413     return;
00414 
00415   SmallVector<EVT, 1> ValueVTs;
00416   ComputeValueVTs(*TLI, Ty, ValueVTs);
00417   assert(ValueVTs.size() == 1 &&
00418          "PHIs with non-vector integer types should have a single VT.");
00419   EVT IntVT = ValueVTs[0];
00420 
00421   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
00422     return;
00423   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
00424   unsigned BitWidth = IntVT.getSizeInBits();
00425 
00426   unsigned DestReg = ValueMap[PN];
00427   if (!TargetRegisterInfo::isVirtualRegister(DestReg))
00428     return;
00429   LiveOutRegInfo.grow(DestReg);
00430   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
00431 
00432   Value *V = PN->getIncomingValue(0);
00433   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00434     DestLOI.NumSignBits = 1;
00435     APInt Zero(BitWidth, 0);
00436     DestLOI.KnownZero = Zero;
00437     DestLOI.KnownOne = Zero;
00438     return;
00439   }
00440 
00441   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00442     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00443     DestLOI.NumSignBits = Val.getNumSignBits();
00444     DestLOI.KnownZero = ~Val;
00445     DestLOI.KnownOne = Val;
00446   } else {
00447     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
00448                                 "CopyToReg node was created.");
00449     unsigned SrcReg = ValueMap[V];
00450     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00451       DestLOI.IsValid = false;
00452       return;
00453     }
00454     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00455     if (!SrcLOI) {
00456       DestLOI.IsValid = false;
00457       return;
00458     }
00459     DestLOI = *SrcLOI;
00460   }
00461 
00462   assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
00463          DestLOI.KnownOne.getBitWidth() == BitWidth &&
00464          "Masks should have the same bit width as the type.");
00465 
00466   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
00467     Value *V = PN->getIncomingValue(i);
00468     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00469       DestLOI.NumSignBits = 1;
00470       APInt Zero(BitWidth, 0);
00471       DestLOI.KnownZero = Zero;
00472       DestLOI.KnownOne = Zero;
00473       return;
00474     }
00475 
00476     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00477       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00478       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
00479       DestLOI.KnownZero &= ~Val;
00480       DestLOI.KnownOne &= Val;
00481       continue;
00482     }
00483 
00484     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
00485                                 "its CopyToReg node was created.");
00486     unsigned SrcReg = ValueMap[V];
00487     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00488       DestLOI.IsValid = false;
00489       return;
00490     }
00491     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00492     if (!SrcLOI) {
00493       DestLOI.IsValid = false;
00494       return;
00495     }
00496     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
00497     DestLOI.KnownZero &= SrcLOI->KnownZero;
00498     DestLOI.KnownOne &= SrcLOI->KnownOne;
00499   }
00500 }
00501 
00502 /// setArgumentFrameIndex - Record frame index for the byval
00503 /// argument. This overrides previous frame index entry for this argument,
00504 /// if any.
00505 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
00506                                                  int FI) {
00507   ByValArgFrameIndexMap[A] = FI;
00508 }
00509 
00510 /// getArgumentFrameIndex - Get frame index for the byval argument.
00511 /// If the argument does not have any assigned frame index then 0 is
00512 /// returned.
00513 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
00514   DenseMap<const Argument *, int>::iterator I =
00515     ByValArgFrameIndexMap.find(A);
00516   if (I != ByValArgFrameIndexMap.end())
00517     return I->second;
00518   DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
00519   return 0;
00520 }
00521 
00522 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
00523 /// being passed to this variadic function, and set the MachineModuleInfo's
00524 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
00525 /// reference to _fltused on Windows, which will link in MSVCRT's
00526 /// floating-point support.
00527 void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
00528                                       MachineModuleInfo *MMI)
00529 {
00530   FunctionType *FT = cast<FunctionType>(
00531     I.getCalledValue()->getType()->getContainedType(0));
00532   if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
00533     for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
00534       Type* T = I.getArgOperand(i)->getType();
00535       for (auto i : post_order(T)) {
00536         if (i->isFloatingPointTy()) {
00537           MMI->setUsesVAFloatArgument(true);
00538           return;
00539         }
00540       }
00541     }
00542   }
00543 }
00544 
00545 /// AddLandingPadInfo - Extract the exception handling information from the
00546 /// landingpad instruction and add them to the specified machine module info.
00547 void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
00548                              MachineBasicBlock *MBB) {
00549   MMI.addPersonality(
00550       MBB,
00551       cast<Function>(
00552           I.getParent()->getParent()->getPersonalityFn()->stripPointerCasts()));
00553 
00554   if (I.isCleanup())
00555     MMI.addCleanup(MBB);
00556 
00557   // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
00558   //        but we need to do it this way because of how the DWARF EH emitter
00559   //        processes the clauses.
00560   for (unsigned i = I.getNumClauses(); i != 0; --i) {
00561     Value *Val = I.getClause(i - 1);
00562     if (I.isCatch(i - 1)) {
00563       MMI.addCatchTypeInfo(MBB,
00564                            dyn_cast<GlobalValue>(Val->stripPointerCasts()));
00565     } else {
00566       // Add filters in a list.
00567       Constant *CVal = cast<Constant>(Val);
00568       SmallVector<const GlobalValue*, 4> FilterList;
00569       for (User::op_iterator
00570              II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
00571         FilterList.push_back(cast<GlobalValue>((*II)->stripPointerCasts()));
00572 
00573       MMI.addFilterTypeInfo(MBB, FilterList);
00574     }
00575   }
00576 }