LLVM API Documentation

FunctionLoweringInfo.cpp
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00001 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This implements routines for translating functions from LLVM IR into
00011 // Machine IR.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "llvm/CodeGen/FunctionLoweringInfo.h"
00016 #include "llvm/ADT/PostOrderIterator.h"
00017 #include "llvm/CodeGen/Analysis.h"
00018 #include "llvm/CodeGen/MachineFrameInfo.h"
00019 #include "llvm/CodeGen/MachineFunction.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/MachineModuleInfo.h"
00022 #include "llvm/CodeGen/MachineRegisterInfo.h"
00023 #include "llvm/IR/DataLayout.h"
00024 #include "llvm/IR/DebugInfo.h"
00025 #include "llvm/IR/DerivedTypes.h"
00026 #include "llvm/IR/Function.h"
00027 #include "llvm/IR/Instructions.h"
00028 #include "llvm/IR/IntrinsicInst.h"
00029 #include "llvm/IR/LLVMContext.h"
00030 #include "llvm/IR/Module.h"
00031 #include "llvm/Support/Debug.h"
00032 #include "llvm/Support/ErrorHandling.h"
00033 #include "llvm/Support/MathExtras.h"
00034 #include "llvm/Target/TargetFrameLowering.h"
00035 #include "llvm/Target/TargetInstrInfo.h"
00036 #include "llvm/Target/TargetLowering.h"
00037 #include "llvm/Target/TargetOptions.h"
00038 #include "llvm/Target/TargetRegisterInfo.h"
00039 #include "llvm/Target/TargetSubtargetInfo.h"
00040 #include <algorithm>
00041 using namespace llvm;
00042 
00043 #define DEBUG_TYPE "function-lowering-info"
00044 
00045 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
00046 /// PHI nodes or outside of the basic block that defines it, or used by a
00047 /// switch or atomic instruction, which may expand to multiple basic blocks.
00048 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
00049   if (I->use_empty()) return false;
00050   if (isa<PHINode>(I)) return true;
00051   const BasicBlock *BB = I->getParent();
00052   for (const User *U : I->users())
00053     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
00054       return true;
00055 
00056   return false;
00057 }
00058 
00059 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
00060                                SelectionDAG *DAG) {
00061   const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
00062 
00063   Fn = &fn;
00064   MF = &mf;
00065   RegInfo = &MF->getRegInfo();
00066 
00067   // Check whether the function can return without sret-demotion.
00068   SmallVector<ISD::OutputArg, 4> Outs;
00069   GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
00070   CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
00071                                        Fn->isVarArg(),
00072                                        Outs, Fn->getContext());
00073 
00074   // Initialize the mapping of values to registers.  This is only set up for
00075   // instruction values that are used outside of the block that defines
00076   // them.
00077   Function::const_iterator BB = Fn->begin(), EB = Fn->end();
00078   for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
00079     if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
00080       // Don't fold inalloca allocas or other dynamic allocas into the initial
00081       // stack frame allocation, even if they are in the entry block.
00082       if (!AI->isStaticAlloca())
00083         continue;
00084 
00085       if (const ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
00086         Type *Ty = AI->getAllocatedType();
00087         uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
00088         unsigned Align =
00089           std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
00090                    AI->getAlignment());
00091 
00092         TySize *= CUI->getZExtValue();   // Get total allocated size.
00093         if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
00094 
00095         StaticAllocaMap[AI] =
00096           MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
00097       }
00098     }
00099 
00100   for (; BB != EB; ++BB)
00101     for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
00102          I != E; ++I) {
00103       // Look for dynamic allocas.
00104       if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
00105         if (!AI->isStaticAlloca()) {
00106           unsigned Align = std::max(
00107               (unsigned)TLI->getDataLayout()->getPrefTypeAlignment(
00108                 AI->getAllocatedType()),
00109               AI->getAlignment());
00110           unsigned StackAlign =
00111               TM.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
00112           if (Align <= StackAlign)
00113             Align = 0;
00114           // Inform the Frame Information that we have variable-sized objects.
00115           MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
00116         }
00117       }
00118 
00119       // Look for inline asm that clobbers the SP register.
00120       if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
00121         ImmutableCallSite CS(I);
00122         if (isa<InlineAsm>(CS.getCalledValue())) {
00123           unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
00124           std::vector<TargetLowering::AsmOperandInfo> Ops =
00125             TLI->ParseConstraints(CS);
00126           for (size_t I = 0, E = Ops.size(); I != E; ++I) {
00127             TargetLowering::AsmOperandInfo &Op = Ops[I];
00128             if (Op.Type == InlineAsm::isClobber) {
00129               // Clobbers don't have SDValue operands, hence SDValue().
00130               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
00131               std::pair<unsigned, const TargetRegisterClass*> PhysReg =
00132                 TLI->getRegForInlineAsmConstraint(Op.ConstraintCode,
00133                                                   Op.ConstraintVT);
00134               if (PhysReg.first == SP)
00135                 MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
00136             }
00137           }
00138         }
00139       }
00140 
00141       // Mark values used outside their block as exported, by allocating
00142       // a virtual register for them.
00143       if (isUsedOutsideOfDefiningBlock(I))
00144         if (!isa<AllocaInst>(I) ||
00145             !StaticAllocaMap.count(cast<AllocaInst>(I)))
00146           InitializeRegForValue(I);
00147 
00148       // Collect llvm.dbg.declare information. This is done now instead of
00149       // during the initial isel pass through the IR so that it is done
00150       // in a predictable order.
00151       if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
00152         MachineModuleInfo &MMI = MF->getMMI();
00153         DIVariable DIVar(DI->getVariable());
00154         assert((!DIVar || DIVar.isVariable()) &&
00155           "Variable in DbgDeclareInst should be either null or a DIVariable.");
00156         if (MMI.hasDebugInfo() &&
00157             DIVar &&
00158             !DI->getDebugLoc().isUnknown()) {
00159           // Don't handle byval struct arguments or VLAs, for example.
00160           // Non-byval arguments are handled here (they refer to the stack
00161           // temporary alloca at this point).
00162           const Value *Address = DI->getAddress();
00163           if (Address) {
00164             if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
00165               Address = BCI->getOperand(0);
00166             if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
00167               DenseMap<const AllocaInst *, int>::iterator SI =
00168                 StaticAllocaMap.find(AI);
00169               if (SI != StaticAllocaMap.end()) { // Check for VLAs.
00170                 int FI = SI->second;
00171                 MMI.setVariableDbgInfo(DI->getVariable(),
00172                                        FI, DI->getDebugLoc());
00173               }
00174             }
00175           }
00176         }
00177       }
00178     }
00179 
00180   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
00181   // also creates the initial PHI MachineInstrs, though none of the input
00182   // operands are populated.
00183   for (BB = Fn->begin(); BB != EB; ++BB) {
00184     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
00185     MBBMap[BB] = MBB;
00186     MF->push_back(MBB);
00187 
00188     // Transfer the address-taken flag. This is necessary because there could
00189     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
00190     // the first one should be marked.
00191     if (BB->hasAddressTaken())
00192       MBB->setHasAddressTaken();
00193 
00194     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
00195     // appropriate.
00196     for (BasicBlock::const_iterator I = BB->begin();
00197          const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
00198       if (PN->use_empty()) continue;
00199 
00200       // Skip empty types
00201       if (PN->getType()->isEmptyTy())
00202         continue;
00203 
00204       DebugLoc DL = PN->getDebugLoc();
00205       unsigned PHIReg = ValueMap[PN];
00206       assert(PHIReg && "PHI node does not have an assigned virtual register!");
00207 
00208       SmallVector<EVT, 4> ValueVTs;
00209       ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
00210       for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
00211         EVT VT = ValueVTs[vti];
00212         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
00213         const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
00214         for (unsigned i = 0; i != NumRegisters; ++i)
00215           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
00216         PHIReg += NumRegisters;
00217       }
00218     }
00219   }
00220 
00221   // Mark landing pad blocks.
00222   for (BB = Fn->begin(); BB != EB; ++BB)
00223     if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
00224       MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
00225 }
00226 
00227 /// clear - Clear out all the function-specific state. This returns this
00228 /// FunctionLoweringInfo to an empty state, ready to be used for a
00229 /// different function.
00230 void FunctionLoweringInfo::clear() {
00231   assert(CatchInfoFound.size() == CatchInfoLost.size() &&
00232          "Not all catch info was assigned to a landing pad!");
00233 
00234   MBBMap.clear();
00235   ValueMap.clear();
00236   StaticAllocaMap.clear();
00237 #ifndef NDEBUG
00238   CatchInfoLost.clear();
00239   CatchInfoFound.clear();
00240 #endif
00241   LiveOutRegInfo.clear();
00242   VisitedBBs.clear();
00243   ArgDbgValues.clear();
00244   ByValArgFrameIndexMap.clear();
00245   RegFixups.clear();
00246 }
00247 
00248 /// CreateReg - Allocate a single virtual register for the given type.
00249 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
00250   return RegInfo->createVirtualRegister(
00251       TM.getSubtargetImpl()->getTargetLowering()->getRegClassFor(VT));
00252 }
00253 
00254 /// CreateRegs - Allocate the appropriate number of virtual registers of
00255 /// the correctly promoted or expanded types.  Assign these registers
00256 /// consecutive vreg numbers and return the first assigned number.
00257 ///
00258 /// In the case that the given value has struct or array type, this function
00259 /// will assign registers for each member or element.
00260 ///
00261 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
00262   const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
00263 
00264   SmallVector<EVT, 4> ValueVTs;
00265   ComputeValueVTs(*TLI, Ty, ValueVTs);
00266 
00267   unsigned FirstReg = 0;
00268   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
00269     EVT ValueVT = ValueVTs[Value];
00270     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
00271 
00272     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
00273     for (unsigned i = 0; i != NumRegs; ++i) {
00274       unsigned R = CreateReg(RegisterVT);
00275       if (!FirstReg) FirstReg = R;
00276     }
00277   }
00278   return FirstReg;
00279 }
00280 
00281 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
00282 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
00283 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
00284 /// the larger bit width by zero extension. The bit width must be no smaller
00285 /// than the LiveOutInfo's existing bit width.
00286 const FunctionLoweringInfo::LiveOutInfo *
00287 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
00288   if (!LiveOutRegInfo.inBounds(Reg))
00289     return nullptr;
00290 
00291   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
00292   if (!LOI->IsValid)
00293     return nullptr;
00294 
00295   if (BitWidth > LOI->KnownZero.getBitWidth()) {
00296     LOI->NumSignBits = 1;
00297     LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
00298     LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
00299   }
00300 
00301   return LOI;
00302 }
00303 
00304 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
00305 /// register based on the LiveOutInfo of its operands.
00306 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
00307   Type *Ty = PN->getType();
00308   if (!Ty->isIntegerTy() || Ty->isVectorTy())
00309     return;
00310 
00311   const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
00312 
00313   SmallVector<EVT, 1> ValueVTs;
00314   ComputeValueVTs(*TLI, Ty, ValueVTs);
00315   assert(ValueVTs.size() == 1 &&
00316          "PHIs with non-vector integer types should have a single VT.");
00317   EVT IntVT = ValueVTs[0];
00318 
00319   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
00320     return;
00321   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
00322   unsigned BitWidth = IntVT.getSizeInBits();
00323 
00324   unsigned DestReg = ValueMap[PN];
00325   if (!TargetRegisterInfo::isVirtualRegister(DestReg))
00326     return;
00327   LiveOutRegInfo.grow(DestReg);
00328   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
00329 
00330   Value *V = PN->getIncomingValue(0);
00331   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00332     DestLOI.NumSignBits = 1;
00333     APInt Zero(BitWidth, 0);
00334     DestLOI.KnownZero = Zero;
00335     DestLOI.KnownOne = Zero;
00336     return;
00337   }
00338 
00339   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00340     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00341     DestLOI.NumSignBits = Val.getNumSignBits();
00342     DestLOI.KnownZero = ~Val;
00343     DestLOI.KnownOne = Val;
00344   } else {
00345     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
00346                                 "CopyToReg node was created.");
00347     unsigned SrcReg = ValueMap[V];
00348     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00349       DestLOI.IsValid = false;
00350       return;
00351     }
00352     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00353     if (!SrcLOI) {
00354       DestLOI.IsValid = false;
00355       return;
00356     }
00357     DestLOI = *SrcLOI;
00358   }
00359 
00360   assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
00361          DestLOI.KnownOne.getBitWidth() == BitWidth &&
00362          "Masks should have the same bit width as the type.");
00363 
00364   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
00365     Value *V = PN->getIncomingValue(i);
00366     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00367       DestLOI.NumSignBits = 1;
00368       APInt Zero(BitWidth, 0);
00369       DestLOI.KnownZero = Zero;
00370       DestLOI.KnownOne = Zero;
00371       return;
00372     }
00373 
00374     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00375       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00376       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
00377       DestLOI.KnownZero &= ~Val;
00378       DestLOI.KnownOne &= Val;
00379       continue;
00380     }
00381 
00382     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
00383                                 "its CopyToReg node was created.");
00384     unsigned SrcReg = ValueMap[V];
00385     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00386       DestLOI.IsValid = false;
00387       return;
00388     }
00389     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00390     if (!SrcLOI) {
00391       DestLOI.IsValid = false;
00392       return;
00393     }
00394     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
00395     DestLOI.KnownZero &= SrcLOI->KnownZero;
00396     DestLOI.KnownOne &= SrcLOI->KnownOne;
00397   }
00398 }
00399 
00400 /// setArgumentFrameIndex - Record frame index for the byval
00401 /// argument. This overrides previous frame index entry for this argument,
00402 /// if any.
00403 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
00404                                                  int FI) {
00405   ByValArgFrameIndexMap[A] = FI;
00406 }
00407 
00408 /// getArgumentFrameIndex - Get frame index for the byval argument.
00409 /// If the argument does not have any assigned frame index then 0 is
00410 /// returned.
00411 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
00412   DenseMap<const Argument *, int>::iterator I =
00413     ByValArgFrameIndexMap.find(A);
00414   if (I != ByValArgFrameIndexMap.end())
00415     return I->second;
00416   DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
00417   return 0;
00418 }
00419 
00420 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
00421 /// being passed to this variadic function, and set the MachineModuleInfo's
00422 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
00423 /// reference to _fltused on Windows, which will link in MSVCRT's
00424 /// floating-point support.
00425 void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
00426                                       MachineModuleInfo *MMI)
00427 {
00428   FunctionType *FT = cast<FunctionType>(
00429     I.getCalledValue()->getType()->getContainedType(0));
00430   if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
00431     for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
00432       Type* T = I.getArgOperand(i)->getType();
00433       for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
00434            i != e; ++i) {
00435         if (i->isFloatingPointTy()) {
00436           MMI->setUsesVAFloatArgument(true);
00437           return;
00438         }
00439       }
00440     }
00441   }
00442 }
00443 
00444 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
00445 /// call, and add them to the specified machine basic block.
00446 void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI,
00447                         MachineBasicBlock *MBB) {
00448   // Inform the MachineModuleInfo of the personality for this landing pad.
00449   const ConstantExpr *CE = cast<ConstantExpr>(I.getArgOperand(1));
00450   assert(CE->getOpcode() == Instruction::BitCast &&
00451          isa<Function>(CE->getOperand(0)) &&
00452          "Personality should be a function");
00453   MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
00454 
00455   // Gather all the type infos for this landing pad and pass them along to
00456   // MachineModuleInfo.
00457   std::vector<const GlobalVariable *> TyInfo;
00458   unsigned N = I.getNumArgOperands();
00459 
00460   for (unsigned i = N - 1; i > 1; --i) {
00461     if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(i))) {
00462       unsigned FilterLength = CI->getZExtValue();
00463       unsigned FirstCatch = i + FilterLength + !FilterLength;
00464       assert(FirstCatch <= N && "Invalid filter length");
00465 
00466       if (FirstCatch < N) {
00467         TyInfo.reserve(N - FirstCatch);
00468         for (unsigned j = FirstCatch; j < N; ++j)
00469           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00470         MMI->addCatchTypeInfo(MBB, TyInfo);
00471         TyInfo.clear();
00472       }
00473 
00474       if (!FilterLength) {
00475         // Cleanup.
00476         MMI->addCleanup(MBB);
00477       } else {
00478         // Filter.
00479         TyInfo.reserve(FilterLength - 1);
00480         for (unsigned j = i + 1; j < FirstCatch; ++j)
00481           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00482         MMI->addFilterTypeInfo(MBB, TyInfo);
00483         TyInfo.clear();
00484       }
00485 
00486       N = i;
00487     }
00488   }
00489 
00490   if (N > 2) {
00491     TyInfo.reserve(N - 2);
00492     for (unsigned j = 2; j < N; ++j)
00493       TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00494     MMI->addCatchTypeInfo(MBB, TyInfo);
00495   }
00496 }
00497 
00498 /// AddLandingPadInfo - Extract the exception handling information from the
00499 /// landingpad instruction and add them to the specified machine module info.
00500 void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
00501                              MachineBasicBlock *MBB) {
00502   MMI.addPersonality(MBB,
00503                      cast<Function>(I.getPersonalityFn()->stripPointerCasts()));
00504 
00505   if (I.isCleanup())
00506     MMI.addCleanup(MBB);
00507 
00508   // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
00509   //        but we need to do it this way because of how the DWARF EH emitter
00510   //        processes the clauses.
00511   for (unsigned i = I.getNumClauses(); i != 0; --i) {
00512     Value *Val = I.getClause(i - 1);
00513     if (I.isCatch(i - 1)) {
00514       MMI.addCatchTypeInfo(MBB,
00515                            dyn_cast<GlobalVariable>(Val->stripPointerCasts()));
00516     } else {
00517       // Add filters in a list.
00518       Constant *CVal = cast<Constant>(Val);
00519       SmallVector<const GlobalVariable*, 4> FilterList;
00520       for (User::op_iterator
00521              II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
00522         FilterList.push_back(cast<GlobalVariable>((*II)->stripPointerCasts()));
00523 
00524       MMI.addFilterTypeInfo(MBB, FilterList);
00525     }
00526   }
00527 }