LLVM API Documentation

FunctionLoweringInfo.cpp
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00001 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This implements routines for translating functions from LLVM IR into
00011 // Machine IR.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "llvm/CodeGen/FunctionLoweringInfo.h"
00016 #include "llvm/ADT/PostOrderIterator.h"
00017 #include "llvm/CodeGen/Analysis.h"
00018 #include "llvm/CodeGen/MachineFrameInfo.h"
00019 #include "llvm/CodeGen/MachineFunction.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/MachineModuleInfo.h"
00022 #include "llvm/CodeGen/MachineRegisterInfo.h"
00023 #include "llvm/IR/DataLayout.h"
00024 #include "llvm/IR/DebugInfo.h"
00025 #include "llvm/IR/DerivedTypes.h"
00026 #include "llvm/IR/Function.h"
00027 #include "llvm/IR/Instructions.h"
00028 #include "llvm/IR/IntrinsicInst.h"
00029 #include "llvm/IR/LLVMContext.h"
00030 #include "llvm/IR/Module.h"
00031 #include "llvm/Support/Debug.h"
00032 #include "llvm/Support/ErrorHandling.h"
00033 #include "llvm/Support/MathExtras.h"
00034 #include "llvm/Target/TargetFrameLowering.h"
00035 #include "llvm/Target/TargetInstrInfo.h"
00036 #include "llvm/Target/TargetLowering.h"
00037 #include "llvm/Target/TargetOptions.h"
00038 #include "llvm/Target/TargetRegisterInfo.h"
00039 #include "llvm/Target/TargetSubtargetInfo.h"
00040 #include <algorithm>
00041 using namespace llvm;
00042 
00043 #define DEBUG_TYPE "function-lowering-info"
00044 
00045 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
00046 /// PHI nodes or outside of the basic block that defines it, or used by a
00047 /// switch or atomic instruction, which may expand to multiple basic blocks.
00048 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
00049   if (I->use_empty()) return false;
00050   if (isa<PHINode>(I)) return true;
00051   const BasicBlock *BB = I->getParent();
00052   for (const User *U : I->users())
00053     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
00054       return true;
00055 
00056   return false;
00057 }
00058 
00059 static ISD::NodeType getPreferredExtendForValue(const Value *V) {
00060   // For the users of the source value being used for compare instruction, if
00061   // the number of signed predicate is greater than unsigned predicate, we
00062   // prefer to use SIGN_EXTEND.
00063   //
00064   // With this optimization, we would be able to reduce some redundant sign or
00065   // zero extension instruction, and eventually more machine CSE opportunities
00066   // can be exposed.
00067   ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
00068   unsigned NumOfSigned = 0, NumOfUnsigned = 0;
00069   for (const User *U : V->users()) {
00070     if (const auto *CI = dyn_cast<CmpInst>(U)) {
00071       NumOfSigned += CI->isSigned();
00072       NumOfUnsigned += CI->isUnsigned();
00073     }
00074   }
00075   if (NumOfSigned > NumOfUnsigned)
00076     ExtendKind = ISD::SIGN_EXTEND;
00077 
00078   return ExtendKind;
00079 }
00080 
00081 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
00082                                SelectionDAG *DAG) {
00083   Fn = &fn;
00084   MF = &mf;
00085   TLI = MF->getSubtarget().getTargetLowering();
00086   RegInfo = &MF->getRegInfo();
00087 
00088   // Check whether the function can return without sret-demotion.
00089   SmallVector<ISD::OutputArg, 4> Outs;
00090   GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
00091   CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
00092                                        Fn->isVarArg(), Outs, Fn->getContext());
00093 
00094   // Initialize the mapping of values to registers.  This is only set up for
00095   // instruction values that are used outside of the block that defines
00096   // them.
00097   Function::const_iterator BB = Fn->begin(), EB = Fn->end();
00098   for (; BB != EB; ++BB)
00099     for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
00100          I != E; ++I) {
00101       if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
00102         // Static allocas can be folded into the initial stack frame adjustment.
00103         if (AI->isStaticAlloca()) {
00104           const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
00105           Type *Ty = AI->getAllocatedType();
00106           uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
00107           unsigned Align =
00108               std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
00109                        AI->getAlignment());
00110 
00111           TySize *= CUI->getZExtValue();   // Get total allocated size.
00112           if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
00113 
00114           StaticAllocaMap[AI] =
00115             MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
00116 
00117         } else {
00118           unsigned Align = std::max(
00119               (unsigned)TLI->getDataLayout()->getPrefTypeAlignment(
00120                 AI->getAllocatedType()),
00121               AI->getAlignment());
00122           unsigned StackAlign =
00123               MF->getSubtarget().getFrameLowering()->getStackAlignment();
00124           if (Align <= StackAlign)
00125             Align = 0;
00126           // Inform the Frame Information that we have variable-sized objects.
00127           MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
00128         }
00129       }
00130 
00131       // Look for inline asm that clobbers the SP register.
00132       if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
00133         ImmutableCallSite CS(I);
00134         if (isa<InlineAsm>(CS.getCalledValue())) {
00135           unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
00136           std::vector<TargetLowering::AsmOperandInfo> Ops =
00137             TLI->ParseConstraints(CS);
00138           for (size_t I = 0, E = Ops.size(); I != E; ++I) {
00139             TargetLowering::AsmOperandInfo &Op = Ops[I];
00140             if (Op.Type == InlineAsm::isClobber) {
00141               // Clobbers don't have SDValue operands, hence SDValue().
00142               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
00143               std::pair<unsigned, const TargetRegisterClass *> PhysReg =
00144                   TLI->getRegForInlineAsmConstraint(Op.ConstraintCode,
00145                                                    Op.ConstraintVT);
00146               if (PhysReg.first == SP)
00147                 MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
00148             }
00149           }
00150         }
00151       }
00152 
00153       // Look for calls to the @llvm.va_start intrinsic. We can omit some
00154       // prologue boilerplate for variadic functions that don't examine their
00155       // arguments.
00156       if (const auto *II = dyn_cast<IntrinsicInst>(I)) {
00157         if (II->getIntrinsicID() == Intrinsic::vastart)
00158           MF->getFrameInfo()->setHasVAStart(true);
00159       }
00160 
00161       // If we have a musttail call in a variadic funciton, we need to ensure we
00162       // forward implicit register parameters.
00163       if (const auto *CI = dyn_cast<CallInst>(I)) {
00164         if (CI->isMustTailCall() && Fn->isVarArg())
00165           MF->getFrameInfo()->setHasMustTailInVarArgFunc(true);
00166       }
00167 
00168       // Mark values used outside their block as exported, by allocating
00169       // a virtual register for them.
00170       if (isUsedOutsideOfDefiningBlock(I))
00171         if (!isa<AllocaInst>(I) ||
00172             !StaticAllocaMap.count(cast<AllocaInst>(I)))
00173           InitializeRegForValue(I);
00174 
00175       // Collect llvm.dbg.declare information. This is done now instead of
00176       // during the initial isel pass through the IR so that it is done
00177       // in a predictable order.
00178       if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
00179         MachineModuleInfo &MMI = MF->getMMI();
00180         DIVariable DIVar(DI->getVariable());
00181         assert((!DIVar || DIVar.isVariable()) &&
00182           "Variable in DbgDeclareInst should be either null or a DIVariable.");
00183         if (MMI.hasDebugInfo() &&
00184             DIVar &&
00185             !DI->getDebugLoc().isUnknown()) {
00186           // Don't handle byval struct arguments or VLAs, for example.
00187           // Non-byval arguments are handled here (they refer to the stack
00188           // temporary alloca at this point).
00189           const Value *Address = DI->getAddress();
00190           if (Address) {
00191             if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
00192               Address = BCI->getOperand(0);
00193             if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
00194               DenseMap<const AllocaInst *, int>::iterator SI =
00195                 StaticAllocaMap.find(AI);
00196               if (SI != StaticAllocaMap.end()) { // Check for VLAs.
00197                 int FI = SI->second;
00198                 MMI.setVariableDbgInfo(DI->getVariable(), DI->getExpression(),
00199                                        FI, DI->getDebugLoc());
00200               }
00201             }
00202           }
00203         }
00204       }
00205 
00206       // Decide the preferred extend type for a value.
00207       PreferredExtendType[I] = getPreferredExtendForValue(I);
00208     }
00209 
00210   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
00211   // also creates the initial PHI MachineInstrs, though none of the input
00212   // operands are populated.
00213   for (BB = Fn->begin(); BB != EB; ++BB) {
00214     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
00215     MBBMap[BB] = MBB;
00216     MF->push_back(MBB);
00217 
00218     // Transfer the address-taken flag. This is necessary because there could
00219     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
00220     // the first one should be marked.
00221     if (BB->hasAddressTaken())
00222       MBB->setHasAddressTaken();
00223 
00224     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
00225     // appropriate.
00226     for (BasicBlock::const_iterator I = BB->begin();
00227          const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
00228       if (PN->use_empty()) continue;
00229 
00230       // Skip empty types
00231       if (PN->getType()->isEmptyTy())
00232         continue;
00233 
00234       DebugLoc DL = PN->getDebugLoc();
00235       unsigned PHIReg = ValueMap[PN];
00236       assert(PHIReg && "PHI node does not have an assigned virtual register!");
00237 
00238       SmallVector<EVT, 4> ValueVTs;
00239       ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
00240       for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
00241         EVT VT = ValueVTs[vti];
00242         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
00243         const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
00244         for (unsigned i = 0; i != NumRegisters; ++i)
00245           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
00246         PHIReg += NumRegisters;
00247       }
00248     }
00249   }
00250 
00251   // Mark landing pad blocks.
00252   for (BB = Fn->begin(); BB != EB; ++BB)
00253     if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
00254       MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
00255 }
00256 
00257 /// clear - Clear out all the function-specific state. This returns this
00258 /// FunctionLoweringInfo to an empty state, ready to be used for a
00259 /// different function.
00260 void FunctionLoweringInfo::clear() {
00261   assert(CatchInfoFound.size() == CatchInfoLost.size() &&
00262          "Not all catch info was assigned to a landing pad!");
00263 
00264   MBBMap.clear();
00265   ValueMap.clear();
00266   StaticAllocaMap.clear();
00267 #ifndef NDEBUG
00268   CatchInfoLost.clear();
00269   CatchInfoFound.clear();
00270 #endif
00271   LiveOutRegInfo.clear();
00272   VisitedBBs.clear();
00273   ArgDbgValues.clear();
00274   ByValArgFrameIndexMap.clear();
00275   RegFixups.clear();
00276   StatepointStackSlots.clear();
00277   PreferredExtendType.clear();
00278 }
00279 
00280 /// CreateReg - Allocate a single virtual register for the given type.
00281 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
00282   return RegInfo->createVirtualRegister(
00283       MF->getSubtarget().getTargetLowering()->getRegClassFor(VT));
00284 }
00285 
00286 /// CreateRegs - Allocate the appropriate number of virtual registers of
00287 /// the correctly promoted or expanded types.  Assign these registers
00288 /// consecutive vreg numbers and return the first assigned number.
00289 ///
00290 /// In the case that the given value has struct or array type, this function
00291 /// will assign registers for each member or element.
00292 ///
00293 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
00294   const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
00295 
00296   SmallVector<EVT, 4> ValueVTs;
00297   ComputeValueVTs(*TLI, Ty, ValueVTs);
00298 
00299   unsigned FirstReg = 0;
00300   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
00301     EVT ValueVT = ValueVTs[Value];
00302     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
00303 
00304     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
00305     for (unsigned i = 0; i != NumRegs; ++i) {
00306       unsigned R = CreateReg(RegisterVT);
00307       if (!FirstReg) FirstReg = R;
00308     }
00309   }
00310   return FirstReg;
00311 }
00312 
00313 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
00314 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
00315 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
00316 /// the larger bit width by zero extension. The bit width must be no smaller
00317 /// than the LiveOutInfo's existing bit width.
00318 const FunctionLoweringInfo::LiveOutInfo *
00319 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
00320   if (!LiveOutRegInfo.inBounds(Reg))
00321     return nullptr;
00322 
00323   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
00324   if (!LOI->IsValid)
00325     return nullptr;
00326 
00327   if (BitWidth > LOI->KnownZero.getBitWidth()) {
00328     LOI->NumSignBits = 1;
00329     LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
00330     LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
00331   }
00332 
00333   return LOI;
00334 }
00335 
00336 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
00337 /// register based on the LiveOutInfo of its operands.
00338 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
00339   Type *Ty = PN->getType();
00340   if (!Ty->isIntegerTy() || Ty->isVectorTy())
00341     return;
00342 
00343   SmallVector<EVT, 1> ValueVTs;
00344   ComputeValueVTs(*TLI, Ty, ValueVTs);
00345   assert(ValueVTs.size() == 1 &&
00346          "PHIs with non-vector integer types should have a single VT.");
00347   EVT IntVT = ValueVTs[0];
00348 
00349   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
00350     return;
00351   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
00352   unsigned BitWidth = IntVT.getSizeInBits();
00353 
00354   unsigned DestReg = ValueMap[PN];
00355   if (!TargetRegisterInfo::isVirtualRegister(DestReg))
00356     return;
00357   LiveOutRegInfo.grow(DestReg);
00358   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
00359 
00360   Value *V = PN->getIncomingValue(0);
00361   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00362     DestLOI.NumSignBits = 1;
00363     APInt Zero(BitWidth, 0);
00364     DestLOI.KnownZero = Zero;
00365     DestLOI.KnownOne = Zero;
00366     return;
00367   }
00368 
00369   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00370     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00371     DestLOI.NumSignBits = Val.getNumSignBits();
00372     DestLOI.KnownZero = ~Val;
00373     DestLOI.KnownOne = Val;
00374   } else {
00375     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
00376                                 "CopyToReg node was created.");
00377     unsigned SrcReg = ValueMap[V];
00378     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00379       DestLOI.IsValid = false;
00380       return;
00381     }
00382     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00383     if (!SrcLOI) {
00384       DestLOI.IsValid = false;
00385       return;
00386     }
00387     DestLOI = *SrcLOI;
00388   }
00389 
00390   assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
00391          DestLOI.KnownOne.getBitWidth() == BitWidth &&
00392          "Masks should have the same bit width as the type.");
00393 
00394   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
00395     Value *V = PN->getIncomingValue(i);
00396     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00397       DestLOI.NumSignBits = 1;
00398       APInt Zero(BitWidth, 0);
00399       DestLOI.KnownZero = Zero;
00400       DestLOI.KnownOne = Zero;
00401       return;
00402     }
00403 
00404     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00405       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00406       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
00407       DestLOI.KnownZero &= ~Val;
00408       DestLOI.KnownOne &= Val;
00409       continue;
00410     }
00411 
00412     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
00413                                 "its CopyToReg node was created.");
00414     unsigned SrcReg = ValueMap[V];
00415     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00416       DestLOI.IsValid = false;
00417       return;
00418     }
00419     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00420     if (!SrcLOI) {
00421       DestLOI.IsValid = false;
00422       return;
00423     }
00424     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
00425     DestLOI.KnownZero &= SrcLOI->KnownZero;
00426     DestLOI.KnownOne &= SrcLOI->KnownOne;
00427   }
00428 }
00429 
00430 /// setArgumentFrameIndex - Record frame index for the byval
00431 /// argument. This overrides previous frame index entry for this argument,
00432 /// if any.
00433 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
00434                                                  int FI) {
00435   ByValArgFrameIndexMap[A] = FI;
00436 }
00437 
00438 /// getArgumentFrameIndex - Get frame index for the byval argument.
00439 /// If the argument does not have any assigned frame index then 0 is
00440 /// returned.
00441 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
00442   DenseMap<const Argument *, int>::iterator I =
00443     ByValArgFrameIndexMap.find(A);
00444   if (I != ByValArgFrameIndexMap.end())
00445     return I->second;
00446   DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
00447   return 0;
00448 }
00449 
00450 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
00451 /// being passed to this variadic function, and set the MachineModuleInfo's
00452 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
00453 /// reference to _fltused on Windows, which will link in MSVCRT's
00454 /// floating-point support.
00455 void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
00456                                       MachineModuleInfo *MMI)
00457 {
00458   FunctionType *FT = cast<FunctionType>(
00459     I.getCalledValue()->getType()->getContainedType(0));
00460   if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
00461     for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
00462       Type* T = I.getArgOperand(i)->getType();
00463       for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
00464            i != e; ++i) {
00465         if (i->isFloatingPointTy()) {
00466           MMI->setUsesVAFloatArgument(true);
00467           return;
00468         }
00469       }
00470     }
00471   }
00472 }
00473 
00474 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
00475 /// call, and add them to the specified machine basic block.
00476 void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI,
00477                         MachineBasicBlock *MBB) {
00478   // Inform the MachineModuleInfo of the personality for this landing pad.
00479   const ConstantExpr *CE = cast<ConstantExpr>(I.getArgOperand(1));
00480   assert(CE->getOpcode() == Instruction::BitCast &&
00481          isa<Function>(CE->getOperand(0)) &&
00482          "Personality should be a function");
00483   MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
00484 
00485   // Gather all the type infos for this landing pad and pass them along to
00486   // MachineModuleInfo.
00487   std::vector<const GlobalValue *> TyInfo;
00488   unsigned N = I.getNumArgOperands();
00489 
00490   for (unsigned i = N - 1; i > 1; --i) {
00491     if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(i))) {
00492       unsigned FilterLength = CI->getZExtValue();
00493       unsigned FirstCatch = i + FilterLength + !FilterLength;
00494       assert(FirstCatch <= N && "Invalid filter length");
00495 
00496       if (FirstCatch < N) {
00497         TyInfo.reserve(N - FirstCatch);
00498         for (unsigned j = FirstCatch; j < N; ++j)
00499           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00500         MMI->addCatchTypeInfo(MBB, TyInfo);
00501         TyInfo.clear();
00502       }
00503 
00504       if (!FilterLength) {
00505         // Cleanup.
00506         MMI->addCleanup(MBB);
00507       } else {
00508         // Filter.
00509         TyInfo.reserve(FilterLength - 1);
00510         for (unsigned j = i + 1; j < FirstCatch; ++j)
00511           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00512         MMI->addFilterTypeInfo(MBB, TyInfo);
00513         TyInfo.clear();
00514       }
00515 
00516       N = i;
00517     }
00518   }
00519 
00520   if (N > 2) {
00521     TyInfo.reserve(N - 2);
00522     for (unsigned j = 2; j < N; ++j)
00523       TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00524     MMI->addCatchTypeInfo(MBB, TyInfo);
00525   }
00526 }
00527 
00528 /// AddLandingPadInfo - Extract the exception handling information from the
00529 /// landingpad instruction and add them to the specified machine module info.
00530 void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
00531                              MachineBasicBlock *MBB) {
00532   MMI.addPersonality(MBB,
00533                      cast<Function>(I.getPersonalityFn()->stripPointerCasts()));
00534 
00535   if (I.isCleanup())
00536     MMI.addCleanup(MBB);
00537 
00538   // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
00539   //        but we need to do it this way because of how the DWARF EH emitter
00540   //        processes the clauses.
00541   for (unsigned i = I.getNumClauses(); i != 0; --i) {
00542     Value *Val = I.getClause(i - 1);
00543     if (I.isCatch(i - 1)) {
00544       MMI.addCatchTypeInfo(MBB,
00545                            dyn_cast<GlobalValue>(Val->stripPointerCasts()));
00546     } else {
00547       // Add filters in a list.
00548       Constant *CVal = cast<Constant>(Val);
00549       SmallVector<const GlobalValue*, 4> FilterList;
00550       for (User::op_iterator
00551              II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
00552         FilterList.push_back(cast<GlobalValue>((*II)->stripPointerCasts()));
00553 
00554       MMI.addFilterTypeInfo(MBB, FilterList);
00555     }
00556   }
00557 }