LLVM API Documentation

FunctionLoweringInfo.cpp
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00001 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This implements routines for translating functions from LLVM IR into
00011 // Machine IR.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "llvm/CodeGen/FunctionLoweringInfo.h"
00016 #include "llvm/ADT/PostOrderIterator.h"
00017 #include "llvm/CodeGen/Analysis.h"
00018 #include "llvm/CodeGen/MachineFrameInfo.h"
00019 #include "llvm/CodeGen/MachineFunction.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/MachineModuleInfo.h"
00022 #include "llvm/CodeGen/MachineRegisterInfo.h"
00023 #include "llvm/IR/DataLayout.h"
00024 #include "llvm/IR/DebugInfo.h"
00025 #include "llvm/IR/DerivedTypes.h"
00026 #include "llvm/IR/Function.h"
00027 #include "llvm/IR/Instructions.h"
00028 #include "llvm/IR/IntrinsicInst.h"
00029 #include "llvm/IR/LLVMContext.h"
00030 #include "llvm/IR/Module.h"
00031 #include "llvm/Support/Debug.h"
00032 #include "llvm/Support/ErrorHandling.h"
00033 #include "llvm/Support/MathExtras.h"
00034 #include "llvm/Target/TargetFrameLowering.h"
00035 #include "llvm/Target/TargetInstrInfo.h"
00036 #include "llvm/Target/TargetLowering.h"
00037 #include "llvm/Target/TargetOptions.h"
00038 #include "llvm/Target/TargetRegisterInfo.h"
00039 #include "llvm/Target/TargetSubtargetInfo.h"
00040 #include <algorithm>
00041 using namespace llvm;
00042 
00043 #define DEBUG_TYPE "function-lowering-info"
00044 
00045 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
00046 /// PHI nodes or outside of the basic block that defines it, or used by a
00047 /// switch or atomic instruction, which may expand to multiple basic blocks.
00048 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
00049   if (I->use_empty()) return false;
00050   if (isa<PHINode>(I)) return true;
00051   const BasicBlock *BB = I->getParent();
00052   for (const User *U : I->users())
00053     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
00054       return true;
00055 
00056   return false;
00057 }
00058 
00059 static ISD::NodeType getPreferredExtendForValue(const Value *V) {
00060   // For the users of the source value being used for compare instruction, if
00061   // the number of signed predicate is greater than unsigned predicate, we
00062   // prefer to use SIGN_EXTEND.
00063   //
00064   // With this optimization, we would be able to reduce some redundant sign or
00065   // zero extension instruction, and eventually more machine CSE opportunities
00066   // can be exposed.
00067   ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
00068   unsigned NumOfSigned = 0, NumOfUnsigned = 0;
00069   for (const User *U : V->users()) {
00070     if (const auto *CI = dyn_cast<CmpInst>(U)) {
00071       NumOfSigned += CI->isSigned();
00072       NumOfUnsigned += CI->isUnsigned();
00073     }
00074   }
00075   if (NumOfSigned > NumOfUnsigned)
00076     ExtendKind = ISD::SIGN_EXTEND;
00077 
00078   return ExtendKind;
00079 }
00080 
00081 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
00082                                SelectionDAG *DAG) {
00083   const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
00084 
00085   Fn = &fn;
00086   MF = &mf;
00087   RegInfo = &MF->getRegInfo();
00088 
00089   // Check whether the function can return without sret-demotion.
00090   SmallVector<ISD::OutputArg, 4> Outs;
00091   GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
00092   CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
00093                                        Fn->isVarArg(),
00094                                        Outs, Fn->getContext());
00095 
00096   // Initialize the mapping of values to registers.  This is only set up for
00097   // instruction values that are used outside of the block that defines
00098   // them.
00099   Function::const_iterator BB = Fn->begin(), EB = Fn->end();
00100   for (; BB != EB; ++BB)
00101     for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
00102          I != E; ++I) {
00103       if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
00104         // Static allocas can be folded into the initial stack frame adjustment.
00105         if (AI->isStaticAlloca()) {
00106           const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
00107           Type *Ty = AI->getAllocatedType();
00108           uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
00109           unsigned Align =
00110             std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
00111                      AI->getAlignment());
00112 
00113           TySize *= CUI->getZExtValue();   // Get total allocated size.
00114           if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
00115 
00116           StaticAllocaMap[AI] =
00117             MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
00118 
00119         } else {
00120           unsigned Align = std::max(
00121               (unsigned)TLI->getDataLayout()->getPrefTypeAlignment(
00122                 AI->getAllocatedType()),
00123               AI->getAlignment());
00124           unsigned StackAlign =
00125               TM.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
00126           if (Align <= StackAlign)
00127             Align = 0;
00128           // Inform the Frame Information that we have variable-sized objects.
00129           MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
00130         }
00131       }
00132 
00133       // Look for inline asm that clobbers the SP register.
00134       if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
00135         ImmutableCallSite CS(I);
00136         if (isa<InlineAsm>(CS.getCalledValue())) {
00137           unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
00138           std::vector<TargetLowering::AsmOperandInfo> Ops =
00139             TLI->ParseConstraints(CS);
00140           for (size_t I = 0, E = Ops.size(); I != E; ++I) {
00141             TargetLowering::AsmOperandInfo &Op = Ops[I];
00142             if (Op.Type == InlineAsm::isClobber) {
00143               // Clobbers don't have SDValue operands, hence SDValue().
00144               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
00145               std::pair<unsigned, const TargetRegisterClass*> PhysReg =
00146                 TLI->getRegForInlineAsmConstraint(Op.ConstraintCode,
00147                                                   Op.ConstraintVT);
00148               if (PhysReg.first == SP)
00149                 MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
00150             }
00151           }
00152         }
00153       }
00154 
00155       // Look for calls to the @llvm.va_start intrinsic. We can omit some
00156       // prologue boilerplate for variadic functions that don't examine their
00157       // arguments.
00158       if (const auto *II = dyn_cast<IntrinsicInst>(I)) {
00159         if (II->getIntrinsicID() == Intrinsic::vastart)
00160           MF->getFrameInfo()->setHasVAStart(true);
00161       }
00162 
00163       // If we have a musttail call in a variadic funciton, we need to ensure we
00164       // forward implicit register parameters.
00165       if (const auto *CI = dyn_cast<CallInst>(I)) {
00166         if (CI->isMustTailCall() && Fn->isVarArg())
00167           MF->getFrameInfo()->setHasMustTailInVarArgFunc(true);
00168       }
00169 
00170       // Mark values used outside their block as exported, by allocating
00171       // a virtual register for them.
00172       if (isUsedOutsideOfDefiningBlock(I))
00173         if (!isa<AllocaInst>(I) ||
00174             !StaticAllocaMap.count(cast<AllocaInst>(I)))
00175           InitializeRegForValue(I);
00176 
00177       // Collect llvm.dbg.declare information. This is done now instead of
00178       // during the initial isel pass through the IR so that it is done
00179       // in a predictable order.
00180       if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
00181         MachineModuleInfo &MMI = MF->getMMI();
00182         DIVariable DIVar(DI->getVariable());
00183         assert((!DIVar || DIVar.isVariable()) &&
00184           "Variable in DbgDeclareInst should be either null or a DIVariable.");
00185         if (MMI.hasDebugInfo() &&
00186             DIVar &&
00187             !DI->getDebugLoc().isUnknown()) {
00188           // Don't handle byval struct arguments or VLAs, for example.
00189           // Non-byval arguments are handled here (they refer to the stack
00190           // temporary alloca at this point).
00191           const Value *Address = DI->getAddress();
00192           if (Address) {
00193             if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
00194               Address = BCI->getOperand(0);
00195             if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
00196               DenseMap<const AllocaInst *, int>::iterator SI =
00197                 StaticAllocaMap.find(AI);
00198               if (SI != StaticAllocaMap.end()) { // Check for VLAs.
00199                 int FI = SI->second;
00200                 MMI.setVariableDbgInfo(DI->getVariable(),
00201                                        FI, DI->getDebugLoc());
00202               }
00203             }
00204           }
00205         }
00206       }
00207 
00208       // Decide the preferred extend type for a value.
00209       PreferredExtendType[I] = getPreferredExtendForValue(I);
00210     }
00211 
00212   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
00213   // also creates the initial PHI MachineInstrs, though none of the input
00214   // operands are populated.
00215   for (BB = Fn->begin(); BB != EB; ++BB) {
00216     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
00217     MBBMap[BB] = MBB;
00218     MF->push_back(MBB);
00219 
00220     // Transfer the address-taken flag. This is necessary because there could
00221     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
00222     // the first one should be marked.
00223     if (BB->hasAddressTaken())
00224       MBB->setHasAddressTaken();
00225 
00226     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
00227     // appropriate.
00228     for (BasicBlock::const_iterator I = BB->begin();
00229          const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
00230       if (PN->use_empty()) continue;
00231 
00232       // Skip empty types
00233       if (PN->getType()->isEmptyTy())
00234         continue;
00235 
00236       DebugLoc DL = PN->getDebugLoc();
00237       unsigned PHIReg = ValueMap[PN];
00238       assert(PHIReg && "PHI node does not have an assigned virtual register!");
00239 
00240       SmallVector<EVT, 4> ValueVTs;
00241       ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
00242       for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
00243         EVT VT = ValueVTs[vti];
00244         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
00245         const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
00246         for (unsigned i = 0; i != NumRegisters; ++i)
00247           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
00248         PHIReg += NumRegisters;
00249       }
00250     }
00251   }
00252 
00253   // Mark landing pad blocks.
00254   for (BB = Fn->begin(); BB != EB; ++BB)
00255     if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
00256       MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
00257 }
00258 
00259 /// clear - Clear out all the function-specific state. This returns this
00260 /// FunctionLoweringInfo to an empty state, ready to be used for a
00261 /// different function.
00262 void FunctionLoweringInfo::clear() {
00263   assert(CatchInfoFound.size() == CatchInfoLost.size() &&
00264          "Not all catch info was assigned to a landing pad!");
00265 
00266   MBBMap.clear();
00267   ValueMap.clear();
00268   StaticAllocaMap.clear();
00269 #ifndef NDEBUG
00270   CatchInfoLost.clear();
00271   CatchInfoFound.clear();
00272 #endif
00273   LiveOutRegInfo.clear();
00274   VisitedBBs.clear();
00275   ArgDbgValues.clear();
00276   ByValArgFrameIndexMap.clear();
00277   RegFixups.clear();
00278   PreferredExtendType.clear();
00279 }
00280 
00281 /// CreateReg - Allocate a single virtual register for the given type.
00282 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
00283   return RegInfo->createVirtualRegister(
00284       TM.getSubtargetImpl()->getTargetLowering()->getRegClassFor(VT));
00285 }
00286 
00287 /// CreateRegs - Allocate the appropriate number of virtual registers of
00288 /// the correctly promoted or expanded types.  Assign these registers
00289 /// consecutive vreg numbers and return the first assigned number.
00290 ///
00291 /// In the case that the given value has struct or array type, this function
00292 /// will assign registers for each member or element.
00293 ///
00294 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
00295   const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
00296 
00297   SmallVector<EVT, 4> ValueVTs;
00298   ComputeValueVTs(*TLI, Ty, ValueVTs);
00299 
00300   unsigned FirstReg = 0;
00301   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
00302     EVT ValueVT = ValueVTs[Value];
00303     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
00304 
00305     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
00306     for (unsigned i = 0; i != NumRegs; ++i) {
00307       unsigned R = CreateReg(RegisterVT);
00308       if (!FirstReg) FirstReg = R;
00309     }
00310   }
00311   return FirstReg;
00312 }
00313 
00314 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
00315 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
00316 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
00317 /// the larger bit width by zero extension. The bit width must be no smaller
00318 /// than the LiveOutInfo's existing bit width.
00319 const FunctionLoweringInfo::LiveOutInfo *
00320 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
00321   if (!LiveOutRegInfo.inBounds(Reg))
00322     return nullptr;
00323 
00324   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
00325   if (!LOI->IsValid)
00326     return nullptr;
00327 
00328   if (BitWidth > LOI->KnownZero.getBitWidth()) {
00329     LOI->NumSignBits = 1;
00330     LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
00331     LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
00332   }
00333 
00334   return LOI;
00335 }
00336 
00337 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
00338 /// register based on the LiveOutInfo of its operands.
00339 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
00340   Type *Ty = PN->getType();
00341   if (!Ty->isIntegerTy() || Ty->isVectorTy())
00342     return;
00343 
00344   const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
00345 
00346   SmallVector<EVT, 1> ValueVTs;
00347   ComputeValueVTs(*TLI, Ty, ValueVTs);
00348   assert(ValueVTs.size() == 1 &&
00349          "PHIs with non-vector integer types should have a single VT.");
00350   EVT IntVT = ValueVTs[0];
00351 
00352   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
00353     return;
00354   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
00355   unsigned BitWidth = IntVT.getSizeInBits();
00356 
00357   unsigned DestReg = ValueMap[PN];
00358   if (!TargetRegisterInfo::isVirtualRegister(DestReg))
00359     return;
00360   LiveOutRegInfo.grow(DestReg);
00361   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
00362 
00363   Value *V = PN->getIncomingValue(0);
00364   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00365     DestLOI.NumSignBits = 1;
00366     APInt Zero(BitWidth, 0);
00367     DestLOI.KnownZero = Zero;
00368     DestLOI.KnownOne = Zero;
00369     return;
00370   }
00371 
00372   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00373     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00374     DestLOI.NumSignBits = Val.getNumSignBits();
00375     DestLOI.KnownZero = ~Val;
00376     DestLOI.KnownOne = Val;
00377   } else {
00378     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
00379                                 "CopyToReg node was created.");
00380     unsigned SrcReg = ValueMap[V];
00381     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00382       DestLOI.IsValid = false;
00383       return;
00384     }
00385     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00386     if (!SrcLOI) {
00387       DestLOI.IsValid = false;
00388       return;
00389     }
00390     DestLOI = *SrcLOI;
00391   }
00392 
00393   assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
00394          DestLOI.KnownOne.getBitWidth() == BitWidth &&
00395          "Masks should have the same bit width as the type.");
00396 
00397   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
00398     Value *V = PN->getIncomingValue(i);
00399     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00400       DestLOI.NumSignBits = 1;
00401       APInt Zero(BitWidth, 0);
00402       DestLOI.KnownZero = Zero;
00403       DestLOI.KnownOne = Zero;
00404       return;
00405     }
00406 
00407     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00408       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00409       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
00410       DestLOI.KnownZero &= ~Val;
00411       DestLOI.KnownOne &= Val;
00412       continue;
00413     }
00414 
00415     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
00416                                 "its CopyToReg node was created.");
00417     unsigned SrcReg = ValueMap[V];
00418     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00419       DestLOI.IsValid = false;
00420       return;
00421     }
00422     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00423     if (!SrcLOI) {
00424       DestLOI.IsValid = false;
00425       return;
00426     }
00427     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
00428     DestLOI.KnownZero &= SrcLOI->KnownZero;
00429     DestLOI.KnownOne &= SrcLOI->KnownOne;
00430   }
00431 }
00432 
00433 /// setArgumentFrameIndex - Record frame index for the byval
00434 /// argument. This overrides previous frame index entry for this argument,
00435 /// if any.
00436 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
00437                                                  int FI) {
00438   ByValArgFrameIndexMap[A] = FI;
00439 }
00440 
00441 /// getArgumentFrameIndex - Get frame index for the byval argument.
00442 /// If the argument does not have any assigned frame index then 0 is
00443 /// returned.
00444 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
00445   DenseMap<const Argument *, int>::iterator I =
00446     ByValArgFrameIndexMap.find(A);
00447   if (I != ByValArgFrameIndexMap.end())
00448     return I->second;
00449   DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
00450   return 0;
00451 }
00452 
00453 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
00454 /// being passed to this variadic function, and set the MachineModuleInfo's
00455 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
00456 /// reference to _fltused on Windows, which will link in MSVCRT's
00457 /// floating-point support.
00458 void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
00459                                       MachineModuleInfo *MMI)
00460 {
00461   FunctionType *FT = cast<FunctionType>(
00462     I.getCalledValue()->getType()->getContainedType(0));
00463   if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
00464     for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
00465       Type* T = I.getArgOperand(i)->getType();
00466       for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
00467            i != e; ++i) {
00468         if (i->isFloatingPointTy()) {
00469           MMI->setUsesVAFloatArgument(true);
00470           return;
00471         }
00472       }
00473     }
00474   }
00475 }
00476 
00477 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
00478 /// call, and add them to the specified machine basic block.
00479 void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI,
00480                         MachineBasicBlock *MBB) {
00481   // Inform the MachineModuleInfo of the personality for this landing pad.
00482   const ConstantExpr *CE = cast<ConstantExpr>(I.getArgOperand(1));
00483   assert(CE->getOpcode() == Instruction::BitCast &&
00484          isa<Function>(CE->getOperand(0)) &&
00485          "Personality should be a function");
00486   MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
00487 
00488   // Gather all the type infos for this landing pad and pass them along to
00489   // MachineModuleInfo.
00490   std::vector<const GlobalVariable *> TyInfo;
00491   unsigned N = I.getNumArgOperands();
00492 
00493   for (unsigned i = N - 1; i > 1; --i) {
00494     if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(i))) {
00495       unsigned FilterLength = CI->getZExtValue();
00496       unsigned FirstCatch = i + FilterLength + !FilterLength;
00497       assert(FirstCatch <= N && "Invalid filter length");
00498 
00499       if (FirstCatch < N) {
00500         TyInfo.reserve(N - FirstCatch);
00501         for (unsigned j = FirstCatch; j < N; ++j)
00502           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00503         MMI->addCatchTypeInfo(MBB, TyInfo);
00504         TyInfo.clear();
00505       }
00506 
00507       if (!FilterLength) {
00508         // Cleanup.
00509         MMI->addCleanup(MBB);
00510       } else {
00511         // Filter.
00512         TyInfo.reserve(FilterLength - 1);
00513         for (unsigned j = i + 1; j < FirstCatch; ++j)
00514           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00515         MMI->addFilterTypeInfo(MBB, TyInfo);
00516         TyInfo.clear();
00517       }
00518 
00519       N = i;
00520     }
00521   }
00522 
00523   if (N > 2) {
00524     TyInfo.reserve(N - 2);
00525     for (unsigned j = 2; j < N; ++j)
00526       TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00527     MMI->addCatchTypeInfo(MBB, TyInfo);
00528   }
00529 }
00530 
00531 /// AddLandingPadInfo - Extract the exception handling information from the
00532 /// landingpad instruction and add them to the specified machine module info.
00533 void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
00534                              MachineBasicBlock *MBB) {
00535   MMI.addPersonality(MBB,
00536                      cast<Function>(I.getPersonalityFn()->stripPointerCasts()));
00537 
00538   if (I.isCleanup())
00539     MMI.addCleanup(MBB);
00540 
00541   // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
00542   //        but we need to do it this way because of how the DWARF EH emitter
00543   //        processes the clauses.
00544   for (unsigned i = I.getNumClauses(); i != 0; --i) {
00545     Value *Val = I.getClause(i - 1);
00546     if (I.isCatch(i - 1)) {
00547       MMI.addCatchTypeInfo(MBB,
00548                            dyn_cast<GlobalVariable>(Val->stripPointerCasts()));
00549     } else {
00550       // Add filters in a list.
00551       Constant *CVal = cast<Constant>(Val);
00552       SmallVector<const GlobalVariable*, 4> FilterList;
00553       for (User::op_iterator
00554              II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
00555         FilterList.push_back(cast<GlobalVariable>((*II)->stripPointerCasts()));
00556 
00557       MMI.addFilterTypeInfo(MBB, FilterList);
00558     }
00559   }
00560 }