LLVM  mainline
FunctionLoweringInfo.cpp
Go to the documentation of this file.
00001 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This implements routines for translating functions from LLVM IR into
00011 // Machine IR.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "llvm/CodeGen/FunctionLoweringInfo.h"
00016 #include "llvm/ADT/PostOrderIterator.h"
00017 #include "llvm/CodeGen/Analysis.h"
00018 #include "llvm/CodeGen/MachineFrameInfo.h"
00019 #include "llvm/CodeGen/MachineFunction.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/MachineModuleInfo.h"
00022 #include "llvm/CodeGen/MachineRegisterInfo.h"
00023 #include "llvm/IR/DataLayout.h"
00024 #include "llvm/IR/DebugInfo.h"
00025 #include "llvm/IR/DerivedTypes.h"
00026 #include "llvm/IR/Function.h"
00027 #include "llvm/IR/Instructions.h"
00028 #include "llvm/IR/IntrinsicInst.h"
00029 #include "llvm/IR/LLVMContext.h"
00030 #include "llvm/IR/Module.h"
00031 #include "llvm/Support/Debug.h"
00032 #include "llvm/Support/ErrorHandling.h"
00033 #include "llvm/Support/MathExtras.h"
00034 #include "llvm/Support/raw_ostream.h"
00035 #include "llvm/Target/TargetFrameLowering.h"
00036 #include "llvm/Target/TargetInstrInfo.h"
00037 #include "llvm/Target/TargetLowering.h"
00038 #include "llvm/Target/TargetOptions.h"
00039 #include "llvm/Target/TargetRegisterInfo.h"
00040 #include "llvm/Target/TargetSubtargetInfo.h"
00041 #include <algorithm>
00042 using namespace llvm;
00043 
00044 #define DEBUG_TYPE "function-lowering-info"
00045 
00046 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
00047 /// PHI nodes or outside of the basic block that defines it, or used by a
00048 /// switch or atomic instruction, which may expand to multiple basic blocks.
00049 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
00050   if (I->use_empty()) return false;
00051   if (isa<PHINode>(I)) return true;
00052   const BasicBlock *BB = I->getParent();
00053   for (const User *U : I->users())
00054     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
00055       return true;
00056 
00057   return false;
00058 }
00059 
00060 static ISD::NodeType getPreferredExtendForValue(const Value *V) {
00061   // For the users of the source value being used for compare instruction, if
00062   // the number of signed predicate is greater than unsigned predicate, we
00063   // prefer to use SIGN_EXTEND.
00064   //
00065   // With this optimization, we would be able to reduce some redundant sign or
00066   // zero extension instruction, and eventually more machine CSE opportunities
00067   // can be exposed.
00068   ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
00069   unsigned NumOfSigned = 0, NumOfUnsigned = 0;
00070   for (const User *U : V->users()) {
00071     if (const auto *CI = dyn_cast<CmpInst>(U)) {
00072       NumOfSigned += CI->isSigned();
00073       NumOfUnsigned += CI->isUnsigned();
00074     }
00075   }
00076   if (NumOfSigned > NumOfUnsigned)
00077     ExtendKind = ISD::SIGN_EXTEND;
00078 
00079   return ExtendKind;
00080 }
00081 
00082 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
00083                                SelectionDAG *DAG) {
00084   Fn = &fn;
00085   MF = &mf;
00086   TLI = MF->getSubtarget().getTargetLowering();
00087   RegInfo = &MF->getRegInfo();
00088 
00089   // Check whether the function can return without sret-demotion.
00090   SmallVector<ISD::OutputArg, 4> Outs;
00091   GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
00092   CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
00093                                        Fn->isVarArg(), Outs, Fn->getContext());
00094 
00095   // Initialize the mapping of values to registers.  This is only set up for
00096   // instruction values that are used outside of the block that defines
00097   // them.
00098   Function::const_iterator BB = Fn->begin(), EB = Fn->end();
00099   for (; BB != EB; ++BB)
00100     for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
00101          I != E; ++I) {
00102       if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
00103         // Static allocas can be folded into the initial stack frame adjustment.
00104         if (AI->isStaticAlloca()) {
00105           const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
00106           Type *Ty = AI->getAllocatedType();
00107           uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
00108           unsigned Align =
00109               std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
00110                        AI->getAlignment());
00111 
00112           TySize *= CUI->getZExtValue();   // Get total allocated size.
00113           if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
00114 
00115           StaticAllocaMap[AI] =
00116             MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
00117 
00118         } else {
00119           unsigned Align = std::max(
00120               (unsigned)TLI->getDataLayout()->getPrefTypeAlignment(
00121                 AI->getAllocatedType()),
00122               AI->getAlignment());
00123           unsigned StackAlign =
00124               MF->getSubtarget().getFrameLowering()->getStackAlignment();
00125           if (Align <= StackAlign)
00126             Align = 0;
00127           // Inform the Frame Information that we have variable-sized objects.
00128           MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
00129         }
00130       }
00131 
00132       // Look for inline asm that clobbers the SP register.
00133       if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
00134         ImmutableCallSite CS(I);
00135         if (isa<InlineAsm>(CS.getCalledValue())) {
00136           unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
00137           const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00138           std::vector<TargetLowering::AsmOperandInfo> Ops =
00139               TLI->ParseConstraints(TRI, CS);
00140           for (size_t I = 0, E = Ops.size(); I != E; ++I) {
00141             TargetLowering::AsmOperandInfo &Op = Ops[I];
00142             if (Op.Type == InlineAsm::isClobber) {
00143               // Clobbers don't have SDValue operands, hence SDValue().
00144               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
00145               std::pair<unsigned, const TargetRegisterClass *> PhysReg =
00146                   TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
00147                                                     Op.ConstraintVT);
00148               if (PhysReg.first == SP)
00149                 MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
00150             }
00151           }
00152         }
00153       }
00154 
00155       // Look for calls to the @llvm.va_start intrinsic. We can omit some
00156       // prologue boilerplate for variadic functions that don't examine their
00157       // arguments.
00158       if (const auto *II = dyn_cast<IntrinsicInst>(I)) {
00159         if (II->getIntrinsicID() == Intrinsic::vastart)
00160           MF->getFrameInfo()->setHasVAStart(true);
00161       }
00162 
00163       // If we have a musttail call in a variadic funciton, we need to ensure we
00164       // forward implicit register parameters.
00165       if (const auto *CI = dyn_cast<CallInst>(I)) {
00166         if (CI->isMustTailCall() && Fn->isVarArg())
00167           MF->getFrameInfo()->setHasMustTailInVarArgFunc(true);
00168       }
00169 
00170       // Mark values used outside their block as exported, by allocating
00171       // a virtual register for them.
00172       if (isUsedOutsideOfDefiningBlock(I))
00173         if (!isa<AllocaInst>(I) ||
00174             !StaticAllocaMap.count(cast<AllocaInst>(I)))
00175           InitializeRegForValue(I);
00176 
00177       // Collect llvm.dbg.declare information. This is done now instead of
00178       // during the initial isel pass through the IR so that it is done
00179       // in a predictable order.
00180       if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
00181         MachineModuleInfo &MMI = MF->getMMI();
00182         DIVariable DIVar(DI->getVariable());
00183         assert((!DIVar || DIVar.isVariable()) &&
00184           "Variable in DbgDeclareInst should be either null or a DIVariable.");
00185         if (MMI.hasDebugInfo() &&
00186             DIVar &&
00187             !DI->getDebugLoc().isUnknown()) {
00188           // Don't handle byval struct arguments or VLAs, for example.
00189           // Non-byval arguments are handled here (they refer to the stack
00190           // temporary alloca at this point).
00191           const Value *Address = DI->getAddress();
00192           if (Address) {
00193             if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
00194               Address = BCI->getOperand(0);
00195             if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
00196               DenseMap<const AllocaInst *, int>::iterator SI =
00197                 StaticAllocaMap.find(AI);
00198               if (SI != StaticAllocaMap.end()) { // Check for VLAs.
00199                 int FI = SI->second;
00200                 MMI.setVariableDbgInfo(DI->getVariable(), DI->getExpression(),
00201                                        FI, DI->getDebugLoc());
00202               }
00203             }
00204           }
00205         }
00206       }
00207 
00208       // Decide the preferred extend type for a value.
00209       PreferredExtendType[I] = getPreferredExtendForValue(I);
00210     }
00211 
00212   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
00213   // also creates the initial PHI MachineInstrs, though none of the input
00214   // operands are populated.
00215   for (BB = Fn->begin(); BB != EB; ++BB) {
00216     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
00217     MBBMap[BB] = MBB;
00218     MF->push_back(MBB);
00219 
00220     // Transfer the address-taken flag. This is necessary because there could
00221     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
00222     // the first one should be marked.
00223     if (BB->hasAddressTaken())
00224       MBB->setHasAddressTaken();
00225 
00226     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
00227     // appropriate.
00228     for (BasicBlock::const_iterator I = BB->begin();
00229          const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
00230       if (PN->use_empty()) continue;
00231 
00232       // Skip empty types
00233       if (PN->getType()->isEmptyTy())
00234         continue;
00235 
00236       DebugLoc DL = PN->getDebugLoc();
00237       unsigned PHIReg = ValueMap[PN];
00238       assert(PHIReg && "PHI node does not have an assigned virtual register!");
00239 
00240       SmallVector<EVT, 4> ValueVTs;
00241       ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
00242       for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
00243         EVT VT = ValueVTs[vti];
00244         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
00245         const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
00246         for (unsigned i = 0; i != NumRegisters; ++i)
00247           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
00248         PHIReg += NumRegisters;
00249       }
00250     }
00251   }
00252 
00253   // Mark landing pad blocks.
00254   for (BB = Fn->begin(); BB != EB; ++BB)
00255     if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
00256       MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
00257 }
00258 
00259 /// clear - Clear out all the function-specific state. This returns this
00260 /// FunctionLoweringInfo to an empty state, ready to be used for a
00261 /// different function.
00262 void FunctionLoweringInfo::clear() {
00263   assert(CatchInfoFound.size() == CatchInfoLost.size() &&
00264          "Not all catch info was assigned to a landing pad!");
00265 
00266   MBBMap.clear();
00267   ValueMap.clear();
00268   StaticAllocaMap.clear();
00269 #ifndef NDEBUG
00270   CatchInfoLost.clear();
00271   CatchInfoFound.clear();
00272 #endif
00273   LiveOutRegInfo.clear();
00274   VisitedBBs.clear();
00275   ArgDbgValues.clear();
00276   ByValArgFrameIndexMap.clear();
00277   RegFixups.clear();
00278   StatepointStackSlots.clear();
00279   PreferredExtendType.clear();
00280 }
00281 
00282 /// CreateReg - Allocate a single virtual register for the given type.
00283 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
00284   return RegInfo->createVirtualRegister(
00285       MF->getSubtarget().getTargetLowering()->getRegClassFor(VT));
00286 }
00287 
00288 /// CreateRegs - Allocate the appropriate number of virtual registers of
00289 /// the correctly promoted or expanded types.  Assign these registers
00290 /// consecutive vreg numbers and return the first assigned number.
00291 ///
00292 /// In the case that the given value has struct or array type, this function
00293 /// will assign registers for each member or element.
00294 ///
00295 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
00296   const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
00297 
00298   SmallVector<EVT, 4> ValueVTs;
00299   ComputeValueVTs(*TLI, Ty, ValueVTs);
00300 
00301   unsigned FirstReg = 0;
00302   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
00303     EVT ValueVT = ValueVTs[Value];
00304     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
00305 
00306     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
00307     for (unsigned i = 0; i != NumRegs; ++i) {
00308       unsigned R = CreateReg(RegisterVT);
00309       if (!FirstReg) FirstReg = R;
00310     }
00311   }
00312   return FirstReg;
00313 }
00314 
00315 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
00316 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
00317 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
00318 /// the larger bit width by zero extension. The bit width must be no smaller
00319 /// than the LiveOutInfo's existing bit width.
00320 const FunctionLoweringInfo::LiveOutInfo *
00321 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
00322   if (!LiveOutRegInfo.inBounds(Reg))
00323     return nullptr;
00324 
00325   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
00326   if (!LOI->IsValid)
00327     return nullptr;
00328 
00329   if (BitWidth > LOI->KnownZero.getBitWidth()) {
00330     LOI->NumSignBits = 1;
00331     LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
00332     LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
00333   }
00334 
00335   return LOI;
00336 }
00337 
00338 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
00339 /// register based on the LiveOutInfo of its operands.
00340 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
00341   Type *Ty = PN->getType();
00342   if (!Ty->isIntegerTy() || Ty->isVectorTy())
00343     return;
00344 
00345   SmallVector<EVT, 1> ValueVTs;
00346   ComputeValueVTs(*TLI, Ty, ValueVTs);
00347   assert(ValueVTs.size() == 1 &&
00348          "PHIs with non-vector integer types should have a single VT.");
00349   EVT IntVT = ValueVTs[0];
00350 
00351   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
00352     return;
00353   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
00354   unsigned BitWidth = IntVT.getSizeInBits();
00355 
00356   unsigned DestReg = ValueMap[PN];
00357   if (!TargetRegisterInfo::isVirtualRegister(DestReg))
00358     return;
00359   LiveOutRegInfo.grow(DestReg);
00360   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
00361 
00362   Value *V = PN->getIncomingValue(0);
00363   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00364     DestLOI.NumSignBits = 1;
00365     APInt Zero(BitWidth, 0);
00366     DestLOI.KnownZero = Zero;
00367     DestLOI.KnownOne = Zero;
00368     return;
00369   }
00370 
00371   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00372     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00373     DestLOI.NumSignBits = Val.getNumSignBits();
00374     DestLOI.KnownZero = ~Val;
00375     DestLOI.KnownOne = Val;
00376   } else {
00377     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
00378                                 "CopyToReg node was created.");
00379     unsigned SrcReg = ValueMap[V];
00380     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00381       DestLOI.IsValid = false;
00382       return;
00383     }
00384     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00385     if (!SrcLOI) {
00386       DestLOI.IsValid = false;
00387       return;
00388     }
00389     DestLOI = *SrcLOI;
00390   }
00391 
00392   assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
00393          DestLOI.KnownOne.getBitWidth() == BitWidth &&
00394          "Masks should have the same bit width as the type.");
00395 
00396   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
00397     Value *V = PN->getIncomingValue(i);
00398     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00399       DestLOI.NumSignBits = 1;
00400       APInt Zero(BitWidth, 0);
00401       DestLOI.KnownZero = Zero;
00402       DestLOI.KnownOne = Zero;
00403       return;
00404     }
00405 
00406     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00407       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00408       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
00409       DestLOI.KnownZero &= ~Val;
00410       DestLOI.KnownOne &= Val;
00411       continue;
00412     }
00413 
00414     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
00415                                 "its CopyToReg node was created.");
00416     unsigned SrcReg = ValueMap[V];
00417     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00418       DestLOI.IsValid = false;
00419       return;
00420     }
00421     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00422     if (!SrcLOI) {
00423       DestLOI.IsValid = false;
00424       return;
00425     }
00426     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
00427     DestLOI.KnownZero &= SrcLOI->KnownZero;
00428     DestLOI.KnownOne &= SrcLOI->KnownOne;
00429   }
00430 }
00431 
00432 /// setArgumentFrameIndex - Record frame index for the byval
00433 /// argument. This overrides previous frame index entry for this argument,
00434 /// if any.
00435 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
00436                                                  int FI) {
00437   ByValArgFrameIndexMap[A] = FI;
00438 }
00439 
00440 /// getArgumentFrameIndex - Get frame index for the byval argument.
00441 /// If the argument does not have any assigned frame index then 0 is
00442 /// returned.
00443 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
00444   DenseMap<const Argument *, int>::iterator I =
00445     ByValArgFrameIndexMap.find(A);
00446   if (I != ByValArgFrameIndexMap.end())
00447     return I->second;
00448   DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
00449   return 0;
00450 }
00451 
00452 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
00453 /// being passed to this variadic function, and set the MachineModuleInfo's
00454 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
00455 /// reference to _fltused on Windows, which will link in MSVCRT's
00456 /// floating-point support.
00457 void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
00458                                       MachineModuleInfo *MMI)
00459 {
00460   FunctionType *FT = cast<FunctionType>(
00461     I.getCalledValue()->getType()->getContainedType(0));
00462   if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
00463     for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
00464       Type* T = I.getArgOperand(i)->getType();
00465       for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
00466            i != e; ++i) {
00467         if (i->isFloatingPointTy()) {
00468           MMI->setUsesVAFloatArgument(true);
00469           return;
00470         }
00471       }
00472     }
00473   }
00474 }
00475 
00476 /// AddLandingPadInfo - Extract the exception handling information from the
00477 /// landingpad instruction and add them to the specified machine module info.
00478 void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
00479                              MachineBasicBlock *MBB) {
00480   MMI.addPersonality(MBB,
00481                      cast<Function>(I.getPersonalityFn()->stripPointerCasts()));
00482 
00483   if (I.isCleanup())
00484     MMI.addCleanup(MBB);
00485 
00486   // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
00487   //        but we need to do it this way because of how the DWARF EH emitter
00488   //        processes the clauses.
00489   for (unsigned i = I.getNumClauses(); i != 0; --i) {
00490     Value *Val = I.getClause(i - 1);
00491     if (I.isCatch(i - 1)) {
00492       MMI.addCatchTypeInfo(MBB,
00493                            dyn_cast<GlobalValue>(Val->stripPointerCasts()));
00494     } else {
00495       // Add filters in a list.
00496       Constant *CVal = cast<Constant>(Val);
00497       SmallVector<const GlobalValue*, 4> FilterList;
00498       for (User::op_iterator
00499              II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
00500         FilterList.push_back(cast<GlobalValue>((*II)->stripPointerCasts()));
00501 
00502       MMI.addFilterTypeInfo(MBB, FilterList);
00503     }
00504   }
00505 }