LLVM API Documentation

FunctionLoweringInfo.cpp
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00001 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This implements routines for translating functions from LLVM IR into
00011 // Machine IR.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #define DEBUG_TYPE "function-lowering-info"
00016 #include "llvm/CodeGen/FunctionLoweringInfo.h"
00017 #include "llvm/ADT/PostOrderIterator.h"
00018 #include "llvm/CodeGen/Analysis.h"
00019 #include "llvm/CodeGen/MachineFrameInfo.h"
00020 #include "llvm/CodeGen/MachineFunction.h"
00021 #include "llvm/CodeGen/MachineInstrBuilder.h"
00022 #include "llvm/CodeGen/MachineModuleInfo.h"
00023 #include "llvm/CodeGen/MachineRegisterInfo.h"
00024 #include "llvm/IR/DataLayout.h"
00025 #include "llvm/IR/DebugInfo.h"
00026 #include "llvm/IR/DerivedTypes.h"
00027 #include "llvm/IR/Function.h"
00028 #include "llvm/IR/Instructions.h"
00029 #include "llvm/IR/IntrinsicInst.h"
00030 #include "llvm/IR/LLVMContext.h"
00031 #include "llvm/IR/Module.h"
00032 #include "llvm/Support/Debug.h"
00033 #include "llvm/Support/ErrorHandling.h"
00034 #include "llvm/Support/MathExtras.h"
00035 #include "llvm/Target/TargetFrameLowering.h"
00036 #include "llvm/Target/TargetInstrInfo.h"
00037 #include "llvm/Target/TargetLowering.h"
00038 #include "llvm/Target/TargetOptions.h"
00039 #include "llvm/Target/TargetRegisterInfo.h"
00040 #include <algorithm>
00041 using namespace llvm;
00042 
00043 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
00044 /// PHI nodes or outside of the basic block that defines it, or used by a
00045 /// switch or atomic instruction, which may expand to multiple basic blocks.
00046 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
00047   if (I->use_empty()) return false;
00048   if (isa<PHINode>(I)) return true;
00049   const BasicBlock *BB = I->getParent();
00050   for (const User *U : I->users())
00051     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
00052       return true;
00053 
00054   return false;
00055 }
00056 
00057 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
00058                                SelectionDAG *DAG) {
00059   const TargetLowering *TLI = TM.getTargetLowering();
00060 
00061   Fn = &fn;
00062   MF = &mf;
00063   RegInfo = &MF->getRegInfo();
00064 
00065   // Check whether the function can return without sret-demotion.
00066   SmallVector<ISD::OutputArg, 4> Outs;
00067   GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
00068   CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
00069                                        Fn->isVarArg(),
00070                                        Outs, Fn->getContext());
00071 
00072   // Initialize the mapping of values to registers.  This is only set up for
00073   // instruction values that are used outside of the block that defines
00074   // them.
00075   Function::const_iterator BB = Fn->begin(), EB = Fn->end();
00076   for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
00077     if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
00078       // Don't fold inalloca allocas or other dynamic allocas into the initial
00079       // stack frame allocation, even if they are in the entry block.
00080       if (!AI->isStaticAlloca())
00081         continue;
00082 
00083       if (const ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
00084         Type *Ty = AI->getAllocatedType();
00085         uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
00086         unsigned Align =
00087           std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
00088                    AI->getAlignment());
00089 
00090         TySize *= CUI->getZExtValue();   // Get total allocated size.
00091         if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
00092 
00093         StaticAllocaMap[AI] =
00094           MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
00095       }
00096     }
00097 
00098   for (; BB != EB; ++BB)
00099     for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
00100          I != E; ++I) {
00101       // Look for dynamic allocas.
00102       if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
00103         if (!AI->isStaticAlloca()) {
00104           unsigned Align = std::max(
00105               (unsigned)TLI->getDataLayout()->getPrefTypeAlignment(
00106                 AI->getAllocatedType()),
00107               AI->getAlignment());
00108           unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
00109           if (Align <= StackAlign)
00110             Align = 0;
00111           // Inform the Frame Information that we have variable-sized objects.
00112           MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
00113         }
00114       }
00115 
00116       // Look for inline asm that clobbers the SP register.
00117       if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
00118         ImmutableCallSite CS(I);
00119         if (isa<InlineAsm>(CS.getCalledValue())) {
00120           unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
00121           std::vector<TargetLowering::AsmOperandInfo> Ops =
00122             TLI->ParseConstraints(CS);
00123           for (size_t I = 0, E = Ops.size(); I != E; ++I) {
00124             TargetLowering::AsmOperandInfo &Op = Ops[I];
00125             if (Op.Type == InlineAsm::isClobber) {
00126               // Clobbers don't have SDValue operands, hence SDValue().
00127               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
00128               std::pair<unsigned, const TargetRegisterClass*> PhysReg =
00129                 TLI->getRegForInlineAsmConstraint(Op.ConstraintCode,
00130                                                   Op.ConstraintVT);
00131               if (PhysReg.first == SP)
00132                 MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
00133             }
00134           }
00135         }
00136       }
00137 
00138       // Mark values used outside their block as exported, by allocating
00139       // a virtual register for them.
00140       if (isUsedOutsideOfDefiningBlock(I))
00141         if (!isa<AllocaInst>(I) ||
00142             !StaticAllocaMap.count(cast<AllocaInst>(I)))
00143           InitializeRegForValue(I);
00144 
00145       // Collect llvm.dbg.declare information. This is done now instead of
00146       // during the initial isel pass through the IR so that it is done
00147       // in a predictable order.
00148       if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
00149         MachineModuleInfo &MMI = MF->getMMI();
00150         DIVariable DIVar(DI->getVariable());
00151         assert((!DIVar || DIVar.isVariable()) &&
00152           "Variable in DbgDeclareInst should be either null or a DIVariable.");
00153         if (MMI.hasDebugInfo() &&
00154             DIVar &&
00155             !DI->getDebugLoc().isUnknown()) {
00156           // Don't handle byval struct arguments or VLAs, for example.
00157           // Non-byval arguments are handled here (they refer to the stack
00158           // temporary alloca at this point).
00159           const Value *Address = DI->getAddress();
00160           if (Address) {
00161             if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
00162               Address = BCI->getOperand(0);
00163             if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
00164               DenseMap<const AllocaInst *, int>::iterator SI =
00165                 StaticAllocaMap.find(AI);
00166               if (SI != StaticAllocaMap.end()) { // Check for VLAs.
00167                 int FI = SI->second;
00168                 MMI.setVariableDbgInfo(DI->getVariable(),
00169                                        FI, DI->getDebugLoc());
00170               }
00171             }
00172           }
00173         }
00174       }
00175     }
00176 
00177   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
00178   // also creates the initial PHI MachineInstrs, though none of the input
00179   // operands are populated.
00180   for (BB = Fn->begin(); BB != EB; ++BB) {
00181     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
00182     MBBMap[BB] = MBB;
00183     MF->push_back(MBB);
00184 
00185     // Transfer the address-taken flag. This is necessary because there could
00186     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
00187     // the first one should be marked.
00188     if (BB->hasAddressTaken())
00189       MBB->setHasAddressTaken();
00190 
00191     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
00192     // appropriate.
00193     for (BasicBlock::const_iterator I = BB->begin();
00194          const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
00195       if (PN->use_empty()) continue;
00196 
00197       // Skip empty types
00198       if (PN->getType()->isEmptyTy())
00199         continue;
00200 
00201       DebugLoc DL = PN->getDebugLoc();
00202       unsigned PHIReg = ValueMap[PN];
00203       assert(PHIReg && "PHI node does not have an assigned virtual register!");
00204 
00205       SmallVector<EVT, 4> ValueVTs;
00206       ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
00207       for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
00208         EVT VT = ValueVTs[vti];
00209         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
00210         const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
00211         for (unsigned i = 0; i != NumRegisters; ++i)
00212           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
00213         PHIReg += NumRegisters;
00214       }
00215     }
00216   }
00217 
00218   // Mark landing pad blocks.
00219   for (BB = Fn->begin(); BB != EB; ++BB)
00220     if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
00221       MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
00222 }
00223 
00224 /// clear - Clear out all the function-specific state. This returns this
00225 /// FunctionLoweringInfo to an empty state, ready to be used for a
00226 /// different function.
00227 void FunctionLoweringInfo::clear() {
00228   assert(CatchInfoFound.size() == CatchInfoLost.size() &&
00229          "Not all catch info was assigned to a landing pad!");
00230 
00231   MBBMap.clear();
00232   ValueMap.clear();
00233   StaticAllocaMap.clear();
00234 #ifndef NDEBUG
00235   CatchInfoLost.clear();
00236   CatchInfoFound.clear();
00237 #endif
00238   LiveOutRegInfo.clear();
00239   VisitedBBs.clear();
00240   ArgDbgValues.clear();
00241   ByValArgFrameIndexMap.clear();
00242   RegFixups.clear();
00243 }
00244 
00245 /// CreateReg - Allocate a single virtual register for the given type.
00246 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
00247   return RegInfo->
00248     createVirtualRegister(TM.getTargetLowering()->getRegClassFor(VT));
00249 }
00250 
00251 /// CreateRegs - Allocate the appropriate number of virtual registers of
00252 /// the correctly promoted or expanded types.  Assign these registers
00253 /// consecutive vreg numbers and return the first assigned number.
00254 ///
00255 /// In the case that the given value has struct or array type, this function
00256 /// will assign registers for each member or element.
00257 ///
00258 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
00259   const TargetLowering *TLI = TM.getTargetLowering();
00260 
00261   SmallVector<EVT, 4> ValueVTs;
00262   ComputeValueVTs(*TLI, Ty, ValueVTs);
00263 
00264   unsigned FirstReg = 0;
00265   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
00266     EVT ValueVT = ValueVTs[Value];
00267     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
00268 
00269     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
00270     for (unsigned i = 0; i != NumRegs; ++i) {
00271       unsigned R = CreateReg(RegisterVT);
00272       if (!FirstReg) FirstReg = R;
00273     }
00274   }
00275   return FirstReg;
00276 }
00277 
00278 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
00279 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
00280 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
00281 /// the larger bit width by zero extension. The bit width must be no smaller
00282 /// than the LiveOutInfo's existing bit width.
00283 const FunctionLoweringInfo::LiveOutInfo *
00284 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
00285   if (!LiveOutRegInfo.inBounds(Reg))
00286     return nullptr;
00287 
00288   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
00289   if (!LOI->IsValid)
00290     return nullptr;
00291 
00292   if (BitWidth > LOI->KnownZero.getBitWidth()) {
00293     LOI->NumSignBits = 1;
00294     LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
00295     LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
00296   }
00297 
00298   return LOI;
00299 }
00300 
00301 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
00302 /// register based on the LiveOutInfo of its operands.
00303 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
00304   Type *Ty = PN->getType();
00305   if (!Ty->isIntegerTy() || Ty->isVectorTy())
00306     return;
00307 
00308   const TargetLowering *TLI = TM.getTargetLowering();
00309 
00310   SmallVector<EVT, 1> ValueVTs;
00311   ComputeValueVTs(*TLI, Ty, ValueVTs);
00312   assert(ValueVTs.size() == 1 &&
00313          "PHIs with non-vector integer types should have a single VT.");
00314   EVT IntVT = ValueVTs[0];
00315 
00316   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
00317     return;
00318   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
00319   unsigned BitWidth = IntVT.getSizeInBits();
00320 
00321   unsigned DestReg = ValueMap[PN];
00322   if (!TargetRegisterInfo::isVirtualRegister(DestReg))
00323     return;
00324   LiveOutRegInfo.grow(DestReg);
00325   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
00326 
00327   Value *V = PN->getIncomingValue(0);
00328   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00329     DestLOI.NumSignBits = 1;
00330     APInt Zero(BitWidth, 0);
00331     DestLOI.KnownZero = Zero;
00332     DestLOI.KnownOne = Zero;
00333     return;
00334   }
00335 
00336   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00337     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00338     DestLOI.NumSignBits = Val.getNumSignBits();
00339     DestLOI.KnownZero = ~Val;
00340     DestLOI.KnownOne = Val;
00341   } else {
00342     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
00343                                 "CopyToReg node was created.");
00344     unsigned SrcReg = ValueMap[V];
00345     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00346       DestLOI.IsValid = false;
00347       return;
00348     }
00349     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00350     if (!SrcLOI) {
00351       DestLOI.IsValid = false;
00352       return;
00353     }
00354     DestLOI = *SrcLOI;
00355   }
00356 
00357   assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
00358          DestLOI.KnownOne.getBitWidth() == BitWidth &&
00359          "Masks should have the same bit width as the type.");
00360 
00361   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
00362     Value *V = PN->getIncomingValue(i);
00363     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00364       DestLOI.NumSignBits = 1;
00365       APInt Zero(BitWidth, 0);
00366       DestLOI.KnownZero = Zero;
00367       DestLOI.KnownOne = Zero;
00368       return;
00369     }
00370 
00371     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00372       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00373       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
00374       DestLOI.KnownZero &= ~Val;
00375       DestLOI.KnownOne &= Val;
00376       continue;
00377     }
00378 
00379     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
00380                                 "its CopyToReg node was created.");
00381     unsigned SrcReg = ValueMap[V];
00382     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00383       DestLOI.IsValid = false;
00384       return;
00385     }
00386     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00387     if (!SrcLOI) {
00388       DestLOI.IsValid = false;
00389       return;
00390     }
00391     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
00392     DestLOI.KnownZero &= SrcLOI->KnownZero;
00393     DestLOI.KnownOne &= SrcLOI->KnownOne;
00394   }
00395 }
00396 
00397 /// setArgumentFrameIndex - Record frame index for the byval
00398 /// argument. This overrides previous frame index entry for this argument,
00399 /// if any.
00400 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
00401                                                  int FI) {
00402   ByValArgFrameIndexMap[A] = FI;
00403 }
00404 
00405 /// getArgumentFrameIndex - Get frame index for the byval argument.
00406 /// If the argument does not have any assigned frame index then 0 is
00407 /// returned.
00408 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
00409   DenseMap<const Argument *, int>::iterator I =
00410     ByValArgFrameIndexMap.find(A);
00411   if (I != ByValArgFrameIndexMap.end())
00412     return I->second;
00413   DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
00414   return 0;
00415 }
00416 
00417 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
00418 /// being passed to this variadic function, and set the MachineModuleInfo's
00419 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
00420 /// reference to _fltused on Windows, which will link in MSVCRT's
00421 /// floating-point support.
00422 void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
00423                                       MachineModuleInfo *MMI)
00424 {
00425   FunctionType *FT = cast<FunctionType>(
00426     I.getCalledValue()->getType()->getContainedType(0));
00427   if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
00428     for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
00429       Type* T = I.getArgOperand(i)->getType();
00430       for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
00431            i != e; ++i) {
00432         if (i->isFloatingPointTy()) {
00433           MMI->setUsesVAFloatArgument(true);
00434           return;
00435         }
00436       }
00437     }
00438   }
00439 }
00440 
00441 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
00442 /// call, and add them to the specified machine basic block.
00443 void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI,
00444                         MachineBasicBlock *MBB) {
00445   // Inform the MachineModuleInfo of the personality for this landing pad.
00446   const ConstantExpr *CE = cast<ConstantExpr>(I.getArgOperand(1));
00447   assert(CE->getOpcode() == Instruction::BitCast &&
00448          isa<Function>(CE->getOperand(0)) &&
00449          "Personality should be a function");
00450   MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
00451 
00452   // Gather all the type infos for this landing pad and pass them along to
00453   // MachineModuleInfo.
00454   std::vector<const GlobalVariable *> TyInfo;
00455   unsigned N = I.getNumArgOperands();
00456 
00457   for (unsigned i = N - 1; i > 1; --i) {
00458     if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(i))) {
00459       unsigned FilterLength = CI->getZExtValue();
00460       unsigned FirstCatch = i + FilterLength + !FilterLength;
00461       assert(FirstCatch <= N && "Invalid filter length");
00462 
00463       if (FirstCatch < N) {
00464         TyInfo.reserve(N - FirstCatch);
00465         for (unsigned j = FirstCatch; j < N; ++j)
00466           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00467         MMI->addCatchTypeInfo(MBB, TyInfo);
00468         TyInfo.clear();
00469       }
00470 
00471       if (!FilterLength) {
00472         // Cleanup.
00473         MMI->addCleanup(MBB);
00474       } else {
00475         // Filter.
00476         TyInfo.reserve(FilterLength - 1);
00477         for (unsigned j = i + 1; j < FirstCatch; ++j)
00478           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00479         MMI->addFilterTypeInfo(MBB, TyInfo);
00480         TyInfo.clear();
00481       }
00482 
00483       N = i;
00484     }
00485   }
00486 
00487   if (N > 2) {
00488     TyInfo.reserve(N - 2);
00489     for (unsigned j = 2; j < N; ++j)
00490       TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00491     MMI->addCatchTypeInfo(MBB, TyInfo);
00492   }
00493 }
00494 
00495 /// AddLandingPadInfo - Extract the exception handling information from the
00496 /// landingpad instruction and add them to the specified machine module info.
00497 void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
00498                              MachineBasicBlock *MBB) {
00499   MMI.addPersonality(MBB,
00500                      cast<Function>(I.getPersonalityFn()->stripPointerCasts()));
00501 
00502   if (I.isCleanup())
00503     MMI.addCleanup(MBB);
00504 
00505   // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
00506   //        but we need to do it this way because of how the DWARF EH emitter
00507   //        processes the clauses.
00508   for (unsigned i = I.getNumClauses(); i != 0; --i) {
00509     Value *Val = I.getClause(i - 1);
00510     if (I.isCatch(i - 1)) {
00511       MMI.addCatchTypeInfo(MBB,
00512                            dyn_cast<GlobalVariable>(Val->stripPointerCasts()));
00513     } else {
00514       // Add filters in a list.
00515       Constant *CVal = cast<Constant>(Val);
00516       SmallVector<const GlobalVariable*, 4> FilterList;
00517       for (User::op_iterator
00518              II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
00519         FilterList.push_back(cast<GlobalVariable>((*II)->stripPointerCasts()));
00520 
00521       MMI.addFilterTypeInfo(MBB, FilterList);
00522     }
00523   }
00524 }