LLVM API Documentation

FunctionLoweringInfo.cpp
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00001 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This implements routines for translating functions from LLVM IR into
00011 // Machine IR.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "llvm/CodeGen/FunctionLoweringInfo.h"
00016 #include "llvm/ADT/PostOrderIterator.h"
00017 #include "llvm/CodeGen/Analysis.h"
00018 #include "llvm/CodeGen/MachineFrameInfo.h"
00019 #include "llvm/CodeGen/MachineFunction.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/MachineModuleInfo.h"
00022 #include "llvm/CodeGen/MachineRegisterInfo.h"
00023 #include "llvm/IR/DataLayout.h"
00024 #include "llvm/IR/DebugInfo.h"
00025 #include "llvm/IR/DerivedTypes.h"
00026 #include "llvm/IR/Function.h"
00027 #include "llvm/IR/Instructions.h"
00028 #include "llvm/IR/IntrinsicInst.h"
00029 #include "llvm/IR/LLVMContext.h"
00030 #include "llvm/IR/Module.h"
00031 #include "llvm/Support/Debug.h"
00032 #include "llvm/Support/ErrorHandling.h"
00033 #include "llvm/Support/MathExtras.h"
00034 #include "llvm/Target/TargetFrameLowering.h"
00035 #include "llvm/Target/TargetInstrInfo.h"
00036 #include "llvm/Target/TargetLowering.h"
00037 #include "llvm/Target/TargetOptions.h"
00038 #include "llvm/Target/TargetRegisterInfo.h"
00039 #include <algorithm>
00040 using namespace llvm;
00041 
00042 #define DEBUG_TYPE "function-lowering-info"
00043 
00044 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
00045 /// PHI nodes or outside of the basic block that defines it, or used by a
00046 /// switch or atomic instruction, which may expand to multiple basic blocks.
00047 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
00048   if (I->use_empty()) return false;
00049   if (isa<PHINode>(I)) return true;
00050   const BasicBlock *BB = I->getParent();
00051   for (const User *U : I->users())
00052     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
00053       return true;
00054 
00055   return false;
00056 }
00057 
00058 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
00059                                SelectionDAG *DAG) {
00060   const TargetLowering *TLI = TM.getTargetLowering();
00061 
00062   Fn = &fn;
00063   MF = &mf;
00064   RegInfo = &MF->getRegInfo();
00065 
00066   // Check whether the function can return without sret-demotion.
00067   SmallVector<ISD::OutputArg, 4> Outs;
00068   GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
00069   CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
00070                                        Fn->isVarArg(),
00071                                        Outs, Fn->getContext());
00072 
00073   // Initialize the mapping of values to registers.  This is only set up for
00074   // instruction values that are used outside of the block that defines
00075   // them.
00076   Function::const_iterator BB = Fn->begin(), EB = Fn->end();
00077   for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
00078     if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
00079       // Don't fold inalloca allocas or other dynamic allocas into the initial
00080       // stack frame allocation, even if they are in the entry block.
00081       if (!AI->isStaticAlloca())
00082         continue;
00083 
00084       if (const ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
00085         Type *Ty = AI->getAllocatedType();
00086         uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
00087         unsigned Align =
00088           std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
00089                    AI->getAlignment());
00090 
00091         TySize *= CUI->getZExtValue();   // Get total allocated size.
00092         if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
00093 
00094         StaticAllocaMap[AI] =
00095           MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
00096       }
00097     }
00098 
00099   for (; BB != EB; ++BB)
00100     for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
00101          I != E; ++I) {
00102       // Look for dynamic allocas.
00103       if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
00104         if (!AI->isStaticAlloca()) {
00105           unsigned Align = std::max(
00106               (unsigned)TLI->getDataLayout()->getPrefTypeAlignment(
00107                 AI->getAllocatedType()),
00108               AI->getAlignment());
00109           unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
00110           if (Align <= StackAlign)
00111             Align = 0;
00112           // Inform the Frame Information that we have variable-sized objects.
00113           MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
00114         }
00115       }
00116 
00117       // Look for inline asm that clobbers the SP register.
00118       if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
00119         ImmutableCallSite CS(I);
00120         if (isa<InlineAsm>(CS.getCalledValue())) {
00121           unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
00122           std::vector<TargetLowering::AsmOperandInfo> Ops =
00123             TLI->ParseConstraints(CS);
00124           for (size_t I = 0, E = Ops.size(); I != E; ++I) {
00125             TargetLowering::AsmOperandInfo &Op = Ops[I];
00126             if (Op.Type == InlineAsm::isClobber) {
00127               // Clobbers don't have SDValue operands, hence SDValue().
00128               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
00129               std::pair<unsigned, const TargetRegisterClass*> PhysReg =
00130                 TLI->getRegForInlineAsmConstraint(Op.ConstraintCode,
00131                                                   Op.ConstraintVT);
00132               if (PhysReg.first == SP)
00133                 MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
00134             }
00135           }
00136         }
00137       }
00138 
00139       // Mark values used outside their block as exported, by allocating
00140       // a virtual register for them.
00141       if (isUsedOutsideOfDefiningBlock(I))
00142         if (!isa<AllocaInst>(I) ||
00143             !StaticAllocaMap.count(cast<AllocaInst>(I)))
00144           InitializeRegForValue(I);
00145 
00146       // Collect llvm.dbg.declare information. This is done now instead of
00147       // during the initial isel pass through the IR so that it is done
00148       // in a predictable order.
00149       if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
00150         MachineModuleInfo &MMI = MF->getMMI();
00151         DIVariable DIVar(DI->getVariable());
00152         assert((!DIVar || DIVar.isVariable()) &&
00153           "Variable in DbgDeclareInst should be either null or a DIVariable.");
00154         if (MMI.hasDebugInfo() &&
00155             DIVar &&
00156             !DI->getDebugLoc().isUnknown()) {
00157           // Don't handle byval struct arguments or VLAs, for example.
00158           // Non-byval arguments are handled here (they refer to the stack
00159           // temporary alloca at this point).
00160           const Value *Address = DI->getAddress();
00161           if (Address) {
00162             if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
00163               Address = BCI->getOperand(0);
00164             if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
00165               DenseMap<const AllocaInst *, int>::iterator SI =
00166                 StaticAllocaMap.find(AI);
00167               if (SI != StaticAllocaMap.end()) { // Check for VLAs.
00168                 int FI = SI->second;
00169                 MMI.setVariableDbgInfo(DI->getVariable(),
00170                                        FI, DI->getDebugLoc());
00171               }
00172             }
00173           }
00174         }
00175       }
00176     }
00177 
00178   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
00179   // also creates the initial PHI MachineInstrs, though none of the input
00180   // operands are populated.
00181   for (BB = Fn->begin(); BB != EB; ++BB) {
00182     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
00183     MBBMap[BB] = MBB;
00184     MF->push_back(MBB);
00185 
00186     // Transfer the address-taken flag. This is necessary because there could
00187     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
00188     // the first one should be marked.
00189     if (BB->hasAddressTaken())
00190       MBB->setHasAddressTaken();
00191 
00192     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
00193     // appropriate.
00194     for (BasicBlock::const_iterator I = BB->begin();
00195          const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
00196       if (PN->use_empty()) continue;
00197 
00198       // Skip empty types
00199       if (PN->getType()->isEmptyTy())
00200         continue;
00201 
00202       DebugLoc DL = PN->getDebugLoc();
00203       unsigned PHIReg = ValueMap[PN];
00204       assert(PHIReg && "PHI node does not have an assigned virtual register!");
00205 
00206       SmallVector<EVT, 4> ValueVTs;
00207       ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
00208       for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
00209         EVT VT = ValueVTs[vti];
00210         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
00211         const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
00212         for (unsigned i = 0; i != NumRegisters; ++i)
00213           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
00214         PHIReg += NumRegisters;
00215       }
00216     }
00217   }
00218 
00219   // Mark landing pad blocks.
00220   for (BB = Fn->begin(); BB != EB; ++BB)
00221     if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
00222       MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
00223 }
00224 
00225 /// clear - Clear out all the function-specific state. This returns this
00226 /// FunctionLoweringInfo to an empty state, ready to be used for a
00227 /// different function.
00228 void FunctionLoweringInfo::clear() {
00229   assert(CatchInfoFound.size() == CatchInfoLost.size() &&
00230          "Not all catch info was assigned to a landing pad!");
00231 
00232   MBBMap.clear();
00233   ValueMap.clear();
00234   StaticAllocaMap.clear();
00235 #ifndef NDEBUG
00236   CatchInfoLost.clear();
00237   CatchInfoFound.clear();
00238 #endif
00239   LiveOutRegInfo.clear();
00240   VisitedBBs.clear();
00241   ArgDbgValues.clear();
00242   ByValArgFrameIndexMap.clear();
00243   RegFixups.clear();
00244 }
00245 
00246 /// CreateReg - Allocate a single virtual register for the given type.
00247 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
00248   return RegInfo->
00249     createVirtualRegister(TM.getTargetLowering()->getRegClassFor(VT));
00250 }
00251 
00252 /// CreateRegs - Allocate the appropriate number of virtual registers of
00253 /// the correctly promoted or expanded types.  Assign these registers
00254 /// consecutive vreg numbers and return the first assigned number.
00255 ///
00256 /// In the case that the given value has struct or array type, this function
00257 /// will assign registers for each member or element.
00258 ///
00259 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
00260   const TargetLowering *TLI = TM.getTargetLowering();
00261 
00262   SmallVector<EVT, 4> ValueVTs;
00263   ComputeValueVTs(*TLI, Ty, ValueVTs);
00264 
00265   unsigned FirstReg = 0;
00266   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
00267     EVT ValueVT = ValueVTs[Value];
00268     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
00269 
00270     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
00271     for (unsigned i = 0; i != NumRegs; ++i) {
00272       unsigned R = CreateReg(RegisterVT);
00273       if (!FirstReg) FirstReg = R;
00274     }
00275   }
00276   return FirstReg;
00277 }
00278 
00279 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
00280 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
00281 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
00282 /// the larger bit width by zero extension. The bit width must be no smaller
00283 /// than the LiveOutInfo's existing bit width.
00284 const FunctionLoweringInfo::LiveOutInfo *
00285 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
00286   if (!LiveOutRegInfo.inBounds(Reg))
00287     return nullptr;
00288 
00289   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
00290   if (!LOI->IsValid)
00291     return nullptr;
00292 
00293   if (BitWidth > LOI->KnownZero.getBitWidth()) {
00294     LOI->NumSignBits = 1;
00295     LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
00296     LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
00297   }
00298 
00299   return LOI;
00300 }
00301 
00302 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
00303 /// register based on the LiveOutInfo of its operands.
00304 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
00305   Type *Ty = PN->getType();
00306   if (!Ty->isIntegerTy() || Ty->isVectorTy())
00307     return;
00308 
00309   const TargetLowering *TLI = TM.getTargetLowering();
00310 
00311   SmallVector<EVT, 1> ValueVTs;
00312   ComputeValueVTs(*TLI, Ty, ValueVTs);
00313   assert(ValueVTs.size() == 1 &&
00314          "PHIs with non-vector integer types should have a single VT.");
00315   EVT IntVT = ValueVTs[0];
00316 
00317   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
00318     return;
00319   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
00320   unsigned BitWidth = IntVT.getSizeInBits();
00321 
00322   unsigned DestReg = ValueMap[PN];
00323   if (!TargetRegisterInfo::isVirtualRegister(DestReg))
00324     return;
00325   LiveOutRegInfo.grow(DestReg);
00326   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
00327 
00328   Value *V = PN->getIncomingValue(0);
00329   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00330     DestLOI.NumSignBits = 1;
00331     APInt Zero(BitWidth, 0);
00332     DestLOI.KnownZero = Zero;
00333     DestLOI.KnownOne = Zero;
00334     return;
00335   }
00336 
00337   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00338     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00339     DestLOI.NumSignBits = Val.getNumSignBits();
00340     DestLOI.KnownZero = ~Val;
00341     DestLOI.KnownOne = Val;
00342   } else {
00343     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
00344                                 "CopyToReg node was created.");
00345     unsigned SrcReg = ValueMap[V];
00346     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00347       DestLOI.IsValid = false;
00348       return;
00349     }
00350     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00351     if (!SrcLOI) {
00352       DestLOI.IsValid = false;
00353       return;
00354     }
00355     DestLOI = *SrcLOI;
00356   }
00357 
00358   assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
00359          DestLOI.KnownOne.getBitWidth() == BitWidth &&
00360          "Masks should have the same bit width as the type.");
00361 
00362   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
00363     Value *V = PN->getIncomingValue(i);
00364     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00365       DestLOI.NumSignBits = 1;
00366       APInt Zero(BitWidth, 0);
00367       DestLOI.KnownZero = Zero;
00368       DestLOI.KnownOne = Zero;
00369       return;
00370     }
00371 
00372     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00373       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00374       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
00375       DestLOI.KnownZero &= ~Val;
00376       DestLOI.KnownOne &= Val;
00377       continue;
00378     }
00379 
00380     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
00381                                 "its CopyToReg node was created.");
00382     unsigned SrcReg = ValueMap[V];
00383     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00384       DestLOI.IsValid = false;
00385       return;
00386     }
00387     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00388     if (!SrcLOI) {
00389       DestLOI.IsValid = false;
00390       return;
00391     }
00392     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
00393     DestLOI.KnownZero &= SrcLOI->KnownZero;
00394     DestLOI.KnownOne &= SrcLOI->KnownOne;
00395   }
00396 }
00397 
00398 /// setArgumentFrameIndex - Record frame index for the byval
00399 /// argument. This overrides previous frame index entry for this argument,
00400 /// if any.
00401 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
00402                                                  int FI) {
00403   ByValArgFrameIndexMap[A] = FI;
00404 }
00405 
00406 /// getArgumentFrameIndex - Get frame index for the byval argument.
00407 /// If the argument does not have any assigned frame index then 0 is
00408 /// returned.
00409 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
00410   DenseMap<const Argument *, int>::iterator I =
00411     ByValArgFrameIndexMap.find(A);
00412   if (I != ByValArgFrameIndexMap.end())
00413     return I->second;
00414   DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
00415   return 0;
00416 }
00417 
00418 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
00419 /// being passed to this variadic function, and set the MachineModuleInfo's
00420 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
00421 /// reference to _fltused on Windows, which will link in MSVCRT's
00422 /// floating-point support.
00423 void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
00424                                       MachineModuleInfo *MMI)
00425 {
00426   FunctionType *FT = cast<FunctionType>(
00427     I.getCalledValue()->getType()->getContainedType(0));
00428   if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
00429     for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
00430       Type* T = I.getArgOperand(i)->getType();
00431       for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
00432            i != e; ++i) {
00433         if (i->isFloatingPointTy()) {
00434           MMI->setUsesVAFloatArgument(true);
00435           return;
00436         }
00437       }
00438     }
00439   }
00440 }
00441 
00442 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
00443 /// call, and add them to the specified machine basic block.
00444 void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI,
00445                         MachineBasicBlock *MBB) {
00446   // Inform the MachineModuleInfo of the personality for this landing pad.
00447   const ConstantExpr *CE = cast<ConstantExpr>(I.getArgOperand(1));
00448   assert(CE->getOpcode() == Instruction::BitCast &&
00449          isa<Function>(CE->getOperand(0)) &&
00450          "Personality should be a function");
00451   MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
00452 
00453   // Gather all the type infos for this landing pad and pass them along to
00454   // MachineModuleInfo.
00455   std::vector<const GlobalVariable *> TyInfo;
00456   unsigned N = I.getNumArgOperands();
00457 
00458   for (unsigned i = N - 1; i > 1; --i) {
00459     if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(i))) {
00460       unsigned FilterLength = CI->getZExtValue();
00461       unsigned FirstCatch = i + FilterLength + !FilterLength;
00462       assert(FirstCatch <= N && "Invalid filter length");
00463 
00464       if (FirstCatch < N) {
00465         TyInfo.reserve(N - FirstCatch);
00466         for (unsigned j = FirstCatch; j < N; ++j)
00467           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00468         MMI->addCatchTypeInfo(MBB, TyInfo);
00469         TyInfo.clear();
00470       }
00471 
00472       if (!FilterLength) {
00473         // Cleanup.
00474         MMI->addCleanup(MBB);
00475       } else {
00476         // Filter.
00477         TyInfo.reserve(FilterLength - 1);
00478         for (unsigned j = i + 1; j < FirstCatch; ++j)
00479           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00480         MMI->addFilterTypeInfo(MBB, TyInfo);
00481         TyInfo.clear();
00482       }
00483 
00484       N = i;
00485     }
00486   }
00487 
00488   if (N > 2) {
00489     TyInfo.reserve(N - 2);
00490     for (unsigned j = 2; j < N; ++j)
00491       TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00492     MMI->addCatchTypeInfo(MBB, TyInfo);
00493   }
00494 }
00495 
00496 /// AddLandingPadInfo - Extract the exception handling information from the
00497 /// landingpad instruction and add them to the specified machine module info.
00498 void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
00499                              MachineBasicBlock *MBB) {
00500   MMI.addPersonality(MBB,
00501                      cast<Function>(I.getPersonalityFn()->stripPointerCasts()));
00502 
00503   if (I.isCleanup())
00504     MMI.addCleanup(MBB);
00505 
00506   // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
00507   //        but we need to do it this way because of how the DWARF EH emitter
00508   //        processes the clauses.
00509   for (unsigned i = I.getNumClauses(); i != 0; --i) {
00510     Value *Val = I.getClause(i - 1);
00511     if (I.isCatch(i - 1)) {
00512       MMI.addCatchTypeInfo(MBB,
00513                            dyn_cast<GlobalVariable>(Val->stripPointerCasts()));
00514     } else {
00515       // Add filters in a list.
00516       Constant *CVal = cast<Constant>(Val);
00517       SmallVector<const GlobalVariable*, 4> FilterList;
00518       for (User::op_iterator
00519              II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
00520         FilterList.push_back(cast<GlobalVariable>((*II)->stripPointerCasts()));
00521 
00522       MMI.addFilterTypeInfo(MBB, FilterList);
00523     }
00524   }
00525 }