LLVM API Documentation

FunctionLoweringInfo.cpp
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00001 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This implements routines for translating functions from LLVM IR into
00011 // Machine IR.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "llvm/CodeGen/FunctionLoweringInfo.h"
00016 #include "llvm/ADT/PostOrderIterator.h"
00017 #include "llvm/CodeGen/Analysis.h"
00018 #include "llvm/CodeGen/MachineFrameInfo.h"
00019 #include "llvm/CodeGen/MachineFunction.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/MachineModuleInfo.h"
00022 #include "llvm/CodeGen/MachineRegisterInfo.h"
00023 #include "llvm/IR/DataLayout.h"
00024 #include "llvm/IR/DebugInfo.h"
00025 #include "llvm/IR/DerivedTypes.h"
00026 #include "llvm/IR/Function.h"
00027 #include "llvm/IR/Instructions.h"
00028 #include "llvm/IR/IntrinsicInst.h"
00029 #include "llvm/IR/LLVMContext.h"
00030 #include "llvm/IR/Module.h"
00031 #include "llvm/Support/Debug.h"
00032 #include "llvm/Support/ErrorHandling.h"
00033 #include "llvm/Support/MathExtras.h"
00034 #include "llvm/Target/TargetFrameLowering.h"
00035 #include "llvm/Target/TargetInstrInfo.h"
00036 #include "llvm/Target/TargetLowering.h"
00037 #include "llvm/Target/TargetOptions.h"
00038 #include "llvm/Target/TargetRegisterInfo.h"
00039 #include "llvm/Target/TargetSubtargetInfo.h"
00040 #include <algorithm>
00041 using namespace llvm;
00042 
00043 #define DEBUG_TYPE "function-lowering-info"
00044 
00045 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
00046 /// PHI nodes or outside of the basic block that defines it, or used by a
00047 /// switch or atomic instruction, which may expand to multiple basic blocks.
00048 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
00049   if (I->use_empty()) return false;
00050   if (isa<PHINode>(I)) return true;
00051   const BasicBlock *BB = I->getParent();
00052   for (const User *U : I->users())
00053     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
00054       return true;
00055 
00056   return false;
00057 }
00058 
00059 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
00060                                SelectionDAG *DAG) {
00061   const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
00062 
00063   Fn = &fn;
00064   MF = &mf;
00065   RegInfo = &MF->getRegInfo();
00066 
00067   // Check whether the function can return without sret-demotion.
00068   SmallVector<ISD::OutputArg, 4> Outs;
00069   GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
00070   CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
00071                                        Fn->isVarArg(),
00072                                        Outs, Fn->getContext());
00073 
00074   // Initialize the mapping of values to registers.  This is only set up for
00075   // instruction values that are used outside of the block that defines
00076   // them.
00077   Function::const_iterator BB = Fn->begin(), EB = Fn->end();
00078   for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
00079     if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
00080       // Don't fold inalloca allocas or other dynamic allocas into the initial
00081       // stack frame allocation, even if they are in the entry block.
00082       if (!AI->isStaticAlloca())
00083         continue;
00084 
00085       if (const ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
00086         Type *Ty = AI->getAllocatedType();
00087         uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
00088         unsigned Align =
00089           std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
00090                    AI->getAlignment());
00091 
00092         TySize *= CUI->getZExtValue();   // Get total allocated size.
00093         if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
00094 
00095         StaticAllocaMap[AI] =
00096           MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
00097       }
00098     }
00099 
00100   for (; BB != EB; ++BB)
00101     for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
00102          I != E; ++I) {
00103       // Look for dynamic allocas.
00104       if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
00105         if (!AI->isStaticAlloca()) {
00106           unsigned Align = std::max(
00107               (unsigned)TLI->getDataLayout()->getPrefTypeAlignment(
00108                 AI->getAllocatedType()),
00109               AI->getAlignment());
00110           unsigned StackAlign =
00111               TM.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
00112           if (Align <= StackAlign)
00113             Align = 0;
00114           // Inform the Frame Information that we have variable-sized objects.
00115           MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
00116         }
00117       }
00118 
00119       // Look for inline asm that clobbers the SP register.
00120       if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
00121         ImmutableCallSite CS(I);
00122         if (isa<InlineAsm>(CS.getCalledValue())) {
00123           unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
00124           std::vector<TargetLowering::AsmOperandInfo> Ops =
00125             TLI->ParseConstraints(CS);
00126           for (size_t I = 0, E = Ops.size(); I != E; ++I) {
00127             TargetLowering::AsmOperandInfo &Op = Ops[I];
00128             if (Op.Type == InlineAsm::isClobber) {
00129               // Clobbers don't have SDValue operands, hence SDValue().
00130               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
00131               std::pair<unsigned, const TargetRegisterClass*> PhysReg =
00132                 TLI->getRegForInlineAsmConstraint(Op.ConstraintCode,
00133                                                   Op.ConstraintVT);
00134               if (PhysReg.first == SP)
00135                 MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
00136             }
00137           }
00138         }
00139       }
00140 
00141       // Look for calls to the @llvm.va_start intrinsic. We can omit some
00142       // prologue boilerplate for variadic functions that don't examine their
00143       // arguments.
00144       if (const auto *II = dyn_cast<IntrinsicInst>(I)) {
00145         if (II->getIntrinsicID() == Intrinsic::vastart)
00146           MF->getFrameInfo()->setHasVAStart(true);
00147       }
00148 
00149       // If we have a musttail call in a variadic funciton, we need to ensure we
00150       // forward implicit register parameters.
00151       if (const auto *CI = dyn_cast<CallInst>(I)) {
00152         if (CI->isMustTailCall() && Fn->isVarArg())
00153           MF->getFrameInfo()->setHasMustTailInVarArgFunc(true);
00154       }
00155 
00156       // Mark values used outside their block as exported, by allocating
00157       // a virtual register for them.
00158       if (isUsedOutsideOfDefiningBlock(I))
00159         if (!isa<AllocaInst>(I) ||
00160             !StaticAllocaMap.count(cast<AllocaInst>(I)))
00161           InitializeRegForValue(I);
00162 
00163       // Collect llvm.dbg.declare information. This is done now instead of
00164       // during the initial isel pass through the IR so that it is done
00165       // in a predictable order.
00166       if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
00167         MachineModuleInfo &MMI = MF->getMMI();
00168         DIVariable DIVar(DI->getVariable());
00169         assert((!DIVar || DIVar.isVariable()) &&
00170           "Variable in DbgDeclareInst should be either null or a DIVariable.");
00171         if (MMI.hasDebugInfo() &&
00172             DIVar &&
00173             !DI->getDebugLoc().isUnknown()) {
00174           // Don't handle byval struct arguments or VLAs, for example.
00175           // Non-byval arguments are handled here (they refer to the stack
00176           // temporary alloca at this point).
00177           const Value *Address = DI->getAddress();
00178           if (Address) {
00179             if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
00180               Address = BCI->getOperand(0);
00181             if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
00182               DenseMap<const AllocaInst *, int>::iterator SI =
00183                 StaticAllocaMap.find(AI);
00184               if (SI != StaticAllocaMap.end()) { // Check for VLAs.
00185                 int FI = SI->second;
00186                 MMI.setVariableDbgInfo(DI->getVariable(),
00187                                        FI, DI->getDebugLoc());
00188               }
00189             }
00190           }
00191         }
00192       }
00193     }
00194 
00195   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
00196   // also creates the initial PHI MachineInstrs, though none of the input
00197   // operands are populated.
00198   for (BB = Fn->begin(); BB != EB; ++BB) {
00199     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
00200     MBBMap[BB] = MBB;
00201     MF->push_back(MBB);
00202 
00203     // Transfer the address-taken flag. This is necessary because there could
00204     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
00205     // the first one should be marked.
00206     if (BB->hasAddressTaken())
00207       MBB->setHasAddressTaken();
00208 
00209     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
00210     // appropriate.
00211     for (BasicBlock::const_iterator I = BB->begin();
00212          const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
00213       if (PN->use_empty()) continue;
00214 
00215       // Skip empty types
00216       if (PN->getType()->isEmptyTy())
00217         continue;
00218 
00219       DebugLoc DL = PN->getDebugLoc();
00220       unsigned PHIReg = ValueMap[PN];
00221       assert(PHIReg && "PHI node does not have an assigned virtual register!");
00222 
00223       SmallVector<EVT, 4> ValueVTs;
00224       ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
00225       for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
00226         EVT VT = ValueVTs[vti];
00227         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
00228         const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
00229         for (unsigned i = 0; i != NumRegisters; ++i)
00230           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
00231         PHIReg += NumRegisters;
00232       }
00233     }
00234   }
00235 
00236   // Mark landing pad blocks.
00237   for (BB = Fn->begin(); BB != EB; ++BB)
00238     if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
00239       MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
00240 }
00241 
00242 /// clear - Clear out all the function-specific state. This returns this
00243 /// FunctionLoweringInfo to an empty state, ready to be used for a
00244 /// different function.
00245 void FunctionLoweringInfo::clear() {
00246   assert(CatchInfoFound.size() == CatchInfoLost.size() &&
00247          "Not all catch info was assigned to a landing pad!");
00248 
00249   MBBMap.clear();
00250   ValueMap.clear();
00251   StaticAllocaMap.clear();
00252 #ifndef NDEBUG
00253   CatchInfoLost.clear();
00254   CatchInfoFound.clear();
00255 #endif
00256   LiveOutRegInfo.clear();
00257   VisitedBBs.clear();
00258   ArgDbgValues.clear();
00259   ByValArgFrameIndexMap.clear();
00260   RegFixups.clear();
00261 }
00262 
00263 /// CreateReg - Allocate a single virtual register for the given type.
00264 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
00265   return RegInfo->createVirtualRegister(
00266       TM.getSubtargetImpl()->getTargetLowering()->getRegClassFor(VT));
00267 }
00268 
00269 /// CreateRegs - Allocate the appropriate number of virtual registers of
00270 /// the correctly promoted or expanded types.  Assign these registers
00271 /// consecutive vreg numbers and return the first assigned number.
00272 ///
00273 /// In the case that the given value has struct or array type, this function
00274 /// will assign registers for each member or element.
00275 ///
00276 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
00277   const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
00278 
00279   SmallVector<EVT, 4> ValueVTs;
00280   ComputeValueVTs(*TLI, Ty, ValueVTs);
00281 
00282   unsigned FirstReg = 0;
00283   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
00284     EVT ValueVT = ValueVTs[Value];
00285     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
00286 
00287     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
00288     for (unsigned i = 0; i != NumRegs; ++i) {
00289       unsigned R = CreateReg(RegisterVT);
00290       if (!FirstReg) FirstReg = R;
00291     }
00292   }
00293   return FirstReg;
00294 }
00295 
00296 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
00297 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
00298 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
00299 /// the larger bit width by zero extension. The bit width must be no smaller
00300 /// than the LiveOutInfo's existing bit width.
00301 const FunctionLoweringInfo::LiveOutInfo *
00302 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
00303   if (!LiveOutRegInfo.inBounds(Reg))
00304     return nullptr;
00305 
00306   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
00307   if (!LOI->IsValid)
00308     return nullptr;
00309 
00310   if (BitWidth > LOI->KnownZero.getBitWidth()) {
00311     LOI->NumSignBits = 1;
00312     LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
00313     LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
00314   }
00315 
00316   return LOI;
00317 }
00318 
00319 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
00320 /// register based on the LiveOutInfo of its operands.
00321 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
00322   Type *Ty = PN->getType();
00323   if (!Ty->isIntegerTy() || Ty->isVectorTy())
00324     return;
00325 
00326   const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
00327 
00328   SmallVector<EVT, 1> ValueVTs;
00329   ComputeValueVTs(*TLI, Ty, ValueVTs);
00330   assert(ValueVTs.size() == 1 &&
00331          "PHIs with non-vector integer types should have a single VT.");
00332   EVT IntVT = ValueVTs[0];
00333 
00334   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
00335     return;
00336   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
00337   unsigned BitWidth = IntVT.getSizeInBits();
00338 
00339   unsigned DestReg = ValueMap[PN];
00340   if (!TargetRegisterInfo::isVirtualRegister(DestReg))
00341     return;
00342   LiveOutRegInfo.grow(DestReg);
00343   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
00344 
00345   Value *V = PN->getIncomingValue(0);
00346   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00347     DestLOI.NumSignBits = 1;
00348     APInt Zero(BitWidth, 0);
00349     DestLOI.KnownZero = Zero;
00350     DestLOI.KnownOne = Zero;
00351     return;
00352   }
00353 
00354   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00355     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00356     DestLOI.NumSignBits = Val.getNumSignBits();
00357     DestLOI.KnownZero = ~Val;
00358     DestLOI.KnownOne = Val;
00359   } else {
00360     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
00361                                 "CopyToReg node was created.");
00362     unsigned SrcReg = ValueMap[V];
00363     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00364       DestLOI.IsValid = false;
00365       return;
00366     }
00367     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00368     if (!SrcLOI) {
00369       DestLOI.IsValid = false;
00370       return;
00371     }
00372     DestLOI = *SrcLOI;
00373   }
00374 
00375   assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
00376          DestLOI.KnownOne.getBitWidth() == BitWidth &&
00377          "Masks should have the same bit width as the type.");
00378 
00379   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
00380     Value *V = PN->getIncomingValue(i);
00381     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
00382       DestLOI.NumSignBits = 1;
00383       APInt Zero(BitWidth, 0);
00384       DestLOI.KnownZero = Zero;
00385       DestLOI.KnownOne = Zero;
00386       return;
00387     }
00388 
00389     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
00390       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
00391       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
00392       DestLOI.KnownZero &= ~Val;
00393       DestLOI.KnownOne &= Val;
00394       continue;
00395     }
00396 
00397     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
00398                                 "its CopyToReg node was created.");
00399     unsigned SrcReg = ValueMap[V];
00400     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
00401       DestLOI.IsValid = false;
00402       return;
00403     }
00404     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
00405     if (!SrcLOI) {
00406       DestLOI.IsValid = false;
00407       return;
00408     }
00409     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
00410     DestLOI.KnownZero &= SrcLOI->KnownZero;
00411     DestLOI.KnownOne &= SrcLOI->KnownOne;
00412   }
00413 }
00414 
00415 /// setArgumentFrameIndex - Record frame index for the byval
00416 /// argument. This overrides previous frame index entry for this argument,
00417 /// if any.
00418 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
00419                                                  int FI) {
00420   ByValArgFrameIndexMap[A] = FI;
00421 }
00422 
00423 /// getArgumentFrameIndex - Get frame index for the byval argument.
00424 /// If the argument does not have any assigned frame index then 0 is
00425 /// returned.
00426 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
00427   DenseMap<const Argument *, int>::iterator I =
00428     ByValArgFrameIndexMap.find(A);
00429   if (I != ByValArgFrameIndexMap.end())
00430     return I->second;
00431   DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
00432   return 0;
00433 }
00434 
00435 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
00436 /// being passed to this variadic function, and set the MachineModuleInfo's
00437 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
00438 /// reference to _fltused on Windows, which will link in MSVCRT's
00439 /// floating-point support.
00440 void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
00441                                       MachineModuleInfo *MMI)
00442 {
00443   FunctionType *FT = cast<FunctionType>(
00444     I.getCalledValue()->getType()->getContainedType(0));
00445   if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
00446     for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
00447       Type* T = I.getArgOperand(i)->getType();
00448       for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
00449            i != e; ++i) {
00450         if (i->isFloatingPointTy()) {
00451           MMI->setUsesVAFloatArgument(true);
00452           return;
00453         }
00454       }
00455     }
00456   }
00457 }
00458 
00459 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
00460 /// call, and add them to the specified machine basic block.
00461 void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI,
00462                         MachineBasicBlock *MBB) {
00463   // Inform the MachineModuleInfo of the personality for this landing pad.
00464   const ConstantExpr *CE = cast<ConstantExpr>(I.getArgOperand(1));
00465   assert(CE->getOpcode() == Instruction::BitCast &&
00466          isa<Function>(CE->getOperand(0)) &&
00467          "Personality should be a function");
00468   MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
00469 
00470   // Gather all the type infos for this landing pad and pass them along to
00471   // MachineModuleInfo.
00472   std::vector<const GlobalVariable *> TyInfo;
00473   unsigned N = I.getNumArgOperands();
00474 
00475   for (unsigned i = N - 1; i > 1; --i) {
00476     if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(i))) {
00477       unsigned FilterLength = CI->getZExtValue();
00478       unsigned FirstCatch = i + FilterLength + !FilterLength;
00479       assert(FirstCatch <= N && "Invalid filter length");
00480 
00481       if (FirstCatch < N) {
00482         TyInfo.reserve(N - FirstCatch);
00483         for (unsigned j = FirstCatch; j < N; ++j)
00484           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00485         MMI->addCatchTypeInfo(MBB, TyInfo);
00486         TyInfo.clear();
00487       }
00488 
00489       if (!FilterLength) {
00490         // Cleanup.
00491         MMI->addCleanup(MBB);
00492       } else {
00493         // Filter.
00494         TyInfo.reserve(FilterLength - 1);
00495         for (unsigned j = i + 1; j < FirstCatch; ++j)
00496           TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00497         MMI->addFilterTypeInfo(MBB, TyInfo);
00498         TyInfo.clear();
00499       }
00500 
00501       N = i;
00502     }
00503   }
00504 
00505   if (N > 2) {
00506     TyInfo.reserve(N - 2);
00507     for (unsigned j = 2; j < N; ++j)
00508       TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
00509     MMI->addCatchTypeInfo(MBB, TyInfo);
00510   }
00511 }
00512 
00513 /// AddLandingPadInfo - Extract the exception handling information from the
00514 /// landingpad instruction and add them to the specified machine module info.
00515 void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
00516                              MachineBasicBlock *MBB) {
00517   MMI.addPersonality(MBB,
00518                      cast<Function>(I.getPersonalityFn()->stripPointerCasts()));
00519 
00520   if (I.isCleanup())
00521     MMI.addCleanup(MBB);
00522 
00523   // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
00524   //        but we need to do it this way because of how the DWARF EH emitter
00525   //        processes the clauses.
00526   for (unsigned i = I.getNumClauses(); i != 0; --i) {
00527     Value *Val = I.getClause(i - 1);
00528     if (I.isCatch(i - 1)) {
00529       MMI.addCatchTypeInfo(MBB,
00530                            dyn_cast<GlobalVariable>(Val->stripPointerCasts()));
00531     } else {
00532       // Add filters in a list.
00533       Constant *CVal = cast<Constant>(Val);
00534       SmallVector<const GlobalVariable*, 4> FilterList;
00535       for (User::op_iterator
00536              II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
00537         FilterList.push_back(cast<GlobalVariable>((*II)->stripPointerCasts()));
00538 
00539       MMI.addFilterTypeInfo(MBB, FilterList);
00540     }
00541   }
00542 }