LLVM API Documentation
00001 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This implements the SelectionDAGISel class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #define DEBUG_TYPE "isel" 00015 #include "llvm/CodeGen/SelectionDAGISel.h" 00016 #include "ScheduleDAGSDNodes.h" 00017 #include "SelectionDAGBuilder.h" 00018 #include "llvm/ADT/PostOrderIterator.h" 00019 #include "llvm/ADT/Statistic.h" 00020 #include "llvm/Analysis/AliasAnalysis.h" 00021 #include "llvm/Analysis/BranchProbabilityInfo.h" 00022 #include "llvm/Analysis/TargetTransformInfo.h" 00023 #include "llvm/CodeGen/FastISel.h" 00024 #include "llvm/CodeGen/FunctionLoweringInfo.h" 00025 #include "llvm/CodeGen/GCMetadata.h" 00026 #include "llvm/CodeGen/GCStrategy.h" 00027 #include "llvm/CodeGen/MachineFrameInfo.h" 00028 #include "llvm/CodeGen/MachineFunction.h" 00029 #include "llvm/CodeGen/MachineInstrBuilder.h" 00030 #include "llvm/CodeGen/MachineModuleInfo.h" 00031 #include "llvm/CodeGen/MachineRegisterInfo.h" 00032 #include "llvm/CodeGen/ScheduleHazardRecognizer.h" 00033 #include "llvm/CodeGen/SchedulerRegistry.h" 00034 #include "llvm/CodeGen/SelectionDAG.h" 00035 #include "llvm/DebugInfo.h" 00036 #include "llvm/IR/Constants.h" 00037 #include "llvm/IR/Function.h" 00038 #include "llvm/IR/InlineAsm.h" 00039 #include "llvm/IR/Instructions.h" 00040 #include "llvm/IR/IntrinsicInst.h" 00041 #include "llvm/IR/Intrinsics.h" 00042 #include "llvm/IR/LLVMContext.h" 00043 #include "llvm/IR/Module.h" 00044 #include "llvm/Support/Compiler.h" 00045 #include "llvm/Support/Debug.h" 00046 #include "llvm/Support/ErrorHandling.h" 00047 #include "llvm/Support/Timer.h" 00048 #include "llvm/Support/raw_ostream.h" 00049 #include "llvm/Target/TargetInstrInfo.h" 00050 #include "llvm/Target/TargetIntrinsicInfo.h" 00051 #include "llvm/Target/TargetLibraryInfo.h" 00052 #include "llvm/Target/TargetLowering.h" 00053 #include "llvm/Target/TargetMachine.h" 00054 #include "llvm/Target/TargetOptions.h" 00055 #include "llvm/Target/TargetRegisterInfo.h" 00056 #include "llvm/Target/TargetSubtargetInfo.h" 00057 #include "llvm/Transforms/Utils/BasicBlockUtils.h" 00058 #include <algorithm> 00059 using namespace llvm; 00060 00061 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 00062 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 00063 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 00064 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 00065 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 00066 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 00067 STATISTIC(NumFastIselFailLowerArguments, 00068 "Number of entry blocks where fast isel failed to lower arguments"); 00069 00070 #ifndef NDEBUG 00071 static cl::opt<bool> 00072 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 00073 cl::desc("Enable extra verbose messages in the \"fast\" " 00074 "instruction selector")); 00075 00076 // Terminators 00077 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 00078 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 00079 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 00080 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 00081 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 00082 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 00083 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 00084 00085 // Standard binary operators... 00086 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 00087 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 00088 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 00089 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 00090 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 00091 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 00092 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 00093 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 00094 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 00095 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 00096 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 00097 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 00098 00099 // Logical operators... 00100 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 00101 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 00102 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 00103 00104 // Memory instructions... 00105 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 00106 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 00107 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 00108 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 00109 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 00110 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 00111 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 00112 00113 // Convert instructions... 00114 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 00115 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 00116 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 00117 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 00118 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 00119 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 00120 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 00121 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 00122 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 00123 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 00124 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 00125 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 00126 00127 // Other instructions... 00128 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 00129 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 00130 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 00131 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 00132 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 00133 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 00134 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 00135 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 00136 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 00137 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 00138 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 00139 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 00140 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 00141 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 00142 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 00143 #endif 00144 00145 static cl::opt<bool> 00146 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 00147 cl::desc("Enable verbose messages in the \"fast\" " 00148 "instruction selector")); 00149 static cl::opt<bool> 00150 EnableFastISelAbort("fast-isel-abort", cl::Hidden, 00151 cl::desc("Enable abort calls when \"fast\" instruction selection " 00152 "fails to lower an instruction")); 00153 static cl::opt<bool> 00154 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 00155 cl::desc("Enable abort calls when \"fast\" instruction selection " 00156 "fails to lower a formal argument")); 00157 00158 static cl::opt<bool> 00159 UseMBPI("use-mbpi", 00160 cl::desc("use Machine Branch Probability Info"), 00161 cl::init(true), cl::Hidden); 00162 00163 #ifndef NDEBUG 00164 static cl::opt<bool> 00165 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 00166 cl::desc("Pop up a window to show dags before the first " 00167 "dag combine pass")); 00168 static cl::opt<bool> 00169 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 00170 cl::desc("Pop up a window to show dags before legalize types")); 00171 static cl::opt<bool> 00172 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 00173 cl::desc("Pop up a window to show dags before legalize")); 00174 static cl::opt<bool> 00175 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 00176 cl::desc("Pop up a window to show dags before the second " 00177 "dag combine pass")); 00178 static cl::opt<bool> 00179 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 00180 cl::desc("Pop up a window to show dags before the post legalize types" 00181 " dag combine pass")); 00182 static cl::opt<bool> 00183 ViewISelDAGs("view-isel-dags", cl::Hidden, 00184 cl::desc("Pop up a window to show isel dags as they are selected")); 00185 static cl::opt<bool> 00186 ViewSchedDAGs("view-sched-dags", cl::Hidden, 00187 cl::desc("Pop up a window to show sched dags as they are processed")); 00188 static cl::opt<bool> 00189 ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 00190 cl::desc("Pop up a window to show SUnit dags after they are processed")); 00191 #else 00192 static const bool ViewDAGCombine1 = false, 00193 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 00194 ViewDAGCombine2 = false, 00195 ViewDAGCombineLT = false, 00196 ViewISelDAGs = false, ViewSchedDAGs = false, 00197 ViewSUnitDAGs = false; 00198 #endif 00199 00200 //===---------------------------------------------------------------------===// 00201 /// 00202 /// RegisterScheduler class - Track the registration of instruction schedulers. 00203 /// 00204 //===---------------------------------------------------------------------===// 00205 MachinePassRegistry RegisterScheduler::Registry; 00206 00207 //===---------------------------------------------------------------------===// 00208 /// 00209 /// ISHeuristic command line option for instruction schedulers. 00210 /// 00211 //===---------------------------------------------------------------------===// 00212 static cl::opt<RegisterScheduler::FunctionPassCtor, false, 00213 RegisterPassParser<RegisterScheduler> > 00214 ISHeuristic("pre-RA-sched", 00215 cl::init(&createDefaultScheduler), 00216 cl::desc("Instruction schedulers available (before register" 00217 " allocation):")); 00218 00219 static RegisterScheduler 00220 defaultListDAGScheduler("default", "Best scheduler for the target", 00221 createDefaultScheduler); 00222 00223 namespace llvm { 00224 //===--------------------------------------------------------------------===// 00225 /// createDefaultScheduler - This creates an instruction scheduler appropriate 00226 /// for the target. 00227 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 00228 CodeGenOpt::Level OptLevel) { 00229 const TargetLowering &TLI = IS->getTargetLowering(); 00230 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 00231 00232 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() || 00233 TLI.getSchedulingPreference() == Sched::Source) 00234 return createSourceListDAGScheduler(IS, OptLevel); 00235 if (TLI.getSchedulingPreference() == Sched::RegPressure) 00236 return createBURRListDAGScheduler(IS, OptLevel); 00237 if (TLI.getSchedulingPreference() == Sched::Hybrid) 00238 return createHybridListDAGScheduler(IS, OptLevel); 00239 if (TLI.getSchedulingPreference() == Sched::VLIW) 00240 return createVLIWDAGScheduler(IS, OptLevel); 00241 assert(TLI.getSchedulingPreference() == Sched::ILP && 00242 "Unknown sched type!"); 00243 return createILPListDAGScheduler(IS, OptLevel); 00244 } 00245 } 00246 00247 // EmitInstrWithCustomInserter - This method should be implemented by targets 00248 // that mark instructions with the 'usesCustomInserter' flag. These 00249 // instructions are special in various ways, which require special support to 00250 // insert. The specified MachineInstr is created but not inserted into any 00251 // basic blocks, and this method is called to expand it into a sequence of 00252 // instructions, potentially also creating new basic blocks and control flow. 00253 // When new basic blocks are inserted and the edges from MBB to its successors 00254 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the 00255 // DenseMap. 00256 MachineBasicBlock * 00257 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 00258 MachineBasicBlock *MBB) const { 00259 #ifndef NDEBUG 00260 dbgs() << "If a target marks an instruction with " 00261 "'usesCustomInserter', it must implement " 00262 "TargetLowering::EmitInstrWithCustomInserter!"; 00263 #endif 00264 llvm_unreachable(0); 00265 } 00266 00267 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 00268 SDNode *Node) const { 00269 assert(!MI->hasPostISelHook() && 00270 "If a target marks an instruction with 'hasPostISelHook', " 00271 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 00272 } 00273 00274 //===----------------------------------------------------------------------===// 00275 // SelectionDAGISel code 00276 //===----------------------------------------------------------------------===// 00277 00278 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 00279 CodeGenOpt::Level OL) : 00280 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 00281 FuncInfo(new FunctionLoweringInfo(TLI)), 00282 CurDAG(new SelectionDAG(tm, OL)), 00283 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 00284 GFI(), 00285 OptLevel(OL), 00286 DAGSize(0) { 00287 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 00288 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 00289 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 00290 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 00291 } 00292 00293 SelectionDAGISel::~SelectionDAGISel() { 00294 delete SDB; 00295 delete CurDAG; 00296 delete FuncInfo; 00297 } 00298 00299 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 00300 AU.addRequired<AliasAnalysis>(); 00301 AU.addPreserved<AliasAnalysis>(); 00302 AU.addRequired<GCModuleInfo>(); 00303 AU.addPreserved<GCModuleInfo>(); 00304 AU.addRequired<TargetLibraryInfo>(); 00305 if (UseMBPI && OptLevel != CodeGenOpt::None) 00306 AU.addRequired<BranchProbabilityInfo>(); 00307 MachineFunctionPass::getAnalysisUsage(AU); 00308 } 00309 00310 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 00311 /// may trap on it. In this case we have to split the edge so that the path 00312 /// through the predecessor block that doesn't go to the phi block doesn't 00313 /// execute the possibly trapping instruction. 00314 /// 00315 /// This is required for correctness, so it must be done at -O0. 00316 /// 00317 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 00318 // Loop for blocks with phi nodes. 00319 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 00320 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 00321 if (PN == 0) continue; 00322 00323 ReprocessBlock: 00324 // For each block with a PHI node, check to see if any of the input values 00325 // are potentially trapping constant expressions. Constant expressions are 00326 // the only potentially trapping value that can occur as the argument to a 00327 // PHI. 00328 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 00329 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 00330 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 00331 if (CE == 0 || !CE->canTrap()) continue; 00332 00333 // The only case we have to worry about is when the edge is critical. 00334 // Since this block has a PHI Node, we assume it has multiple input 00335 // edges: check to see if the pred has multiple successors. 00336 BasicBlock *Pred = PN->getIncomingBlock(i); 00337 if (Pred->getTerminator()->getNumSuccessors() == 1) 00338 continue; 00339 00340 // Okay, we have to split this edge. 00341 SplitCriticalEdge(Pred->getTerminator(), 00342 GetSuccessorNumber(Pred, BB), SDISel, true); 00343 goto ReprocessBlock; 00344 } 00345 } 00346 } 00347 00348 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 00349 // Do some sanity-checking on the command-line options. 00350 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 00351 "-fast-isel-verbose requires -fast-isel"); 00352 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 00353 "-fast-isel-abort requires -fast-isel"); 00354 00355 const Function &Fn = *mf.getFunction(); 00356 const TargetInstrInfo &TII = *TM.getInstrInfo(); 00357 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 00358 00359 MF = &mf; 00360 RegInfo = &MF->getRegInfo(); 00361 AA = &getAnalysis<AliasAnalysis>(); 00362 LibInfo = &getAnalysis<TargetLibraryInfo>(); 00363 TTI = getAnalysisIfAvailable<TargetTransformInfo>(); 00364 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 00365 00366 TargetSubtargetInfo &ST = 00367 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 00368 ST.resetSubtargetFeatures(MF); 00369 TM.resetTargetOptions(MF); 00370 00371 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 00372 00373 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 00374 00375 CurDAG->init(*MF, TTI); 00376 FuncInfo->set(Fn, *MF); 00377 00378 if (UseMBPI && OptLevel != CodeGenOpt::None) 00379 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 00380 else 00381 FuncInfo->BPI = 0; 00382 00383 SDB->init(GFI, *AA, LibInfo); 00384 00385 MF->setHasMSInlineAsm(false); 00386 SelectAllBasicBlocks(Fn); 00387 00388 // If the first basic block in the function has live ins that need to be 00389 // copied into vregs, emit the copies into the top of the block before 00390 // emitting the code for the block. 00391 MachineBasicBlock *EntryMBB = MF->begin(); 00392 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 00393 00394 DenseMap<unsigned, unsigned> LiveInMap; 00395 if (!FuncInfo->ArgDbgValues.empty()) 00396 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 00397 E = RegInfo->livein_end(); LI != E; ++LI) 00398 if (LI->second) 00399 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 00400 00401 // Insert DBG_VALUE instructions for function arguments to the entry block. 00402 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 00403 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 00404 unsigned Reg = MI->getOperand(0).getReg(); 00405 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 00406 EntryMBB->insert(EntryMBB->begin(), MI); 00407 else { 00408 MachineInstr *Def = RegInfo->getVRegDef(Reg); 00409 MachineBasicBlock::iterator InsertPos = Def; 00410 // FIXME: VR def may not be in entry block. 00411 Def->getParent()->insert(llvm::next(InsertPos), MI); 00412 } 00413 00414 // If Reg is live-in then update debug info to track its copy in a vreg. 00415 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 00416 if (LDI != LiveInMap.end()) { 00417 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 00418 MachineBasicBlock::iterator InsertPos = Def; 00419 const MDNode *Variable = 00420 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 00421 unsigned Offset = MI->getOperand(1).getImm(); 00422 // Def is never a terminator here, so it is ok to increment InsertPos. 00423 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 00424 TII.get(TargetOpcode::DBG_VALUE)) 00425 .addReg(LDI->second, RegState::Debug) 00426 .addImm(Offset).addMetadata(Variable); 00427 00428 // If this vreg is directly copied into an exported register then 00429 // that COPY instructions also need DBG_VALUE, if it is the only 00430 // user of LDI->second. 00431 MachineInstr *CopyUseMI = NULL; 00432 for (MachineRegisterInfo::use_iterator 00433 UI = RegInfo->use_begin(LDI->second); 00434 MachineInstr *UseMI = UI.skipInstruction();) { 00435 if (UseMI->isDebugValue()) continue; 00436 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 00437 CopyUseMI = UseMI; continue; 00438 } 00439 // Otherwise this is another use or second copy use. 00440 CopyUseMI = NULL; break; 00441 } 00442 if (CopyUseMI) { 00443 MachineInstr *NewMI = 00444 BuildMI(*MF, CopyUseMI->getDebugLoc(), 00445 TII.get(TargetOpcode::DBG_VALUE)) 00446 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 00447 .addImm(Offset).addMetadata(Variable); 00448 MachineBasicBlock::iterator Pos = CopyUseMI; 00449 EntryMBB->insertAfter(Pos, NewMI); 00450 } 00451 } 00452 } 00453 00454 // Determine if there are any calls in this machine function. 00455 MachineFrameInfo *MFI = MF->getFrameInfo(); 00456 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; 00457 ++I) { 00458 00459 if (MFI->hasCalls() && MF->hasMSInlineAsm()) 00460 break; 00461 00462 const MachineBasicBlock *MBB = I; 00463 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); 00464 II != IE; ++II) { 00465 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 00466 if ((MCID.isCall() && !MCID.isReturn()) || 00467 II->isStackAligningInlineAsm()) { 00468 MFI->setHasCalls(true); 00469 } 00470 if (II->isMSInlineAsm()) { 00471 MF->setHasMSInlineAsm(true); 00472 } 00473 } 00474 } 00475 00476 // Determine if there is a call to setjmp in the machine function. 00477 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 00478 00479 // Replace forward-declared registers with the registers containing 00480 // the desired value. 00481 MachineRegisterInfo &MRI = MF->getRegInfo(); 00482 for (DenseMap<unsigned, unsigned>::iterator 00483 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 00484 I != E; ++I) { 00485 unsigned From = I->first; 00486 unsigned To = I->second; 00487 // If To is also scheduled to be replaced, find what its ultimate 00488 // replacement is. 00489 for (;;) { 00490 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 00491 if (J == E) break; 00492 To = J->second; 00493 } 00494 // Replace it. 00495 MRI.replaceRegWith(From, To); 00496 } 00497 00498 // Freeze the set of reserved registers now that MachineFrameInfo has been 00499 // set up. All the information required by getReservedRegs() should be 00500 // available now. 00501 MRI.freezeReservedRegs(*MF); 00502 00503 // Release function-specific state. SDB and CurDAG are already cleared 00504 // at this point. 00505 FuncInfo->clear(); 00506 00507 return true; 00508 } 00509 00510 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 00511 BasicBlock::const_iterator End, 00512 bool &HadTailCall) { 00513 // Lower all of the non-terminator instructions. If a call is emitted 00514 // as a tail call, cease emitting nodes for this block. Terminators 00515 // are handled below. 00516 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 00517 SDB->visit(*I); 00518 00519 // Make sure the root of the DAG is up-to-date. 00520 CurDAG->setRoot(SDB->getControlRoot()); 00521 HadTailCall = SDB->HasTailCall; 00522 SDB->clear(); 00523 00524 // Final step, emit the lowered DAG as machine code. 00525 CodeGenAndEmitDAG(); 00526 } 00527 00528 void SelectionDAGISel::ComputeLiveOutVRegInfo() { 00529 SmallPtrSet<SDNode*, 128> VisitedNodes; 00530 SmallVector<SDNode*, 128> Worklist; 00531 00532 Worklist.push_back(CurDAG->getRoot().getNode()); 00533 00534 APInt KnownZero; 00535 APInt KnownOne; 00536 00537 do { 00538 SDNode *N = Worklist.pop_back_val(); 00539 00540 // If we've already seen this node, ignore it. 00541 if (!VisitedNodes.insert(N)) 00542 continue; 00543 00544 // Otherwise, add all chain operands to the worklist. 00545 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 00546 if (N->getOperand(i).getValueType() == MVT::Other) 00547 Worklist.push_back(N->getOperand(i).getNode()); 00548 00549 // If this is a CopyToReg with a vreg dest, process it. 00550 if (N->getOpcode() != ISD::CopyToReg) 00551 continue; 00552 00553 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 00554 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 00555 continue; 00556 00557 // Ignore non-scalar or non-integer values. 00558 SDValue Src = N->getOperand(2); 00559 EVT SrcVT = Src.getValueType(); 00560 if (!SrcVT.isInteger() || SrcVT.isVector()) 00561 continue; 00562 00563 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 00564 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 00565 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 00566 } while (!Worklist.empty()); 00567 } 00568 00569 void SelectionDAGISel::CodeGenAndEmitDAG() { 00570 std::string GroupName; 00571 if (TimePassesIsEnabled) 00572 GroupName = "Instruction Selection and Scheduling"; 00573 std::string BlockName; 00574 int BlockNumber = -1; 00575 (void)BlockNumber; 00576 #ifdef NDEBUG 00577 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 00578 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 00579 ViewSUnitDAGs) 00580 #endif 00581 { 00582 BlockNumber = FuncInfo->MBB->getNumber(); 00583 BlockName = MF->getName().str() + ":" + 00584 FuncInfo->MBB->getBasicBlock()->getName().str(); 00585 } 00586 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 00587 << " '" << BlockName << "'\n"; CurDAG->dump()); 00588 00589 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 00590 00591 // Run the DAG combiner in pre-legalize mode. 00592 { 00593 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 00594 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 00595 } 00596 00597 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 00598 << " '" << BlockName << "'\n"; CurDAG->dump()); 00599 00600 // Second step, hack on the DAG until it only uses operations and types that 00601 // the target supports. 00602 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 00603 BlockName); 00604 00605 bool Changed; 00606 { 00607 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 00608 Changed = CurDAG->LegalizeTypes(); 00609 } 00610 00611 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 00612 << " '" << BlockName << "'\n"; CurDAG->dump()); 00613 00614 if (Changed) { 00615 if (ViewDAGCombineLT) 00616 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 00617 00618 // Run the DAG combiner in post-type-legalize mode. 00619 { 00620 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 00621 TimePassesIsEnabled); 00622 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 00623 } 00624 00625 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 00626 << " '" << BlockName << "'\n"; CurDAG->dump()); 00627 } 00628 00629 { 00630 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 00631 Changed = CurDAG->LegalizeVectors(); 00632 } 00633 00634 if (Changed) { 00635 { 00636 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 00637 CurDAG->LegalizeTypes(); 00638 } 00639 00640 if (ViewDAGCombineLT) 00641 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 00642 00643 // Run the DAG combiner in post-type-legalize mode. 00644 { 00645 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 00646 TimePassesIsEnabled); 00647 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 00648 } 00649 00650 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 00651 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 00652 } 00653 00654 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 00655 00656 { 00657 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 00658 CurDAG->Legalize(); 00659 } 00660 00661 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 00662 << " '" << BlockName << "'\n"; CurDAG->dump()); 00663 00664 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 00665 00666 // Run the DAG combiner in post-legalize mode. 00667 { 00668 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 00669 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 00670 } 00671 00672 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 00673 << " '" << BlockName << "'\n"; CurDAG->dump()); 00674 00675 if (OptLevel != CodeGenOpt::None) 00676 ComputeLiveOutVRegInfo(); 00677 00678 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 00679 00680 // Third, instruction select all of the operations to machine code, adding the 00681 // code to the MachineBasicBlock. 00682 { 00683 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 00684 DoInstructionSelection(); 00685 } 00686 00687 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 00688 << " '" << BlockName << "'\n"; CurDAG->dump()); 00689 00690 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 00691 00692 // Schedule machine code. 00693 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 00694 { 00695 NamedRegionTimer T("Instruction Scheduling", GroupName, 00696 TimePassesIsEnabled); 00697 Scheduler->Run(CurDAG, FuncInfo->MBB); 00698 } 00699 00700 if (ViewSUnitDAGs) Scheduler->viewGraph(); 00701 00702 // Emit machine code to BB. This can change 'BB' to the last block being 00703 // inserted into. 00704 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 00705 { 00706 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 00707 00708 // FuncInfo->InsertPt is passed by reference and set to the end of the 00709 // scheduled instructions. 00710 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 00711 } 00712 00713 // If the block was split, make sure we update any references that are used to 00714 // update PHI nodes later on. 00715 if (FirstMBB != LastMBB) 00716 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 00717 00718 // Free the scheduler state. 00719 { 00720 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 00721 TimePassesIsEnabled); 00722 delete Scheduler; 00723 } 00724 00725 // Free the SelectionDAG state, now that we're finished with it. 00726 CurDAG->clear(); 00727 } 00728 00729 namespace { 00730 /// ISelUpdater - helper class to handle updates of the instruction selection 00731 /// graph. 00732 class ISelUpdater : public SelectionDAG::DAGUpdateListener { 00733 SelectionDAG::allnodes_iterator &ISelPosition; 00734 public: 00735 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 00736 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 00737 00738 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 00739 /// deleted is the current ISelPosition node, update ISelPosition. 00740 /// 00741 virtual void NodeDeleted(SDNode *N, SDNode *E) { 00742 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 00743 ++ISelPosition; 00744 } 00745 }; 00746 } // end anonymous namespace 00747 00748 void SelectionDAGISel::DoInstructionSelection() { 00749 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 00750 << FuncInfo->MBB->getNumber() 00751 << " '" << FuncInfo->MBB->getName() << "'\n"); 00752 00753 PreprocessISelDAG(); 00754 00755 // Select target instructions for the DAG. 00756 { 00757 // Number all nodes with a topological order and set DAGSize. 00758 DAGSize = CurDAG->AssignTopologicalOrder(); 00759 00760 // Create a dummy node (which is not added to allnodes), that adds 00761 // a reference to the root node, preventing it from being deleted, 00762 // and tracking any changes of the root. 00763 HandleSDNode Dummy(CurDAG->getRoot()); 00764 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 00765 ++ISelPosition; 00766 00767 // Make sure that ISelPosition gets properly updated when nodes are deleted 00768 // in calls made from this function. 00769 ISelUpdater ISU(*CurDAG, ISelPosition); 00770 00771 // The AllNodes list is now topological-sorted. Visit the 00772 // nodes by starting at the end of the list (the root of the 00773 // graph) and preceding back toward the beginning (the entry 00774 // node). 00775 while (ISelPosition != CurDAG->allnodes_begin()) { 00776 SDNode *Node = --ISelPosition; 00777 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 00778 // but there are currently some corner cases that it misses. Also, this 00779 // makes it theoretically possible to disable the DAGCombiner. 00780 if (Node->use_empty()) 00781 continue; 00782 00783 SDNode *ResNode = Select(Node); 00784 00785 // FIXME: This is pretty gross. 'Select' should be changed to not return 00786 // anything at all and this code should be nuked with a tactical strike. 00787 00788 // If node should not be replaced, continue with the next one. 00789 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 00790 continue; 00791 // Replace node. 00792 if (ResNode) { 00793 // Propagate ordering 00794 CurDAG->AssignOrdering(ResNode, CurDAG->GetOrdering(Node)); 00795 00796 ReplaceUses(Node, ResNode); 00797 } 00798 00799 // If after the replacement this node is not used any more, 00800 // remove this dead node. 00801 if (Node->use_empty()) // Don't delete EntryToken, etc. 00802 CurDAG->RemoveDeadNode(Node); 00803 } 00804 00805 CurDAG->setRoot(Dummy.getValue()); 00806 } 00807 00808 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 00809 00810 PostprocessISelDAG(); 00811 } 00812 00813 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 00814 /// do other setup for EH landing-pad blocks. 00815 void SelectionDAGISel::PrepareEHLandingPad() { 00816 MachineBasicBlock *MBB = FuncInfo->MBB; 00817 00818 // Add a label to mark the beginning of the landing pad. Deletion of the 00819 // landing pad can thus be detected via the MachineModuleInfo. 00820 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 00821 00822 // Assign the call site to the landing pad's begin label. 00823 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 00824 00825 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 00826 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 00827 .addSym(Label); 00828 00829 // Mark exception register as live in. 00830 unsigned Reg = TLI.getExceptionPointerRegister(); 00831 if (Reg) MBB->addLiveIn(Reg); 00832 00833 // Mark exception selector register as live in. 00834 Reg = TLI.getExceptionSelectorRegister(); 00835 if (Reg) MBB->addLiveIn(Reg); 00836 } 00837 00838 /// isFoldedOrDeadInstruction - Return true if the specified instruction is 00839 /// side-effect free and is either dead or folded into a generated instruction. 00840 /// Return false if it needs to be emitted. 00841 static bool isFoldedOrDeadInstruction(const Instruction *I, 00842 FunctionLoweringInfo *FuncInfo) { 00843 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 00844 !isa<TerminatorInst>(I) && // Terminators aren't folded. 00845 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 00846 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 00847 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 00848 } 00849 00850 #ifndef NDEBUG 00851 // Collect per Instruction statistics for fast-isel misses. Only those 00852 // instructions that cause the bail are accounted for. It does not account for 00853 // instructions higher in the block. Thus, summing the per instructions stats 00854 // will not add up to what is reported by NumFastIselFailures. 00855 static void collectFailStats(const Instruction *I) { 00856 switch (I->getOpcode()) { 00857 default: assert (0 && "<Invalid operator> "); 00858 00859 // Terminators 00860 case Instruction::Ret: NumFastIselFailRet++; return; 00861 case Instruction::Br: NumFastIselFailBr++; return; 00862 case Instruction::Switch: NumFastIselFailSwitch++; return; 00863 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 00864 case Instruction::Invoke: NumFastIselFailInvoke++; return; 00865 case Instruction::Resume: NumFastIselFailResume++; return; 00866 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 00867 00868 // Standard binary operators... 00869 case Instruction::Add: NumFastIselFailAdd++; return; 00870 case Instruction::FAdd: NumFastIselFailFAdd++; return; 00871 case Instruction::Sub: NumFastIselFailSub++; return; 00872 case Instruction::FSub: NumFastIselFailFSub++; return; 00873 case Instruction::Mul: NumFastIselFailMul++; return; 00874 case Instruction::FMul: NumFastIselFailFMul++; return; 00875 case Instruction::UDiv: NumFastIselFailUDiv++; return; 00876 case Instruction::SDiv: NumFastIselFailSDiv++; return; 00877 case Instruction::FDiv: NumFastIselFailFDiv++; return; 00878 case Instruction::URem: NumFastIselFailURem++; return; 00879 case Instruction::SRem: NumFastIselFailSRem++; return; 00880 case Instruction::FRem: NumFastIselFailFRem++; return; 00881 00882 // Logical operators... 00883 case Instruction::And: NumFastIselFailAnd++; return; 00884 case Instruction::Or: NumFastIselFailOr++; return; 00885 case Instruction::Xor: NumFastIselFailXor++; return; 00886 00887 // Memory instructions... 00888 case Instruction::Alloca: NumFastIselFailAlloca++; return; 00889 case Instruction::Load: NumFastIselFailLoad++; return; 00890 case Instruction::Store: NumFastIselFailStore++; return; 00891 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 00892 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 00893 case Instruction::Fence: NumFastIselFailFence++; return; 00894 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 00895 00896 // Convert instructions... 00897 case Instruction::Trunc: NumFastIselFailTrunc++; return; 00898 case Instruction::ZExt: NumFastIselFailZExt++; return; 00899 case Instruction::SExt: NumFastIselFailSExt++; return; 00900 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 00901 case Instruction::FPExt: NumFastIselFailFPExt++; return; 00902 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 00903 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 00904 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 00905 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 00906 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 00907 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 00908 case Instruction::BitCast: NumFastIselFailBitCast++; return; 00909 00910 // Other instructions... 00911 case Instruction::ICmp: NumFastIselFailICmp++; return; 00912 case Instruction::FCmp: NumFastIselFailFCmp++; return; 00913 case Instruction::PHI: NumFastIselFailPHI++; return; 00914 case Instruction::Select: NumFastIselFailSelect++; return; 00915 case Instruction::Call: NumFastIselFailCall++; return; 00916 case Instruction::Shl: NumFastIselFailShl++; return; 00917 case Instruction::LShr: NumFastIselFailLShr++; return; 00918 case Instruction::AShr: NumFastIselFailAShr++; return; 00919 case Instruction::VAArg: NumFastIselFailVAArg++; return; 00920 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 00921 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 00922 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 00923 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 00924 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 00925 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 00926 } 00927 } 00928 #endif 00929 00930 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 00931 // Initialize the Fast-ISel state, if needed. 00932 FastISel *FastIS = 0; 00933 if (TM.Options.EnableFastISel) 00934 FastIS = TLI.createFastISel(*FuncInfo, LibInfo); 00935 00936 // Iterate over all basic blocks in the function. 00937 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 00938 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 00939 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 00940 const BasicBlock *LLVMBB = *I; 00941 00942 if (OptLevel != CodeGenOpt::None) { 00943 bool AllPredsVisited = true; 00944 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 00945 PI != PE; ++PI) { 00946 if (!FuncInfo->VisitedBBs.count(*PI)) { 00947 AllPredsVisited = false; 00948 break; 00949 } 00950 } 00951 00952 if (AllPredsVisited) { 00953 for (BasicBlock::const_iterator I = LLVMBB->begin(); 00954 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 00955 FuncInfo->ComputePHILiveOutRegInfo(PN); 00956 } else { 00957 for (BasicBlock::const_iterator I = LLVMBB->begin(); 00958 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 00959 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 00960 } 00961 00962 FuncInfo->VisitedBBs.insert(LLVMBB); 00963 } 00964 00965 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 00966 BasicBlock::const_iterator const End = LLVMBB->end(); 00967 BasicBlock::const_iterator BI = End; 00968 00969 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 00970 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 00971 00972 // Setup an EH landing-pad block. 00973 if (FuncInfo->MBB->isLandingPad()) 00974 PrepareEHLandingPad(); 00975 00976 // Before doing SelectionDAG ISel, see if FastISel has been requested. 00977 if (FastIS) { 00978 FastIS->startNewBlock(); 00979 00980 // Emit code for any incoming arguments. This must happen before 00981 // beginning FastISel on the entry block. 00982 if (LLVMBB == &Fn.getEntryBlock()) { 00983 ++NumEntryBlocks; 00984 00985 // Lower any arguments needed in this block if this is the entry block. 00986 if (!FastIS->LowerArguments()) { 00987 // Fast isel failed to lower these arguments 00988 ++NumFastIselFailLowerArguments; 00989 if (EnableFastISelAbortArgs) 00990 llvm_unreachable("FastISel didn't lower all arguments"); 00991 00992 // Use SelectionDAG argument lowering 00993 LowerArguments(Fn); 00994 CurDAG->setRoot(SDB->getControlRoot()); 00995 SDB->clear(); 00996 CodeGenAndEmitDAG(); 00997 } 00998 00999 // If we inserted any instructions at the beginning, make a note of 01000 // where they are, so we can be sure to emit subsequent instructions 01001 // after them. 01002 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 01003 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 01004 else 01005 FastIS->setLastLocalValue(0); 01006 } 01007 01008 unsigned NumFastIselRemaining = std::distance(Begin, End); 01009 // Do FastISel on as many instructions as possible. 01010 for (; BI != Begin; --BI) { 01011 const Instruction *Inst = llvm::prior(BI); 01012 01013 // If we no longer require this instruction, skip it. 01014 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 01015 --NumFastIselRemaining; 01016 continue; 01017 } 01018 01019 // Bottom-up: reset the insert pos at the top, after any local-value 01020 // instructions. 01021 FastIS->recomputeInsertPt(); 01022 01023 // Try to select the instruction with FastISel. 01024 if (FastIS->SelectInstruction(Inst)) { 01025 --NumFastIselRemaining; 01026 ++NumFastIselSuccess; 01027 // If fast isel succeeded, skip over all the folded instructions, and 01028 // then see if there is a load right before the selected instructions. 01029 // Try to fold the load if so. 01030 const Instruction *BeforeInst = Inst; 01031 while (BeforeInst != Begin) { 01032 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 01033 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 01034 break; 01035 } 01036 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 01037 BeforeInst->hasOneUse() && 01038 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 01039 // If we succeeded, don't re-select the load. 01040 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 01041 --NumFastIselRemaining; 01042 ++NumFastIselSuccess; 01043 } 01044 continue; 01045 } 01046 01047 #ifndef NDEBUG 01048 if (EnableFastISelVerbose2) 01049 collectFailStats(Inst); 01050 #endif 01051 01052 // Then handle certain instructions as single-LLVM-Instruction blocks. 01053 if (isa<CallInst>(Inst)) { 01054 01055 if (EnableFastISelVerbose || EnableFastISelAbort) { 01056 dbgs() << "FastISel missed call: "; 01057 Inst->dump(); 01058 } 01059 01060 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 01061 unsigned &R = FuncInfo->ValueMap[Inst]; 01062 if (!R) 01063 R = FuncInfo->CreateRegs(Inst->getType()); 01064 } 01065 01066 bool HadTailCall = false; 01067 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 01068 SelectBasicBlock(Inst, BI, HadTailCall); 01069 01070 // If the call was emitted as a tail call, we're done with the block. 01071 // We also need to delete any previously emitted instructions. 01072 if (HadTailCall) { 01073 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 01074 --BI; 01075 break; 01076 } 01077 01078 // Recompute NumFastIselRemaining as Selection DAG instruction 01079 // selection may have handled the call, input args, etc. 01080 unsigned RemainingNow = std::distance(Begin, BI); 01081 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 01082 NumFastIselRemaining = RemainingNow; 01083 continue; 01084 } 01085 01086 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 01087 // Don't abort, and use a different message for terminator misses. 01088 NumFastIselFailures += NumFastIselRemaining; 01089 if (EnableFastISelVerbose || EnableFastISelAbort) { 01090 dbgs() << "FastISel missed terminator: "; 01091 Inst->dump(); 01092 } 01093 } else { 01094 NumFastIselFailures += NumFastIselRemaining; 01095 if (EnableFastISelVerbose || EnableFastISelAbort) { 01096 dbgs() << "FastISel miss: "; 01097 Inst->dump(); 01098 } 01099 if (EnableFastISelAbort) 01100 // The "fast" selector couldn't handle something and bailed. 01101 // For the purpose of debugging, just abort. 01102 llvm_unreachable("FastISel didn't select the entire block"); 01103 } 01104 break; 01105 } 01106 01107 FastIS->recomputeInsertPt(); 01108 } else { 01109 // Lower any arguments needed in this block if this is the entry block. 01110 if (LLVMBB == &Fn.getEntryBlock()) { 01111 ++NumEntryBlocks; 01112 LowerArguments(Fn); 01113 } 01114 } 01115 01116 if (Begin != BI) 01117 ++NumDAGBlocks; 01118 else 01119 ++NumFastIselBlocks; 01120 01121 if (Begin != BI) { 01122 // Run SelectionDAG instruction selection on the remainder of the block 01123 // not handled by FastISel. If FastISel is not run, this is the entire 01124 // block. 01125 bool HadTailCall; 01126 SelectBasicBlock(Begin, BI, HadTailCall); 01127 } 01128 01129 FinishBasicBlock(); 01130 FuncInfo->PHINodesToUpdate.clear(); 01131 } 01132 01133 delete FastIS; 01134 SDB->clearDanglingDebugInfo(); 01135 } 01136 01137 void 01138 SelectionDAGISel::FinishBasicBlock() { 01139 01140 DEBUG(dbgs() << "Total amount of phi nodes to update: " 01141 << FuncInfo->PHINodesToUpdate.size() << "\n"; 01142 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 01143 dbgs() << "Node " << i << " : (" 01144 << FuncInfo->PHINodesToUpdate[i].first 01145 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 01146 01147 // Next, now that we know what the last MBB the LLVM BB expanded is, update 01148 // PHI nodes in successors. 01149 if (SDB->SwitchCases.empty() && 01150 SDB->JTCases.empty() && 01151 SDB->BitTestCases.empty()) { 01152 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 01153 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 01154 assert(PHI->isPHI() && 01155 "This is not a machine PHI node that we are updating!"); 01156 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 01157 continue; 01158 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 01159 } 01160 return; 01161 } 01162 01163 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 01164 // Lower header first, if it wasn't already lowered 01165 if (!SDB->BitTestCases[i].Emitted) { 01166 // Set the current basic block to the mbb we wish to insert the code into 01167 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 01168 FuncInfo->InsertPt = FuncInfo->MBB->end(); 01169 // Emit the code 01170 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 01171 CurDAG->setRoot(SDB->getRoot()); 01172 SDB->clear(); 01173 CodeGenAndEmitDAG(); 01174 } 01175 01176 uint32_t UnhandledWeight = 0; 01177 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 01178 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 01179 01180 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 01181 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 01182 // Set the current basic block to the mbb we wish to insert the code into 01183 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 01184 FuncInfo->InsertPt = FuncInfo->MBB->end(); 01185 // Emit the code 01186 if (j+1 != ej) 01187 SDB->visitBitTestCase(SDB->BitTestCases[i], 01188 SDB->BitTestCases[i].Cases[j+1].ThisBB, 01189 UnhandledWeight, 01190 SDB->BitTestCases[i].Reg, 01191 SDB->BitTestCases[i].Cases[j], 01192 FuncInfo->MBB); 01193 else 01194 SDB->visitBitTestCase(SDB->BitTestCases[i], 01195 SDB->BitTestCases[i].Default, 01196 UnhandledWeight, 01197 SDB->BitTestCases[i].Reg, 01198 SDB->BitTestCases[i].Cases[j], 01199 FuncInfo->MBB); 01200 01201 01202 CurDAG->setRoot(SDB->getRoot()); 01203 SDB->clear(); 01204 CodeGenAndEmitDAG(); 01205 } 01206 01207 // Update PHI Nodes 01208 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 01209 pi != pe; ++pi) { 01210 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 01211 MachineBasicBlock *PHIBB = PHI->getParent(); 01212 assert(PHI->isPHI() && 01213 "This is not a machine PHI node that we are updating!"); 01214 // This is "default" BB. We have two jumps to it. From "header" BB and 01215 // from last "case" BB. 01216 if (PHIBB == SDB->BitTestCases[i].Default) 01217 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 01218 .addMBB(SDB->BitTestCases[i].Parent) 01219 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 01220 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 01221 // One of "cases" BB. 01222 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 01223 j != ej; ++j) { 01224 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 01225 if (cBB->isSuccessor(PHIBB)) 01226 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 01227 } 01228 } 01229 } 01230 SDB->BitTestCases.clear(); 01231 01232 // If the JumpTable record is filled in, then we need to emit a jump table. 01233 // Updating the PHI nodes is tricky in this case, since we need to determine 01234 // whether the PHI is a successor of the range check MBB or the jump table MBB 01235 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 01236 // Lower header first, if it wasn't already lowered 01237 if (!SDB->JTCases[i].first.Emitted) { 01238 // Set the current basic block to the mbb we wish to insert the code into 01239 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 01240 FuncInfo->InsertPt = FuncInfo->MBB->end(); 01241 // Emit the code 01242 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 01243 FuncInfo->MBB); 01244 CurDAG->setRoot(SDB->getRoot()); 01245 SDB->clear(); 01246 CodeGenAndEmitDAG(); 01247 } 01248 01249 // Set the current basic block to the mbb we wish to insert the code into 01250 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 01251 FuncInfo->InsertPt = FuncInfo->MBB->end(); 01252 // Emit the code 01253 SDB->visitJumpTable(SDB->JTCases[i].second); 01254 CurDAG->setRoot(SDB->getRoot()); 01255 SDB->clear(); 01256 CodeGenAndEmitDAG(); 01257 01258 // Update PHI Nodes 01259 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 01260 pi != pe; ++pi) { 01261 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 01262 MachineBasicBlock *PHIBB = PHI->getParent(); 01263 assert(PHI->isPHI() && 01264 "This is not a machine PHI node that we are updating!"); 01265 // "default" BB. We can go there only from header BB. 01266 if (PHIBB == SDB->JTCases[i].second.Default) 01267 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 01268 .addMBB(SDB->JTCases[i].first.HeaderBB); 01269 // JT BB. Just iterate over successors here 01270 if (FuncInfo->MBB->isSuccessor(PHIBB)) 01271 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 01272 } 01273 } 01274 SDB->JTCases.clear(); 01275 01276 // If the switch block involved a branch to one of the actual successors, we 01277 // need to update PHI nodes in that block. 01278 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 01279 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 01280 assert(PHI->isPHI() && 01281 "This is not a machine PHI node that we are updating!"); 01282 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 01283 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 01284 } 01285 01286 // If we generated any switch lowering information, build and codegen any 01287 // additional DAGs necessary. 01288 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 01289 // Set the current basic block to the mbb we wish to insert the code into 01290 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 01291 FuncInfo->InsertPt = FuncInfo->MBB->end(); 01292 01293 // Determine the unique successors. 01294 SmallVector<MachineBasicBlock *, 2> Succs; 01295 Succs.push_back(SDB->SwitchCases[i].TrueBB); 01296 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 01297 Succs.push_back(SDB->SwitchCases[i].FalseBB); 01298 01299 // Emit the code. Note that this could result in FuncInfo->MBB being split. 01300 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 01301 CurDAG->setRoot(SDB->getRoot()); 01302 SDB->clear(); 01303 CodeGenAndEmitDAG(); 01304 01305 // Remember the last block, now that any splitting is done, for use in 01306 // populating PHI nodes in successors. 01307 MachineBasicBlock *ThisBB = FuncInfo->MBB; 01308 01309 // Handle any PHI nodes in successors of this chunk, as if we were coming 01310 // from the original BB before switch expansion. Note that PHI nodes can 01311 // occur multiple times in PHINodesToUpdate. We have to be very careful to 01312 // handle them the right number of times. 01313 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 01314 FuncInfo->MBB = Succs[i]; 01315 FuncInfo->InsertPt = FuncInfo->MBB->end(); 01316 // FuncInfo->MBB may have been removed from the CFG if a branch was 01317 // constant folded. 01318 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 01319 for (MachineBasicBlock::iterator 01320 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 01321 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 01322 MachineInstrBuilder PHI(*MF, MBBI); 01323 // This value for this PHI node is recorded in PHINodesToUpdate. 01324 for (unsigned pn = 0; ; ++pn) { 01325 assert(pn != FuncInfo->PHINodesToUpdate.size() && 01326 "Didn't find PHI entry!"); 01327 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 01328 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 01329 break; 01330 } 01331 } 01332 } 01333 } 01334 } 01335 } 01336 SDB->SwitchCases.clear(); 01337 } 01338 01339 01340 /// Create the scheduler. If a specific scheduler was specified 01341 /// via the SchedulerRegistry, use it, otherwise select the 01342 /// one preferred by the target. 01343 /// 01344 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 01345 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 01346 01347 if (!Ctor) { 01348 Ctor = ISHeuristic; 01349 RegisterScheduler::setDefault(Ctor); 01350 } 01351 01352 return Ctor(this, OptLevel); 01353 } 01354 01355 //===----------------------------------------------------------------------===// 01356 // Helper functions used by the generated instruction selector. 01357 //===----------------------------------------------------------------------===// 01358 // Calls to these methods are generated by tblgen. 01359 01360 /// CheckAndMask - The isel is trying to match something like (and X, 255). If 01361 /// the dag combiner simplified the 255, we still want to match. RHS is the 01362 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 01363 /// specified in the .td file (e.g. 255). 01364 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 01365 int64_t DesiredMaskS) const { 01366 const APInt &ActualMask = RHS->getAPIntValue(); 01367 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 01368 01369 // If the actual mask exactly matches, success! 01370 if (ActualMask == DesiredMask) 01371 return true; 01372 01373 // If the actual AND mask is allowing unallowed bits, this doesn't match. 01374 if (ActualMask.intersects(~DesiredMask)) 01375 return false; 01376 01377 // Otherwise, the DAG Combiner may have proven that the value coming in is 01378 // either already zero or is not demanded. Check for known zero input bits. 01379 APInt NeededMask = DesiredMask & ~ActualMask; 01380 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 01381 return true; 01382 01383 // TODO: check to see if missing bits are just not demanded. 01384 01385 // Otherwise, this pattern doesn't match. 01386 return false; 01387 } 01388 01389 /// CheckOrMask - The isel is trying to match something like (or X, 255). If 01390 /// the dag combiner simplified the 255, we still want to match. RHS is the 01391 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 01392 /// specified in the .td file (e.g. 255). 01393 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 01394 int64_t DesiredMaskS) const { 01395 const APInt &ActualMask = RHS->getAPIntValue(); 01396 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 01397 01398 // If the actual mask exactly matches, success! 01399 if (ActualMask == DesiredMask) 01400 return true; 01401 01402 // If the actual AND mask is allowing unallowed bits, this doesn't match. 01403 if (ActualMask.intersects(~DesiredMask)) 01404 return false; 01405 01406 // Otherwise, the DAG Combiner may have proven that the value coming in is 01407 // either already zero or is not demanded. Check for known zero input bits. 01408 APInt NeededMask = DesiredMask & ~ActualMask; 01409 01410 APInt KnownZero, KnownOne; 01411 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 01412 01413 // If all the missing bits in the or are already known to be set, match! 01414 if ((NeededMask & KnownOne) == NeededMask) 01415 return true; 01416 01417 // TODO: check to see if missing bits are just not demanded. 01418 01419 // Otherwise, this pattern doesn't match. 01420 return false; 01421 } 01422 01423 01424 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 01425 /// by tblgen. Others should not call it. 01426 void SelectionDAGISel:: 01427 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 01428 std::vector<SDValue> InOps; 01429 std::swap(InOps, Ops); 01430 01431 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 01432 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 01433 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 01434 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 01435 01436 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 01437 if (InOps[e-1].getValueType() == MVT::Glue) 01438 --e; // Don't process a glue operand if it is here. 01439 01440 while (i != e) { 01441 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 01442 if (!InlineAsm::isMemKind(Flags)) { 01443 // Just skip over this operand, copying the operands verbatim. 01444 Ops.insert(Ops.end(), InOps.begin()+i, 01445 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 01446 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 01447 } else { 01448 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 01449 "Memory operand with multiple values?"); 01450 // Otherwise, this is a memory operand. Ask the target to select it. 01451 std::vector<SDValue> SelOps; 01452 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 01453 report_fatal_error("Could not match memory address. Inline asm" 01454 " failure!"); 01455 01456 // Add this to the output node. 01457 unsigned NewFlags = 01458 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 01459 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 01460 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 01461 i += 2; 01462 } 01463 } 01464 01465 // Add the glue input back if present. 01466 if (e != InOps.size()) 01467 Ops.push_back(InOps.back()); 01468 } 01469 01470 /// findGlueUse - Return use of MVT::Glue value produced by the specified 01471 /// SDNode. 01472 /// 01473 static SDNode *findGlueUse(SDNode *N) { 01474 unsigned FlagResNo = N->getNumValues()-1; 01475 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 01476 SDUse &Use = I.getUse(); 01477 if (Use.getResNo() == FlagResNo) 01478 return Use.getUser(); 01479 } 01480 return NULL; 01481 } 01482 01483 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 01484 /// This function recursively traverses up the operand chain, ignoring 01485 /// certain nodes. 01486 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 01487 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 01488 bool IgnoreChains) { 01489 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 01490 // greater than all of its (recursive) operands. If we scan to a point where 01491 // 'use' is smaller than the node we're scanning for, then we know we will 01492 // never find it. 01493 // 01494 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 01495 // happen because we scan down to newly selected nodes in the case of glue 01496 // uses. 01497 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 01498 return false; 01499 01500 // Don't revisit nodes if we already scanned it and didn't fail, we know we 01501 // won't fail if we scan it again. 01502 if (!Visited.insert(Use)) 01503 return false; 01504 01505 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 01506 // Ignore chain uses, they are validated by HandleMergeInputChains. 01507 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 01508 continue; 01509 01510 SDNode *N = Use->getOperand(i).getNode(); 01511 if (N == Def) { 01512 if (Use == ImmedUse || Use == Root) 01513 continue; // We are not looking for immediate use. 01514 assert(N != Root); 01515 return true; 01516 } 01517 01518 // Traverse up the operand chain. 01519 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 01520 return true; 01521 } 01522 return false; 01523 } 01524 01525 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 01526 /// operand node N of U during instruction selection that starts at Root. 01527 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 01528 SDNode *Root) const { 01529 if (OptLevel == CodeGenOpt::None) return false; 01530 return N.hasOneUse(); 01531 } 01532 01533 /// IsLegalToFold - Returns true if the specific operand node N of 01534 /// U can be folded during instruction selection that starts at Root. 01535 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 01536 CodeGenOpt::Level OptLevel, 01537 bool IgnoreChains) { 01538 if (OptLevel == CodeGenOpt::None) return false; 01539 01540 // If Root use can somehow reach N through a path that that doesn't contain 01541 // U then folding N would create a cycle. e.g. In the following 01542 // diagram, Root can reach N through X. If N is folded into into Root, then 01543 // X is both a predecessor and a successor of U. 01544 // 01545 // [N*] // 01546 // ^ ^ // 01547 // / \ // 01548 // [U*] [X]? // 01549 // ^ ^ // 01550 // \ / // 01551 // \ / // 01552 // [Root*] // 01553 // 01554 // * indicates nodes to be folded together. 01555 // 01556 // If Root produces glue, then it gets (even more) interesting. Since it 01557 // will be "glued" together with its glue use in the scheduler, we need to 01558 // check if it might reach N. 01559 // 01560 // [N*] // 01561 // ^ ^ // 01562 // / \ // 01563 // [U*] [X]? // 01564 // ^ ^ // 01565 // \ \ // 01566 // \ | // 01567 // [Root*] | // 01568 // ^ | // 01569 // f | // 01570 // | / // 01571 // [Y] / // 01572 // ^ / // 01573 // f / // 01574 // | / // 01575 // [GU] // 01576 // 01577 // If GU (glue use) indirectly reaches N (the load), and Root folds N 01578 // (call it Fold), then X is a predecessor of GU and a successor of 01579 // Fold. But since Fold and GU are glued together, this will create 01580 // a cycle in the scheduling graph. 01581 01582 // If the node has glue, walk down the graph to the "lowest" node in the 01583 // glueged set. 01584 EVT VT = Root->getValueType(Root->getNumValues()-1); 01585 while (VT == MVT::Glue) { 01586 SDNode *GU = findGlueUse(Root); 01587 if (GU == NULL) 01588 break; 01589 Root = GU; 01590 VT = Root->getValueType(Root->getNumValues()-1); 01591 01592 // If our query node has a glue result with a use, we've walked up it. If 01593 // the user (which has already been selected) has a chain or indirectly uses 01594 // the chain, our WalkChainUsers predicate will not consider it. Because of 01595 // this, we cannot ignore chains in this predicate. 01596 IgnoreChains = false; 01597 } 01598 01599 01600 SmallPtrSet<SDNode*, 16> Visited; 01601 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 01602 } 01603 01604 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 01605 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 01606 SelectInlineAsmMemoryOperands(Ops); 01607 01608 EVT VTs[] = { MVT::Other, MVT::Glue }; 01609 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 01610 VTs, &Ops[0], Ops.size()); 01611 New->setNodeId(-1); 01612 return New.getNode(); 01613 } 01614 01615 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 01616 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 01617 } 01618 01619 /// GetVBR - decode a vbr encoding whose top bit is set. 01620 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 01621 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 01622 assert(Val >= 128 && "Not a VBR"); 01623 Val &= 127; // Remove first vbr bit. 01624 01625 unsigned Shift = 7; 01626 uint64_t NextBits; 01627 do { 01628 NextBits = MatcherTable[Idx++]; 01629 Val |= (NextBits&127) << Shift; 01630 Shift += 7; 01631 } while (NextBits & 128); 01632 01633 return Val; 01634 } 01635 01636 01637 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of 01638 /// interior glue and chain results to use the new glue and chain results. 01639 void SelectionDAGISel:: 01640 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 01641 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 01642 SDValue InputGlue, 01643 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 01644 bool isMorphNodeTo) { 01645 SmallVector<SDNode*, 4> NowDeadNodes; 01646 01647 // Now that all the normal results are replaced, we replace the chain and 01648 // glue results if present. 01649 if (!ChainNodesMatched.empty()) { 01650 assert(InputChain.getNode() != 0 && 01651 "Matched input chains but didn't produce a chain"); 01652 // Loop over all of the nodes we matched that produced a chain result. 01653 // Replace all the chain results with the final chain we ended up with. 01654 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 01655 SDNode *ChainNode = ChainNodesMatched[i]; 01656 01657 // If this node was already deleted, don't look at it. 01658 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 01659 continue; 01660 01661 // Don't replace the results of the root node if we're doing a 01662 // MorphNodeTo. 01663 if (ChainNode == NodeToMatch && isMorphNodeTo) 01664 continue; 01665 01666 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 01667 if (ChainVal.getValueType() == MVT::Glue) 01668 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 01669 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 01670 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 01671 01672 // If the node became dead and we haven't already seen it, delete it. 01673 if (ChainNode->use_empty() && 01674 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 01675 NowDeadNodes.push_back(ChainNode); 01676 } 01677 } 01678 01679 // If the result produces glue, update any glue results in the matched 01680 // pattern with the glue result. 01681 if (InputGlue.getNode() != 0) { 01682 // Handle any interior nodes explicitly marked. 01683 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 01684 SDNode *FRN = GlueResultNodesMatched[i]; 01685 01686 // If this node was already deleted, don't look at it. 01687 if (FRN->getOpcode() == ISD::DELETED_NODE) 01688 continue; 01689 01690 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 01691 "Doesn't have a glue result"); 01692 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 01693 InputGlue); 01694 01695 // If the node became dead and we haven't already seen it, delete it. 01696 if (FRN->use_empty() && 01697 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 01698 NowDeadNodes.push_back(FRN); 01699 } 01700 } 01701 01702 if (!NowDeadNodes.empty()) 01703 CurDAG->RemoveDeadNodes(NowDeadNodes); 01704 01705 DEBUG(dbgs() << "ISEL: Match complete!\n"); 01706 } 01707 01708 enum ChainResult { 01709 CR_Simple, 01710 CR_InducesCycle, 01711 CR_LeadsToInteriorNode 01712 }; 01713 01714 /// WalkChainUsers - Walk down the users of the specified chained node that is 01715 /// part of the pattern we're matching, looking at all of the users we find. 01716 /// This determines whether something is an interior node, whether we have a 01717 /// non-pattern node in between two pattern nodes (which prevent folding because 01718 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched 01719 /// between pattern nodes (in which case the TF becomes part of the pattern). 01720 /// 01721 /// The walk we do here is guaranteed to be small because we quickly get down to 01722 /// already selected nodes "below" us. 01723 static ChainResult 01724 WalkChainUsers(const SDNode *ChainedNode, 01725 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 01726 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 01727 ChainResult Result = CR_Simple; 01728 01729 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 01730 E = ChainedNode->use_end(); UI != E; ++UI) { 01731 // Make sure the use is of the chain, not some other value we produce. 01732 if (UI.getUse().getValueType() != MVT::Other) continue; 01733 01734 SDNode *User = *UI; 01735 01736 // If we see an already-selected machine node, then we've gone beyond the 01737 // pattern that we're selecting down into the already selected chunk of the 01738 // DAG. 01739 if (User->isMachineOpcode() || 01740 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 01741 continue; 01742 01743 unsigned UserOpcode = User->getOpcode(); 01744 if (UserOpcode == ISD::CopyToReg || 01745 UserOpcode == ISD::CopyFromReg || 01746 UserOpcode == ISD::INLINEASM || 01747 UserOpcode == ISD::EH_LABEL || 01748 UserOpcode == ISD::LIFETIME_START || 01749 UserOpcode == ISD::LIFETIME_END) { 01750 // If their node ID got reset to -1 then they've already been selected. 01751 // Treat them like a MachineOpcode. 01752 if (User->getNodeId() == -1) 01753 continue; 01754 } 01755 01756 // If we have a TokenFactor, we handle it specially. 01757 if (User->getOpcode() != ISD::TokenFactor) { 01758 // If the node isn't a token factor and isn't part of our pattern, then it 01759 // must be a random chained node in between two nodes we're selecting. 01760 // This happens when we have something like: 01761 // x = load ptr 01762 // call 01763 // y = x+4 01764 // store y -> ptr 01765 // Because we structurally match the load/store as a read/modify/write, 01766 // but the call is chained between them. We cannot fold in this case 01767 // because it would induce a cycle in the graph. 01768 if (!std::count(ChainedNodesInPattern.begin(), 01769 ChainedNodesInPattern.end(), User)) 01770 return CR_InducesCycle; 01771 01772 // Otherwise we found a node that is part of our pattern. For example in: 01773 // x = load ptr 01774 // y = x+4 01775 // store y -> ptr 01776 // This would happen when we're scanning down from the load and see the 01777 // store as a user. Record that there is a use of ChainedNode that is 01778 // part of the pattern and keep scanning uses. 01779 Result = CR_LeadsToInteriorNode; 01780 InteriorChainedNodes.push_back(User); 01781 continue; 01782 } 01783 01784 // If we found a TokenFactor, there are two cases to consider: first if the 01785 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 01786 // uses of the TF are in our pattern) we just want to ignore it. Second, 01787 // the TokenFactor can be sandwiched in between two chained nodes, like so: 01788 // [Load chain] 01789 // ^ 01790 // | 01791 // [Load] 01792 // ^ ^ 01793 // | \ DAG's like cheese 01794 // / \ do you? 01795 // / | 01796 // [TokenFactor] [Op] 01797 // ^ ^ 01798 // | | 01799 // \ / 01800 // \ / 01801 // [Store] 01802 // 01803 // In this case, the TokenFactor becomes part of our match and we rewrite it 01804 // as a new TokenFactor. 01805 // 01806 // To distinguish these two cases, do a recursive walk down the uses. 01807 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 01808 case CR_Simple: 01809 // If the uses of the TokenFactor are just already-selected nodes, ignore 01810 // it, it is "below" our pattern. 01811 continue; 01812 case CR_InducesCycle: 01813 // If the uses of the TokenFactor lead to nodes that are not part of our 01814 // pattern that are not selected, folding would turn this into a cycle, 01815 // bail out now. 01816 return CR_InducesCycle; 01817 case CR_LeadsToInteriorNode: 01818 break; // Otherwise, keep processing. 01819 } 01820 01821 // Okay, we know we're in the interesting interior case. The TokenFactor 01822 // is now going to be considered part of the pattern so that we rewrite its 01823 // uses (it may have uses that are not part of the pattern) with the 01824 // ultimate chain result of the generated code. We will also add its chain 01825 // inputs as inputs to the ultimate TokenFactor we create. 01826 Result = CR_LeadsToInteriorNode; 01827 ChainedNodesInPattern.push_back(User); 01828 InteriorChainedNodes.push_back(User); 01829 continue; 01830 } 01831 01832 return Result; 01833 } 01834 01835 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 01836 /// operation for when the pattern matched at least one node with a chains. The 01837 /// input vector contains a list of all of the chained nodes that we match. We 01838 /// must determine if this is a valid thing to cover (i.e. matching it won't 01839 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 01840 /// be used as the input node chain for the generated nodes. 01841 static SDValue 01842 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 01843 SelectionDAG *CurDAG) { 01844 // Walk all of the chained nodes we've matched, recursively scanning down the 01845 // users of the chain result. This adds any TokenFactor nodes that are caught 01846 // in between chained nodes to the chained and interior nodes list. 01847 SmallVector<SDNode*, 3> InteriorChainedNodes; 01848 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 01849 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 01850 InteriorChainedNodes) == CR_InducesCycle) 01851 return SDValue(); // Would induce a cycle. 01852 } 01853 01854 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 01855 // that we are interested in. Form our input TokenFactor node. 01856 SmallVector<SDValue, 3> InputChains; 01857 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 01858 // Add the input chain of this node to the InputChains list (which will be 01859 // the operands of the generated TokenFactor) if it's not an interior node. 01860 SDNode *N = ChainNodesMatched[i]; 01861 if (N->getOpcode() != ISD::TokenFactor) { 01862 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 01863 continue; 01864 01865 // Otherwise, add the input chain. 01866 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 01867 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 01868 InputChains.push_back(InChain); 01869 continue; 01870 } 01871 01872 // If we have a token factor, we want to add all inputs of the token factor 01873 // that are not part of the pattern we're matching. 01874 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 01875 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 01876 N->getOperand(op).getNode())) 01877 InputChains.push_back(N->getOperand(op)); 01878 } 01879 } 01880 01881 SDValue Res; 01882 if (InputChains.size() == 1) 01883 return InputChains[0]; 01884 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 01885 MVT::Other, &InputChains[0], InputChains.size()); 01886 } 01887 01888 /// MorphNode - Handle morphing a node in place for the selector. 01889 SDNode *SelectionDAGISel:: 01890 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 01891 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 01892 // It is possible we're using MorphNodeTo to replace a node with no 01893 // normal results with one that has a normal result (or we could be 01894 // adding a chain) and the input could have glue and chains as well. 01895 // In this case we need to shift the operands down. 01896 // FIXME: This is a horrible hack and broken in obscure cases, no worse 01897 // than the old isel though. 01898 int OldGlueResultNo = -1, OldChainResultNo = -1; 01899 01900 unsigned NTMNumResults = Node->getNumValues(); 01901 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 01902 OldGlueResultNo = NTMNumResults-1; 01903 if (NTMNumResults != 1 && 01904 Node->getValueType(NTMNumResults-2) == MVT::Other) 01905 OldChainResultNo = NTMNumResults-2; 01906 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 01907 OldChainResultNo = NTMNumResults-1; 01908 01909 // Call the underlying SelectionDAG routine to do the transmogrification. Note 01910 // that this deletes operands of the old node that become dead. 01911 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 01912 01913 // MorphNodeTo can operate in two ways: if an existing node with the 01914 // specified operands exists, it can just return it. Otherwise, it 01915 // updates the node in place to have the requested operands. 01916 if (Res == Node) { 01917 // If we updated the node in place, reset the node ID. To the isel, 01918 // this should be just like a newly allocated machine node. 01919 Res->setNodeId(-1); 01920 } 01921 01922 unsigned ResNumResults = Res->getNumValues(); 01923 // Move the glue if needed. 01924 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 01925 (unsigned)OldGlueResultNo != ResNumResults-1) 01926 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 01927 SDValue(Res, ResNumResults-1)); 01928 01929 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 01930 --ResNumResults; 01931 01932 // Move the chain reference if needed. 01933 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 01934 (unsigned)OldChainResultNo != ResNumResults-1) 01935 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 01936 SDValue(Res, ResNumResults-1)); 01937 01938 // Otherwise, no replacement happened because the node already exists. Replace 01939 // Uses of the old node with the new one. 01940 if (Res != Node) 01941 CurDAG->ReplaceAllUsesWith(Node, Res); 01942 01943 return Res; 01944 } 01945 01946 /// CheckSame - Implements OP_CheckSame. 01947 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 01948 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 01949 SDValue N, 01950 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 01951 // Accept if it is exactly the same as a previously recorded node. 01952 unsigned RecNo = MatcherTable[MatcherIndex++]; 01953 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 01954 return N == RecordedNodes[RecNo].first; 01955 } 01956 01957 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 01958 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 01959 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 01960 const SelectionDAGISel &SDISel) { 01961 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 01962 } 01963 01964 /// CheckNodePredicate - Implements OP_CheckNodePredicate. 01965 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 01966 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 01967 const SelectionDAGISel &SDISel, SDNode *N) { 01968 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 01969 } 01970 01971 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 01972 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 01973 SDNode *N) { 01974 uint16_t Opc = MatcherTable[MatcherIndex++]; 01975 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 01976 return N->getOpcode() == Opc; 01977 } 01978 01979 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 01980 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 01981 SDValue N, const TargetLowering &TLI) { 01982 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 01983 if (N.getValueType() == VT) return true; 01984 01985 // Handle the case when VT is iPTR. 01986 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 01987 } 01988 01989 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 01990 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 01991 SDValue N, const TargetLowering &TLI, 01992 unsigned ChildNo) { 01993 if (ChildNo >= N.getNumOperands()) 01994 return false; // Match fails if out of range child #. 01995 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 01996 } 01997 01998 01999 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 02000 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 02001 SDValue N) { 02002 return cast<CondCodeSDNode>(N)->get() == 02003 (ISD::CondCode)MatcherTable[MatcherIndex++]; 02004 } 02005 02006 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 02007 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 02008 SDValue N, const TargetLowering &TLI) { 02009 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 02010 if (cast<VTSDNode>(N)->getVT() == VT) 02011 return true; 02012 02013 // Handle the case when VT is iPTR. 02014 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 02015 } 02016 02017 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 02018 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 02019 SDValue N) { 02020 int64_t Val = MatcherTable[MatcherIndex++]; 02021 if (Val & 128) 02022 Val = GetVBR(Val, MatcherTable, MatcherIndex); 02023 02024 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 02025 return C != 0 && C->getSExtValue() == Val; 02026 } 02027 02028 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 02029 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 02030 SDValue N, const SelectionDAGISel &SDISel) { 02031 int64_t Val = MatcherTable[MatcherIndex++]; 02032 if (Val & 128) 02033 Val = GetVBR(Val, MatcherTable, MatcherIndex); 02034 02035 if (N->getOpcode() != ISD::AND) return false; 02036 02037 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 02038 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 02039 } 02040 02041 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 02042 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 02043 SDValue N, const SelectionDAGISel &SDISel) { 02044 int64_t Val = MatcherTable[MatcherIndex++]; 02045 if (Val & 128) 02046 Val = GetVBR(Val, MatcherTable, MatcherIndex); 02047 02048 if (N->getOpcode() != ISD::OR) return false; 02049 02050 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 02051 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 02052 } 02053 02054 /// IsPredicateKnownToFail - If we know how and can do so without pushing a 02055 /// scope, evaluate the current node. If the current predicate is known to 02056 /// fail, set Result=true and return anything. If the current predicate is 02057 /// known to pass, set Result=false and return the MatcherIndex to continue 02058 /// with. If the current predicate is unknown, set Result=false and return the 02059 /// MatcherIndex to continue with. 02060 static unsigned IsPredicateKnownToFail(const unsigned char *Table, 02061 unsigned Index, SDValue N, 02062 bool &Result, 02063 const SelectionDAGISel &SDISel, 02064 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 02065 switch (Table[Index++]) { 02066 default: 02067 Result = false; 02068 return Index-1; // Could not evaluate this predicate. 02069 case SelectionDAGISel::OPC_CheckSame: 02070 Result = !::CheckSame(Table, Index, N, RecordedNodes); 02071 return Index; 02072 case SelectionDAGISel::OPC_CheckPatternPredicate: 02073 Result = !::CheckPatternPredicate(Table, Index, SDISel); 02074 return Index; 02075 case SelectionDAGISel::OPC_CheckPredicate: 02076 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 02077 return Index; 02078 case SelectionDAGISel::OPC_CheckOpcode: 02079 Result = !::CheckOpcode(Table, Index, N.getNode()); 02080 return Index; 02081 case SelectionDAGISel::OPC_CheckType: 02082 Result = !::CheckType(Table, Index, N, SDISel.TLI); 02083 return Index; 02084 case SelectionDAGISel::OPC_CheckChild0Type: 02085 case SelectionDAGISel::OPC_CheckChild1Type: 02086 case SelectionDAGISel::OPC_CheckChild2Type: 02087 case SelectionDAGISel::OPC_CheckChild3Type: 02088 case SelectionDAGISel::OPC_CheckChild4Type: 02089 case SelectionDAGISel::OPC_CheckChild5Type: 02090 case SelectionDAGISel::OPC_CheckChild6Type: 02091 case SelectionDAGISel::OPC_CheckChild7Type: 02092 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 02093 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 02094 return Index; 02095 case SelectionDAGISel::OPC_CheckCondCode: 02096 Result = !::CheckCondCode(Table, Index, N); 02097 return Index; 02098 case SelectionDAGISel::OPC_CheckValueType: 02099 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 02100 return Index; 02101 case SelectionDAGISel::OPC_CheckInteger: 02102 Result = !::CheckInteger(Table, Index, N); 02103 return Index; 02104 case SelectionDAGISel::OPC_CheckAndImm: 02105 Result = !::CheckAndImm(Table, Index, N, SDISel); 02106 return Index; 02107 case SelectionDAGISel::OPC_CheckOrImm: 02108 Result = !::CheckOrImm(Table, Index, N, SDISel); 02109 return Index; 02110 } 02111 } 02112 02113 namespace { 02114 02115 struct MatchScope { 02116 /// FailIndex - If this match fails, this is the index to continue with. 02117 unsigned FailIndex; 02118 02119 /// NodeStack - The node stack when the scope was formed. 02120 SmallVector<SDValue, 4> NodeStack; 02121 02122 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 02123 unsigned NumRecordedNodes; 02124 02125 /// NumMatchedMemRefs - The number of matched memref entries. 02126 unsigned NumMatchedMemRefs; 02127 02128 /// InputChain/InputGlue - The current chain/glue 02129 SDValue InputChain, InputGlue; 02130 02131 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 02132 bool HasChainNodesMatched, HasGlueResultNodesMatched; 02133 }; 02134 02135 } 02136 02137 SDNode *SelectionDAGISel:: 02138 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 02139 unsigned TableSize) { 02140 // FIXME: Should these even be selected? Handle these cases in the caller? 02141 switch (NodeToMatch->getOpcode()) { 02142 default: 02143 break; 02144 case ISD::EntryToken: // These nodes remain the same. 02145 case ISD::BasicBlock: 02146 case ISD::Register: 02147 case ISD::RegisterMask: 02148 //case ISD::VALUETYPE: 02149 //case ISD::CONDCODE: 02150 case ISD::HANDLENODE: 02151 case ISD::MDNODE_SDNODE: 02152 case ISD::TargetConstant: 02153 case ISD::TargetConstantFP: 02154 case ISD::TargetConstantPool: 02155 case ISD::TargetFrameIndex: 02156 case ISD::TargetExternalSymbol: 02157 case ISD::TargetBlockAddress: 02158 case ISD::TargetJumpTable: 02159 case ISD::TargetGlobalTLSAddress: 02160 case ISD::TargetGlobalAddress: 02161 case ISD::TokenFactor: 02162 case ISD::CopyFromReg: 02163 case ISD::CopyToReg: 02164 case ISD::EH_LABEL: 02165 case ISD::LIFETIME_START: 02166 case ISD::LIFETIME_END: 02167 NodeToMatch->setNodeId(-1); // Mark selected. 02168 return 0; 02169 case ISD::AssertSext: 02170 case ISD::AssertZext: 02171 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 02172 NodeToMatch->getOperand(0)); 02173 return 0; 02174 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 02175 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 02176 } 02177 02178 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 02179 02180 // Set up the node stack with NodeToMatch as the only node on the stack. 02181 SmallVector<SDValue, 8> NodeStack; 02182 SDValue N = SDValue(NodeToMatch, 0); 02183 NodeStack.push_back(N); 02184 02185 // MatchScopes - Scopes used when matching, if a match failure happens, this 02186 // indicates where to continue checking. 02187 SmallVector<MatchScope, 8> MatchScopes; 02188 02189 // RecordedNodes - This is the set of nodes that have been recorded by the 02190 // state machine. The second value is the parent of the node, or null if the 02191 // root is recorded. 02192 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 02193 02194 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 02195 // pattern. 02196 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 02197 02198 // These are the current input chain and glue for use when generating nodes. 02199 // Various Emit operations change these. For example, emitting a copytoreg 02200 // uses and updates these. 02201 SDValue InputChain, InputGlue; 02202 02203 // ChainNodesMatched - If a pattern matches nodes that have input/output 02204 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 02205 // which ones they are. The result is captured into this list so that we can 02206 // update the chain results when the pattern is complete. 02207 SmallVector<SDNode*, 3> ChainNodesMatched; 02208 SmallVector<SDNode*, 3> GlueResultNodesMatched; 02209 02210 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 02211 NodeToMatch->dump(CurDAG); 02212 dbgs() << '\n'); 02213 02214 // Determine where to start the interpreter. Normally we start at opcode #0, 02215 // but if the state machine starts with an OPC_SwitchOpcode, then we 02216 // accelerate the first lookup (which is guaranteed to be hot) with the 02217 // OpcodeOffset table. 02218 unsigned MatcherIndex = 0; 02219 02220 if (!OpcodeOffset.empty()) { 02221 // Already computed the OpcodeOffset table, just index into it. 02222 if (N.getOpcode() < OpcodeOffset.size()) 02223 MatcherIndex = OpcodeOffset[N.getOpcode()]; 02224 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 02225 02226 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 02227 // Otherwise, the table isn't computed, but the state machine does start 02228 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 02229 // is the first time we're selecting an instruction. 02230 unsigned Idx = 1; 02231 while (1) { 02232 // Get the size of this case. 02233 unsigned CaseSize = MatcherTable[Idx++]; 02234 if (CaseSize & 128) 02235 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 02236 if (CaseSize == 0) break; 02237 02238 // Get the opcode, add the index to the table. 02239 uint16_t Opc = MatcherTable[Idx++]; 02240 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 02241 if (Opc >= OpcodeOffset.size()) 02242 OpcodeOffset.resize((Opc+1)*2); 02243 OpcodeOffset[Opc] = Idx; 02244 Idx += CaseSize; 02245 } 02246 02247 // Okay, do the lookup for the first opcode. 02248 if (N.getOpcode() < OpcodeOffset.size()) 02249 MatcherIndex = OpcodeOffset[N.getOpcode()]; 02250 } 02251 02252 while (1) { 02253 assert(MatcherIndex < TableSize && "Invalid index"); 02254 #ifndef NDEBUG 02255 unsigned CurrentOpcodeIndex = MatcherIndex; 02256 #endif 02257 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 02258 switch (Opcode) { 02259 case OPC_Scope: { 02260 // Okay, the semantics of this operation are that we should push a scope 02261 // then evaluate the first child. However, pushing a scope only to have 02262 // the first check fail (which then pops it) is inefficient. If we can 02263 // determine immediately that the first check (or first several) will 02264 // immediately fail, don't even bother pushing a scope for them. 02265 unsigned FailIndex; 02266 02267 while (1) { 02268 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 02269 if (NumToSkip & 128) 02270 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 02271 // Found the end of the scope with no match. 02272 if (NumToSkip == 0) { 02273 FailIndex = 0; 02274 break; 02275 } 02276 02277 FailIndex = MatcherIndex+NumToSkip; 02278 02279 unsigned MatcherIndexOfPredicate = MatcherIndex; 02280 (void)MatcherIndexOfPredicate; // silence warning. 02281 02282 // If we can't evaluate this predicate without pushing a scope (e.g. if 02283 // it is a 'MoveParent') or if the predicate succeeds on this node, we 02284 // push the scope and evaluate the full predicate chain. 02285 bool Result; 02286 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 02287 Result, *this, RecordedNodes); 02288 if (!Result) 02289 break; 02290 02291 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 02292 << "index " << MatcherIndexOfPredicate 02293 << ", continuing at " << FailIndex << "\n"); 02294 ++NumDAGIselRetries; 02295 02296 // Otherwise, we know that this case of the Scope is guaranteed to fail, 02297 // move to the next case. 02298 MatcherIndex = FailIndex; 02299 } 02300 02301 // If the whole scope failed to match, bail. 02302 if (FailIndex == 0) break; 02303 02304 // Push a MatchScope which indicates where to go if the first child fails 02305 // to match. 02306 MatchScope NewEntry; 02307 NewEntry.FailIndex = FailIndex; 02308 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 02309 NewEntry.NumRecordedNodes = RecordedNodes.size(); 02310 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 02311 NewEntry.InputChain = InputChain; 02312 NewEntry.InputGlue = InputGlue; 02313 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 02314 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 02315 MatchScopes.push_back(NewEntry); 02316 continue; 02317 } 02318 case OPC_RecordNode: { 02319 // Remember this node, it may end up being an operand in the pattern. 02320 SDNode *Parent = 0; 02321 if (NodeStack.size() > 1) 02322 Parent = NodeStack[NodeStack.size()-2].getNode(); 02323 RecordedNodes.push_back(std::make_pair(N, Parent)); 02324 continue; 02325 } 02326 02327 case OPC_RecordChild0: case OPC_RecordChild1: 02328 case OPC_RecordChild2: case OPC_RecordChild3: 02329 case OPC_RecordChild4: case OPC_RecordChild5: 02330 case OPC_RecordChild6: case OPC_RecordChild7: { 02331 unsigned ChildNo = Opcode-OPC_RecordChild0; 02332 if (ChildNo >= N.getNumOperands()) 02333 break; // Match fails if out of range child #. 02334 02335 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 02336 N.getNode())); 02337 continue; 02338 } 02339 case OPC_RecordMemRef: 02340 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 02341 continue; 02342 02343 case OPC_CaptureGlueInput: 02344 // If the current node has an input glue, capture it in InputGlue. 02345 if (N->getNumOperands() != 0 && 02346 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 02347 InputGlue = N->getOperand(N->getNumOperands()-1); 02348 continue; 02349 02350 case OPC_MoveChild: { 02351 unsigned ChildNo = MatcherTable[MatcherIndex++]; 02352 if (ChildNo >= N.getNumOperands()) 02353 break; // Match fails if out of range child #. 02354 N = N.getOperand(ChildNo); 02355 NodeStack.push_back(N); 02356 continue; 02357 } 02358 02359 case OPC_MoveParent: 02360 // Pop the current node off the NodeStack. 02361 NodeStack.pop_back(); 02362 assert(!NodeStack.empty() && "Node stack imbalance!"); 02363 N = NodeStack.back(); 02364 continue; 02365 02366 case OPC_CheckSame: 02367 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 02368 continue; 02369 case OPC_CheckPatternPredicate: 02370 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 02371 continue; 02372 case OPC_CheckPredicate: 02373 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 02374 N.getNode())) 02375 break; 02376 continue; 02377 case OPC_CheckComplexPat: { 02378 unsigned CPNum = MatcherTable[MatcherIndex++]; 02379 unsigned RecNo = MatcherTable[MatcherIndex++]; 02380 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 02381 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 02382 RecordedNodes[RecNo].first, CPNum, 02383 RecordedNodes)) 02384 break; 02385 continue; 02386 } 02387 case OPC_CheckOpcode: 02388 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 02389 continue; 02390 02391 case OPC_CheckType: 02392 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 02393 continue; 02394 02395 case OPC_SwitchOpcode: { 02396 unsigned CurNodeOpcode = N.getOpcode(); 02397 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 02398 unsigned CaseSize; 02399 while (1) { 02400 // Get the size of this case. 02401 CaseSize = MatcherTable[MatcherIndex++]; 02402 if (CaseSize & 128) 02403 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 02404 if (CaseSize == 0) break; 02405 02406 uint16_t Opc = MatcherTable[MatcherIndex++]; 02407 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 02408 02409 // If the opcode matches, then we will execute this case. 02410 if (CurNodeOpcode == Opc) 02411 break; 02412 02413 // Otherwise, skip over this case. 02414 MatcherIndex += CaseSize; 02415 } 02416 02417 // If no cases matched, bail out. 02418 if (CaseSize == 0) break; 02419 02420 // Otherwise, execute the case we found. 02421 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 02422 << " to " << MatcherIndex << "\n"); 02423 continue; 02424 } 02425 02426 case OPC_SwitchType: { 02427 MVT CurNodeVT = N.getValueType().getSimpleVT(); 02428 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 02429 unsigned CaseSize; 02430 while (1) { 02431 // Get the size of this case. 02432 CaseSize = MatcherTable[MatcherIndex++]; 02433 if (CaseSize & 128) 02434 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 02435 if (CaseSize == 0) break; 02436 02437 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 02438 if (CaseVT == MVT::iPTR) 02439 CaseVT = TLI.getPointerTy(); 02440 02441 // If the VT matches, then we will execute this case. 02442 if (CurNodeVT == CaseVT) 02443 break; 02444 02445 // Otherwise, skip over this case. 02446 MatcherIndex += CaseSize; 02447 } 02448 02449 // If no cases matched, bail out. 02450 if (CaseSize == 0) break; 02451 02452 // Otherwise, execute the case we found. 02453 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 02454 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 02455 continue; 02456 } 02457 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 02458 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 02459 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 02460 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 02461 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 02462 Opcode-OPC_CheckChild0Type)) 02463 break; 02464 continue; 02465 case OPC_CheckCondCode: 02466 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 02467 continue; 02468 case OPC_CheckValueType: 02469 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 02470 continue; 02471 case OPC_CheckInteger: 02472 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 02473 continue; 02474 case OPC_CheckAndImm: 02475 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 02476 continue; 02477 case OPC_CheckOrImm: 02478 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 02479 continue; 02480 02481 case OPC_CheckFoldableChainNode: { 02482 assert(NodeStack.size() != 1 && "No parent node"); 02483 // Verify that all intermediate nodes between the root and this one have 02484 // a single use. 02485 bool HasMultipleUses = false; 02486 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 02487 if (!NodeStack[i].hasOneUse()) { 02488 HasMultipleUses = true; 02489 break; 02490 } 02491 if (HasMultipleUses) break; 02492 02493 // Check to see that the target thinks this is profitable to fold and that 02494 // we can fold it without inducing cycles in the graph. 02495 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 02496 NodeToMatch) || 02497 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 02498 NodeToMatch, OptLevel, 02499 true/*We validate our own chains*/)) 02500 break; 02501 02502 continue; 02503 } 02504 case OPC_EmitInteger: { 02505 MVT::SimpleValueType VT = 02506 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 02507 int64_t Val = MatcherTable[MatcherIndex++]; 02508 if (Val & 128) 02509 Val = GetVBR(Val, MatcherTable, MatcherIndex); 02510 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 02511 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 02512 continue; 02513 } 02514 case OPC_EmitRegister: { 02515 MVT::SimpleValueType VT = 02516 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 02517 unsigned RegNo = MatcherTable[MatcherIndex++]; 02518 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 02519 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 02520 continue; 02521 } 02522 case OPC_EmitRegister2: { 02523 // For targets w/ more than 256 register names, the register enum 02524 // values are stored in two bytes in the matcher table (just like 02525 // opcodes). 02526 MVT::SimpleValueType VT = 02527 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 02528 unsigned RegNo = MatcherTable[MatcherIndex++]; 02529 RegNo |= MatcherTable[MatcherIndex++] << 8; 02530 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 02531 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 02532 continue; 02533 } 02534 02535 case OPC_EmitConvertToTarget: { 02536 // Convert from IMM/FPIMM to target version. 02537 unsigned RecNo = MatcherTable[MatcherIndex++]; 02538 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 02539 SDValue Imm = RecordedNodes[RecNo].first; 02540 02541 if (Imm->getOpcode() == ISD::Constant) { 02542 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 02543 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 02544 } else if (Imm->getOpcode() == ISD::ConstantFP) { 02545 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 02546 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 02547 } 02548 02549 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 02550 continue; 02551 } 02552 02553 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 02554 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 02555 // These are space-optimized forms of OPC_EmitMergeInputChains. 02556 assert(InputChain.getNode() == 0 && 02557 "EmitMergeInputChains should be the first chain producing node"); 02558 assert(ChainNodesMatched.empty() && 02559 "Should only have one EmitMergeInputChains per match"); 02560 02561 // Read all of the chained nodes. 02562 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 02563 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 02564 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 02565 02566 // FIXME: What if other value results of the node have uses not matched 02567 // by this pattern? 02568 if (ChainNodesMatched.back() != NodeToMatch && 02569 !RecordedNodes[RecNo].first.hasOneUse()) { 02570 ChainNodesMatched.clear(); 02571 break; 02572 } 02573 02574 // Merge the input chains if they are not intra-pattern references. 02575 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 02576 02577 if (InputChain.getNode() == 0) 02578 break; // Failed to merge. 02579 continue; 02580 } 02581 02582 case OPC_EmitMergeInputChains: { 02583 assert(InputChain.getNode() == 0 && 02584 "EmitMergeInputChains should be the first chain producing node"); 02585 // This node gets a list of nodes we matched in the input that have 02586 // chains. We want to token factor all of the input chains to these nodes 02587 // together. However, if any of the input chains is actually one of the 02588 // nodes matched in this pattern, then we have an intra-match reference. 02589 // Ignore these because the newly token factored chain should not refer to 02590 // the old nodes. 02591 unsigned NumChains = MatcherTable[MatcherIndex++]; 02592 assert(NumChains != 0 && "Can't TF zero chains"); 02593 02594 assert(ChainNodesMatched.empty() && 02595 "Should only have one EmitMergeInputChains per match"); 02596 02597 // Read all of the chained nodes. 02598 for (unsigned i = 0; i != NumChains; ++i) { 02599 unsigned RecNo = MatcherTable[MatcherIndex++]; 02600 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 02601 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 02602 02603 // FIXME: What if other value results of the node have uses not matched 02604 // by this pattern? 02605 if (ChainNodesMatched.back() != NodeToMatch && 02606 !RecordedNodes[RecNo].first.hasOneUse()) { 02607 ChainNodesMatched.clear(); 02608 break; 02609 } 02610 } 02611 02612 // If the inner loop broke out, the match fails. 02613 if (ChainNodesMatched.empty()) 02614 break; 02615 02616 // Merge the input chains if they are not intra-pattern references. 02617 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 02618 02619 if (InputChain.getNode() == 0) 02620 break; // Failed to merge. 02621 02622 continue; 02623 } 02624 02625 case OPC_EmitCopyToReg: { 02626 unsigned RecNo = MatcherTable[MatcherIndex++]; 02627 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 02628 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 02629 02630 if (InputChain.getNode() == 0) 02631 InputChain = CurDAG->getEntryNode(); 02632 02633 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 02634 DestPhysReg, RecordedNodes[RecNo].first, 02635 InputGlue); 02636 02637 InputGlue = InputChain.getValue(1); 02638 continue; 02639 } 02640 02641 case OPC_EmitNodeXForm: { 02642 unsigned XFormNo = MatcherTable[MatcherIndex++]; 02643 unsigned RecNo = MatcherTable[MatcherIndex++]; 02644 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 02645 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 02646 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 02647 continue; 02648 } 02649 02650 case OPC_EmitNode: 02651 case OPC_MorphNodeTo: { 02652 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 02653 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 02654 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 02655 // Get the result VT list. 02656 unsigned NumVTs = MatcherTable[MatcherIndex++]; 02657 SmallVector<EVT, 4> VTs; 02658 for (unsigned i = 0; i != NumVTs; ++i) { 02659 MVT::SimpleValueType VT = 02660 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 02661 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 02662 VTs.push_back(VT); 02663 } 02664 02665 if (EmitNodeInfo & OPFL_Chain) 02666 VTs.push_back(MVT::Other); 02667 if (EmitNodeInfo & OPFL_GlueOutput) 02668 VTs.push_back(MVT::Glue); 02669 02670 // This is hot code, so optimize the two most common cases of 1 and 2 02671 // results. 02672 SDVTList VTList; 02673 if (VTs.size() == 1) 02674 VTList = CurDAG->getVTList(VTs[0]); 02675 else if (VTs.size() == 2) 02676 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 02677 else 02678 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 02679 02680 // Get the operand list. 02681 unsigned NumOps = MatcherTable[MatcherIndex++]; 02682 SmallVector<SDValue, 8> Ops; 02683 for (unsigned i = 0; i != NumOps; ++i) { 02684 unsigned RecNo = MatcherTable[MatcherIndex++]; 02685 if (RecNo & 128) 02686 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 02687 02688 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 02689 Ops.push_back(RecordedNodes[RecNo].first); 02690 } 02691 02692 // If there are variadic operands to add, handle them now. 02693 if (EmitNodeInfo & OPFL_VariadicInfo) { 02694 // Determine the start index to copy from. 02695 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 02696 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 02697 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 02698 "Invalid variadic node"); 02699 // Copy all of the variadic operands, not including a potential glue 02700 // input. 02701 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 02702 i != e; ++i) { 02703 SDValue V = NodeToMatch->getOperand(i); 02704 if (V.getValueType() == MVT::Glue) break; 02705 Ops.push_back(V); 02706 } 02707 } 02708 02709 // If this has chain/glue inputs, add them. 02710 if (EmitNodeInfo & OPFL_Chain) 02711 Ops.push_back(InputChain); 02712 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 02713 Ops.push_back(InputGlue); 02714 02715 // Create the node. 02716 SDNode *Res = 0; 02717 if (Opcode != OPC_MorphNodeTo) { 02718 // If this is a normal EmitNode command, just create the new node and 02719 // add the results to the RecordedNodes list. 02720 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 02721 VTList, Ops); 02722 02723 // Add all the non-glue/non-chain results to the RecordedNodes list. 02724 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 02725 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 02726 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 02727 (SDNode*) 0)); 02728 } 02729 02730 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 02731 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 02732 EmitNodeInfo); 02733 } else { 02734 // NodeToMatch was eliminated by CSE when the target changed the DAG. 02735 // We will visit the equivalent node later. 02736 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 02737 return 0; 02738 } 02739 02740 // If the node had chain/glue results, update our notion of the current 02741 // chain and glue. 02742 if (EmitNodeInfo & OPFL_GlueOutput) { 02743 InputGlue = SDValue(Res, VTs.size()-1); 02744 if (EmitNodeInfo & OPFL_Chain) 02745 InputChain = SDValue(Res, VTs.size()-2); 02746 } else if (EmitNodeInfo & OPFL_Chain) 02747 InputChain = SDValue(Res, VTs.size()-1); 02748 02749 // If the OPFL_MemRefs glue is set on this node, slap all of the 02750 // accumulated memrefs onto it. 02751 // 02752 // FIXME: This is vastly incorrect for patterns with multiple outputs 02753 // instructions that access memory and for ComplexPatterns that match 02754 // loads. 02755 if (EmitNodeInfo & OPFL_MemRefs) { 02756 // Only attach load or store memory operands if the generated 02757 // instruction may load or store. 02758 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 02759 bool mayLoad = MCID.mayLoad(); 02760 bool mayStore = MCID.mayStore(); 02761 02762 unsigned NumMemRefs = 0; 02763 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 02764 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 02765 if ((*I)->isLoad()) { 02766 if (mayLoad) 02767 ++NumMemRefs; 02768 } else if ((*I)->isStore()) { 02769 if (mayStore) 02770 ++NumMemRefs; 02771 } else { 02772 ++NumMemRefs; 02773 } 02774 } 02775 02776 MachineSDNode::mmo_iterator MemRefs = 02777 MF->allocateMemRefsArray(NumMemRefs); 02778 02779 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 02780 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 02781 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 02782 if ((*I)->isLoad()) { 02783 if (mayLoad) 02784 *MemRefsPos++ = *I; 02785 } else if ((*I)->isStore()) { 02786 if (mayStore) 02787 *MemRefsPos++ = *I; 02788 } else { 02789 *MemRefsPos++ = *I; 02790 } 02791 } 02792 02793 cast<MachineSDNode>(Res) 02794 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 02795 } 02796 02797 DEBUG(dbgs() << " " 02798 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 02799 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 02800 02801 // If this was a MorphNodeTo then we're completely done! 02802 if (Opcode == OPC_MorphNodeTo) { 02803 // Update chain and glue uses. 02804 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 02805 InputGlue, GlueResultNodesMatched, true); 02806 return Res; 02807 } 02808 02809 continue; 02810 } 02811 02812 case OPC_MarkGlueResults: { 02813 unsigned NumNodes = MatcherTable[MatcherIndex++]; 02814 02815 // Read and remember all the glue-result nodes. 02816 for (unsigned i = 0; i != NumNodes; ++i) { 02817 unsigned RecNo = MatcherTable[MatcherIndex++]; 02818 if (RecNo & 128) 02819 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 02820 02821 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 02822 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 02823 } 02824 continue; 02825 } 02826 02827 case OPC_CompleteMatch: { 02828 // The match has been completed, and any new nodes (if any) have been 02829 // created. Patch up references to the matched dag to use the newly 02830 // created nodes. 02831 unsigned NumResults = MatcherTable[MatcherIndex++]; 02832 02833 for (unsigned i = 0; i != NumResults; ++i) { 02834 unsigned ResSlot = MatcherTable[MatcherIndex++]; 02835 if (ResSlot & 128) 02836 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 02837 02838 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 02839 SDValue Res = RecordedNodes[ResSlot].first; 02840 02841 assert(i < NodeToMatch->getNumValues() && 02842 NodeToMatch->getValueType(i) != MVT::Other && 02843 NodeToMatch->getValueType(i) != MVT::Glue && 02844 "Invalid number of results to complete!"); 02845 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 02846 NodeToMatch->getValueType(i) == MVT::iPTR || 02847 Res.getValueType() == MVT::iPTR || 02848 NodeToMatch->getValueType(i).getSizeInBits() == 02849 Res.getValueType().getSizeInBits()) && 02850 "invalid replacement"); 02851 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 02852 } 02853 02854 // If the root node defines glue, add it to the glue nodes to update list. 02855 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 02856 GlueResultNodesMatched.push_back(NodeToMatch); 02857 02858 // Update chain and glue uses. 02859 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 02860 InputGlue, GlueResultNodesMatched, false); 02861 02862 assert(NodeToMatch->use_empty() && 02863 "Didn't replace all uses of the node?"); 02864 02865 // FIXME: We just return here, which interacts correctly with SelectRoot 02866 // above. We should fix this to not return an SDNode* anymore. 02867 return 0; 02868 } 02869 } 02870 02871 // If the code reached this point, then the match failed. See if there is 02872 // another child to try in the current 'Scope', otherwise pop it until we 02873 // find a case to check. 02874 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 02875 ++NumDAGIselRetries; 02876 while (1) { 02877 if (MatchScopes.empty()) { 02878 CannotYetSelect(NodeToMatch); 02879 return 0; 02880 } 02881 02882 // Restore the interpreter state back to the point where the scope was 02883 // formed. 02884 MatchScope &LastScope = MatchScopes.back(); 02885 RecordedNodes.resize(LastScope.NumRecordedNodes); 02886 NodeStack.clear(); 02887 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 02888 N = NodeStack.back(); 02889 02890 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 02891 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 02892 MatcherIndex = LastScope.FailIndex; 02893 02894 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 02895 02896 InputChain = LastScope.InputChain; 02897 InputGlue = LastScope.InputGlue; 02898 if (!LastScope.HasChainNodesMatched) 02899 ChainNodesMatched.clear(); 02900 if (!LastScope.HasGlueResultNodesMatched) 02901 GlueResultNodesMatched.clear(); 02902 02903 // Check to see what the offset is at the new MatcherIndex. If it is zero 02904 // we have reached the end of this scope, otherwise we have another child 02905 // in the current scope to try. 02906 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 02907 if (NumToSkip & 128) 02908 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 02909 02910 // If we have another child in this scope to match, update FailIndex and 02911 // try it. 02912 if (NumToSkip != 0) { 02913 LastScope.FailIndex = MatcherIndex+NumToSkip; 02914 break; 02915 } 02916 02917 // End of this scope, pop it and try the next child in the containing 02918 // scope. 02919 MatchScopes.pop_back(); 02920 } 02921 } 02922 } 02923 02924 02925 02926 void SelectionDAGISel::CannotYetSelect(SDNode *N) { 02927 std::string msg; 02928 raw_string_ostream Msg(msg); 02929 Msg << "Cannot select: "; 02930 02931 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 02932 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 02933 N->getOpcode() != ISD::INTRINSIC_VOID) { 02934 N->printrFull(Msg, CurDAG); 02935 Msg << "\nIn function: " << MF->getName(); 02936 } else { 02937 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 02938 unsigned iid = 02939 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 02940 if (iid < Intrinsic::num_intrinsics) 02941 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 02942 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 02943 Msg << "target intrinsic %" << TII->getName(iid); 02944 else 02945 Msg << "unknown intrinsic #" << iid; 02946 } 02947 report_fatal_error(Msg.str()); 02948 } 02949 02950 char SelectionDAGISel::ID = 0;