80#include "llvm/IR/IntrinsicsWebAssembly.h"
118#define DEBUG_TYPE "isel"
119#define ISEL_DUMP_DEBUG_TYPE DEBUG_TYPE "-dump"
121STATISTIC(NumFastIselFailures,
"Number of instructions fast isel failed on");
122STATISTIC(NumFastIselSuccess,
"Number of instructions fast isel selected");
123STATISTIC(NumFastIselBlocks,
"Number of blocks selected entirely by fast isel");
124STATISTIC(NumDAGBlocks,
"Number of blocks selected using DAG");
125STATISTIC(NumDAGIselRetries,
"Number of times dag isel has to try another path");
126STATISTIC(NumEntryBlocks,
"Number of entry blocks encountered");
128 "Number of entry blocks where fast isel failed to lower arguments");
132 cl::desc(
"Enable abort calls when \"fast\" instruction selection "
133 "fails to lower an instruction: 0 disable the abort, 1 will "
134 "abort but for args, calls and terminators, 2 will also "
135 "abort for argument lowering, and 3 will never fallback "
136 "to SelectionDAG."));
140 cl::desc(
"Emit a diagnostic when \"fast\" instruction selection "
141 "falls back to SelectionDAG."));
145 cl::desc(
"use Machine Branch Probability Info"),
151 cl::desc(
"Only display the basic block whose name "
152 "matches this for all view-*-dags options"));
155 cl::desc(
"Pop up a window to show dags before the first "
156 "dag combine pass"));
159 cl::desc(
"Pop up a window to show dags before legalize types"));
162 cl::desc(
"Pop up a window to show dags before the post "
163 "legalize types dag combine pass"));
166 cl::desc(
"Pop up a window to show dags before legalize"));
169 cl::desc(
"Pop up a window to show dags before the second "
170 "dag combine pass"));
173 cl::desc(
"Pop up a window to show isel dags as they are selected"));
176 cl::desc(
"Pop up a window to show sched dags as they are processed"));
179 cl::desc(
"Pop up a window to show SUnit dags after they are processed"));
188#define ISEL_DUMP(X) \
190 if (llvm::DebugFlag && \
191 (isCurrentDebugType(DEBUG_TYPE) || \
192 (isCurrentDebugType(ISEL_DUMP_DEBUG_TYPE) && MatchFilterFuncName))) { \
197#define ISEL_DUMP(X) do { } while (false)
217 cl::desc(
"Instruction schedulers available (before register"
230 return Arg.hasAttribute(Attribute::AttrKind::SwiftAsync);
249 if (NewOptLevel != SavedOptLevel) {
252 LLVM_DEBUG(
dbgs() <<
"\nChanging optimization level for Function "
254 LLVM_DEBUG(
dbgs() <<
"\tBefore: -O" <<
static_cast<int>(SavedOptLevel)
255 <<
" ; After: -O" <<
static_cast<int>(NewOptLevel)
263 dbgs() <<
"\tFastISel is "
271 LLVM_DEBUG(
dbgs() <<
"\nRestoring optimization level for Function "
274 <<
" ; After: -O" <<
static_cast<int>(SavedOptLevel) <<
"\n");
290 if (
auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
291 return SchedulerCtor(IS, OptLevel);
295 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
309 "Unknown sched type!");
319 dbgs() <<
"If a target marks an instruction with "
320 "'usesCustomInserter', it must implement "
321 "TargetLowering::EmitInstrWithCustomInserter!\n";
329 "If a target marks an instruction with 'hasPostISelHook', "
330 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
338 char &
ID, std::unique_ptr<SelectionDAGISel> S)
370 : Selector->OptLevel;
374 Selector->initializeAnalysisResults(*
this);
375 return Selector->runOnMachineFunction(MF);
449 : Selector->OptLevel;
452 Selector->initializeAnalysisResults(MFAM);
453 Selector->runOnMachineFunction(MF);
476 ORE = std::make_unique<OptimizationRemarkEmitter>(&Fn);
511#if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
531 ORE = std::make_unique<OptimizationRemarkEmitter>(&Fn);
544 UA = &UAPass->getUniformityInfo();
569#if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
601 if (isa<UnreachableInst>(Term) || isa<ReturnInst>(Term))
615 SelectAllBasicBlocks(Fn);
643 MRI.constrainRegClass(To,
MRI.getRegClass(
From));
649 if (!
MRI.use_empty(To))
669 if (Term !=
MBB.
end() && Term->isReturn()) {
678 if (!
FuncInfo->ArgDbgValues.empty())
684 for (
unsigned i = 0, e =
FuncInfo->ArgDbgValues.size(); i != e; ++i) {
686 assert(
MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST &&
687 "Function parameters should not be described by DBG_VALUE_LIST.");
688 bool hasFI =
MI->getDebugOperand(0).isFI();
690 hasFI ?
TRI.getFrameRegister(*
MF) :
MI->getDebugOperand(0).getReg();
691 if (Reg.isPhysical())
698 Def->getParent()->insert(std::next(InsertPos),
MI);
709 if (!Reg.isPhysical())
712 if (LDI != LiveInMap.
end()) {
713 assert(!hasFI &&
"There's no handling of frame pointer updating here yet "
717 const MDNode *Variable =
MI->getDebugVariable();
718 const MDNode *Expr =
MI->getDebugExpression();
720 bool IsIndirect =
MI->isIndirectDebugValue();
722 assert(
MI->getDebugOffset().getImm() == 0 &&
723 "DBG_VALUE with nonzero offset");
724 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
DL) &&
725 "Expected inlined-at fields to agree");
726 assert(
MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST &&
727 "Didn't expect to see a DBG_VALUE_LIST here");
730 IsIndirect, LDI->second, Variable, Expr);
737 if (
UseMI.isDebugValue())
739 if (
UseMI.isCopy() && !CopyUseMI &&
UseMI.getParent() == EntryMBB) {
748 TRI.getRegSizeInBits(LDI->second,
MRI) ==
768 for (
const auto &
MBB : *
MF) {
772 for (
const auto &
MI :
MBB) {
775 MI.isStackAligningInlineAsm()) {
778 if (
MI.isInlineAsm()) {
788 ISEL_DUMP(
dbgs() <<
"*** MachineFunction at end of ISel ***\n");
800 if (!R.getLocation().isValid() || ShouldAbort)
801 R << (
" (in function: " + MF.
getName() +
")").str();
816 if (--
I == Begin || !isa<ReturnInst>(*
I))
819 bool HaveFakeUse =
false;
820 bool HaveTailCall =
false;
822 if (
const CallInst *CI = dyn_cast<CallInst>(--
I))
823 if (CI->isTailCall()) {
828 if (
II->getIntrinsicID() == Intrinsic::fake_use)
830 }
while (
I != Begin);
833 if (!HaveTailCall || !HaveFakeUse)
843 if (
auto UsedDef = dyn_cast<Instruction>(FakeUse->getOperand(0));
844 !UsedDef || UsedDef->getParent() !=
I->getParent() ||
845 UsedDef->comesBefore(&*
I))
850 for (
auto *Inst : FakeUses)
851 Inst->moveBefore(*Inst->getParent(),
I);
867 SDB->visitDbgInfo(*
I);
872 HadTailCall =
SDB->HasTailCall;
873 SDB->resolveOrClearDbgInfo();
880void SelectionDAGISel::ComputeLiveOutVRegInfo() {
894 if (
Op.getValueType() == MVT::Other &&
Added.insert(
Op.getNode()).second)
901 Register DestReg = cast<RegisterSDNode>(
N->getOperand(1))->getReg();
907 EVT SrcVT = Src.getValueType();
913 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, Known);
914 }
while (!Worklist.
empty());
917void SelectionDAGISel::CodeGenAndEmitDAG() {
919 StringRef GroupDescription =
"Instruction Selection and Scheduling";
920 std::string BlockName;
921 bool MatchFilterBB =
false;
930 FuncInfo->MBB->getBasicBlock()->getName());
946#if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
948 CurDAG->VerifyDAGDivergence();
966#if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
968 CurDAG->VerifyDAGDivergence();
988#if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
990 CurDAG->VerifyDAGDivergence();
1007 ISEL_DUMP(
dbgs() <<
"\nOptimized type-legalized selection DAG: "
1012#if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
1014 CurDAG->VerifyDAGDivergence();
1030#if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
1032 CurDAG->VerifyDAGDivergence();
1041 ISEL_DUMP(
dbgs() <<
"\nVector/type-legalized selection DAG: "
1046#if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
1048 CurDAG->VerifyDAGDivergence();
1061 ISEL_DUMP(
dbgs() <<
"\nOptimized vector-legalized selection DAG: "
1066#if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
1068 CurDAG->VerifyDAGDivergence();
1086#if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
1088 CurDAG->VerifyDAGDivergence();
1106#if !defined(NDEBUG) && LLVM_ENABLE_ABI_BREAKING_CHECKS
1108 CurDAG->VerifyDAGDivergence();
1112 ComputeLiveOutVRegInfo();
1122 DoInstructionSelection();
1158 if (FirstMBB != LastMBB)
1159 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
1181 :
SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
1194 void NodeInserted(
SDNode *
N)
override {
1195 SDNode *CurNode = &*ISelPosition;
1196 if (
MDNode *MD = DAG.getPCSections(CurNode))
1197 DAG.addPCSections(
N, MD);
1198 if (
MDNode *MMRA = DAG.getMMRAMetadata(CurNode))
1199 DAG.addMMRAMetadata(
N, MMRA);
1229 while (!Nodes.
empty()) {
1231 for (
auto *U :
N->users()) {
1232 auto UId = U->getNodeId();
1245 int InvalidId = -(
N->getNodeId() + 1);
1246 N->setNodeId(InvalidId);
1251 int Id =
N->getNodeId();
1257void SelectionDAGISel::DoInstructionSelection() {
1260 <<
FuncInfo->MBB->getName() <<
"'\n");
1278 ISelUpdater ISU(*
CurDAG, ISelPosition);
1285 SDNode *Node = &*--ISelPosition;
1289 if (Node->use_empty())
1296 while (!Nodes.
empty()) {
1313 "Node has already selected predecessor node");
1330 switch (
Node->getOpcode()) {
1339 ActionVT =
Node->getOperand(1).getValueType();
1342 ActionVT =
Node->getValueType(0);
1350 LLVM_DEBUG(
dbgs() <<
"\nISEL: Starting selection on root node: ";
1366 if (
const IntrinsicInst *EHPtrCall = dyn_cast<IntrinsicInst>(U)) {
1368 if (IID == Intrinsic::eh_exceptionpointer ||
1369 IID == Intrinsic::eh_exceptioncode)
1384 bool IsSingleCatchAllClause =
1389 bool IsCatchLongjmp = CPI->
arg_size() == 0;
1390 if (!IsSingleCatchAllClause && !IsCatchLongjmp) {
1392 bool IntrFound =
false;
1394 if (
const auto *Call = dyn_cast<IntrinsicInst>(U)) {
1396 if (IID == Intrinsic::wasm_landingpad_index) {
1397 Value *IndexArg = Call->getArgOperand(1);
1398 int Index = cast<ConstantInt>(IndexArg)->getZExtValue();
1405 assert(IntrFound &&
"wasm.landingpad.index intrinsic not found!");
1412bool SelectionDAGISel::PrepareEHLandingPad() {
1424 if (
const auto *CPI = dyn_cast<CatchPadInst>(LLVMBB->
getFirstNonPHIIt())) {
1429 assert(EHPhysReg &&
"target lacks exception pointer register");
1431 unsigned VReg =
FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
1433 TII->
get(TargetOpcode::COPY), VReg)
1451 if (
auto *RegMask =
TRI.getCustomEHPadPreservedMask(*
MF))
1495 TII->
get(TargetOpcode::EH_LABEL))
1504 TII->
get(TargetOpcode::EH_LABEL))
1515 return !
I->mayWriteToMemory() &&
1516 !
I->isTerminator() &&
1517 !isa<DbgInfoIntrinsic>(
I) &&
1529 auto ArgIt = FuncInfo.
ValueMap.find(Arg);
1530 if (ArgIt == FuncInfo.
ValueMap.end())
1532 Register ArgVReg = ArgIt->getSecond();
1536 if (VirtReg == ArgVReg) {
1540 LLVM_DEBUG(
dbgs() <<
"processDbgDeclare: setVariableDbgInfo Var=" << *Var
1541 <<
", Expr=" << *Expr <<
", MCRegister=" << PhysReg
1542 <<
", DbgLoc=" << DbgLoc <<
"\n");
1553 <<
" (bad address)\n");
1563 assert(Var &&
"Missing variable");
1564 assert(DbgLoc &&
"Missing location");
1574 int FI = std::numeric_limits<int>::max();
1575 if (
const auto *AI = dyn_cast<AllocaInst>(
Address)) {
1579 }
else if (
const auto *Arg = dyn_cast<Argument>(
Address))
1582 if (FI == std::numeric_limits<int>::max())
1585 if (
Offset.getBoolValue())
1589 LLVM_DEBUG(
dbgs() <<
"processDbgDeclare: setVariableDbgInfo Var=" << *Var
1590 <<
", Expr=" << *Expr <<
", FI=" << FI
1591 <<
", DbgLoc=" << DbgLoc <<
"\n");
1600 const auto *DI = dyn_cast<DbgDeclareInst>(&
I);
1602 DI->getVariable(), DI->getDebugLoc()))
1607 DVR.getExpression(), DVR.getVariable(),
1622 assert(!It->Values.hasArgList() &&
"Single loc variadic ops not supported");
1628void SelectionDAGISel::SelectAllBasicBlocks(
const Function &Fn) {
1658 ++NumFastIselFailLowerArguments;
1663 R <<
"FastISel didn't lower all arguments: "
1671 CodeGenAndEmitDAG();
1685 if (FastIS && Inserted)
1690 "expected AssignmentTrackingAnalysis pass results");
1700 bool AllPredsVisited =
true;
1702 if (!
FuncInfo->VisitedBBs[Pred->getNumber()]) {
1703 AllPredsVisited =
false;
1708 if (AllPredsVisited) {
1710 FuncInfo->ComputePHILiveOutRegInfo(&PN);
1713 FuncInfo->InvalidatePHILiveOutRegInfo(&PN);
1724 const_cast<BasicBlock *
>(LLVMBB)->getFirstNonPHIIt();
1741 FuncInfo->ExceptionPointerVirtReg = 0;
1742 FuncInfo->ExceptionSelectorVirtReg = 0;
1744 if (!PrepareEHLandingPad())
1752 unsigned NumFastIselRemaining = std::distance(Begin,
End);
1758 for (; BI != Begin; --BI) {
1764 --NumFastIselRemaining;
1775 --NumFastIselRemaining;
1776 ++NumFastIselSuccess;
1783 while (BeforeInst != &*Begin) {
1788 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1793 <<
"FastISel folded load: " << *BeforeInst <<
"\n");
1796 --NumFastIselRemaining;
1797 ++NumFastIselSuccess;
1809 if (isa<CallInst>(Inst) && !isa<GCStatepointInst>(Inst) &&
1810 !isa<GCRelocateInst>(Inst) && !isa<GCResultInst>(Inst)) {
1814 R <<
"FastISel missed call";
1817 std::string InstStrStorage;
1821 R <<
": " << InstStrStorage;
1833 bool HadTailCall =
false;
1835 SelectBasicBlock(Inst->
getIterator(), BI, HadTailCall);
1847 unsigned RemainingNow = std::distance(Begin, BI);
1848 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1849 NumFastIselRemaining = RemainingNow;
1859 R <<
"FastISel missed terminator";
1863 R <<
"FastISel missed";
1867 std::string InstStrStorage;
1870 R <<
": " << InstStrStorage;
1875 NumFastIselFailures += NumFastIselRemaining;
1883 bool FunctionBasedInstrumentation =
1885 SDB->SPDescriptor.initialize(LLVMBB,
FuncInfo->getMBB(LLVMBB),
1886 FunctionBasedInstrumentation);
1892 ++NumFastIselBlocks;
1899 SelectBasicBlock(Begin, BI, HadTailCall);
1911 FuncInfo->PHINodesToUpdate.clear();
1917 reportIPToStateForBlocks(
MF);
1924 SDB->clearDanglingDebugInfo();
1925 SDB->SPDescriptor.resetPerFunctionState();
1929SelectionDAGISel::FinishBasicBlock() {
1931 <<
FuncInfo->PHINodesToUpdate.size() <<
"\n";
1932 for (
unsigned i = 0, e =
FuncInfo->PHINodesToUpdate.size(); i != e;
1934 <<
"Node " << i <<
" : (" <<
FuncInfo->PHINodesToUpdate[i].first
1935 <<
", " <<
FuncInfo->PHINodesToUpdate[i].second <<
")\n");
1939 for (
unsigned i = 0, e =
FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1942 "This is not a machine PHI node that we are updating!");
1943 if (!
FuncInfo->MBB->isSuccessor(
PHI->getParent()))
1949 if (
SDB->SPDescriptor.shouldEmitFunctionBasedCheckStackProtector()) {
1958 SDB->visitSPDescriptorParent(
SDB->SPDescriptor, ParentMBB);
1961 CodeGenAndEmitDAG();
1964 SDB->SPDescriptor.resetPerBBState();
1965 }
else if (
SDB->SPDescriptor.shouldEmitStackProtector()) {
1979 SuccessMBB->
splice(SuccessMBB->
end(), ParentMBB,
1986 SDB->visitSPDescriptorParent(
SDB->SPDescriptor, ParentMBB);
1989 CodeGenAndEmitDAG();
1993 if (FailureMBB->
empty()) {
1996 SDB->visitSPDescriptorFailure(
SDB->SPDescriptor);
1999 CodeGenAndEmitDAG();
2003 SDB->SPDescriptor.resetPerBBState();
2007 for (
auto &BTB :
SDB->SL->BitTestCases) {
2017 CodeGenAndEmitDAG();
2021 for (
unsigned j = 0, ej = BTB.Cases.size(); j != ej; ++j) {
2022 UnhandledProb -= BTB.Cases[
j].ExtraProb;
2037 if ((BTB.ContiguousRange || BTB.FallthroughUnreachable) && j + 2 == ej) {
2040 NextMBB = BTB.Cases[
j + 1].TargetBB;
2041 }
else if (j + 1 == ej) {
2043 NextMBB = BTB.Default;
2046 NextMBB = BTB.Cases[
j + 1].ThisBB;
2049 SDB->visitBitTestCase(BTB, NextMBB, UnhandledProb, BTB.Reg, BTB.Cases[j],
2054 CodeGenAndEmitDAG();
2056 if ((BTB.ContiguousRange || BTB.FallthroughUnreachable) && j + 2 == ej) {
2058 BTB.Cases.pop_back();
2064 for (
const std::pair<MachineInstr *, unsigned> &
P :
2069 "This is not a machine PHI node that we are updating!");
2072 if (PHIBB == BTB.Default) {
2073 PHI.addReg(
P.second).addMBB(BTB.Parent);
2074 if (!BTB.ContiguousRange) {
2075 PHI.addReg(
P.second).addMBB(BTB.Cases.back().ThisBB);
2082 PHI.addReg(
P.second).addMBB(cBB);
2086 SDB->SL->BitTestCases.clear();
2091 for (
unsigned i = 0, e =
SDB->SL->JTCases.size(); i != e; ++i) {
2093 if (!
SDB->SL->JTCases[i].first.Emitted) {
2095 FuncInfo->MBB =
SDB->SL->JTCases[i].first.HeaderBB;
2098 SDB->visitJumpTableHeader(
SDB->SL->JTCases[i].second,
2102 CodeGenAndEmitDAG();
2109 SDB->visitJumpTable(
SDB->SL->JTCases[i].second);
2112 CodeGenAndEmitDAG();
2115 for (
unsigned pi = 0, pe =
FuncInfo->PHINodesToUpdate.size();
2120 "This is not a machine PHI node that we are updating!");
2122 if (PHIBB ==
SDB->SL->JTCases[i].second.Default)
2124 .addMBB(
SDB->SL->JTCases[i].first.HeaderBB);
2126 if (
FuncInfo->MBB->isSuccessor(PHIBB))
2130 SDB->SL->JTCases.clear();
2134 for (
unsigned i = 0, e =
SDB->SL->SwitchCases.size(); i != e; ++i) {
2142 if (
SDB->SL->SwitchCases[i].TrueBB !=
SDB->SL->SwitchCases[i].FalseBB)
2149 CodeGenAndEmitDAG();
2170 for (
unsigned pn = 0; ; ++pn) {
2172 "Didn't find PHI entry!");
2173 if (
FuncInfo->PHINodesToUpdate[pn].first ==
PHI) {
2174 PHI.addReg(
FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
2182 SDB->SL->SwitchCases.clear();
2203 int64_t DesiredMaskS)
const {
2204 const APInt &ActualMask =
RHS->getAPIntValue();
2207 const APInt &DesiredMask =
APInt(
LHS.getValueSizeInBits(), DesiredMaskS,
2211 if (ActualMask == DesiredMask)
2220 APInt NeededMask = DesiredMask & ~ActualMask;
2235 int64_t DesiredMaskS)
const {
2236 const APInt &ActualMask =
RHS->getAPIntValue();
2239 const APInt &DesiredMask =
APInt(
LHS.getValueSizeInBits(), DesiredMaskS,
2243 if (ActualMask == DesiredMask)
2252 APInt NeededMask = DesiredMask & ~ActualMask;
2272 std::list<HandleSDNode> Handles;
2277 Handles.emplace_back(
2286 if (!Flags.isMemKind() && !Flags.isFuncKind()) {
2288 Handles.insert(Handles.end(), Ops.begin() + i,
2289 Ops.begin() + i + Flags.getNumOperandRegisters() + 1);
2290 i += Flags.getNumOperandRegisters() + 1;
2292 assert(Flags.getNumOperandRegisters() == 1 &&
2293 "Memory operand with multiple values?");
2295 unsigned TiedToOperand;
2296 if (Flags.isUseOperandTiedToDef(TiedToOperand)) {
2300 for (; TiedToOperand; --TiedToOperand) {
2301 CurOp += Flags.getNumOperandRegisters() + 1;
2307 std::vector<SDValue> SelOps;
2309 Flags.getMemoryConstraintID();
2318 Flags.setMemConstraint(ConstraintID);
2320 Handles.insert(Handles.end(), SelOps.begin(), SelOps.end());
2326 if (e != Ops.size())
2327 Handles.emplace_back(Ops.back());
2330 for (
auto &handle : Handles)
2331 Ops.push_back(handle.getValue());
2337 bool IgnoreChains) {
2346 Visited.
insert(ImmedUse);
2351 if ((
Op.getValueType() == MVT::Other && IgnoreChains) ||
N == Def)
2353 if (!Visited.
insert(
N).second)
2359 if (Root != ImmedUse) {
2363 if ((
Op.getValueType() == MVT::Other && IgnoreChains) ||
N == Def)
2365 if (!Visited.
insert(
N).second)
2380 return N.hasOneUse();
2387 bool IgnoreChains) {
2436 while (VT == MVT::Glue) {
2447 IgnoreChains =
false;
2453void SelectionDAGISel::Select_INLINEASM(
SDNode *
N) {
2456 std::vector<SDValue> Ops(
N->op_begin(),
N->op_end());
2459 const EVT VTs[] = {MVT::Other, MVT::Glue};
2466void SelectionDAGISel::Select_READ_REGISTER(
SDNode *
Op) {
2471 EVT VT =
Op->getValueType(0);
2477 Op->getOperand(0), dl, Reg,
Op->getValueType(0));
2483void SelectionDAGISel::Select_WRITE_REGISTER(
SDNode *
Op) {
2488 EVT VT =
Op->getOperand(2).getValueType();
2494 Op->getOperand(0), dl, Reg,
Op->getOperand(2));
2500void SelectionDAGISel::Select_UNDEF(
SDNode *
N) {
2506void SelectionDAGISel::Select_FAKE_USE(
SDNode *
N) {
2508 N->getOperand(1),
N->getOperand(0));
2511void SelectionDAGISel::Select_FREEZE(
SDNode *
N) {
2519void SelectionDAGISel::Select_ARITH_FENCE(
SDNode *
N) {
2524void SelectionDAGISel::Select_MEMBARRIER(
SDNode *
N) {
2529void SelectionDAGISel::Select_CONVERGENCECTRL_ANCHOR(
SDNode *
N) {
2531 N->getValueType(0));
2534void SelectionDAGISel::Select_CONVERGENCECTRL_ENTRY(
SDNode *
N) {
2536 N->getValueType(0));
2539void SelectionDAGISel::Select_CONVERGENCECTRL_LOOP(
SDNode *
N) {
2541 N->getValueType(0),
N->getOperand(0));
2562void SelectionDAGISel::Select_STACKMAP(
SDNode *
N) {
2564 auto *It =
N->op_begin();
2573 assert(
ID.getValueType() == MVT::i64);
2582 for (; It !=
N->op_end(); It++)
2583 pushStackMapLiveVariable(Ops, *It,
DL);
2592void SelectionDAGISel::Select_PATCHPOINT(
SDNode *
N) {
2594 auto *It =
N->op_begin();
2599 std::optional<SDValue> Glue;
2600 if (It->getValueType() == MVT::Glue)
2606 assert(
ID.getValueType() == MVT::i64);
2630 for (; It !=
N->op_end(); It++)
2631 pushStackMapLiveVariable(Ops, *It,
DL);
2636 if (Glue.has_value())
2646 assert(Val >= 128 &&
"Not a VBR");
2652 NextBits = MatcherTable[
Idx++];
2653 Val |= (NextBits&127) << Shift;
2655 }
while (NextBits & 128);
2663getSimpleVT(
const unsigned char *MatcherTable,
unsigned &MatcherIndex) {
2664 unsigned SimpleVT = MatcherTable[MatcherIndex++];
2666 SimpleVT =
GetVBR(SimpleVT, MatcherTable, MatcherIndex);
2671void SelectionDAGISel::Select_JUMP_TABLE_DEBUG_INFO(
SDNode *
N) {
2675 dl, MVT::i64,
true));
2680void SelectionDAGISel::UpdateChains(
2687 if (!ChainNodesMatched.
empty()) {
2689 "Matched input chains but didn't produce a chain");
2692 for (
unsigned i = 0, e = ChainNodesMatched.
size(); i != e; ++i) {
2693 SDNode *ChainNode = ChainNodesMatched[i];
2700 "Deleted node left in chain");
2704 if (ChainNode == NodeToMatch && isMorphNodeTo)
2713 std::replace(ChainNodesMatched.
begin(), ChainNodesMatched.
end(),
N,
2714 static_cast<SDNode *
>(
nullptr));
2720 if (ChainNode != NodeToMatch && ChainNode->
use_empty() &&
2726 if (!NowDeadNodes.
empty())
2745 unsigned int Max = 8192;
2748 if (ChainNodesMatched.
size() == 1)
2749 return ChainNodesMatched[0]->getOperand(0);
2753 std::function<void(
const SDValue)> AddChains = [&](
const SDValue V) {
2754 if (V.getValueType() != MVT::Other)
2758 if (!Visited.
insert(V.getNode()).second)
2761 for (
const SDValue &
Op : V->op_values())
2767 for (
auto *
N : ChainNodesMatched) {
2772 while (!Worklist.
empty())
2776 if (InputChains.
size() == 0)
2786 for (
auto *
N : ChainNodesMatched)
2791 if (InputChains.
size() == 1)
2792 return InputChains[0];
2794 MVT::Other, InputChains);
2798SDNode *SelectionDAGISel::
2807 int OldGlueResultNo = -1, OldChainResultNo = -1;
2809 unsigned NTMNumResults =
Node->getNumValues();
2810 if (
Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2811 OldGlueResultNo = NTMNumResults-1;
2812 if (NTMNumResults != 1 &&
2813 Node->getValueType(NTMNumResults-2) == MVT::Other)
2814 OldChainResultNo = NTMNumResults-2;
2815 }
else if (
Node->getValueType(NTMNumResults-1) == MVT::Other)
2816 OldChainResultNo = NTMNumResults-1;
2834 static_cast<unsigned>(OldGlueResultNo) != ResNumResults - 1)
2836 SDValue(Res, ResNumResults - 1));
2842 if ((EmitNodeInfo &
OPFL_Chain) && OldChainResultNo != -1 &&
2843 static_cast<unsigned>(OldChainResultNo) != ResNumResults - 1)
2845 SDValue(Res, ResNumResults - 1));
2863 unsigned RecNo = MatcherTable[MatcherIndex++];
2864 assert(RecNo < RecordedNodes.size() &&
"Invalid CheckSame");
2865 return N == RecordedNodes[RecNo].first;
2870 const unsigned char *MatcherTable,
unsigned &MatcherIndex,
SDValue N,
2873 if (ChildNo >=
N.getNumOperands())
2875 return ::CheckSame(MatcherTable, MatcherIndex,
N.getOperand(ChildNo),
2883 bool TwoBytePredNo =
2887 ? MatcherTable[MatcherIndex++]
2890 PredNo |= MatcherTable[MatcherIndex++] << 8;
2900 ? MatcherTable[MatcherIndex++]
2908 uint16_t Opc = MatcherTable[MatcherIndex++];
2909 Opc |=
static_cast<uint16_t>(MatcherTable[MatcherIndex++]) << 8;
2910 return N->getOpcode() == Opc;
2917 if (
N.getValueType() == VT)
2927 if (ChildNo >=
N.getNumOperands())
2929 return ::CheckType(VT,
N.getOperand(ChildNo), TLI,
DL);
2935 return cast<CondCodeSDNode>(
N)->get() ==
2942 if (2 >=
N.getNumOperands())
2944 return ::CheckCondCode(MatcherTable, MatcherIndex,
N.getOperand(2));
2951 if (cast<VTSDNode>(
N)->getVT() == VT)
2955 return VT == MVT::iPTR && cast<VTSDNode>(
N)->getVT() == TLI->
getPointerTy(
DL);
2972 int64_t Val = MatcherTable[MatcherIndex++];
2974 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
2979 return C &&
C->getAPIntValue().trySExtValue() == Val;
2985 if (ChildNo >=
N.getNumOperands())
2987 return ::CheckInteger(MatcherTable, MatcherIndex,
N.getOperand(ChildNo));
2993 int64_t Val = MatcherTable[MatcherIndex++];
2995 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
2997 if (
N->getOpcode() !=
ISD::AND)
return false;
3006 int64_t Val = MatcherTable[MatcherIndex++];
3008 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
3010 if (
N->getOpcode() !=
ISD::OR)
return false;
3027 unsigned Opcode = Table[Index++];
3087 unsigned Res = Table[Index++];
3174 unsigned NumRecordedNodes;
3177 unsigned NumMatchedMemRefs;
3180 SDValue InputChain, InputGlue;
3183 bool HasChainNodesMatched;
3200 :
SelectionDAG::DAGUpdateListener(DAG), NodeToMatch(NodeToMatch),
3201 RecordedNodes(
RN), MatchScopes(MS) {}
3209 if (!
E ||
E->isMachineOpcode())
3212 if (
N == *NodeToMatch)
3217 for (
auto &
I : RecordedNodes)
3218 if (
I.first.getNode() ==
N)
3221 for (
auto &
I : MatchScopes)
3222 for (
auto &J :
I.NodeStack)
3223 if (J.getNode() ==
N)
3231 const unsigned char *MatcherTable,
3232 unsigned TableSize) {
3271 Select_INLINEASM(NodeToMatch);
3274 Select_READ_REGISTER(NodeToMatch);
3277 Select_WRITE_REGISTER(NodeToMatch);
3280 Select_UNDEF(NodeToMatch);
3283 Select_FAKE_USE(NodeToMatch);
3286 Select_FREEZE(NodeToMatch);
3289 Select_ARITH_FENCE(NodeToMatch);
3292 Select_MEMBARRIER(NodeToMatch);
3295 Select_STACKMAP(NodeToMatch);
3298 Select_PATCHPOINT(NodeToMatch);
3301 Select_JUMP_TABLE_DEBUG_INFO(NodeToMatch);
3304 Select_CONVERGENCECTRL_ANCHOR(NodeToMatch);
3307 Select_CONVERGENCECTRL_ENTRY(NodeToMatch);
3310 Select_CONVERGENCECTRL_LOOP(NodeToMatch);
3337 SDValue InputChain, InputGlue;
3351 unsigned MatcherIndex = 0;
3353 if (!OpcodeOffset.empty()) {
3355 if (
N.getOpcode() < OpcodeOffset.size())
3356 MatcherIndex = OpcodeOffset[
N.getOpcode()];
3357 LLVM_DEBUG(
dbgs() <<
" Initial Opcode index to " << MatcherIndex <<
"\n");
3366 unsigned CaseSize = MatcherTable[
Idx++];
3368 CaseSize =
GetVBR(CaseSize, MatcherTable,
Idx);
3369 if (CaseSize == 0)
break;
3373 Opc |=
static_cast<uint16_t>(MatcherTable[
Idx++]) << 8;
3374 if (Opc >= OpcodeOffset.size())
3375 OpcodeOffset.resize((Opc+1)*2);
3376 OpcodeOffset[Opc] =
Idx;
3381 if (
N.getOpcode() < OpcodeOffset.size())
3382 MatcherIndex = OpcodeOffset[
N.getOpcode()];
3386 assert(MatcherIndex < TableSize &&
"Invalid index");
3388 unsigned CurrentOpcodeIndex = MatcherIndex;
3402 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3403 if (NumToSkip & 128)
3404 NumToSkip =
GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3406 if (NumToSkip == 0) {
3411 FailIndex = MatcherIndex+NumToSkip;
3413 unsigned MatcherIndexOfPredicate = MatcherIndex;
3414 (void)MatcherIndexOfPredicate;
3421 Result, *
this, RecordedNodes);
3426 dbgs() <<
" Skipped scope entry (due to false predicate) at "
3427 <<
"index " << MatcherIndexOfPredicate <<
", continuing at "
3428 << FailIndex <<
"\n");
3429 ++NumDAGIselRetries;
3433 MatcherIndex = FailIndex;
3437 if (FailIndex == 0)
break;
3441 MatchScope NewEntry;
3442 NewEntry.FailIndex = FailIndex;
3443 NewEntry.NodeStack.append(NodeStack.
begin(), NodeStack.
end());
3444 NewEntry.NumRecordedNodes = RecordedNodes.
size();
3445 NewEntry.NumMatchedMemRefs = MatchedMemRefs.
size();
3446 NewEntry.InputChain = InputChain;
3447 NewEntry.InputGlue = InputGlue;
3448 NewEntry.HasChainNodesMatched = !ChainNodesMatched.
empty();
3454 SDNode *Parent =
nullptr;
3455 if (NodeStack.
size() > 1)
3456 Parent = NodeStack[NodeStack.
size()-2].getNode();
3457 RecordedNodes.
push_back(std::make_pair(
N, Parent));
3466 if (ChildNo >=
N.getNumOperands())
3469 RecordedNodes.
push_back(std::make_pair(
N->getOperand(ChildNo),
3474 if (
auto *MN = dyn_cast<MemSDNode>(
N))
3475 MatchedMemRefs.
push_back(MN->getMemOperand());
3485 if (
N->getNumOperands() != 0 &&
3486 N->getOperand(
N->getNumOperands()-1).getValueType() == MVT::Glue)
3487 InputGlue =
N->getOperand(
N->getNumOperands()-1);
3491 unsigned ChildNo = MatcherTable[MatcherIndex++];
3492 if (ChildNo >=
N.getNumOperands())
3494 N =
N.getOperand(ChildNo);
3504 if (ChildNo >=
N.getNumOperands())
3506 N =
N.getOperand(ChildNo);
3522 assert(!NodeStack.
empty() &&
"Node stack imbalance!");
3523 N = NodeStack.
back();
3526 ? MatcherTable[MatcherIndex++]
3528 if (SiblingNo >=
N.getNumOperands())
3530 N =
N.getOperand(SiblingNo);
3537 assert(!NodeStack.
empty() &&
"Node stack imbalance!");
3538 N = NodeStack.
back();
3542 if (!
::CheckSame(MatcherTable, MatcherIndex,
N, RecordedNodes))
break;
3579 unsigned OpNum = MatcherTable[MatcherIndex++];
3582 for (
unsigned i = 0; i < OpNum; ++i)
3583 Operands.push_back(RecordedNodes[MatcherTable[MatcherIndex++]].first);
3585 unsigned PredNo = MatcherTable[MatcherIndex++];
3600 ? MatcherTable[MatcherIndex++]
3602 unsigned RecNo = MatcherTable[MatcherIndex++];
3603 assert(RecNo < RecordedNodes.
size() &&
"Invalid CheckComplexPat");
3607 std::unique_ptr<MatchStateUpdater> MSU;
3609 MSU.reset(
new MatchStateUpdater(*
CurDAG, &NodeToMatch, RecordedNodes,
3613 RecordedNodes[RecNo].first, CPNum,
3619 if (!
::CheckOpcode(MatcherTable, MatcherIndex,
N.getNode()))
break;
3642 unsigned Res = MatcherTable[MatcherIndex++];
3650 unsigned CurNodeOpcode =
N.getOpcode();
3651 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
3655 CaseSize = MatcherTable[MatcherIndex++];
3657 CaseSize =
GetVBR(CaseSize, MatcherTable, MatcherIndex);
3658 if (CaseSize == 0)
break;
3660 uint16_t Opc = MatcherTable[MatcherIndex++];
3661 Opc |=
static_cast<uint16_t>(MatcherTable[MatcherIndex++]) << 8;
3664 if (CurNodeOpcode == Opc)
3668 MatcherIndex += CaseSize;
3672 if (CaseSize == 0)
break;
3675 LLVM_DEBUG(
dbgs() <<
" OpcodeSwitch from " << SwitchStart <<
" to "
3676 << MatcherIndex <<
"\n");
3681 MVT CurNodeVT =
N.getSimpleValueType();
3682 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
3686 CaseSize = MatcherTable[MatcherIndex++];
3688 CaseSize =
GetVBR(CaseSize, MatcherTable, MatcherIndex);
3689 if (CaseSize == 0)
break;
3692 if (CaseVT == MVT::iPTR)
3696 if (CurNodeVT == CaseVT)
3700 MatcherIndex += CaseSize;
3704 if (CaseSize == 0)
break;
3708 <<
"] from " << SwitchStart <<
" to " << MatcherIndex
3778 if (!
::CheckOrImm(MatcherTable, MatcherIndex,
N, *
this))
break;
3790 assert(NodeStack.
size() != 1 &&
"No parent node");
3793 bool HasMultipleUses =
false;
3794 for (
unsigned i = 1, e = NodeStack.
size()-1; i != e; ++i) {
3795 unsigned NNonChainUses = 0;
3796 SDNode *NS = NodeStack[i].getNode();
3798 if (U.getValueType() != MVT::Other)
3799 if (++NNonChainUses > 1) {
3800 HasMultipleUses =
true;
3803 if (HasMultipleUses)
break;
3805 if (HasMultipleUses)
break;
3844 int64_t Val = MatcherTable[MatcherIndex++];
3846 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
3849 RecordedNodes.
push_back(std::pair<SDValue, SDNode *>(
3870 unsigned RegNo = MatcherTable[MatcherIndex++];
3871 RecordedNodes.
push_back(std::pair<SDValue, SDNode *>(
3880 unsigned RegNo = MatcherTable[MatcherIndex++];
3881 RegNo |= MatcherTable[MatcherIndex++] << 8;
3882 RecordedNodes.
push_back(std::pair<SDValue, SDNode*>(
3898 ? MatcherTable[MatcherIndex++]
3900 assert(RecNo < RecordedNodes.
size() &&
"Invalid EmitConvertToTarget");
3901 SDValue Imm = RecordedNodes[RecNo].first;
3904 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
3906 Imm.getValueType());
3908 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
3910 Imm.getValueType());
3913 RecordedNodes.
push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
3922 "EmitMergeInputChains should be the first chain producing node");
3924 "Should only have one EmitMergeInputChains per match");
3928 assert(RecNo < RecordedNodes.
size() &&
"Invalid EmitMergeInputChains");
3929 ChainNodesMatched.
push_back(RecordedNodes[RecNo].first.getNode());
3935 if (ChainNodesMatched.
back() != NodeToMatch &&
3936 !RecordedNodes[RecNo].first.hasOneUse()) {
3937 ChainNodesMatched.
clear();
3951 "EmitMergeInputChains should be the first chain producing node");
3958 unsigned NumChains = MatcherTable[MatcherIndex++];
3959 assert(NumChains != 0 &&
"Can't TF zero chains");
3962 "Should only have one EmitMergeInputChains per match");
3965 for (
unsigned i = 0; i != NumChains; ++i) {
3966 unsigned RecNo = MatcherTable[MatcherIndex++];
3967 assert(RecNo < RecordedNodes.
size() &&
"Invalid EmitMergeInputChains");
3968 ChainNodesMatched.
push_back(RecordedNodes[RecNo].first.getNode());
3974 if (ChainNodesMatched.
back() != NodeToMatch &&
3975 !RecordedNodes[RecNo].first.hasOneUse()) {
3976 ChainNodesMatched.
clear();
3982 if (ChainNodesMatched.
empty())
4007 : MatcherTable[MatcherIndex++];
4008 assert(RecNo < RecordedNodes.
size() &&
"Invalid EmitCopyToReg");
4009 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
4011 DestPhysReg |= MatcherTable[MatcherIndex++] << 8;
4017 DestPhysReg, RecordedNodes[RecNo].first,
4020 InputGlue = InputChain.
getValue(1);
4025 unsigned XFormNo = MatcherTable[MatcherIndex++];
4026 unsigned RecNo = MatcherTable[MatcherIndex++];
4027 assert(RecNo < RecordedNodes.
size() &&
"Invalid EmitNodeXForm");
4029 RecordedNodes.
push_back(std::pair<SDValue,SDNode*>(Res,
nullptr));
4035 unsigned index = MatcherTable[MatcherIndex++];
4036 index |= (MatcherTable[MatcherIndex++] << 8);
4037 index |= (MatcherTable[MatcherIndex++] << 16);
4038 index |= (MatcherTable[MatcherIndex++] << 24);
4070 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
4071 TargetOpc |=
static_cast<uint16_t>(MatcherTable[MatcherIndex++]) << 8;
4072 unsigned EmitNodeInfo;
4091 EmitNodeInfo = MatcherTable[MatcherIndex++];
4116 NumVTs = MatcherTable[MatcherIndex++];
4118 for (
unsigned i = 0; i != NumVTs; ++i) {
4120 if (VT == MVT::iPTR)
4133 if (VTs.
size() == 1)
4135 else if (VTs.
size() == 2)
4141 unsigned NumOps = MatcherTable[MatcherIndex++];
4143 for (
unsigned i = 0; i != NumOps; ++i) {
4144 unsigned RecNo = MatcherTable[MatcherIndex++];
4146 RecNo =
GetVBR(RecNo, MatcherTable, MatcherIndex);
4148 assert(RecNo < RecordedNodes.
size() &&
"Invalid EmitNode");
4149 Ops.
push_back(RecordedNodes[RecNo].first);
4156 FirstOpToCopy += (EmitNodeInfo &
OPFL_Chain) ? 1 : 0;
4158 "Invalid variadic node");
4161 for (
unsigned i = FirstOpToCopy, e = NodeToMatch->
getNumOperands();
4164 if (V.getValueType() == MVT::Glue)
break;
4179 bool MayRaiseFPException =
4186 bool IsMorphNodeTo =
4189 if (!IsMorphNodeTo) {
4196 for (
unsigned i = 0, e = VTs.
size(); i != e; ++i) {
4197 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue)
break;
4203 "NodeToMatch was removed partway through selection");
4207 auto &Chain = ChainNodesMatched;
4209 "Chain node replaced during MorphNode");
4212 Res = cast<MachineSDNode>(MorphNode(NodeToMatch, TargetOpc, VTList,
4213 Ops, EmitNodeInfo));
4240 bool mayLoad = MCID.
mayLoad();
4247 if (MMO->isLoad()) {
4250 }
else if (MMO->isStore()) {
4262 if (!MatchedMemRefs.
empty() && Res->memoperands_empty())
4263 dbgs() <<
" Dropping mem operands\n";
4264 dbgs() <<
" " << (IsMorphNodeTo ?
"Morphed" :
"Created") <<
" node: ";
4269 if (IsMorphNodeTo) {
4271 UpdateChains(Res, InputChain, ChainNodesMatched,
true);
4281 unsigned NumResults = MatcherTable[MatcherIndex++];
4283 for (
unsigned i = 0; i != NumResults; ++i) {
4284 unsigned ResSlot = MatcherTable[MatcherIndex++];
4286 ResSlot =
GetVBR(ResSlot, MatcherTable, MatcherIndex);
4288 assert(ResSlot < RecordedNodes.
size() &&
"Invalid CompleteMatch");
4289 SDValue Res = RecordedNodes[ResSlot].first;
4291 assert(i < NodeToMatch->getNumValues() &&
4294 "Invalid number of results to complete!");
4300 "invalid replacement");
4305 UpdateChains(NodeToMatch, InputChain, ChainNodesMatched,
false);
4318 "Didn't replace all uses of the node?");
4328 LLVM_DEBUG(
dbgs() <<
" Match failed at index " << CurrentOpcodeIndex
4330 ++NumDAGIselRetries;
4332 if (MatchScopes.
empty()) {
4333 CannotYetSelect(NodeToMatch);
4339 MatchScope &LastScope = MatchScopes.
back();
4340 RecordedNodes.
resize(LastScope.NumRecordedNodes);
4342 NodeStack.
append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
4343 N = NodeStack.
back();
4345 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.
size())
4346 MatchedMemRefs.
resize(LastScope.NumMatchedMemRefs);
4347 MatcherIndex = LastScope.FailIndex;
4351 InputChain = LastScope.InputChain;
4352 InputGlue = LastScope.InputGlue;
4353 if (!LastScope.HasChainNodesMatched)
4354 ChainNodesMatched.
clear();
4359 unsigned NumToSkip = MatcherTable[MatcherIndex++];
4360 if (NumToSkip & 128)
4361 NumToSkip =
GetVBR(NumToSkip, MatcherTable, MatcherIndex);
4365 if (NumToSkip != 0) {
4366 LastScope.FailIndex = MatcherIndex+NumToSkip;
4380 if (
N->isMachineOpcode()) {
4387 if (
N->isTargetOpcode()) {
4391 return N->isStrictFPOpcode();
4396 auto *
C = dyn_cast<ConstantSDNode>(
N->getOperand(1));
4401 if (
auto *FN = dyn_cast<FrameIndexSDNode>(
N->getOperand(0))) {
4404 int32_t Off =
C->getSExtValue();
4407 return (Off >= 0) && (((
A.value() - 1) & Off) ==
unsigned(Off));
4412void SelectionDAGISel::CannotYetSelect(
SDNode *
N) {
4415 Msg <<
"Cannot select: ";
4421 Msg <<
"\nIn function: " <<
MF->
getName();
4423 bool HasInputChain =
N->getOperand(0).getValueType() == MVT::Other;
4424 unsigned iid =
N->getConstantOperandVal(HasInputChain);
4425 if (iid < Intrinsic::num_intrinsics)
4428 Msg <<
"target intrinsic %" <<
TII->
getName(iid);
4430 Msg <<
"unknown intrinsic #" << iid;
unsigned const MachineRegisterInfo * MRI
for(const MachineOperand &MO :llvm::drop_begin(OldMI.operands(), Desc.getNumOperands()))
MachineInstrBuilder & UseMI
AMDGPU Register Bank Select
This file implements a class to represent arbitrary precision integral constant values and operations...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Expand Atomic instructions
BlockVerifier::State From
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_ATTRIBUTE_ALWAYS_INLINE
LLVM_ATTRIBUTE_ALWAYS_INLINE - On compilers where we have a directive to do so, mark a method "always...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
This file defines the FastISel class.
Module.h This file contains the declarations for the Module class.
mir Rename Register Operands
Machine Instruction Scheduler
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
FunctionAnalysisManager FAM
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static Type * getValueType(Value *V)
Returns the type of the given value/instruction V.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const TargetLowering *TLI, const DataLayout &DL)
static cl::opt< bool > ViewSUnitDAGs("view-sunit-dags", cl::Hidden, cl::desc("Pop up a window to show SUnit dags after they are processed"))
static cl::opt< bool > ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the post " "legalize types dag combine pass"))
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckPatternPredicate(unsigned Opcode, const unsigned char *MatcherTable, unsigned &MatcherIndex, const SelectionDAGISel &SDISel)
CheckPatternPredicate - Implements OP_CheckPatternPredicate.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SmallVectorImpl< std::pair< SDValue, SDNode * > > &RecordedNodes, unsigned ChildNo)
CheckChildSame - Implements OP_CheckChildXSame.
static uint64_t decodeSignRotatedValue(uint64_t V)
Decode a signed value stored with the sign bit in the LSB for dense VBR encoding.
static cl::opt< bool > ViewISelDAGs("view-isel-dags", cl::Hidden, cl::desc("Pop up a window to show isel dags as they are selected"))
static LLVM_ATTRIBUTE_ALWAYS_INLINE uint64_t GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx)
GetVBR - decode a vbr encoding whose top bit is set.
static void reportFastISelFailure(MachineFunction &MF, OptimizationRemarkEmitter &ORE, OptimizationRemarkMissed &R, bool ShouldAbort)
static cl::opt< bool > ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the second " "dag combine pass"))
static RegisterScheduler defaultListDAGScheduler("default", "Best scheduler for the target", createDefaultScheduler)
static unsigned IsPredicateKnownToFail(const unsigned char *Table, unsigned Index, SDValue N, bool &Result, const SelectionDAGISel &SDISel, SmallVectorImpl< std::pair< SDValue, SDNode * > > &RecordedNodes)
IsPredicateKnownToFail - If we know how and can do so without pushing a scope, evaluate the current n...
static cl::opt< int > EnableFastISelAbort("fast-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"fast\" instruction selection " "fails to lower an instruction: 0 disable the abort, 1 will " "abort but for args, calls and terminators, 2 will also " "abort for argument lowering, and 3 will never fallback " "to SelectionDAG."))
static void mapWasmLandingPadIndex(MachineBasicBlock *MBB, const CatchPadInst *CPI)
static void processSingleLocVars(FunctionLoweringInfo &FuncInfo, FunctionVarLocs const *FnVarLocs)
Collect single location variable information generated with assignment tracking.
static LLVM_ATTRIBUTE_ALWAYS_INLINE MVT::SimpleValueType getSimpleVT(const unsigned char *MatcherTable, unsigned &MatcherIndex)
getSimpleVT - Decode a value in MatcherTable, if it's a VBR encoded value, use GetVBR to decode it.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SelectionDAGISel &SDISel)
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SelectionDAGISel &SDISel)
static cl::opt< bool > UseMBPI("use-mbpi", cl::desc("use Machine Branch Probability Info"), cl::init(true), cl::Hidden)
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChildType(MVT::SimpleValueType VT, SDValue N, const TargetLowering *TLI, const DataLayout &DL, unsigned ChildNo)
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SmallVectorImpl< std::pair< SDValue, SDNode * > > &RecordedNodes)
CheckSame - Implements OP_CheckSame.
static bool dontUseFastISelFor(const Function &Fn)
static bool findNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse, bool IgnoreChains)
findNonImmUse - Return true if "Def" is a predecessor of "Root" via a path beyond "ImmedUse".
static cl::opt< bool > ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the first " "dag combine pass"))
static bool processIfEntryValueDbgDeclare(FunctionLoweringInfo &FuncInfo, const Value *Arg, DIExpression *Expr, DILocalVariable *Var, DebugLoc DbgLoc)
static cl::opt< bool > ViewSchedDAGs("view-sched-dags", cl::Hidden, cl::desc("Pop up a window to show sched dags as they are processed"))
static void processDbgDeclares(FunctionLoweringInfo &FuncInfo)
Collect llvm.dbg.declare information.
static void preserveFakeUses(BasicBlock::iterator Begin, BasicBlock::iterator End)
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckType(MVT::SimpleValueType VT, SDValue N, const TargetLowering *TLI, const DataLayout &DL)
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)
static bool hasExceptionPointerOrCodeUser(const CatchPadInst *CPI)
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChild2CondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)
static cl::opt< bool > ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, cl::desc("Pop up a window to show dags before legalize"))
static cl::opt< bool > ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, cl::desc("Pop up a window to show dags before legalize types"))
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckNodePredicate(unsigned Opcode, const unsigned char *MatcherTable, unsigned &MatcherIndex, const SelectionDAGISel &SDISel, SDNode *N)
CheckNodePredicate - Implements OP_CheckNodePredicate.
static cl::opt< RegisterScheduler::FunctionPassCtor, false, RegisterPassParser< RegisterScheduler > > ISHeuristic("pre-RA-sched", cl::init(&createDefaultScheduler), cl::Hidden, cl::desc("Instruction schedulers available (before register" " allocation):"))
ISHeuristic command line option for instruction schedulers.
static cl::opt< bool > EnableFastISelFallbackReport("fast-isel-report-on-fallback", cl::Hidden, cl::desc("Emit a diagnostic when \"fast\" instruction selection " "falls back to SelectionDAG."))
static bool processDbgDeclare(FunctionLoweringInfo &FuncInfo, const Value *Address, DIExpression *Expr, DILocalVariable *Var, DebugLoc DbgLoc)
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDNode *N)
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, unsigned ChildNo)
static cl::opt< std::string > FilterDAGBasicBlockName("filter-view-dags", cl::Hidden, cl::desc("Only display the basic block whose name " "matches this for all view-*-dags options"))
static SDValue HandleMergeInputChains(SmallVectorImpl< SDNode * > &ChainNodesMatched, SelectionDAG *CurDAG)
HandleMergeInputChains - This implements the OPC_EmitMergeInputChains operation for when the pattern ...
static bool isFoldedOrDeadInstruction(const Instruction *I, const FunctionLoweringInfo &FuncInfo)
isFoldedOrDeadInstruction - Return true if the specified instruction is side-effect free and is eithe...
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
This file describes how to lower LLVM code to machine code.
DEMANGLE_DUMP_METHOD void dump() const
A manager for alias analyses.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
AAResults & getAAResults()
Class for arbitrary precision integers.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
A container for analyses that lazily runs them and caches their results.
PassT::Result * getCachedResult(IRUnitT &IR) const
Get the cached result of an analysis pass for a given IR unit.
PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)
Get the result of an analysis pass for a given IR unit.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
A function analysis which provides an AssumptionCache.
An immutable pass that tracks lazily created AssumptionCache objects.
LLVM Basic Block Representation.
unsigned getNumber() const
iterator_range< const_phi_iterator > phis() const
Returns a range that iterates over the phis in the basic block.
InstListType::const_iterator getFirstNonPHIIt() const
Returns an iterator to the first instruction in this block that is not a PHINode instruction.
InstListType::const_iterator const_iterator
InstListType::iterator iterator
Instruction iterators...
bool isEHPad() const
Return true if this basic block is an exception handling block.
const Instruction * getFirstMayFaultInst() const
Returns the first potential AsynchEH faulty instruction currently it checks for loads/stores (which m...
Analysis pass which computes BlockFrequencyInfo.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Analysis pass which computes BranchProbabilityInfo.
Legacy analysis pass which computes BranchProbabilityInfo.
This class represents a function call, abstracting a target machine's calling convention.
ConstantFP - Floating Point Values [float, double].
This is the shared class of boolean and integer constants.
This is an important base class in LLVM.
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
static DIExpression * append(const DIExpression *Expr, ArrayRef< uint64_t > Ops)
Append the opcodes Ops to DIExpr.
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Record of a variable value-assignment, aka a non instruction representation of the dbg....
iterator find(const_arg_type_t< KeyT > Val)
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Diagnostic information for ISel fallback path.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
void setLastLocalValue(MachineInstr *I)
Update the position of the last instruction emitted for materializing constants for use in the curren...
void handleDbgInfo(const Instruction *II)
Target-independent lowering of non-instruction debug info associated with this instruction.
bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst)
We're checking to see if we can fold LI into FoldInst.
void removeDeadCode(MachineBasicBlock::iterator I, MachineBasicBlock::iterator E)
Remove all dead instructions between the I and E.
void startNewBlock()
Set the current block to which generated machine instructions will be appended.
bool selectInstruction(const Instruction *I)
Do "fast" instruction selection for the given LLVM IR instruction and append the generated machine in...
void finishBasicBlock()
Flush the local value map.
void recomputeInsertPt()
Reset InsertPt to prepare for inserting instructions into the current block.
bool lowerArguments()
Do "fast" instruction selection for function arguments and append the machine instructions to the cur...
unsigned arg_size() const
arg_size - Return the number of funcletpad arguments.
Value * getArgOperand(unsigned i) const
getArgOperand/setArgOperand - Return/set the i-th funcletpad argument.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
SmallPtrSet< const DbgVariableRecord *, 8 > PreprocessedDVRDeclares
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block.
int getArgumentFrameIndex(const Argument *A)
getArgumentFrameIndex - Get frame index for the byval argument.
bool isExportedInst(const Value *V) const
isExportedInst - Return true if the specified value is an instruction exported from its block.
SmallPtrSet< const DbgDeclareInst *, 8 > PreprocessedDbgDeclares
Collection of dbg.declare instructions handled after argument lowering and before ISel proper.
DenseMap< const Value *, Register > ValueMap
ValueMap - Since we emit code for the function a basic block at a time, we must remember which virtua...
MachineRegisterInfo * RegInfo
bool skipFunction(const Function &F) const
Optional passes call this function to check whether the pass should be skipped.
Data structure describing the variable locations in a function.
const VarLocInfo * single_locs_begin() const
DILocalVariable * getDILocalVariable(const VarLocInfo *Loc) const
Return the DILocalVariable for the location definition represented by ID.
const VarLocInfo * single_locs_end() const
One past the last single-location variable location definition.
const BasicBlock & getEntryBlock() const
FunctionType * getFunctionType() const
Returns the FunctionType for me.
unsigned getMaxBlockNumber() const
Return a value larger than the largest block number.
iterator_range< arg_iterator > args()
DISubprogram * getSubprogram() const
Get the attached subprogram.
bool hasGC() const
hasGC/getGC/setGC/clearGC - The name of the garbage collection algorithm to use during code generatio...
bool hasOptNone() const
Do not optimize this function (-O0).
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
An analysis pass which caches information about the Function.
An analysis pass which caches information about the entire Module.
Module * getParent()
Get the module that this global value is contained inside of...
This class is used to form a handle around another node that is persistent and is updated across invo...
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
bool isTerminator() const
A wrapper class for inspecting calls to intrinsic functions.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
This is an alternative analysis pass to BlockFrequencyInfoWrapperPass.
static void getLazyBFIAnalysisUsage(AnalysisUsage &AU)
Helper for client passes to set up the analysis usage on behalf of this pass.
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Describe properties that are true of each instruction in the target description file.
bool mayStore() const
Return true if this instruction could possibly modify memory.
bool mayLoad() const
Return true if this instruction could possibly read memory.
bool mayRaiseFPException() const
Return true if this instruction may raise a floating-point exception.
bool isCall() const
Return true if the instruction is a call.
bool isReturn() const
Return true if the instruction is a return.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
const MDNode * getMD() const
const MDOperand & getOperand(unsigned I) const
StringRef getString() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
instr_iterator instr_end()
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator insertAfter(iterator I, MachineInstr *MI)
Insert MI into the instruction list after I.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasCalls() const
Return true if the current function has any function calls.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool hasProperty(Property P) const
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling.
bool useDebugInstrRef() const
Returns true if the function's variable locations are tracked with instruction referencing.
void setHasInlineAsm(bool B)
Set a flag that indicates that the function contains inline assembly.
void setWasmLandingPadIndex(const MachineBasicBlock *LPad, unsigned Index)
Map the landing pad to its index. Used for Wasm exception handling.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void finalizeDebugInstrRefs()
Finalise any partially emitted debug instructions.
void setCallSiteLandingPad(MCSymbol *Sym, ArrayRef< unsigned > Sites)
Map the landing pad's EH symbol to the call site indexes.
void setUseDebugInstrRef(bool UseInstrRef)
Set whether this function will use instruction referencing or not.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
MCSymbol * addLandingPad(MachineBasicBlock *LandingPad)
Add a new panding pad, and extract the exception handling information from the landingpad instruction...
Function & getFunction()
Return the LLVM function that this machine code represents.
bool shouldUseDebugInstrRef() const
Determine whether, in the current machine configuration, we should use instruction referencing or not...
const MachineFunctionProperties & getProperties() const
Get the function properties.
void setVariableDbgInfo(const DILocalVariable *Var, const DIExpression *Expr, int Slot, const DILocation *Loc)
Collect information used to emit debugging information of a variable in a stack slot.
const MachineBasicBlock & front() const
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
const MachineOperand & getOperand(unsigned i) const
A description of a memory reference used in the backend.
An analysis that produces MachineModuleInfo for a module.
This class contains meta information specific to a module.
Register getReg() const
getReg - Returns the register number.
MachinePassRegistry - Track the registration of machine passes.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
ArrayRef< std::pair< MCRegister, Register > > liveins() const
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
An SDNode that represents everything that will be needed to construct a MachineInstr.
Metadata * getModuleFlag(StringRef Key) const
Return the corresponding value if Key appears in module flags, otherwise return null.
This class is used by SelectionDAGISel to temporarily override the optimization level on a per-functi...
OptLevelChanger(SelectionDAGISel &ISel, CodeGenOptLevel NewOptLevel)
An analysis over an "inner" IR unit that provides access to an analysis manager over a "outer" IR uni...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
AnalysisType & getAnalysis() const
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information ...
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
A set of analyses that are preserved following a run of a transformation pass.
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
An analysis pass based on the new PM to deliver ProfileSummaryInfo.
An analysis pass based on legacy pass manager to deliver ProfileSummaryInfo.
RegisterPassParser class - Handle the addition of new machine passes.
ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOptLevel) FunctionPassCtor
static MachinePassRegistry< FunctionPassCtor > Registry
RegisterScheduler class - Track the registration of instruction schedulers.
Wrapper class representing virtual and physical registers.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SDNode * getGluedUser() const
If this node has a glue value with a user, return the user (there is at most one).
bool isOnlyUserOf(const SDNode *N) const
Return true if this node is the only use of N.
iterator_range< value_op_iterator > op_values() const
iterator_range< use_iterator > uses()
void setNodeId(int Id)
Set unique node id.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallVectorImpl< const SDNode * > &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
bool use_empty() const
Return true if there are no uses of this node.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
unsigned getNumOperands() const
Return the number of values used by this operation.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Represents a use of a SDNode.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
void copyToMachineFrameInfo(MachineFrameInfo &MFI) const
bool shouldEmitSDCheck(const BasicBlock &BB) const
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
SelectionDAGISelLegacy(char &ID, std::unique_ptr< SelectionDAGISel > S)
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
std::optional< BatchAAResults > BatchAA
std::unique_ptr< FunctionLoweringInfo > FuncInfo
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps)
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckOrMask - The isel is trying to match something like (or X, 255).
void initializeAnalysisResults(MachineFunctionAnalysisManager &MFAM)
const TargetLowering * TLI
virtual void PostprocessISelDAG()
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const
CheckNodePredicate - This function is generated by tblgen in the target.
std::unique_ptr< OptimizationRemarkEmitter > ORE
Current optimization remark emitter.
MachineRegisterInfo * RegInfo
unsigned DAGSize
DAGSize - Size of DAG being instruction selected.
@ OPC_MorphNodeTo2GlueOutput
@ OPC_CheckPatternPredicate5
@ OPC_EmitCopyToRegTwoByte
@ OPC_MorphNodeTo2GlueInput
@ OPC_CheckChild2CondCode
@ OPC_CheckPatternPredicateTwoByte
@ OPC_CheckPatternPredicate1
@ OPC_MorphNodeTo1GlueOutput
@ OPC_EmitMergeInputChains1_1
@ OPC_CheckPatternPredicate2
@ OPC_EmitConvertToTarget2
@ OPC_EmitConvertToTarget0
@ OPC_CheckPatternPredicate4
@ OPC_EmitConvertToTarget1
@ OPC_CheckPatternPredicate
@ OPC_MorphNodeTo0GlueInput
@ OPC_CheckPatternPredicate6
@ OPC_MorphNodeTo0GlueOutput
@ OPC_CheckPatternPredicate7
@ OPC_EmitMergeInputChains
@ OPC_EmitMergeInputChains1_0
@ OPC_CheckFoldableChainNode
@ OPC_EmitConvertToTarget3
@ OPC_CheckPredicateWithOperands
@ OPC_EmitConvertToTarget4
@ OPC_EmitStringInteger32
@ OPC_EmitConvertToTarget7
@ OPC_EmitMergeInputChains1_2
@ OPC_EmitConvertToTarget5
@ OPC_CheckPatternPredicate0
@ OPC_MorphNodeTo1GlueInput
@ OPC_CheckPatternPredicate3
@ OPC_EmitConvertToTarget
@ OPC_EmitConvertToTarget6
bool isOrEquivalentToAdd(const SDNode *N) const
virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
virtual bool CheckPatternPredicate(unsigned PredNo) const
CheckPatternPredicate - This function is generated by tblgen in the target.
static int getNumFixedFromVariadicInfo(unsigned Flags)
getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values ...
const TargetLibraryInfo * LibInfo
static int getUninvalidatedNodeId(SDNode *N)
const TargetInstrInfo * TII
virtual bool CheckNodePredicateWithOperands(SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize)
static void EnforceNodeIdInvariant(SDNode *N)
void ReplaceUses(SDValue F, SDValue T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const
IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during ...
virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo)
bool MatchFilterFuncName
True if the function currently processing is in the function printing list (i.e.
void SelectInlineAsmMemoryOperands(std::vector< SDValue > &Ops, const SDLoc &DL)
SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, CodeGenOptLevel OptLevel, bool IgnoreChains=false)
IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction sel...
virtual bool ComplexPatternFuncMutatesDAG() const
Return true if complex patterns for this target can mutate the DAG.
virtual void PreprocessISelDAG()
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
BatchAAResults * getBatchAA() const
Returns a (possibly null) pointer to the current BatchAAResults.
bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckAndMask - The isel is trying to match something like (and X, 255).
SwiftErrorValueTracking * SwiftError
virtual ~SelectionDAGISel()
virtual StringRef getPatternForIndex(unsigned index)
getPatternForIndex - Patterns selected by tablegen during ISEL
bool mayRaiseFPException(SDNode *Node) const
Return whether the node may raise an FP exception.
std::unique_ptr< SelectionDAGBuilder > SDB
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
SelectionDAGISel(TargetMachine &tm, CodeGenOptLevel OL=CodeGenOptLevel::Default)
virtual bool runOnMachineFunction(MachineFunction &mf)
static void InvalidateNodeId(SDNode *N)
virtual StringRef getIncludePathForIndex(unsigned index)
getIncludePathForIndex - get the td source location of pattern instantiation
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
virtual bool mayRaiseFPException(unsigned Opcode) const
Returns true if a node with the given target-specific opcode may raise a floating-point exception.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg, SDValue N)
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
bool LegalizeVectors()
This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported ...
SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type,...
void Combine(CombineLevel Level, BatchAAResults *BatchAA, CodeGenOptLevel OptLevel)
This iterates over the nodes in the SelectionDAG, folding certain types of nodes together,...
void setFunctionLoweringInfo(FunctionLoweringInfo *FuncInfo)
SDValue getRegister(Register Reg, EVT VT)
SDNode * mutateStrictFPToFP(SDNode *Node)
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain a...
bool NewNodesMustHaveLegalTypes
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG n...
void salvageDebugInfo(SDNode &N)
To be invoked on an SDNode that is slated to be erased.
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
allnodes_const_iterator allnodes_begin() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT)
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
const DataLayout & getDataLayout() const
void viewGraph(const std::string &Title)
Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
void Legalize()
This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction s...
const SelectionDAGTargetInfo & getSelectionDAGInfo() const
void clear()
Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
SDValue getSignedConstant(int64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
void RemoveDeadNodes()
This method deletes all unreachable nodes in the SelectionDAG.
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
unsigned AssignTopologicalOrder()
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on th...
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
MachineFunction & getMachineFunction() const
const FunctionVarLocs * getFunctionVarLocs() const
Returns the result of the AssignmentTrackingAnalysis pass if it's available, otherwise return nullptr...
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, MachineModuleInfo &MMI, FunctionVarLocs const *FnVarLocs)
Prepare this SelectionDAG to process code in the given MachineFunction.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
ilist< SDNode >::iterator allnodes_iterator
bool LegalizeTypes()
This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the t...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
bool createEntriesInEntryBlock(DebugLoc DbgLoc)
Create initial definitions of swifterror values in the entry block of the current function.
void setFunction(MachineFunction &MF)
Initialize data structures for specified new function.
void preassignVRegs(MachineBasicBlock *MBB, BasicBlock::const_iterator Begin, BasicBlock::const_iterator End)
void propagateVRegs()
Propagate assigned swifterror vregs through a function, synthesizing PHI nodes when needed to maintai...
Analysis pass providing the TargetTransformInfo.
TargetIntrinsicInfo - Interface to description of machine instruction set.
Analysis pass providing the TargetLibraryInfo.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
bool isStrictFPEnabled() const
Return true if the target support strict float operation.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual Register getRegisterByName(const char *RegName, LLT Ty, const MachineFunction &MF) const
Return the register ID of the name passed in.
virtual void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const
Insert explicit copies in entry and exit blocks.
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual void initializeSplitCSR(MachineBasicBlock *Entry) const
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
virtual FastISel * createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Primary interface to the complete machine description for the target machine.
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
void setFastISel(bool Enable)
void setOptLevel(CodeGenOptLevel Level)
Overrides the optimization level.
bool getO0WantsFastISel()
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetLowering * getTargetLowering() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
bool isTokenTy() const
Return true if this is 'token'.
bool isVoidTy() const
Return true if this is 'void'.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
bool hasOneUse() const
Return true if there is exactly one use of this value.
iterator_range< user_iterator > users()
StringRef getName() const
Return a constant reference to the value's name.
self_iterator getIterator()
A raw_ostream that writes to an std::string.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
bool isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are ~0 ...
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ JUMP_TABLE_DEBUG_INFO
JUMP_TABLE_DEBUG_INFO - Jumptable debug info.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ MEMBARRIER
MEMBARRIER - Compiler barrier only; generate a no-op.
@ FAKE_USE
FAKE_USE represents a use of the operand but does not do anything.
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
@ UNDEF
UNDEF - An undefined node.
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
@ BasicBlock
Various leaf nodes.
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ ARITH_FENCE
ARITH_FENCE - This corresponds to a arithmetic fence intrinsic.
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
@ READ_REGISTER
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
@ LIFETIME_START
This corresponds to the llvm.lifetime.
@ STRICT_SINT_TO_FP
STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
@ FREEZE
FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or is evaluated to UNDEF),...
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ INLINEASM
INLINEASM - Represents an inline asm block.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
bool isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are 0 o...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
@ Kill
The last use of a register.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
DiagnosticInfoOptimizationBase::Argument NV
const_iterator end(StringRef path LLVM_LIFETIME_BOUND)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
ScheduleDAGSDNodes * createDefaultScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createDefaultScheduler - This creates an instruction scheduler appropriate for the target.
bool succ_empty(const Instruction *I)
ScheduleDAGSDNodes * createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createBURRListDAGScheduler - This creates a bottom up register usage reduction list scheduler.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
ScheduleDAGSDNodes * createHybridListDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel)
createHybridListDAGScheduler - This creates a bottom up register pressure aware list scheduler that m...
MachineBasicBlock::iterator findSplitPointForStackProtector(MachineBasicBlock *BB, const TargetInstrInfo &TII)
Find the split point at which to splice the end of BB into its success stack protector check machine ...
bool TimePassesIsEnabled
If the user specifies the -time-passes argument on an LLVM tool command line then the value of this b...
LLT getLLTForMVT(MVT Ty)
Get a rough equivalent of an LLT for a given MVT.
void initializeBranchProbabilityInfoWrapperPassPass(PassRegistry &)
ScheduleDAGSDNodes * createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createFastDAGScheduler - This creates a "fast" scheduler.
PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
void erase(Container &C, ValueType V)
Wrapper function to remove a value from a container:
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
ScheduleDAGSDNodes * createDAGLinearizer(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createDAGLinearizer - This creates a "no-scheduling" scheduler which linearize the DAG using topologi...
void initializeAAResultsWrapperPassPass(PassRegistry &)
void initializeGCModuleInfoPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isFunctionInPrintList(StringRef FunctionName)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
CodeGenOptLevel
Code generation optimization level.
bool isFuncletEHPersonality(EHPersonality Pers)
Returns true if this is a personality function that invokes handler funclets (which must return to it...
ScheduleDAGSDNodes * createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createSourceListDAGScheduler - This creates a bottom up list scheduler that schedules nodes in source...
bool isAssignmentTrackingEnabled(const Module &M)
Return true if assignment tracking is enabled for module M.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
ScheduleDAGSDNodes * createILPListDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel)
createILPListDAGScheduler - This creates a bottom up register pressure aware list scheduler that trie...
auto predecessors(const MachineBasicBlock *BB)
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
void initializeTargetLibraryInfoWrapperPassPass(PassRegistry &)
ScheduleDAGSDNodes * createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createVLIWDAGScheduler - Scheduler for VLIW targets.
static auto filterDbgVars(iterator_range< simple_ilist< DbgRecord >::iterator > R)
Filter the DbgRecord range to DbgVariableRecord types only and downcast.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Implement std::hash so that hash_code can be used in STL containers.
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
bool isInteger() const
Return true if this is an integer or a vector integer type.
This class is basically a combination of TimeRegion and Timer.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Clients of various APIs that cause global effects on the DAG can optionally implement this interface.
void addIPToStateRange(const InvokeInst *II, MCSymbol *InvokeBegin, MCSymbol *InvokeEnd)
DenseMap< const BasicBlock *, int > BlockToStateMap