40#include "llvm/IR/IntrinsicsAMDGPU.h"
41#include "llvm/IR/IntrinsicsR600.h"
49#define DEBUG_TYPE "si-lower"
54 "amdgpu-disable-loop-alignment",
55 cl::desc(
"Do not align and prefetch loops"),
59 "amdgpu-use-divergent-register-indexing",
61 cl::desc(
"Use indirect register addressing for divergent indexes"),
75 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
76 for (
unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
78 return AMDGPU::SGPR0 + Reg;
194 {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32,
195 MVT::v6i32, MVT::v7i32, MVT::v8i32, MVT::v9i32,
196 MVT::v10i32, MVT::v11i32, MVT::v12i32, MVT::v16i32,
197 MVT::i1, MVT::v32i32},
201 {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32,
202 MVT::v6i32, MVT::v7i32, MVT::v8i32, MVT::v9i32,
203 MVT::v10i32, MVT::v11i32, MVT::v12i32, MVT::v16i32,
204 MVT::i1, MVT::v32i32},
277 {MVT::f32, MVT::i32, MVT::i64, MVT::f64, MVT::i1},
Expand);
284 {MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32,
285 MVT::v6i32, MVT::v7i32, MVT::v8i32, MVT::v9i32,
286 MVT::v10i32, MVT::v11i32, MVT::v12i32, MVT::v16i32},
289 {MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32,
290 MVT::v6f32, MVT::v7f32, MVT::v8f32, MVT::v9f32,
291 MVT::v10f32, MVT::v11f32, MVT::v12f32, MVT::v16f32},
295 {MVT::v2i1, MVT::v4i1, MVT::v2i8, MVT::v4i8, MVT::v2i16,
296 MVT::v3i16, MVT::v4i16, MVT::Other},
301 {MVT::i1, MVT::i32, MVT::i64, MVT::f32, MVT::f64},
Expand);
317 {MVT::v8i32, MVT::v8f32, MVT::v9i32, MVT::v9f32, MVT::v10i32,
318 MVT::v10f32, MVT::v11i32, MVT::v11f32, MVT::v12i32, MVT::v12f32,
319 MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64, MVT::v4i16,
320 MVT::v4f16, MVT::v4bf16, MVT::v3i64, MVT::v3f64, MVT::v6i32,
321 MVT::v6f32, MVT::v4i64, MVT::v4f64, MVT::v8i64, MVT::v8f64,
322 MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, MVT::v16f16,
323 MVT::v16bf16, MVT::v16i64, MVT::v16f64, MVT::v32i32, MVT::v32f32,
324 MVT::v32i16, MVT::v32f16, MVT::v32bf16}) {
356 for (
MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
370 for (
MVT Vec64 : { MVT::v3i64, MVT::v3f64 }) {
384 for (
MVT Vec64 : { MVT::v4i64, MVT::v4f64 }) {
398 for (
MVT Vec64 : { MVT::v8i64, MVT::v8f64 }) {
412 for (
MVT Vec64 : { MVT::v16i64, MVT::v16f64 }) {
427 {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32},
436 {MVT::v2i16, MVT::v2f16, MVT::v2bf16, MVT::v2i8, MVT::v4i8,
437 MVT::v8i8, MVT::v4i16, MVT::v4f16, MVT::v4bf16},
442 {MVT::v3i32, MVT::v3f32, MVT::v4i32, MVT::v4f32},
Custom);
446 {MVT::v5i32, MVT::v5f32, MVT::v6i32, MVT::v6f32,
447 MVT::v7i32, MVT::v7f32, MVT::v8i32, MVT::v8f32,
448 MVT::v9i32, MVT::v9f32, MVT::v10i32, MVT::v10f32,
449 MVT::v11i32, MVT::v11f32, MVT::v12i32, MVT::v12f32},
530 {MVT::f32, MVT::f64},
Legal);
623 {MVT::v2i16, MVT::v2f16, MVT::v2bf16, MVT::v4i16, MVT::v4f16,
624 MVT::v4bf16, MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16,
625 MVT::v16f16, MVT::v16bf16, MVT::v32i16, MVT::v32f16}) {
750 {MVT::v2i16, MVT::v2f16, MVT::v2bf16},
Custom);
761 {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16},
765 {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16},
769 {MVT::v8i16, MVT::v8f16, MVT::v8bf16, MVT::v16i16, MVT::v16f16,
770 MVT::v16bf16, MVT::v32i16, MVT::v32f16, MVT::v32bf16}) {
792 {MVT::v4f16, MVT::v4i16, MVT::v8f16, MVT::v8i16,
793 MVT::v16f16, MVT::v16i16, MVT::v32f16, MVT::v32i16},
796 for (
MVT VT : {MVT::v4i16, MVT::v8i16, MVT::v16i16, MVT::v32i16})
804 for (
MVT VT : {MVT::v4f16, MVT::v8f16, MVT::v16f16, MVT::v32f16})
820 {MVT::v4f32, MVT::v8f32, MVT::v16f32, MVT::v32f32},
840 {MVT::v4i16, MVT::v4f16, MVT::v4bf16, MVT::v2i8, MVT::v4i8,
841 MVT::v8i8, MVT::v8i16, MVT::v8f16, MVT::v8bf16,
842 MVT::v16i16, MVT::v16f16, MVT::v16bf16, MVT::v32i16,
843 MVT::v32f16, MVT::v32bf16},
859 {MVT::f16, MVT::f32, MVT::f64, MVT::v2f16},
Legal);
862 {MVT::Other, MVT::f32, MVT::v4f32, MVT::i16, MVT::f16,
863 MVT::v2i16, MVT::v2f16, MVT::i128, MVT::i8},
867 {MVT::v2f16, MVT::v2i16, MVT::v3f16, MVT::v3i16,
868 MVT::v4f16, MVT::v4i16, MVT::v8f16, MVT::Other, MVT::f16,
869 MVT::i16, MVT::i8, MVT::i128},
873 {MVT::Other, MVT::v2i16, MVT::v2f16, MVT::v3i16,
874 MVT::v3f16, MVT::v4f16, MVT::v4i16, MVT::f16, MVT::i16,
969 EVT DestVT,
EVT SrcVT)
const {
979 LLT DestTy,
LLT SrcTy)
const {
980 return ((Opcode == TargetOpcode::G_FMAD && Subtarget->
hasMadMixInsts()) ||
981 (Opcode == TargetOpcode::G_FMA && Subtarget->
hasFmaMixInsts())) &&
1007 return (ScalarVT == MVT::bf16 ? MVT::i32 : MVT::v2f16);
1009 return VT.
isInteger() ? MVT::i32 : MVT::f32;
1036 return (NumElts + 1) / 2;
1042 return NumElts * ((
Size + 31) / 32);
1051 EVT VT,
EVT &IntermediateVT,
1052 unsigned &NumIntermediates,
MVT &RegisterVT)
const {
1061 if (ScalarVT == MVT::bf16) {
1062 RegisterVT = MVT::i32;
1063 IntermediateVT = MVT::v2bf16;
1065 RegisterVT = VT.
isInteger() ? MVT::v2i16 : MVT::v2f16;
1066 IntermediateVT = RegisterVT;
1068 NumIntermediates = (NumElts + 1) / 2;
1069 return NumIntermediates;
1074 IntermediateVT = RegisterVT;
1075 NumIntermediates = NumElts;
1076 return NumIntermediates;
1079 if (Size < 16 && Subtarget->has16BitInsts()) {
1081 RegisterVT = MVT::i16;
1082 IntermediateVT = ScalarVT;
1083 NumIntermediates = NumElts;
1084 return NumIntermediates;
1089 RegisterVT = MVT::i32;
1090 IntermediateVT = ScalarVT;
1091 NumIntermediates = NumElts;
1092 return NumIntermediates;
1096 RegisterVT = MVT::i32;
1097 IntermediateVT = RegisterVT;
1098 NumIntermediates = NumElts * ((
Size + 31) / 32);
1099 return NumIntermediates;
1104 Context,
CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
1108 assert(MaxNumLanes != 0);
1110 if (
auto *VT = dyn_cast<FixedVectorType>(Ty)) {
1111 unsigned NumElts = std::min(MaxNumLanes, VT->getNumElements());
1122 auto *ST = dyn_cast<StructType>(Ty);
1127 assert(ST->getNumContainedTypes() == 2 &&
1128 ST->getContainedType(1)->isIntegerTy(32));
1143 DL.getPointerSizeInBits(AS) == 192)
1153 DL.getPointerSizeInBits(AS) == 160) ||
1155 DL.getPointerSizeInBits(AS) == 192))
1163 unsigned IntrID)
const {
1165 if (CI.
hasMetadata(LLVMContext::MD_invariant_load))
1179 if (RsrcIntr->IsImage)
1183 if (
auto *RsrcPtrTy = dyn_cast<PointerType>(RsrcArg->
getType())) {
1190 Info.ptrVal = RsrcArg;
1198 unsigned MaxNumLanes = 4;
1200 if (RsrcIntr->IsImage) {
1224 if (RsrcIntr->IsImage) {
1225 unsigned DMask = cast<ConstantInt>(CI.
getArgOperand(1))->getZExtValue();
1246 case Intrinsic::amdgcn_raw_buffer_load_lds:
1247 case Intrinsic::amdgcn_raw_ptr_buffer_load_lds:
1248 case Intrinsic::amdgcn_struct_buffer_load_lds:
1249 case Intrinsic::amdgcn_struct_ptr_buffer_load_lds: {
1250 unsigned Width = cast<ConstantInt>(CI.
getArgOperand(2))->getZExtValue();
1261 case Intrinsic::amdgcn_ds_ordered_add:
1262 case Intrinsic::amdgcn_ds_ordered_swap:
1263 case Intrinsic::amdgcn_ds_fadd:
1264 case Intrinsic::amdgcn_ds_fmin:
1265 case Intrinsic::amdgcn_ds_fmax: {
1278 case Intrinsic::amdgcn_buffer_atomic_fadd: {
1286 if (!Vol || !Vol->
isZero())
1291 case Intrinsic::amdgcn_ds_add_gs_reg_rtn:
1292 case Intrinsic::amdgcn_ds_sub_gs_reg_rtn: {
1295 Info.ptrVal =
nullptr;
1300 case Intrinsic::amdgcn_ds_append:
1301 case Intrinsic::amdgcn_ds_consume: {
1314 case Intrinsic::amdgcn_global_atomic_csub: {
1324 case Intrinsic::amdgcn_image_bvh_intersect_ray: {
1334 case Intrinsic::amdgcn_global_atomic_fadd:
1335 case Intrinsic::amdgcn_global_atomic_fmin:
1336 case Intrinsic::amdgcn_global_atomic_fmax:
1337 case Intrinsic::amdgcn_global_atomic_fmin_num:
1338 case Intrinsic::amdgcn_global_atomic_fmax_num:
1339 case Intrinsic::amdgcn_global_atomic_ordered_add_b64:
1340 case Intrinsic::amdgcn_flat_atomic_fadd:
1341 case Intrinsic::amdgcn_flat_atomic_fmin:
1342 case Intrinsic::amdgcn_flat_atomic_fmax:
1343 case Intrinsic::amdgcn_flat_atomic_fmin_num:
1344 case Intrinsic::amdgcn_flat_atomic_fmax_num:
1345 case Intrinsic::amdgcn_global_atomic_fadd_v2bf16:
1346 case Intrinsic::amdgcn_atomic_cond_sub_u32:
1347 case Intrinsic::amdgcn_flat_atomic_fadd_v2bf16: {
1358 case Intrinsic::amdgcn_global_load_tr_b64:
1359 case Intrinsic::amdgcn_global_load_tr_b128: {
1367 case Intrinsic::amdgcn_ds_gws_init:
1368 case Intrinsic::amdgcn_ds_gws_barrier:
1369 case Intrinsic::amdgcn_ds_gws_sema_v:
1370 case Intrinsic::amdgcn_ds_gws_sema_br:
1371 case Intrinsic::amdgcn_ds_gws_sema_p:
1372 case Intrinsic::amdgcn_ds_gws_sema_release_all: {
1382 Info.memVT = MVT::i32;
1386 if (IntrID == Intrinsic::amdgcn_ds_gws_barrier)
1392 case Intrinsic::amdgcn_global_load_lds: {
1394 unsigned Width = cast<ConstantInt>(CI.
getArgOperand(2))->getZExtValue();
1400 case Intrinsic::amdgcn_ds_bvh_stack_rtn: {
1410 Info.memVT = MVT::i32;
1425 case Intrinsic::amdgcn_addrspacecast_nonnull: {
1428 unsigned SrcAS =
I.getOperand(0)->getType()->getPointerAddressSpace();
1429 unsigned DstAS =
I.getType()->getPointerAddressSpace();
1441 Type *&AccessTy)
const {
1444 case Intrinsic::amdgcn_atomic_cond_sub_u32:
1445 case Intrinsic::amdgcn_ds_append:
1446 case Intrinsic::amdgcn_ds_consume:
1447 case Intrinsic::amdgcn_ds_fadd:
1448 case Intrinsic::amdgcn_ds_fmax:
1449 case Intrinsic::amdgcn_ds_fmin:
1450 case Intrinsic::amdgcn_ds_ordered_add:
1451 case Intrinsic::amdgcn_ds_ordered_swap:
1452 case Intrinsic::amdgcn_flat_atomic_fadd:
1453 case Intrinsic::amdgcn_flat_atomic_fadd_v2bf16:
1454 case Intrinsic::amdgcn_flat_atomic_fmax:
1455 case Intrinsic::amdgcn_flat_atomic_fmax_num:
1456 case Intrinsic::amdgcn_flat_atomic_fmin:
1457 case Intrinsic::amdgcn_flat_atomic_fmin_num:
1458 case Intrinsic::amdgcn_global_atomic_csub:
1459 case Intrinsic::amdgcn_global_atomic_fadd:
1460 case Intrinsic::amdgcn_global_atomic_fadd_v2bf16:
1461 case Intrinsic::amdgcn_global_atomic_fmax:
1462 case Intrinsic::amdgcn_global_atomic_fmax_num:
1463 case Intrinsic::amdgcn_global_atomic_fmin:
1464 case Intrinsic::amdgcn_global_atomic_fmin_num:
1465 case Intrinsic::amdgcn_global_atomic_ordered_add_b64:
1466 case Intrinsic::amdgcn_global_load_tr_b64:
1467 case Intrinsic::amdgcn_global_load_tr_b128:
1470 case Intrinsic::amdgcn_global_load_lds:
1481bool SITargetLowering::isLegalFlatAddressingMode(
const AddrMode &AM,
1487 return AM.BaseOffs == 0 && AM.Scale == 0;
1490 return AM.Scale == 0 &&
1492 AM.BaseOffs, AddrSpace, FlatVariant));
1514 return isLegalMUBUFAddressingMode(AM);
1517bool SITargetLowering::isLegalMUBUFAddressingMode(
const AddrMode &AM)
const {
1528 if (!
TII->isLegalMUBUFImmOffset(AM.BaseOffs))
1540 if (AM.HasBaseReg) {
1571 return isLegalMUBUFAddressingMode(AM);
1578 if (Ty->
isSized() &&
DL.getTypeStoreSize(Ty) < 4)
1619 : isLegalMUBUFAddressingMode(AM);
1667 unsigned Size,
unsigned AddrSpace,
Align Alignment,
1681 Alignment < RequiredAlignment)
1702 RequiredAlignment =
Align(4);
1720 *IsFast = (Alignment >= RequiredAlignment) ? 64
1721 : (Alignment <
Align(4)) ? 32
1743 *IsFast = (Alignment >= RequiredAlignment) ? 96
1744 : (Alignment <
Align(4)) ? 32
1757 RequiredAlignment =
Align(8);
1768 *IsFast = (Alignment >= RequiredAlignment) ? 128
1769 : (Alignment <
Align(4)) ? 32
1786 *IsFast = (Alignment >= RequiredAlignment) ?
Size : 0;
1788 return Alignment >= RequiredAlignment ||
1793 bool AlignedBy4 = Alignment >=
Align(4);
1795 *IsFast = AlignedBy4;
1797 return AlignedBy4 ||
1807 bool AlignedBy4 = Alignment >=
Align(4);
1809 *IsFast = AlignedBy4;
1820 return Alignment >=
Align(4) ||
1834 return Size >= 32 && Alignment >=
Align(4);
1839 unsigned *IsFast)
const {
1841 Alignment, Flags, IsFast);
1851 if (
Op.size() >= 16 &&
1855 if (
Op.size() >= 8 &&
Op.isDstAligned(
Align(4)))
1863 const MemSDNode *MemNode = cast<MemSDNode>(
N);
1873 unsigned DestAS)
const {
1881 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
1885 const MemSDNode *MemNode = cast<MemSDNode>(
N);
1905 unsigned Index)
const {
1952 std::tie(InputPtrReg, RC, ArgTy) =
1962 MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT);
1968 const SDLoc &SL)
const {
1975 const SDLoc &SL)
const {
1978 std::optional<uint32_t> KnownSize =
1980 if (KnownSize.has_value())
2007 Val = getFPExtOrFPRound(DAG, Val, SL, VT);
2016SDValue SITargetLowering::lowerKernargMemParameter(
2028 int64_t OffsetDiff =
Offset - AlignDownOffset;
2034 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset);
2044 ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal,
Signed, Arg);
2055 SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load,
Signed, Arg);
2102 ExtType, SL, VA.
getLocVT(), Chain, FIN,
2131 Reg = &WorkGroupIDX;
2132 RC = &AMDGPU::SReg_32RegClass;
2136 Reg = &WorkGroupIDY;
2137 RC = &AMDGPU::SReg_32RegClass;
2141 Reg = &WorkGroupIDZ;
2142 RC = &AMDGPU::SReg_32RegClass;
2173 for (
unsigned I = 0, E = Ins.size(), PSInputNum = 0;
I != E; ++
I) {
2177 "vector type argument should have been split");
2182 bool SkipArg = !Arg->
Used && !
Info->isPSInputAllocated(PSInputNum);
2191 "unexpected vector split in ps argument type");
2205 Info->markPSInputAllocated(PSInputNum);
2207 Info->markPSInputEnabled(PSInputNum);
2224 if (
Info.hasWorkItemIDX()) {
2230 Info.hasWorkItemIDY()) ? 0x3ff : ~0u;
2234 if (
Info.hasWorkItemIDY()) {
2240 unsigned Reg = AMDGPU::VGPR1;
2248 if (
Info.hasWorkItemIDZ()) {
2254 unsigned Reg = AMDGPU::VGPR2;
2274 if (RegIdx == ArgVGPRs.
size()) {
2281 unsigned Reg = ArgVGPRs[RegIdx];
2283 assert(Reg != AMDGPU::NoRegister);
2293 unsigned NumArgRegs) {
2296 if (RegIdx == ArgSGPRs.
size())
2299 unsigned Reg = ArgSGPRs[RegIdx];
2301 assert(Reg != AMDGPU::NoRegister);
2315 assert(Reg != AMDGPU::NoRegister);
2341 const unsigned Mask = 0x3ff;
2344 if (
Info.hasWorkItemIDX()) {
2346 Info.setWorkItemIDX(Arg);
2349 if (
Info.hasWorkItemIDY()) {
2351 Info.setWorkItemIDY(Arg);
2354 if (
Info.hasWorkItemIDZ())
2366 const unsigned Mask = 0x3ff;
2391 if (
Info.hasImplicitArgPtr())
2399 if (
Info.hasWorkGroupIDX())
2402 if (
Info.hasWorkGroupIDY())
2405 if (
Info.hasWorkGroupIDZ())
2408 if (
Info.hasLDSKernelId())
2420 MF.
addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
2427 MF.
addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
2433 MF.
addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
2441 MF.
addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
2456 MF.
addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
2462 MF.
addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
2477 unsigned LastExplicitArgOffset =
2480 bool InPreloadSequence =
true;
2482 for (
auto &Arg :
F.args()) {
2483 if (!InPreloadSequence || !Arg.hasInRegAttr())
2486 int ArgIdx = Arg.getArgNo();
2489 if (InIdx < Ins.size() && (!Ins[InIdx].isOrigArg() ||
2490 (
int)Ins[InIdx].getOrigArgIndex() != ArgIdx))
2493 for (; InIdx < Ins.size() && Ins[InIdx].isOrigArg() &&
2494 (
int)Ins[InIdx].getOrigArgIndex() == ArgIdx;
2496 assert(ArgLocs[ArgIdx].isMemLoc());
2497 auto &ArgLoc = ArgLocs[InIdx];
2499 unsigned ArgOffset = ArgLoc.getLocMemOffset();
2501 unsigned NumAllocSGPRs =
2502 alignTo(ArgLoc.getLocVT().getFixedSizeInBits(), 32) / 32;
2505 if (ArgLoc.getLocVT().getStoreSize() < 4 && Alignment < 4) {
2506 Info.getArgInfo().PreloadKernArgs[InIdx].Regs.push_back(
2507 Info.getArgInfo().PreloadKernArgs[InIdx - 1].Regs[0]);
2511 unsigned Padding = ArgOffset - LastExplicitArgOffset;
2512 unsigned PaddingSGPRs =
alignTo(Padding, 4) / 4;
2514 if (PaddingSGPRs + NumAllocSGPRs + 1 >
2516 InPreloadSequence =
false;
2522 TRI.getSGPRClassForBitWidth(NumAllocSGPRs * 32);
2524 Info.addPreloadedKernArg(
TRI, RC, NumAllocSGPRs, InIdx, PaddingSGPRs);
2526 if (PreloadRegs->
size() > 1)
2527 RC = &AMDGPU::SGPR_32RegClass;
2528 for (
auto &Reg : *PreloadRegs) {
2534 LastExplicitArgOffset = NumAllocSGPRs * 4 + ArgOffset;
2543 if (
Info.hasLDSKernelId()) {
2545 MF.
addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2555 bool IsShader)
const {
2563 assert(!HasArchitectedSGPRs &&
"Unhandled feature for the subtarget");
2565 unsigned CurrentUserSGPRs =
Info.getNumUserSGPRs();
2569 unsigned NumRequiredSystemSGPRs =
Info.hasWorkGroupIDX() +
2570 Info.hasWorkGroupIDY() +
2571 Info.hasWorkGroupIDZ() +
2572 Info.hasWorkGroupInfo();
2573 for (
unsigned i = NumRequiredSystemSGPRs + CurrentUserSGPRs; i < 16; ++i) {
2575 MF.
addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2580 if (!HasArchitectedSGPRs) {
2581 if (
Info.hasWorkGroupIDX()) {
2583 MF.
addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2587 if (
Info.hasWorkGroupIDY()) {
2589 MF.
addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2593 if (
Info.hasWorkGroupIDZ()) {
2595 MF.
addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2600 if (
Info.hasWorkGroupInfo()) {
2602 MF.
addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2606 if (
Info.hasPrivateSegmentWaveByteOffset()) {
2608 unsigned PrivateSegmentWaveByteOffsetReg;
2611 PrivateSegmentWaveByteOffsetReg =
2612 Info.getPrivateSegmentWaveByteOffsetSystemSGPR();
2616 if (PrivateSegmentWaveByteOffsetReg == AMDGPU::NoRegister) {
2618 Info.setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg);
2621 PrivateSegmentWaveByteOffsetReg =
Info.addPrivateSegmentWaveByteOffset();
2623 MF.
addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
2624 CCInfo.
AllocateReg(PrivateSegmentWaveByteOffsetReg);
2628 Info.getNumPreloadedSGPRs() >= 16);
2643 if (HasStackObjects)
2644 Info.setHasNonSpillStackObjects(
true);
2649 HasStackObjects =
true;
2653 bool RequiresStackAccess = HasStackObjects || MFI.
hasCalls();
2655 if (!ST.enableFlatScratch()) {
2656 if (RequiresStackAccess && ST.isAmdHsaOrMesa(MF.
getFunction())) {
2663 Info.setScratchRSrcReg(PrivateSegmentBufferReg);
2665 unsigned ReservedBufferReg =
TRI.reservedPrivateSegmentBufferReg(MF);
2675 Info.setScratchRSrcReg(ReservedBufferReg);
2694 if (!
MRI.isLiveIn(AMDGPU::SGPR32)) {
2695 Info.setStackPtrOffsetReg(AMDGPU::SGPR32);
2702 for (
unsigned Reg : AMDGPU::SGPR_32RegClass) {
2703 if (!
MRI.isLiveIn(Reg)) {
2704 Info.setStackPtrOffsetReg(Reg);
2709 if (
Info.getStackPtrOffsetReg() == AMDGPU::SP_REG)
2716 if (ST.getFrameLowering()->hasFP(MF)) {
2717 Info.setFrameOffsetReg(AMDGPU::SGPR33);
2723 return !
Info->isEntryFunction();
2735 const MCPhysReg *IStart =
TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
2744 if (AMDGPU::SReg_64RegClass.
contains(*
I))
2745 RC = &AMDGPU::SGPR_64RegClass;
2746 else if (AMDGPU::SReg_32RegClass.
contains(*
I))
2747 RC = &AMDGPU::SGPR_32RegClass;
2753 Entry->addLiveIn(*
I);
2758 for (
auto *Exit : Exits)
2760 TII->get(TargetOpcode::COPY), *
I)
2778 Fn,
"unsupported non-compute shaders with HSA",
DL.getDebugLoc());
2797 !
Info->hasLDSKernelId() && !
Info->hasWorkItemIDX() &&
2798 !
Info->hasWorkItemIDY() && !
Info->hasWorkItemIDZ());
2806 !
Info->hasWorkGroupIDZ());
2825 if ((
Info->getPSInputAddr() & 0x7F) == 0 ||
2826 ((
Info->getPSInputAddr() & 0xF) == 0 &&
Info->isPSInputAllocated(11))) {
2829 Info->markPSInputAllocated(0);
2830 Info->markPSInputEnabled(0);
2841 unsigned PsInputBits =
Info->getPSInputAddr() &
Info->getPSInputEnable();
2842 if ((PsInputBits & 0x7F) == 0 ||
2843 ((PsInputBits & 0xF) == 0 && (PsInputBits >> 11 & 1)))
2846 }
else if (IsKernel) {
2849 Splits.
append(Ins.begin(), Ins.end());
2862 }
else if (!IsGraphics) {
2887 for (
unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
2897 if (IsEntryFunc && VA.
isMemLoc()) {
2920 if (Arg.
isOrigArg() &&
Info->getArgInfo().PreloadKernArgs.count(i)) {
2924 int64_t OffsetDiff =
Offset - AlignDownOffset;
2931 Info->getArgInfo().PreloadKernArgs.find(i)->getSecond().Regs[0];
2942 NewArg = convertArgType(DAG, VT, MemVT,
DL, ArgVal,
2943 Ins[i].Flags.isSExt(), &Ins[i]);
2951 Info->getArgInfo().PreloadKernArgs.find(i)->getSecond().Regs;
2954 if (PreloadRegs.
size() == 1) {
2955 Register VReg =
MRI.getLiveInVirtReg(PreloadRegs[0]);
2960 TRI->getRegSizeInBits(*RC)));
2968 for (
auto Reg : PreloadRegs) {
2975 PreloadRegs.size()),
2984 NewArg = convertArgType(DAG, VT, MemVT,
DL, CMemVT,
2985 Ins[i].Flags.isSExt(), &Ins[i]);
2990 lowerKernargMemParameter(DAG, VT, MemVT,
DL, Chain,
Offset,
2991 Alignment, Ins[i].Flags.isSExt(), &Ins[i]);
2996 dyn_cast<PointerType>(FType->
getParamType(Ins[i].getOrigArgIndex()));
3009 }
else if (!IsEntryFunc && VA.
isMemLoc()) {
3010 SDValue Val = lowerStackParameter(DAG, VA,
DL, Chain, Arg);
3021 if (AMDGPU::VGPR_32RegClass.
contains(Reg))
3022 RC = &AMDGPU::VGPR_32RegClass;
3023 else if (AMDGPU::SGPR_32RegClass.
contains(Reg))
3024 RC = &AMDGPU::SGPR_32RegClass;
3077 auto &ArgUsageInfo =
3082 Info->setBytesInStackArgArea(StackArgSize);
3084 return Chains.
empty() ? Chain :
3108 unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
3109 for (
unsigned i = MaxNumVGPRs; i < TotalNumVGPRs; ++i)
3110 if (CCInfo.
isAllocated(AMDGPU::VGPR_32RegClass.getRegister(i)))
3133 bool IsWaveEnd =
Info->returnsVoid() && IsShader;
3151 for (
unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.
size();
I != E;
3152 ++
I, ++RealRVLocIdx) {
3156 SDValue Arg = OutVals[RealRVLocIdx];
3184 if (!
Info->isEntryFunction()) {
3190 if (AMDGPU::SReg_64RegClass.
contains(*
I))
3192 else if (AMDGPU::SReg_32RegClass.
contains(*
I))
3208 return DAG.
getNode(Opc,
DL, MVT::Other, RetOps);
3225 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
3291 auto &ArgUsageInfo =
3293 CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
3322 std::tie(OutgoingArg, ArgRC, ArgTy) =
3330 std::tie(IncomingArg, IncomingArgRC, Ty) =
3332 assert(IncomingArgRC == ArgRC);
3335 EVT ArgVT =
TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32;
3343 InputReg = getImplicitArgPtr(DAG,
DL);
3345 std::optional<uint32_t> Id =
3347 if (Id.has_value()) {
3359 RegsToPass.emplace_back(OutgoingArg->
getRegister(), InputReg);
3363 unsigned SpecialArgOffset =
3377 std::tie(OutgoingArg, ArgRC, Ty) =
3380 std::tie(OutgoingArg, ArgRC, Ty) =
3383 std::tie(OutgoingArg, ArgRC, Ty) =
3398 const bool NeedWorkItemIDX = !CLI.
CB->
hasFnAttr(
"amdgpu-no-workitem-id-x");
3399 const bool NeedWorkItemIDY = !CLI.
CB->
hasFnAttr(
"amdgpu-no-workitem-id-y");
3400 const bool NeedWorkItemIDZ = !CLI.
CB->
hasFnAttr(
"amdgpu-no-workitem-id-z");
3417 InputReg = InputReg.
getNode() ?
3426 InputReg = InputReg.
getNode() ?
3430 if (!InputReg && (NeedWorkItemIDX || NeedWorkItemIDY || NeedWorkItemIDZ)) {
3431 if (!IncomingArgX && !IncomingArgY && !IncomingArgZ) {
3441 IncomingArgX ? *IncomingArgX :
3442 IncomingArgY ? *IncomingArgY :
3443 *IncomingArgZ, ~0u);
3450 RegsToPass.emplace_back(OutgoingArg->
getRegister(), InputReg);
3491 if (Callee->isDivergent())
3498 const uint32_t *CallerPreserved =
TRI->getCallPreservedMask(MF, CallerCC);
3502 if (!CallerPreserved)
3505 bool CCMatch = CallerCC == CalleeCC;
3518 if (Arg.hasByValAttr())
3532 const uint32_t *CalleePreserved =
TRI->getCallPreservedMask(MF, CalleeCC);
3533 if (!
TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
3542 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);
3576 if (IsChainCallConv) {
3580 RequestedExec = CLI.
Args.back();
3581 assert(RequestedExec.
Node &&
"No node for EXEC");
3586 assert(CLI.
Outs.back().OrigArgIndex == 2 &&
"Unexpected last arg");
3587 CLI.
Outs.pop_back();
3591 assert(CLI.
Outs.back().OrigArgIndex == 2 &&
"Exec wasn't split up");
3592 CLI.
Outs.pop_back();
3597 "Haven't popped all the pieces of the EXEC mask");
3608 bool IsSibCall =
false;
3613 for (
unsigned I = 0, E = CLI.
Ins.size();
I != E; ++
I)
3622 "unsupported call to variadic function ");
3630 "unsupported required tail call to function ");
3635 Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
3639 "site marked musttail or on llvm.amdgcn.cs.chain");
3646 if (!TailCallOpt && IsTailCall)
3691 if (!IsSibCall || IsChainCallConv) {
3698 RegsToPass.emplace_back(IsChainCallConv
3699 ? AMDGPU::SGPR48_SGPR49_SGPR50_SGPR51
3700 : AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3,
3707 MVT PtrVT = MVT::i32;
3710 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
3738 RegsToPass.push_back(std::pair(VA.
getLocReg(), Arg));
3746 int32_t
Offset = LocMemOffset;
3753 unsigned OpSize = Flags.isByVal() ?
3759 ? Flags.getNonZeroByValAlign()
3786 if (Outs[i].Flags.isByVal()) {
3788 DAG.
getConstant(Outs[i].Flags.getByValSize(),
DL, MVT::i32);
3791 Outs[i].Flags.getNonZeroByValAlign(),
3799 DAG.
getStore(Chain,
DL, Arg, DstAddr, DstInfo, Alignment);
3805 if (!MemOpChains.
empty())
3811 for (
auto &RegToPass : RegsToPass) {
3813 RegToPass.second, InGlue);
3822 if (IsTailCall && !IsSibCall) {
3827 std::vector<SDValue> Ops;
3828 Ops.push_back(Chain);
3829 Ops.push_back(Callee);
3846 if (IsChainCallConv)
3847 Ops.push_back(RequestedExec.
Node);
3851 for (
auto &RegToPass : RegsToPass) {
3853 RegToPass.second.getValueType()));
3858 const uint32_t *Mask =
TRI->getCallPreservedMask(MF, CallConv);
3859 assert(Mask &&
"Missing call preserved mask for calling convention");
3863 Ops.push_back(InGlue);
3872 DL, MVT::Glue, Token),
3893 return DAG.
getNode(OPC,
DL, NodeTys, Ops);
3898 Chain = Call.getValue(0);
3899 InGlue = Call.getValue(1);
3901 uint64_t CalleePopBytes = NumBytes;
3920 EVT VT =
Op.getValueType();
3935 MaybeAlign Alignment = cast<ConstantSDNode>(Tmp3)->getMaybeAlignValue();
3946 Tmp1 = DAG.
getNode(Opc, dl, VT, SP, ScaledSize);
3947 if (Alignment && *Alignment > StackAlign) {
3968 if (isa<ConstantSDNode>(
Size))
3975 if (
Op.getValueType() != MVT::i32)
3994 assert(
Op.getValueType() == MVT::i32);
4003 Op.getOperand(0), IntrinID, GetRoundBothImm);
4037 SDValue RoundModeTimesNumBits =
4057 TableEntry, EnumOffset);
4063 if (
Op->isDivergent())
4066 switch (cast<MemSDNode>(
Op)->getAddressSpace()) {
4082 SDValue Src =
Op.getOperand(IsStrict ? 1 : 0);
4083 EVT SrcVT = Src.getValueType();
4092 EVT DstVT =
Op.getValueType();
4101 if (
Op.getValueType() != MVT::i64)
4115 Op.getOperand(0), IntrinID, ModeHwRegImm);
4117 Op.getOperand(0), IntrinID, TrapHwRegImm);
4131 if (
Op.getOperand(1).getValueType() != MVT::i64)
4143 ReadFirstLaneID, NewModeReg);
4145 ReadFirstLaneID, NewTrapReg);
4147 unsigned ModeHwReg =
4150 unsigned TrapHwReg =
4158 IntrinID, ModeHwRegImm, NewModeReg);
4161 IntrinID, TrapHwRegImm, NewTrapReg);
4168 .
Case(
"m0", AMDGPU::M0)
4169 .
Case(
"exec", AMDGPU::EXEC)
4170 .
Case(
"exec_lo", AMDGPU::EXEC_LO)
4171 .
Case(
"exec_hi", AMDGPU::EXEC_HI)
4172 .
Case(
"flat_scratch", AMDGPU::FLAT_SCR)
4173 .
Case(
"flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
4174 .
Case(
"flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
4177 if (Reg == AMDGPU::NoRegister) {
4191 case AMDGPU::EXEC_LO:
4192 case AMDGPU::EXEC_HI:
4193 case AMDGPU::FLAT_SCR_LO:
4194 case AMDGPU::FLAT_SCR_HI:
4199 case AMDGPU::FLAT_SCR:
4218 MI.setDesc(
TII->getKillTerminatorFromPseudo(
MI.getOpcode()));
4227static std::pair<MachineBasicBlock *, MachineBasicBlock *>
4249 auto Next = std::next(
I);
4262 return std::pair(LoopBB, RemainderBB);
4269 auto I =
MI.getIterator();
4270 auto E = std::next(
I);
4292 Src->setIsKill(
false);
4308 Register Reg =
MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4311 BuildMI(*LoopBB,
I,
DL,
TII->get(AMDGPU::S_GETREG_B32), Reg)
4333 unsigned InitReg,
unsigned ResultReg,
unsigned PhiReg,
4334 unsigned InitSaveExecReg,
int Offset,
bool UseGPRIdxMode,
4343 Register PhiExec =
MRI.createVirtualRegister(BoolRC);
4344 Register NewExec =
MRI.createVirtualRegister(BoolRC);
4345 Register CurrentIdxReg =
MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4346 Register CondReg =
MRI.createVirtualRegister(BoolRC);
4354 BuildMI(LoopBB,
I,
DL,
TII->get(TargetOpcode::PHI), PhiExec)
4361 BuildMI(LoopBB,
I,
DL,
TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
4365 BuildMI(LoopBB,
I,
DL,
TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
4370 BuildMI(LoopBB,
I,
DL,
TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32
4371 : AMDGPU::S_AND_SAVEEXEC_B64),
4375 MRI.setSimpleHint(NewExec, CondReg);
4377 if (UseGPRIdxMode) {
4379 SGPRIdxReg = CurrentIdxReg;
4381 SGPRIdxReg =
MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4382 BuildMI(LoopBB,
I,
DL,
TII->get(AMDGPU::S_ADD_I32), SGPRIdxReg)
4389 BuildMI(LoopBB,
I,
DL,
TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
4392 BuildMI(LoopBB,
I,
DL,
TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
4399 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
4401 BuildMI(LoopBB,
I,
DL,
TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term
4402 : AMDGPU::S_XOR_B64_term), Exec)
4423 unsigned InitResultReg,
unsigned PhiReg,
int Offset,
4424 bool UseGPRIdxMode,
Register &SGPRIdxReg) {
4432 const auto *BoolXExecRC =
TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4434 Register SaveExec =
MRI.createVirtualRegister(BoolXExecRC);
4435 Register TmpExec =
MRI.createVirtualRegister(BoolXExecRC);
4436 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
4437 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
4452 InitResultReg, DstReg, PhiReg, TmpExec,
4453 Offset, UseGPRIdxMode, SGPRIdxReg);
4470static std::pair<unsigned, int>
4475 int NumElts =
TRI.getRegSizeInBits(*SuperRC) / 32;
4480 return std::pair(AMDGPU::sub0,
Offset);
4494 assert(
Idx->getReg() != AMDGPU::NoRegister);
4515 return Idx->getReg();
4517 Register Tmp =
MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4534 Register SrcReg =
TII->getNamedOperand(
MI, AMDGPU::OpName::src)->getReg();
4535 int Offset =
TII->getNamedOperand(
MI, AMDGPU::OpName::offset)->getImm();
4544 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
4547 if (
TII->getRegisterInfo().isSGPRClass(IdxRC)) {
4551 if (UseGPRIdxMode) {
4558 TII->getIndirectGPRIDXPseudo(
TRI.getRegSizeInBits(*VecRC),
true);
4571 MI.eraseFromParent();
4580 Register PhiReg =
MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4581 Register InitReg =
MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4587 UseGPRIdxMode, SGPRIdxReg);
4591 if (UseGPRIdxMode) {
4593 TII->getIndirectGPRIDXPseudo(
TRI.getRegSizeInBits(*VecRC),
true);
4595 BuildMI(*LoopBB, InsPt,
DL, GPRIDXDesc, Dst)
4600 BuildMI(*LoopBB, InsPt,
DL,
TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
4605 MI.eraseFromParent();
4622 int Offset =
TII->getNamedOperand(
MI, AMDGPU::OpName::offset)->getImm();
4633 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
4635 if (
Idx->getReg() == AMDGPU::NoRegister) {
4646 MI.eraseFromParent();
4651 if (
TII->getRegisterInfo().isSGPRClass(IdxRC)) {
4655 if (UseGPRIdxMode) {
4659 TII->getIndirectGPRIDXPseudo(
TRI.getRegSizeInBits(*VecRC),
false);
4668 const MCInstrDesc &MovRelDesc =
TII->getIndirectRegWriteMovRelPseudo(
4669 TRI.getRegSizeInBits(*VecRC), 32,
false);
4675 MI.eraseFromParent();
4685 Register PhiReg =
MRI.createVirtualRegister(VecRC);
4689 UseGPRIdxMode, SGPRIdxReg);
4692 if (UseGPRIdxMode) {
4694 TII->getIndirectGPRIDXPseudo(
TRI.getRegSizeInBits(*VecRC),
false);
4696 BuildMI(*LoopBB, InsPt,
DL, GPRIDXDesc, Dst)
4702 const MCInstrDesc &MovRelDesc =
TII->getIndirectRegWriteMovRelPseudo(
4703 TRI.getRegSizeInBits(*VecRC), 32,
false);
4704 BuildMI(*LoopBB, InsPt,
DL, MovRelDesc, Dst)
4710 MI.eraseFromParent();
4725 bool isSGPR =
TRI->isSGPRClass(
MRI.getRegClass(SrcReg));
4753 Register LoopIterator =
MRI.createVirtualRegister(WaveMaskRegClass);
4754 Register InitalValReg =
MRI.createVirtualRegister(DstRegClass);
4756 Register AccumulatorReg =
MRI.createVirtualRegister(DstRegClass);
4757 Register ActiveBitsReg =
MRI.createVirtualRegister(WaveMaskRegClass);
4758 Register NewActiveBitsReg =
MRI.createVirtualRegister(WaveMaskRegClass);
4760 Register FF1Reg =
MRI.createVirtualRegister(DstRegClass);
4761 Register LaneValueReg =
MRI.createVirtualRegister(DstRegClass);
4763 bool IsWave32 = ST.isWave32();
4764 unsigned MovOpc = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
4765 unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
4770 (Opc == AMDGPU::S_MIN_U32) ? std::numeric_limits<uint32_t>::max() : 0;
4773 BuildMI(BB,
I,
DL,
TII->get(AMDGPU::S_MOV_B32), InitalValReg)
4778 I = ComputeLoop->end();
4780 BuildMI(*ComputeLoop,
I,
DL,
TII->get(AMDGPU::PHI), AccumulatorReg)
4784 BuildMI(*ComputeLoop,
I,
DL,
TII->get(AMDGPU::PHI), ActiveBitsReg)
4785 .
addReg(TmpSReg->getOperand(0).getReg())
4789 unsigned SFFOpc = IsWave32 ? AMDGPU::S_FF1_I32_B32 : AMDGPU::S_FF1_I32_B64;
4790 auto FF1 =
BuildMI(*ComputeLoop,
I,
DL,
TII->get(SFFOpc), FF1Reg)
4791 .
addReg(ActiveBits->getOperand(0).getReg());
4792 auto LaneValue =
BuildMI(*ComputeLoop,
I,
DL,
4793 TII->get(AMDGPU::V_READLANE_B32), LaneValueReg)
4795 .
addReg(FF1->getOperand(0).getReg());
4796 auto NewAccumulator =
BuildMI(*ComputeLoop,
I,
DL,
TII->get(Opc), DstReg)
4798 .
addReg(LaneValue->getOperand(0).getReg());
4801 unsigned BITSETOpc =
4802 IsWave32 ? AMDGPU::S_BITSET0_B32 : AMDGPU::S_BITSET0_B64;
4803 auto NewActiveBits =
4804 BuildMI(*ComputeLoop,
I,
DL,
TII->get(BITSETOpc), NewActiveBitsReg)
4805 .
addReg(FF1->getOperand(0).getReg())
4806 .
addReg(ActiveBits->getOperand(0).getReg());
4809 Accumulator.addReg(NewAccumulator->getOperand(0).getReg())
4810 .addMBB(ComputeLoop);
4811 ActiveBits.addReg(NewActiveBits->getOperand(0).getReg())
4812 .addMBB(ComputeLoop);
4815 unsigned CMPOpc = IsWave32 ? AMDGPU::S_CMP_LG_U32 : AMDGPU::S_CMP_LG_U64;
4817 .
addReg(NewActiveBits->getOperand(0).getReg())
4819 BuildMI(*ComputeLoop,
I,
DL,
TII->get(AMDGPU::S_CBRANCH_SCC1))
4824 MI.eraseFromParent();
4835 switch (
MI.getOpcode()) {
4836 case AMDGPU::WAVE_REDUCE_UMIN_PSEUDO_U32:
4838 case AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U32:
4840 case AMDGPU::S_UADDO_PSEUDO:
4841 case AMDGPU::S_USUBO_PSEUDO: {
4848 unsigned Opc = (
MI.getOpcode() == AMDGPU::S_UADDO_PSEUDO)
4850 : AMDGPU::S_SUB_I32;
4857 MI.eraseFromParent();
4860 case AMDGPU::S_ADD_U64_PSEUDO:
4861 case AMDGPU::S_SUB_U64_PSEUDO: {
4870 bool IsAdd = (
MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
4872 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U64 : AMDGPU::S_SUB_U64;
4880 Register DestSub0 =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4881 Register DestSub1 =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4884 MI,
MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
4886 MI,
MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
4889 MI,
MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
4891 MI,
MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
4893 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
4894 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
4907 MI.eraseFromParent();
4910 case AMDGPU::V_ADD_U64_PSEUDO:
4911 case AMDGPU::V_SUB_U64_PSEUDO: {
4917 bool IsAdd = (
MI.getOpcode() == AMDGPU::V_ADD_U64_PSEUDO);
4923 if (IsAdd && ST.hasLshlAddB64()) {
4929 TII->legalizeOperands(*
Add);
4930 MI.eraseFromParent();
4934 const auto *CarryRC =
TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4936 Register DestSub0 =
MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4937 Register DestSub1 =
MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4939 Register CarryReg =
MRI.createVirtualRegister(CarryRC);
4940 Register DeadCarryReg =
MRI.createVirtualRegister(CarryRC);
4944 : &AMDGPU::VReg_64RegClass;
4947 : &AMDGPU::VReg_64RegClass;
4950 TRI->getSubRegisterClass(Src0RC, AMDGPU::sub0);
4952 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1);
4955 MI,
MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
4957 MI,
MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
4960 MI,
MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
4962 MI,
MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
4964 unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64;
4971 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64;
4985 TII->legalizeOperands(*LoHalf);
4986 TII->legalizeOperands(*HiHalf);
4987 MI.eraseFromParent();
4990 case AMDGPU::S_ADD_CO_PSEUDO:
4991 case AMDGPU::S_SUB_CO_PSEUDO: {
5005 unsigned Opc = (
MI.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO)
5006 ? AMDGPU::S_ADDC_U32
5007 : AMDGPU::S_SUBB_U32;
5009 Register RegOp0 =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5010 BuildMI(*BB, MII,
DL,
TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp0)
5015 Register RegOp1 =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5016 BuildMI(*BB, MII,
DL,
TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp1)
5020 Register RegOp2 =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5022 BuildMI(*BB, MII,
DL,
TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp2)
5028 unsigned WaveSize =
TRI->getRegSizeInBits(*Src2RC);
5029 assert(WaveSize == 64 || WaveSize == 32);
5031 if (WaveSize == 64) {
5032 if (ST.hasScalarCompareEq64()) {
5038 TRI->getSubRegisterClass(Src2RC, AMDGPU::sub0);
5040 MII,
MRI, Src2, Src2RC, AMDGPU::sub0, SubRC);
5042 MII,
MRI, Src2, Src2RC, AMDGPU::sub1, SubRC);
5043 Register Src2_32 =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5045 BuildMI(*BB, MII,
DL,
TII->get(AMDGPU::S_OR_B32), Src2_32)
5062 (WaveSize == 64) ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32;
5068 MI.eraseFromParent();
5071 case AMDGPU::SI_INIT_M0: {
5073 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
5074 .
add(
MI.getOperand(0));
5075 MI.eraseFromParent();
5078 case AMDGPU::GET_GROUPSTATICSIZE: {
5083 .
add(
MI.getOperand(0))
5085 MI.eraseFromParent();
5088 case AMDGPU::GET_SHADERCYCLESHILO: {
5102 using namespace AMDGPU::Hwreg;
5103 Register RegHi1 =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5105 .
addImm(HwregEncoding::encode(ID_SHADER_CYCLES_HI, 0, 32));
5106 Register RegLo1 =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5108 .
addImm(HwregEncoding::encode(ID_SHADER_CYCLES, 0, 32));
5109 Register RegHi2 =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5111 .
addImm(HwregEncoding::encode(ID_SHADER_CYCLES_HI, 0, 32));
5115 Register RegLo =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5120 .
add(
MI.getOperand(0))
5125 MI.eraseFromParent();
5128 case AMDGPU::SI_INDIRECT_SRC_V1:
5129 case AMDGPU::SI_INDIRECT_SRC_V2:
5130 case AMDGPU::SI_INDIRECT_SRC_V4:
5131 case AMDGPU::SI_INDIRECT_SRC_V8:
5132 case AMDGPU::SI_INDIRECT_SRC_V9:
5133 case AMDGPU::SI_INDIRECT_SRC_V10:
5134 case AMDGPU::SI_INDIRECT_SRC_V11:
5135 case AMDGPU::SI_INDIRECT_SRC_V12:
5136 case AMDGPU::SI_INDIRECT_SRC_V16:
5137 case AMDGPU::SI_INDIRECT_SRC_V32:
5139 case AMDGPU::SI_INDIRECT_DST_V1:
5140 case AMDGPU::SI_INDIRECT_DST_V2:
5141 case AMDGPU::SI_INDIRECT_DST_V4:
5142 case AMDGPU::SI_INDIRECT_DST_V8:
5143 case AMDGPU::SI_INDIRECT_DST_V9:
5144 case AMDGPU::SI_INDIRECT_DST_V10:
5145 case AMDGPU::SI_INDIRECT_DST_V11:
5146 case AMDGPU::SI_INDIRECT_DST_V12:
5147 case AMDGPU::SI_INDIRECT_DST_V16:
5148 case AMDGPU::SI_INDIRECT_DST_V32:
5150 case AMDGPU::SI_KILL_F32_COND_IMM_PSEUDO:
5151 case AMDGPU::SI_KILL_I1_PSEUDO:
5153 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
5162 Register SrcCond =
MI.getOperand(3).getReg();
5164 Register DstLo =
MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5165 Register DstHi =
MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5166 const auto *CondRC =
TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
5167 Register SrcCondCopy =
MRI.createVirtualRegister(CondRC);
5171 : &AMDGPU::VReg_64RegClass;
5174 : &AMDGPU::VReg_64RegClass;
5177 TRI->getSubRegisterClass(Src0RC, AMDGPU::sub0);
5179 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1);
5182 MI,
MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
5184 MI,
MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
5187 MI,
MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
5189 MI,
MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
5211 MI.eraseFromParent();
5214 case AMDGPU::SI_BR_UNDEF: {
5218 .
add(
MI.getOperand(0));
5220 MI.eraseFromParent();
5223 case AMDGPU::ADJCALLSTACKUP:
5224 case AMDGPU::ADJCALLSTACKDOWN: {
5231 case AMDGPU::SI_CALL_ISEL: {
5235 unsigned ReturnAddrReg =
TII->getRegisterInfo().getReturnAddressReg(*MF);
5238 MIB =
BuildMI(*BB,
MI,
DL,
TII->get(AMDGPU::SI_CALL), ReturnAddrReg);
5244 MI.eraseFromParent();
5247 case AMDGPU::V_ADD_CO_U32_e32:
5248 case AMDGPU::V_SUB_CO_U32_e32:
5249 case AMDGPU::V_SUBREV_CO_U32_e32: {
5252 unsigned Opc =
MI.getOpcode();
5254 bool NeedClampOperand =
false;
5255 if (
TII->pseudoToMCOpcode(Opc) == -1) {
5257 NeedClampOperand =
true;
5261 if (
TII->isVOP3(*
I)) {
5266 I.add(
MI.getOperand(1))
5267 .add(
MI.getOperand(2));
5268 if (NeedClampOperand)
5271 TII->legalizeOperands(*
I);
5273 MI.eraseFromParent();
5276 case AMDGPU::V_ADDC_U32_e32:
5277 case AMDGPU::V_SUBB_U32_e32:
5278 case AMDGPU::V_SUBBREV_U32_e32:
5281 TII->legalizeOperands(
MI);
5283 case AMDGPU::DS_GWS_INIT:
5284 case AMDGPU::DS_GWS_SEMA_BR:
5285 case AMDGPU::DS_GWS_BARRIER:
5286 TII->enforceOperandRCAlignment(
MI, AMDGPU::OpName::data0);
5288 case AMDGPU::DS_GWS_SEMA_V:
5289 case AMDGPU::DS_GWS_SEMA_P:
5290 case AMDGPU::DS_GWS_SEMA_RELEASE_ALL:
5298 case AMDGPU::S_SETREG_B32: {
5313 const unsigned WidthMask = maskTrailingOnes<unsigned>(Width);
5314 const unsigned SetMask = WidthMask <<
Offset;
5317 unsigned SetDenormOp = 0;
5318 unsigned SetRoundOp = 0;
5326 SetRoundOp = AMDGPU::S_ROUND_MODE;
5327 SetDenormOp = AMDGPU::S_DENORM_MODE;
5329 SetRoundOp = AMDGPU::S_ROUND_MODE;
5331 SetDenormOp = AMDGPU::S_DENORM_MODE;
5334 if (SetRoundOp || SetDenormOp) {
5337 if (Def && Def->isMoveImmediate() && Def->getOperand(1).isImm()) {
5338 unsigned ImmVal = Def->getOperand(1).getImm();
5352 MI.eraseFromParent();
5361 MI.setDesc(
TII->get(AMDGPU::S_SETREG_B32_mode));
5365 case AMDGPU::S_INVERSE_BALLOT_U32:
5366 case AMDGPU::S_INVERSE_BALLOT_U64: {
5371 const Register DstReg =
MI.getOperand(0).getReg();
5372 Register MaskReg =
MI.getOperand(1).getReg();
5374 const bool IsVALU =
TRI->isVectorRegister(
MRI, MaskReg);
5377 MaskReg =
TII->readlaneVGPRToSGPR(MaskReg,
MI,
MRI);
5381 MI.eraseFromParent();
5384 case AMDGPU::ENDPGM_TRAP: {
5387 MI.setDesc(
TII->get(AMDGPU::S_ENDPGM));
5405 MI.eraseFromParent();
5408 case AMDGPU::SIMULATED_TRAP: {
5412 TII->insertSimulatedTrap(
MRI, *BB,
MI,
MI.getDebugLoc());
5413 MI.eraseFromParent();
5450 return (VT == MVT::i16) ? MVT::i16 : MVT::i32;
5537 EVT VT =
N->getValueType(0);
5541 if (VT == MVT::f16) {
5557 unsigned Opc =
Op.getOpcode();
5558 EVT VT =
Op.getValueType();
5559 assert(VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 ||
5560 VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v16i16 ||
5561 VT == MVT::v16f16 || VT == MVT::v8f32 || VT == MVT::v16f32 ||
5562 VT == MVT::v32f32 || VT == MVT::v32i16 || VT == MVT::v32f16);
5580 unsigned Opc =
Op.getOpcode();
5581 EVT VT =
Op.getValueType();
5582 assert(VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 ||
5583 VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v16i16 ||
5584 VT == MVT::v16f16 || VT == MVT::v8f32 || VT == MVT::v16f32 ||
5585 VT == MVT::v32f32 || VT == MVT::v32i16 || VT == MVT::v32f16);
5604 unsigned Opc =
Op.getOpcode();
5605 EVT VT =
Op.getValueType();
5606 assert(VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v8i16 ||
5607 VT == MVT::v8f16 || VT == MVT::v4f32 || VT == MVT::v16i16 ||
5608 VT == MVT::v16f16 || VT == MVT::v8f32 || VT == MVT::v16f32 ||
5609 VT == MVT::v32f32 || VT == MVT::v32f16 || VT == MVT::v32i16 ||
5610 VT == MVT::v4bf16 || VT == MVT::v8bf16 || VT == MVT::v16bf16 ||
5611 VT == MVT::v32bf16);
5617 : std::pair(Op0, Op0);
5636 switch (
Op.getOpcode()) {
5642 assert((!Result.getNode() ||
5643 Result.getNode()->getNumValues() == 2) &&
5644 "Load should return a value and a chain");
5648 EVT VT =
Op.getValueType();
5650 return lowerFSQRTF32(
Op, DAG);
5652 return lowerFSQRTF64(
Op, DAG);
5657 return LowerTrig(
Op, DAG);
5666 return LowerGlobalAddress(MFI,
Op, DAG);
5673 return lowerINSERT_SUBVECTOR(
Op, DAG);
5675 return lowerINSERT_VECTOR_ELT(
Op, DAG);
5677 return lowerEXTRACT_VECTOR_ELT(
Op, DAG);
5679 return lowerVECTOR_SHUFFLE(
Op, DAG);
5681 return lowerSCALAR_TO_VECTOR(
Op, DAG);
5683 return lowerBUILD_VECTOR(
Op, DAG);
5686 return lowerFP_ROUND(
Op, DAG);
5691 if (
Op.getOperand(0)->getValueType(0) != MVT::f32)
5695 int RoundMode =
Op.getConstantOperandVal(1);
5703 return DAG.
getNode(Opc,
DL,
Op.getNode()->getVTList(),
Op->getOperand(0));
5706 return lowerTRAP(
Op, DAG);
5708 return lowerDEBUGTRAP(
Op, DAG);
5716 return lowerFMINNUM_FMAXNUM(
Op, DAG);
5719 return lowerFLDEXP(
Op, DAG);
5744 return lowerMUL(
Op, DAG);
5747 return lowerXMULO(
Op, DAG);
5750 return lowerXMUL_LOHI(
Op, DAG);
5781 EVT FittingLoadVT = LoadVT;
5813SDValue SITargetLowering::adjustLoadValueType(
unsigned Opcode,
5817 bool IsIntrinsic)
const {
5821 EVT LoadVT =
M->getValueType(0);
5823 EVT EquivLoadVT = LoadVT;
5842 VTList, Ops,
M->getMemoryVT(),
5843 M->getMemOperand());
5854 EVT LoadVT =
M->getValueType(0);
5860 assert(
M->getNumValues() == 2 ||
M->getNumValues() == 3);
5861 bool IsTFE =
M->getNumValues() == 3;
5880 return handleByteShortBufferLoads(DAG, LoadVT,
DL, Ops,
M->getMemOperand());
5883 return getMemIntrinsicNode(Opc,
DL,
M->getVTList(), Ops, IntVT,
5884 M->getMemOperand(), DAG);
5889 SDValue MemNode = getMemIntrinsicNode(Opc,
DL, VTList, Ops, CastVT,
5890 M->getMemOperand(), DAG);
5898 EVT VT =
N->getValueType(0);
5899 unsigned CondCode =
N->getConstantOperandVal(3);
5910 EVT CmpVT =
LHS.getValueType();
5911 if (CmpVT == MVT::i16 && !TLI.
isTypeLegal(MVT::i16)) {
5932 EVT VT =
N->getValueType(0);
5934 unsigned CondCode =
N->getConstantOperandVal(3);
5943 if (CmpVT == MVT::f16 && !TLI.
isTypeLegal(CmpVT)) {
5961 EVT VT =
N->getValueType(0);
5968 Src.getOperand(1), Src.getOperand(2));
5979 Exec = AMDGPU::EXEC_LO;
5981 Exec = AMDGPU::EXEC;
5999 switch (
N->getOpcode()) {
6011 unsigned IID =
N->getConstantOperandVal(0);
6013 case Intrinsic::amdgcn_make_buffer_rsrc:
6014 Results.push_back(lowerPointerAsRsrcIntrin(
N, DAG));
6016 case Intrinsic::amdgcn_cvt_pkrtz: {
6025 case Intrinsic::amdgcn_cvt_pknorm_i16:
6026 case Intrinsic::amdgcn_cvt_pknorm_u16:
6027 case Intrinsic::amdgcn_cvt_pk_i16:
6028 case Intrinsic::amdgcn_cvt_pk_u16: {
6034 if (IID == Intrinsic::amdgcn_cvt_pknorm_i16)
6036 else if (IID == Intrinsic::amdgcn_cvt_pknorm_u16)
6038 else if (IID == Intrinsic::amdgcn_cvt_pk_i16)
6043 EVT VT =
N->getValueType(0);
6052 case Intrinsic::amdgcn_s_buffer_load: {
6064 EVT VT =
Op.getValueType();
6065 assert(VT == MVT::i8 &&
"Expected 8-bit s_buffer_load intrinsics.\n");
6077 if (!
Offset->isDivergent()) {
6096 LoadVal = handleByteShortBufferLoads(DAG, VT,
DL, Ops, MMO);
6108 for (
unsigned I = 0;
I < Res.getNumOperands();
I++) {
6109 Results.push_back(Res.getOperand(
I));
6113 Results.push_back(Res.getValue(1));
6122 EVT VT =
N->getValueType(0);
6127 EVT SelectVT = NewVT;
6128 if (NewVT.
bitsLT(MVT::i32)) {
6131 SelectVT = MVT::i32;
6137 if (NewVT != SelectVT)
6143 if (
N->getValueType(0) != MVT::v2f16)
6156 if (
N->getValueType(0) != MVT::v2f16)
6169 if (
N->getValueType(0) != MVT::f16)
6187 if (
I.getUse().get() !=
Value)
6190 if (
I->getOpcode() == Opcode)
6196unsigned SITargetLowering::isCFIntrinsic(
const SDNode *
Intr)
const {
6198 switch (
Intr->getConstantOperandVal(1)) {
6199 case Intrinsic::amdgcn_if:
6201 case Intrinsic::amdgcn_else:
6203 case Intrinsic::amdgcn_loop:
6205 case Intrinsic::amdgcn_end_cf:
6253 SDNode *
Intr = BRCOND.getOperand(1).getNode();
6266 assert(BR &&
"brcond missing unconditional branch user");
6267 Target = BR->getOperand(1);
6270 unsigned CFNode = isCFIntrinsic(
Intr);
6289 Ops.
append(
Intr->op_begin() + (HaveChain ? 2 : 1),
Intr->op_end());
6319 for (
unsigned i = 1, e =
Intr->getNumValues() - 1; i != e; ++i) {
6336 Intr->getOperand(0));
6343 MVT VT =
Op.getSimpleValueType();
6346 if (
Op.getConstantOperandVal(0) != 0)
6352 if (
Info->isEntryFunction())
6370 return Op.getValueType().bitsLE(VT) ?
6377 assert(
Op.getValueType() == MVT::f16 &&
6378 "Do not know how to custom lower FP_ROUND for non-f16 type");
6381 EVT SrcVT = Src.getValueType();
6382 if (SrcVT != MVT::f64)
6398 EVT VT =
Op.getValueType();
6401 bool IsIEEEMode =
Info->getMode().IEEE;
6410 if (VT == MVT::v4f16 || VT == MVT::v8f16 || VT == MVT::v16f16 ||
6418 EVT VT =
Op.getValueType();
6422 EVT ExpVT =
Exp.getValueType();
6423 if (ExpVT == MVT::i16)
6444 {
Op.getOperand(0),
Op.getOperand(1), TruncExp});
6452 EVT VT =
Op.getValueType();
6458 assert(VT == MVT::i64 &&
"The following code is a special for s_mul_u64");
6485 if (
Op->isDivergent())
6498 if (Op0LeadingZeros >= 32 && Op1LeadingZeros >= 32)
6500 DAG.
getMachineNode(AMDGPU::S_MUL_U64_U32_PSEUDO, SL, VT, Op0, Op1), 0);
6503 if (Op0SignBits >= 33 && Op1SignBits >= 33)
6505 DAG.
getMachineNode(AMDGPU::S_MUL_I64_I32_PSEUDO, SL, VT, Op0, Op1), 0);
6511 EVT VT =
Op.getValueType();
6518 const APInt &
C = RHSC->getAPIntValue();
6520 if (
C.isPowerOf2()) {
6522 bool UseArithShift =
isSigned && !
C.isMinSignedValue();
6527 SL, VT, Result, ShiftAmt),
6547 if (
Op->isDivergent()) {
6564 return lowerTrapEndpgm(
Op, DAG);
6567 lowerTrapHsaQueuePtr(
Op, DAG);
6570SDValue SITargetLowering::lowerTrapEndpgm(
6578 const SDLoc &
DL,
Align Alignment, ImplicitParameter Param)
const {
6588SDValue SITargetLowering::lowerTrapHsaQueuePtr(
6598 loadImplicitKernelArgument(DAG, MVT::i64, SL,
Align(8),
QUEUE_PTR);
6604 if (UserSGPR == AMDGPU::NoRegister) {
6629SDValue SITargetLowering::lowerTrapHsa(
6655 "debugtrap handler not supported",
6671SDValue SITargetLowering::getSegmentAperture(
unsigned AS,
const SDLoc &
DL,
6675 ? AMDGPU::SRC_SHARED_BASE
6676 : AMDGPU::SRC_PRIVATE_BASE;
6699 {SDValue(Mov, 0), DAG.getConstant(32, DL, MVT::i64)}));
6708 return loadImplicitKernelArgument(DAG, MVT::i32,
DL,
Align(4), Param);
6714 if (UserSGPR == AMDGPU::NoRegister) {
6721 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
6744 if (isa<FrameIndexSDNode>(Val) || isa<GlobalAddressSDNode>(Val) ||
6745 isa<BasicBlockSDNode>(Val))
6748 if (
auto *ConstVal = dyn_cast<ConstantSDNode>(Val))
6749 return ConstVal->getSExtValue() !=
TM.getNullPointerValue(AddrSpace);
6763 unsigned DestAS, SrcAS;
6765 bool IsNonNull =
false;
6766 if (
const auto *ASC = dyn_cast<AddrSpaceCastSDNode>(
Op)) {
6767 SrcAS = ASC->getSrcAddressSpace();
6768 Src = ASC->getOperand(0);
6769 DestAS = ASC->getDestAddressSpace();
6772 Op.getConstantOperandVal(0) ==
6773 Intrinsic::amdgcn_addrspacecast_nonnull);
6774 Src =
Op->getOperand(1);
6775 SrcAS =
Op->getConstantOperandVal(2);
6776 DestAS =
Op->getConstantOperandVal(3);
6791 unsigned NullVal =
TM.getNullPointerValue(DestAS);
6805 SDValue Aperture = getSegmentAperture(SrcAS, SL, DAG);
6813 unsigned NullVal =
TM.getNullPointerValue(SrcAS);
6825 Op.getValueType() == MVT::i64) {
6834 Src.getValueType() == MVT::i64)
6858 EVT InsVT =
Ins.getValueType();
6861 unsigned IdxVal =
Idx->getAsZExtVal();
6866 assert(InsNumElts % 2 == 0 &&
"expect legal vector types");
6871 EVT NewInsVT = InsNumElts == 2 ? MVT::i32
6873 MVT::i32, InsNumElts / 2);
6878 for (
unsigned I = 0;
I != InsNumElts / 2; ++
I) {
6880 if (InsNumElts == 2) {
6893 for (
unsigned I = 0;
I != InsNumElts; ++
I) {
6915 auto KIdx = dyn_cast<ConstantSDNode>(
Idx);
6916 if (NumElts == 4 && EltSize == 16 && KIdx) {
6927 unsigned Idx = KIdx->getZExtValue();
6928 bool InsertLo =
Idx < 2;
6930 InsertLo ? LoVec : HiVec,
6945 if (isa<ConstantSDNode>(
Idx))
6951 assert(VecSize <= 64 &&
"Expected target vector size to be <= 64 bits");
6957 const auto EltMask = maskTrailingOnes<uint64_t>(EltSize);
6973 DAG.
getNOT(SL, BFM, IntVT), BCVec);
6985 EVT ResultVT =
Op.getValueType();
6998 if (
SDValue Combined = performExtractVectorEltCombine(
Op.getNode(), DCI))
7001 if (VecSize == 128 || VecSize == 256 || VecSize == 512) {
7006 if (VecSize == 128) {
7014 }
else if (VecSize == 256) {
7017 for (
unsigned P = 0;
P < 4; ++
P) {
7023 Parts[0], Parts[1]));
7025 Parts[2], Parts[3]));
7031 for (
unsigned P = 0;
P < 8; ++
P) {
7038 Parts[0], Parts[1], Parts[2], Parts[3]));
7041 Parts[4], Parts[5],Parts[6], Parts[7]));
7044 EVT IdxVT =
Idx.getValueType();
7061 Src = DAG.
getBitcast(Src.getValueType().changeTypeToInteger(), Src);
7076 if (ResultVT == MVT::f16 || ResultVT == MVT::bf16) {
7086 return Mask[Elt + 1] == Mask[Elt] + 1 && (Mask[Elt] % 2 == 0);
7092 EVT ResultVT =
Op.getValueType();
7095 EVT PackVT = ResultVT.
isInteger() ? MVT::v2i16 : MVT::v2f16;
7097 int SrcNumElts =
Op.getOperand(0).getValueType().getVectorNumElements();
7113 int VecIdx =
Idx < SrcNumElts ? 0 : 1;
7114 int EltIdx =
Idx < SrcNumElts ?
Idx :
Idx - SrcNumElts;
7122 int VecIdx0 = Idx0 < SrcNumElts ? 0 : 1;
7123 int VecIdx1 = Idx1 < SrcNumElts ? 0 : 1;
7124 int EltIdx0 = Idx0 < SrcNumElts ? Idx0 : Idx0 - SrcNumElts;
7125 int EltIdx1 = Idx1 < SrcNumElts ? Idx1 : Idx1 - SrcNumElts;
7144 EVT ResultVT =
Op.getValueType();
7160 EVT VT =
Op.getValueType();
7162 if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v8i16 ||
7163 VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) {
7182 { CastLo, CastHi });
7186 if (VT == MVT::v16i16 || VT == MVT::v16f16 || VT == MVT::v16bf16) {
7193 for (
unsigned P = 0;
P < 4; ++
P)
7194 Parts[
P].push_back(
Op.getOperand(
I +
P * E));
7197 for (
unsigned P = 0;
P < 4; ++
P) {
7207 if (VT == MVT::v32i16 || VT == MVT::v32f16 || VT == MVT::v32bf16) {
7214 for (
unsigned P = 0;
P < 8; ++
P)
7215 Parts[
P].push_back(
Op.getOperand(
I +
P * E));
7218 for (
unsigned P = 0;
P < 8; ++
P) {
7228 assert(VT == MVT::v2f16 || VT == MVT::v2i16 || VT == MVT::v2bf16);
7280 assert(isInt<32>(
Offset + 4) &&
"32-bit offset is expected!");
7318 EVT PtrVT =
Op.getValueType();
7334 assert(PtrVT == MVT::i32 &&
"32-bit pointer is expected.");
7407 SDValue Param = lowerKernargMemParameter(
7417 "non-hsa intrinsic with hsa target",
7426 "intrinsic not supported on subtarget",
7436 unsigned NumElts = Elts.
size();
7438 if (NumElts <= 12) {
7447 for (
unsigned i = 0; i < Elts.
size(); ++i) {
7453 for (
unsigned i = Elts.
size(); i < NumElts; ++i)
7454 VecElts[i] = DAG.
getUNDEF(MVT::f32);
7463 EVT SrcVT = Src.getValueType();
7484 bool Unpacked,
bool IsD16,
int DMaskPop,
7485 int NumVDataDwords,
bool IsAtomicPacked16Bit,
7488 EVT ReqRetVT = ResultTypes[0];
7490 int NumDataDwords = ((IsD16 && !Unpacked) || IsAtomicPacked16Bit)
7491 ? (ReqRetNumElts + 1) / 2
7494 int MaskPopDwords = (!IsD16 || (IsD16 && Unpacked)) ?
7495 DMaskPop : (DMaskPop + 1) / 2;
7497 MVT DataDwordVT = NumDataDwords == 1 ?
7500 MVT MaskPopVT = MaskPopDwords == 1 ?
7506 if (DMaskPop > 0 &&
Data.getValueType() != MaskPopVT) {
7517 if (DataDwordVT.
isVector() && !IsAtomicPacked16Bit)
7519 NumDataDwords - MaskPopDwords);
7524 EVT LegalReqRetVT = ReqRetVT;
7526 if (!
Data.getValueType().isInteger())
7528 Data.getValueType().changeTypeToInteger(),
Data);
7549 if (Result->getNumValues() == 1)
7556 SDValue *LWE,
bool &IsTexFail) {
7557 auto TexFailCtrlConst = cast<ConstantSDNode>(TexFailCtrl.
getNode());
7576 unsigned DimIdx,
unsigned EndIdx,
7577 unsigned NumGradients) {
7579 for (
unsigned I = DimIdx;
I < EndIdx;
I++) {
7587 if (((
I + 1) >= EndIdx) ||
7588 ((NumGradients / 2) % 2 == 1 && (
I == DimIdx + (NumGradients / 2) - 1 ||
7589 I == DimIdx + NumGradients - 1))) {
7590 if (
Addr.getValueType() != MVT::i16)
7611 unsigned IntrOpcode =
Intr->BaseOpcode;
7623 bool AdjustRetType =
false;
7624 bool IsAtomicPacked16Bit =
false;
7627 const unsigned ArgOffset = WithChain ? 2 : 1;
7630 unsigned DMaskLanes = 0;
7632 if (BaseOpcode->Atomic) {
7633 VData =
Op.getOperand(2);
7635 IsAtomicPacked16Bit =
7636 (
Intr->BaseOpcode == AMDGPU::IMAGE_ATOMIC_PK_ADD_F16 ||
7637 Intr->BaseOpcode == AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16);
7640 if (BaseOpcode->AtomicX2) {
7647 ResultTypes[0] = Is64Bit ? MVT::v2i64 : MVT::v2i32;
7648 DMask = Is64Bit ? 0xf : 0x3;
7649 NumVDataDwords = Is64Bit ? 4 : 2;
7651 DMask = Is64Bit ? 0x3 : 0x1;
7652 NumVDataDwords = Is64Bit ? 2 : 1;
7655 DMask =
Op->getConstantOperandVal(ArgOffset +
Intr->DMaskIndex);
7658 if (BaseOpcode->Store) {
7659 VData =
Op.getOperand(2);
7667 VData = handleD16VData(VData, DAG,
true);
7684 (!LoadVT.
isVector() && DMaskLanes > 1))
7692 NumVDataDwords = (DMaskLanes + 1) / 2;
7694 NumVDataDwords = DMaskLanes;
7696 AdjustRetType =
true;
7700 unsigned VAddrEnd = ArgOffset +
Intr->VAddrEnd;
7705 Op.getOperand(ArgOffset +
Intr->GradientStart).getSimpleValueType();
7707 MVT GradPackVectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;
7708 IsG16 = VAddrScalarVT == MVT::f16 || VAddrScalarVT == MVT::i16;
7710 VAddrVT =
Op.getOperand(ArgOffset +
Intr->CoordStart).getSimpleValueType();
7712 MVT AddrPackVectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;
7713 IsA16 = VAddrScalarVT == MVT::f16 || VAddrScalarVT == MVT::i16;
7716 for (
unsigned I =
Intr->VAddrStart; I < Intr->GradientStart;
I++) {
7717 if (IsA16 && (
Op.getOperand(ArgOffset +
I).getValueType() == MVT::f16)) {
7718 assert(
I ==
Intr->BiasIndex &&
"Got unexpected 16-bit extra argument");
7723 {
Op.getOperand(ArgOffset +
I), DAG.
getUNDEF(MVT::f16)});
7727 "Bias needs to be converted to 16 bit in A16 mode");
7732 if (BaseOpcode->Gradients && !
ST->hasG16() && (IsA16 != IsG16)) {
7736 dbgs() <<
"Failed to lower image intrinsic: 16 bit addresses "
7737 "require 16 bit args for both gradients and addresses");
7742 if (!
ST->hasA16()) {
7743 LLVM_DEBUG(
dbgs() <<
"Failed to lower image intrinsic: Target does not "
7744 "support 16 bit addresses\n");
7754 if (BaseOpcode->Gradients && IsG16 &&
ST->hasG16()) {
7758 IntrOpcode = G16MappingInfo->
G16;
7766 ArgOffset +
Intr->GradientStart,
7767 ArgOffset +
Intr->CoordStart,
Intr->NumGradients);
7769 for (
unsigned I = ArgOffset +
Intr->GradientStart;
7770 I < ArgOffset + Intr->CoordStart;
I++)
7777 ArgOffset +
Intr->CoordStart, VAddrEnd,
7781 for (
unsigned I = ArgOffset +
Intr->CoordStart;
I < VAddrEnd;
I++)
7799 const unsigned NSAMaxSize =
ST->getNSAMaxSize(BaseOpcode->Sampler);
7800 const bool HasPartialNSAEncoding =
ST->hasPartialNSAEncoding();
7801 const bool UseNSA =
ST->hasNSAEncoding() &&
7802 VAddrs.
size() >=
ST->getNSAThreshold(MF) &&
7803 (VAddrs.
size() <= NSAMaxSize || HasPartialNSAEncoding);
7804 const bool UsePartialNSA =
7805 UseNSA && HasPartialNSAEncoding && VAddrs.
size() > NSAMaxSize;
7808 if (UsePartialNSA) {
7810 ArrayRef(VAddrs).drop_front(NSAMaxSize - 1));
7819 if (!BaseOpcode->Sampler) {
7823 Op.getConstantOperandVal(ArgOffset +
Intr->UnormIndex);
7825 Unorm = UnormConst ? True : False;
7830 SDValue TexFail =
Op.getOperand(ArgOffset +
Intr->TexFailCtrlIndex);
7831 bool IsTexFail =
false;
7832 if (!
parseTexFail(TexFail, DAG, &TFE, &LWE, IsTexFail))
7843 NumVDataDwords += 1;
7844 AdjustRetType =
true;
7849 if (AdjustRetType) {
7851 if (DMaskLanes == 0 && !BaseOpcode->Store) {
7854 if (isa<MemSDNode>(
Op))
7859 EVT NewVT = NumVDataDwords > 1 ?
7863 ResultTypes[0] = NewVT;
7864 if (ResultTypes.size() == 3) {
7868 ResultTypes.erase(&ResultTypes[1]);
7872 unsigned CPol =
Op.getConstantOperandVal(ArgOffset +
Intr->CachePolicyIndex);
7873 if (BaseOpcode->Atomic)
7880 if (BaseOpcode->Store || BaseOpcode->Atomic)
7882 if (UsePartialNSA) {
7891 if (BaseOpcode->Sampler)
7896 if (!IsGFX12Plus || BaseOpcode->Sampler || BaseOpcode->MSAA)
7900 ST->hasFeature(AMDGPU::FeatureR128A16) ? True : False);
7908 if (!IsGFX12Plus || BaseOpcode->Sampler || BaseOpcode->MSAA)
7912 if (BaseOpcode->HasD16)
7914 if (isa<MemSDNode>(
Op))
7917 int NumVAddrDwords =
7923 NumVDataDwords, NumVAddrDwords);
7924 }
else if (IsGFX11Plus) {
7926 UseNSA ? AMDGPU::MIMGEncGfx11NSA
7927 : AMDGPU::MIMGEncGfx11Default,
7928 NumVDataDwords, NumVAddrDwords);
7929 }
else if (IsGFX10Plus) {
7931 UseNSA ? AMDGPU::MIMGEncGfx10NSA
7932 : AMDGPU::MIMGEncGfx10Default,
7933 NumVDataDwords, NumVAddrDwords);
7937 NumVDataDwords, NumVAddrDwords);
7940 "requested image instruction is not supported on this GPU");
7945 NumVDataDwords, NumVAddrDwords);
7948 NumVDataDwords, NumVAddrDwords);
7954 if (
auto MemOp = dyn_cast<MemSDNode>(
Op)) {
7959 if (BaseOpcode->AtomicX2) {
7964 if (BaseOpcode->Store)
7968 NumVDataDwords, IsAtomicPacked16Bit,
DL);
7986 if (!
Offset->isDivergent()) {
8031 return handleByteShortBufferLoads(DAG, VT,
DL, Ops, MMO);
8035 unsigned NumLoads = 1;
8041 if (NumElts == 8 || NumElts == 16) {
8042 NumLoads = NumElts / 4;
8050 setBufferOffsets(
Offset, DAG, &Ops[3],
8051 NumLoads > 1 ?
Align(16 * NumLoads) :
Align(4));
8054 for (
unsigned i = 0; i < NumLoads; ++i) {
8060 if (NumElts == 8 || NumElts == 16)
8107 EVT VT =
Op.getValueType();
8109 unsigned IntrinsicID =
Op.getConstantOperandVal(0);
8113 switch (IntrinsicID) {
8114 case Intrinsic::amdgcn_implicit_buffer_ptr: {
8117 return getPreloadedValue(DAG, *MFI, VT,
8120 case Intrinsic::amdgcn_dispatch_ptr:
8121 case Intrinsic::amdgcn_queue_ptr: {
8124 MF.
getFunction(),
"unsupported hsa intrinsic without hsa target",
8130 auto RegID = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ?
8132 return getPreloadedValue(DAG, *MFI, VT, RegID);
8134 case Intrinsic::amdgcn_implicitarg_ptr: {
8136 return getImplicitArgPtr(DAG,
DL);
8137 return getPreloadedValue(DAG, *MFI, VT,
8140 case Intrinsic::amdgcn_kernarg_segment_ptr: {
8146 return getPreloadedValue(DAG, *MFI, VT,
8149 case Intrinsic::amdgcn_dispatch_id: {
8152 case Intrinsic::amdgcn_rcp:
8154 case Intrinsic::amdgcn_rsq:
8156 case Intrinsic::amdgcn_rsq_legacy:
8160 case Intrinsic::amdgcn_rcp_legacy:
8164 case Intrinsic::amdgcn_rsq_clamp: {
8178 case Intrinsic::r600_read_ngroups_x:
8182 return lowerKernargMemParameter(DAG, VT, VT,
DL, DAG.
getEntryNode(),
8185 case Intrinsic::r600_read_ngroups_y:
8189 return lowerKernargMemParameter(DAG, VT, VT,
DL, DAG.
getEntryNode(),
8192 case Intrinsic::r600_read_ngroups_z:
8196 return lowerKernargMemParameter(DAG, VT, VT,
DL, DAG.
getEntryNode(),
8199 case Intrinsic::r600_read_global_size_x:
8203 return lowerKernargMemParameter(DAG, VT, VT,
DL, DAG.
getEntryNode(),
8206 case Intrinsic::r600_read_global_size_y:
8210 return lowerKernargMemParameter(DAG, VT, VT,
DL, DAG.
getEntryNode(),
8213 case Intrinsic::r600_read_global_size_z:
8217 return lowerKernargMemParameter(DAG, VT, VT,
DL, DAG.
getEntryNode(),
8220 case Intrinsic::r600_read_local_size_x:
8224 return lowerImplicitZextParam(DAG,
Op, MVT::i16,
8226 case Intrinsic::r600_read_local_size_y:
8230 return lowerImplicitZextParam(DAG,
Op, MVT::i16,
8232 case Intrinsic::r600_read_local_size_z:
8236 return lowerImplicitZextParam(DAG,
Op, MVT::i16,
8238 case Intrinsic::amdgcn_workgroup_id_x:
8239 return getPreloadedValue(DAG, *MFI, VT,
8241 case Intrinsic::amdgcn_workgroup_id_y:
8242 return getPreloadedValue(DAG, *MFI, VT,
8244 case Intrinsic::amdgcn_workgroup_id_z:
8245 return getPreloadedValue(DAG, *MFI, VT,
8247 case Intrinsic::amdgcn_wave_id:
8248 return lowerWaveID(DAG,
Op);
8249 case Intrinsic::amdgcn_lds_kernel_id: {
8251 return getLDSKernelId(DAG,
DL);
8252 return getPreloadedValue(DAG, *MFI, VT,
8255 case Intrinsic::amdgcn_workitem_id_x:
8256 return lowerWorkitemID(DAG,
Op, 0, MFI->getArgInfo().WorkItemIDX);
8257 case Intrinsic::amdgcn_workitem_id_y:
8258 return lowerWorkitemID(DAG,
Op, 1, MFI->getArgInfo().WorkItemIDY);
8259 case Intrinsic::amdgcn_workitem_id_z:
8260 return lowerWorkitemID(DAG,
Op, 2, MFI->getArgInfo().WorkItemIDZ);
8261 case Intrinsic::amdgcn_wavefrontsize:
8264 case Intrinsic::amdgcn_s_buffer_load: {
8265 unsigned CPol =
Op.getConstantOperandVal(3);
8272 return lowerSBuffer(VT,
DL,
Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3),
8275 case Intrinsic::amdgcn_fdiv_fast:
8276 return lowerFDIV_FAST(
Op, DAG);
8277 case Intrinsic::amdgcn_sin:
8280 case Intrinsic::amdgcn_cos:
8283 case Intrinsic::amdgcn_mul_u24:
8285 case Intrinsic::amdgcn_mul_i24:
8288 case Intrinsic::amdgcn_log_clamp: {
8294 case Intrinsic::amdgcn_fract:
8297 case Intrinsic::amdgcn_class:
8299 Op.getOperand(1),
Op.getOperand(2));
8300 case Intrinsic::amdgcn_div_fmas:
8302 Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3),
8305 case Intrinsic::amdgcn_div_fixup:
8307 Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3));
8309 case Intrinsic::amdgcn_div_scale: {
8322 SDValue Src0 =
Param->isAllOnes() ? Numerator : Denominator;
8325 Denominator, Numerator);
8327 case Intrinsic::amdgcn_icmp: {
8329 if (
Op.getOperand(1).getValueType() == MVT::i1 &&
8330 Op.getConstantOperandVal(2) == 0 &&
8335 case Intrinsic::amdgcn_fcmp: {
8338 case Intrinsic::amdgcn_ballot:
8340 case Intrinsic::amdgcn_fmed3:
8342 Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3));
8343 case Intrinsic::amdgcn_fdot2:
8345 Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3),
8347 case Intrinsic::amdgcn_fmul_legacy:
8349 Op.getOperand(1),
Op.getOperand(2));
8350 case Intrinsic::amdgcn_sffbh:
8352 case Intrinsic::amdgcn_sbfe:
8354 Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3));
8355 case Intrinsic::amdgcn_ubfe:
8357 Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3));
8358 case Intrinsic::amdgcn_cvt_pkrtz:
8359 case Intrinsic::amdgcn_cvt_pknorm_i16:
8360 case Intrinsic::amdgcn_cvt_pknorm_u16:
8361 case Intrinsic::amdgcn_cvt_pk_i16:
8362 case Intrinsic::amdgcn_cvt_pk_u16: {
8364 EVT VT =
Op.getValueType();
8367 if (IntrinsicID == Intrinsic::amdgcn_cvt_pkrtz)
8369 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pknorm_i16)
8371 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pknorm_u16)
8373 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pk_i16)
8379 return DAG.
getNode(Opcode,
DL, VT,
Op.getOperand(1),
Op.getOperand(2));
8382 Op.getOperand(1),
Op.getOperand(2));
8385 case Intrinsic::amdgcn_fmad_ftz:
8387 Op.getOperand(2),
Op.getOperand(3));
8389 case Intrinsic::amdgcn_if_break:
8391 Op->getOperand(1),
Op->getOperand(2)), 0);
8393 case Intrinsic::amdgcn_groupstaticsize: {
8405 case Intrinsic::amdgcn_is_shared:
8406 case Intrinsic::amdgcn_is_private: {
8408 unsigned AS = (IntrinsicID == Intrinsic::amdgcn_is_shared) ?
8410 SDValue Aperture = getSegmentAperture(AS, SL, DAG);
8418 case Intrinsic::amdgcn_perm:
8420 Op.getOperand(2),
Op.getOperand(3));
8421 case Intrinsic::amdgcn_reloc_constant: {
8425 auto RelocSymbol = cast<GlobalVariable>(
8431 case Intrinsic::amdgcn_swmmac_f16_16x16x32_f16:
8432 case Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16:
8433 case Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16:
8434 case Intrinsic::amdgcn_swmmac_f32_16x16x32_f16:
8435 case Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8:
8436 case Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8:
8437 case Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8:
8438 case Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8: {
8439 if (
Op.getOperand(4).getValueType() == MVT::i32)
8445 Op.getOperand(0),
Op.getOperand(1),
Op.getOperand(2),
8446 Op.getOperand(3), IndexKeyi32);
8448 case Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4:
8449 case Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8:
8450 case Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4: {
8451 if (
Op.getOperand(6).getValueType() == MVT::i32)
8457 {Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
8458 Op.getOperand(3), Op.getOperand(4), Op.getOperand(5),
8459 IndexKeyi32, Op.getOperand(7)});
8461 case Intrinsic::amdgcn_addrspacecast_nonnull:
8462 return lowerADDRSPACECAST(
Op, DAG);
8466 return lowerImage(
Op, ImageDimIntr, DAG,
false);
8477 return DAG.
getRegister(AMDGPU::SGPR_NULL, MVT::i32);
8483 unsigned NewOpcode)
const {
8487 SDValue Rsrc = bufferRsrcPtrToVector(
Op.getOperand(3), DAG);
8488 auto Offsets = splitBufferOffsets(
Op.getOperand(4), DAG);
8502 auto *
M = cast<MemSDNode>(
Op);
8506 M->getMemOperand());
8517 unsigned NewOpcode)
const {
8521 SDValue Rsrc = bufferRsrcPtrToVector(
Op.getOperand(3), DAG);
8522 auto Offsets = splitBufferOffsets(
Op.getOperand(5), DAG);
8536 auto *
M = cast<MemSDNode>(
Op);
8540 M->getMemOperand());
8545 unsigned IntrID =
Op.getConstantOperandVal(1);
8549 case Intrinsic::amdgcn_ds_ordered_add:
8550 case Intrinsic::amdgcn_ds_ordered_swap: {
8555 unsigned IndexOperand =
M->getConstantOperandVal(7);
8556 unsigned WaveRelease =
M->getConstantOperandVal(8);
8557 unsigned WaveDone =
M->getConstantOperandVal(9);
8559 unsigned OrderedCountIndex = IndexOperand & 0x3f;
8560 IndexOperand &= ~0x3f;
8561 unsigned CountDw = 0;
8564 CountDw = (IndexOperand >> 24) & 0xf;
8565 IndexOperand &= ~(0xf << 24);
8567 if (CountDw < 1 || CountDw > 4) {
8569 "ds_ordered_count: dword count must be between 1 and 4");
8576 if (WaveDone && !WaveRelease)
8579 unsigned Instruction = IntrID == Intrinsic::amdgcn_ds_ordered_add ? 0 : 1;
8580 unsigned ShaderType =
8582 unsigned Offset0 = OrderedCountIndex << 2;
8583 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (
Instruction << 4);
8586 Offset1 |= (CountDw - 1) << 6;
8589 Offset1 |= ShaderType << 2;
8591 unsigned Offset = Offset0 | (Offset1 << 8);
8600 M->getVTList(), Ops,
M->getMemoryVT(),
8601 M->getMemOperand());
8603 case Intrinsic::amdgcn_ds_fadd: {
8607 case Intrinsic::amdgcn_ds_fadd:
8613 M->getOperand(0),
M->getOperand(2),
M->getOperand(3),
8614 M->getMemOperand());
8616 case Intrinsic::amdgcn_ds_fmin:
8617 case Intrinsic::amdgcn_ds_fmax: {
8621 case Intrinsic::amdgcn_ds_fmin:
8624 case Intrinsic::amdgcn_ds_fmax:
8637 M->getMemoryVT(),
M->getMemOperand());
8639 case Intrinsic::amdgcn_buffer_load:
8640 case Intrinsic::amdgcn_buffer_load_format: {
8641 unsigned Glc =
Op.getConstantOperandVal(5);
8642 unsigned Slc =
Op.getConstantOperandVal(6);
8654 setBufferOffsets(
Op.getOperand(4), DAG, &Ops[3]);
8656 unsigned Opc = (IntrID == Intrinsic::amdgcn_buffer_load) ?
8659 EVT VT =
Op.getValueType();
8661 auto *
M = cast<MemSDNode>(
Op);
8662 EVT LoadVT =
Op.getValueType();
8670 return handleByteShortBufferLoads(DAG, LoadVT,
DL, Ops,
8671 M->getMemOperand());
8673 return getMemIntrinsicNode(Opc,
DL,
Op->getVTList(), Ops, IntVT,
8674 M->getMemOperand(), DAG);
8676 case Intrinsic::amdgcn_raw_buffer_load:
8677 case Intrinsic::amdgcn_raw_ptr_buffer_load:
8678 case Intrinsic::amdgcn_raw_buffer_load_format:
8679 case Intrinsic::amdgcn_raw_ptr_buffer_load_format: {
8680 const bool IsFormat =
8681 IntrID == Intrinsic::amdgcn_raw_buffer_load_format ||
8682 IntrID == Intrinsic::amdgcn_raw_ptr_buffer_load_format;
8684 SDValue Rsrc = bufferRsrcPtrToVector(
Op.getOperand(2), DAG);
8685 auto Offsets = splitBufferOffsets(
Op.getOperand(3), DAG);
8698 auto *
M = cast<MemSDNode>(
Op);
8699 return lowerIntrinsicLoad(M, IsFormat, DAG, Ops);
8701 case Intrinsic::amdgcn_struct_buffer_load:
8702 case Intrinsic::amdgcn_struct_ptr_buffer_load:
8703 case Intrinsic::amdgcn_struct_buffer_load_format:
8704 case Intrinsic::amdgcn_struct_ptr_buffer_load_format: {
8705 const bool IsFormat =
8706 IntrID == Intrinsic::amdgcn_struct_buffer_load_format ||
8707 IntrID == Intrinsic::amdgcn_struct_ptr_buffer_load_format;
8709 SDValue Rsrc = bufferRsrcPtrToVector(
Op.getOperand(2), DAG);
8710 auto Offsets = splitBufferOffsets(
Op.getOperand(4), DAG);
8723 return lowerIntrinsicLoad(cast<MemSDNode>(
Op), IsFormat, DAG, Ops);
8725 case Intrinsic::amdgcn_tbuffer_load: {
8727 EVT LoadVT =
Op.getValueType();
8730 unsigned Dfmt =
Op.getConstantOperandVal(7);
8731 unsigned Nfmt =
Op.getConstantOperandVal(8);
8732 unsigned Glc =
Op.getConstantOperandVal(9);
8733 unsigned Slc =
Op.getConstantOperandVal(10);
8751 Op->getVTList(), Ops, LoadVT,
M->getMemOperand(),
8754 case Intrinsic::amdgcn_raw_tbuffer_load:
8755 case Intrinsic::amdgcn_raw_ptr_tbuffer_load: {
8757 EVT LoadVT =
Op.getValueType();
8758 SDValue Rsrc = bufferRsrcPtrToVector(
Op.getOperand(2), DAG);
8759 auto Offsets = splitBufferOffsets(
Op.getOperand(3), DAG);
8778 Op->getVTList(), Ops, LoadVT,
M->getMemOperand(),
8781 case Intrinsic::amdgcn_struct_tbuffer_load:
8782 case Intrinsic::amdgcn_struct_ptr_tbuffer_load: {
8784 EVT LoadVT =
Op.getValueType();
8785 SDValue Rsrc = bufferRsrcPtrToVector(
Op.getOperand(2), DAG);
8786 auto Offsets = splitBufferOffsets(
Op.getOperand(4), DAG);
8805 Op->getVTList(), Ops, LoadVT,
M->getMemOperand(),
8808 case Intrinsic::amdgcn_buffer_atomic_swap:
8809 case Intrinsic::amdgcn_buffer_atomic_add:
8810 case Intrinsic::amdgcn_buffer_atomic_sub:
8811 case Intrinsic::amdgcn_buffer_atomic_csub:
8812 case Intrinsic::amdgcn_buffer_atomic_smin:
8813 case Intrinsic::amdgcn_buffer_atomic_umin:
8814 case Intrinsic::amdgcn_buffer_atomic_smax:
8815 case Intrinsic::amdgcn_buffer_atomic_umax:
8816 case Intrinsic::amdgcn_buffer_atomic_and:
8817 case Intrinsic::amdgcn_buffer_atomic_or:
8818 case Intrinsic::amdgcn_buffer_atomic_xor:
8819 case Intrinsic::amdgcn_buffer_atomic_fadd: {
8820 unsigned Slc =
Op.getConstantOperandVal(6);
8833 setBufferOffsets(
Op.getOperand(5), DAG, &Ops[4]);
8835 EVT VT =
Op.getValueType();
8837 auto *
M = cast<MemSDNode>(
Op);
8838 unsigned Opcode = 0;
8841 case Intrinsic::amdgcn_buffer_atomic_swap:
8844 case Intrinsic::amdgcn_buffer_atomic_add:
8847 case Intrinsic::amdgcn_buffer_atomic_sub:
8850 case Intrinsic::amdgcn_buffer_atomic_csub:
8853 case Intrinsic::amdgcn_buffer_atomic_smin:
8856 case Intrinsic::amdgcn_buffer_atomic_umin:
8859 case Intrinsic::amdgcn_buffer_atomic_smax:
8862 case Intrinsic::amdgcn_buffer_atomic_umax:
8865 case Intrinsic::amdgcn_buffer_atomic_and:
8868 case Intrinsic::amdgcn_buffer_atomic_or:
8871 case Intrinsic::amdgcn_buffer_atomic_xor:
8874 case Intrinsic::amdgcn_buffer_atomic_fadd:
8882 M->getMemOperand());
8884 case Intrinsic::amdgcn_raw_buffer_atomic_fadd:
8885 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_fadd:
8887 case Intrinsic::amdgcn_raw_buffer_atomic_fadd_v2bf16:
8888 return lowerRawBufferAtomicIntrin(
Op, DAG,
8890 case Intrinsic::amdgcn_struct_buffer_atomic_fadd:
8891 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_fadd:
8893 case Intrinsic::amdgcn_struct_buffer_atomic_fadd_v2bf16:
8894 return lowerStructBufferAtomicIntrin(
Op, DAG,
8896 case Intrinsic::amdgcn_raw_buffer_atomic_fmin:
8897 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_fmin:
8899 case Intrinsic::amdgcn_struct_buffer_atomic_fmin:
8900 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_fmin:
8902 case Intrinsic::amdgcn_raw_buffer_atomic_fmax:
8903 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_fmax:
8905 case Intrinsic::amdgcn_struct_buffer_atomic_fmax:
8906 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_fmax:
8908 case Intrinsic::amdgcn_raw_buffer_atomic_swap:
8909 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_swap:
8911 case Intrinsic::amdgcn_raw_buffer_atomic_add:
8912 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_add:
8914 case Intrinsic::amdgcn_raw_buffer_atomic_sub:
8915 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_sub:
8917 case Intrinsic::amdgcn_raw_buffer_atomic_smin:
8918 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_smin:
8920 case Intrinsic::amdgcn_raw_buffer_atomic_umin:
8921 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_umin:
8923 case Intrinsic::amdgcn_raw_buffer_atomic_smax:
8924 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_smax:
8926 case Intrinsic::amdgcn_raw_buffer_atomic_umax:
8927 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_umax:
8929 case Intrinsic::amdgcn_raw_buffer_atomic_and:
8930 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_and:
8932 case Intrinsic::amdgcn_raw_buffer_atomic_or:
8933 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_or:
8935 case Intrinsic::amdgcn_raw_buffer_atomic_xor:
8936 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_xor:
8938 case Intrinsic::amdgcn_raw_buffer_atomic_inc:
8939 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_inc:
8941 case Intrinsic::amdgcn_raw_buffer_atomic_dec:
8942 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_dec:
8944 case Intrinsic::amdgcn_raw_buffer_atomic_cond_sub_u32:
8945 return lowerRawBufferAtomicIntrin(
Op, DAG,
8947 case Intrinsic::amdgcn_struct_buffer_atomic_swap:
8948 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_swap:
8949 return lowerStructBufferAtomicIntrin(
Op, DAG,
8951 case Intrinsic::amdgcn_struct_buffer_atomic_add:
8952 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_add:
8954 case Intrinsic::amdgcn_struct_buffer_atomic_sub:
8955 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_sub:
8957 case Intrinsic::amdgcn_struct_buffer_atomic_smin:
8958 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_smin:
8959 return lowerStructBufferAtomicIntrin(
Op, DAG,
8961 case Intrinsic::amdgcn_struct_buffer_atomic_umin:
8962 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_umin:
8963 return lowerStructBufferAtomicIntrin(
Op, DAG,
8965 case Intrinsic::amdgcn_struct_buffer_atomic_smax:
8966 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_smax:
8967 return lowerStructBufferAtomicIntrin(
Op, DAG,
8969 case Intrinsic::amdgcn_struct_buffer_atomic_umax:
8970 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_umax:
8971 return lowerStructBufferAtomicIntrin(
Op, DAG,
8973 case Intrinsic::amdgcn_struct_buffer_atomic_and:
8974 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_and:
8976 case Intrinsic::amdgcn_struct_buffer_atomic_or:
8977 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_or:
8979 case Intrinsic::amdgcn_struct_buffer_atomic_xor:
8980 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_xor:
8982 case Intrinsic::amdgcn_struct_buffer_atomic_inc:
8983 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_inc:
8985 case Intrinsic::amdgcn_struct_buffer_atomic_dec:
8986 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_dec:
8988 case Intrinsic::amdgcn_struct_buffer_atomic_cond_sub_u32:
8989 return lowerStructBufferAtomicIntrin(
Op, DAG,
8992 case Intrinsic::amdgcn_buffer_atomic_cmpswap: {
8993 unsigned Slc =
Op.getConstantOperandVal(7);
9007 setBufferOffsets(
Op.getOperand(6), DAG, &Ops[5]);
9009 EVT VT =
Op.getValueType();
9010 auto *
M = cast<MemSDNode>(
Op);
9013 Op->getVTList(), Ops, VT,
M->getMemOperand());
9015 case Intrinsic::amdgcn_raw_buffer_atomic_cmpswap:
9016 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_cmpswap: {
9017 SDValue Rsrc = bufferRsrcPtrToVector(
Op.getOperand(4), DAG);
9018 auto Offsets = splitBufferOffsets(
Op.getOperand(5), DAG);
9032 EVT VT =
Op.getValueType();
9033 auto *
M = cast<MemSDNode>(
Op);
9036 Op->getVTList(), Ops, VT,
M->getMemOperand());
9038 case Intrinsic::amdgcn_struct_buffer_atomic_cmpswap:
9039 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_cmpswap: {
9040 SDValue Rsrc = bufferRsrcPtrToVector(
Op->getOperand(4), DAG);
9041 auto Offsets = splitBufferOffsets(
Op.getOperand(6), DAG);
9055 EVT VT =
Op.getValueType();
9056 auto *
M = cast<MemSDNode>(
Op);
9059 Op->getVTList(), Ops, VT,
M->getMemOperand());
9061 case Intrinsic::amdgcn_image_bvh_intersect_ray: {
9063 SDValue NodePtr =
M->getOperand(2);
9064 SDValue RayExtent =
M->getOperand(3);
9065 SDValue RayOrigin =
M->getOperand(4);
9067 SDValue RayInvDir =
M->getOperand(6);
9085 const unsigned NumVDataDwords = 4;
9086 const unsigned NumVAddrDwords = IsA16 ? (Is64 ? 9 : 8) : (Is64 ? 12 : 11);
9087 const unsigned NumVAddrs = IsGFX11Plus ? (IsA16 ? 4 : 5) : NumVAddrDwords;
9091 const unsigned BaseOpcodes[2][2] = {
9092 {AMDGPU::IMAGE_BVH_INTERSECT_RAY, AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16},
9093 {AMDGPU::IMAGE_BVH64_INTERSECT_RAY,
9094 AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16}};
9098 IsGFX12Plus ? AMDGPU::MIMGEncGfx12
9099 : IsGFX11 ? AMDGPU::MIMGEncGfx11NSA
9100 : AMDGPU::MIMGEncGfx10NSA,
9101 NumVDataDwords, NumVAddrDwords);
9105 IsGFX11 ? AMDGPU::MIMGEncGfx11Default
9106 : AMDGPU::MIMGEncGfx10Default,
9107 NumVDataDwords, NumVAddrDwords);
9113 auto packLanes = [&DAG, &Ops, &
DL] (
SDValue Op,
bool IsAligned) {
9116 if (Lanes[0].getValueSizeInBits() == 32) {
9117 for (
unsigned I = 0;
I < 3; ++
I)
9124 { Lanes[0], Lanes[1] })));
9131 { Elt0, Lanes[0] })));
9135 { Lanes[1], Lanes[2] })));
9140 if (UseNSA && IsGFX11Plus) {
9148 for (
unsigned I = 0;
I < 3; ++
I) {
9151 {DirLanes[I], InvDirLanes[I]})));
9166 packLanes(RayOrigin,
true);
9167 packLanes(RayDir,
true);
9168 packLanes(RayInvDir,
false);
9173 if (NumVAddrDwords > 12) {
9193 case Intrinsic::amdgcn_global_atomic_fmin:
9194 case Intrinsic::amdgcn_global_atomic_fmax:
9195 case Intrinsic::amdgcn_global_atomic_fmin_num:
9196 case Intrinsic::amdgcn_global_atomic_fmax_num:
9197 case Intrinsic::amdgcn_flat_atomic_fmin:
9198 case Intrinsic::amdgcn_flat_atomic_fmax:
9199 case Intrinsic::amdgcn_flat_atomic_fmin_num:
9200 case Intrinsic::amdgcn_flat_atomic_fmax_num: {
9207 unsigned Opcode = 0;
9209 case Intrinsic::amdgcn_global_atomic_fmin:
9210 case Intrinsic::amdgcn_global_atomic_fmin_num:
9211 case Intrinsic::amdgcn_flat_atomic_fmin:
9212 case Intrinsic::amdgcn_flat_atomic_fmin_num: {
9216 case Intrinsic::amdgcn_global_atomic_fmax:
9217 case Intrinsic::amdgcn_global_atomic_fmax_num:
9218 case Intrinsic::amdgcn_flat_atomic_fmax:
9219 case Intrinsic::amdgcn_flat_atomic_fmax_num: {
9227 M->getVTList(), Ops,
M->getMemoryVT(),
9228 M->getMemOperand());
9230 case Intrinsic::amdgcn_s_get_barrier_state: {
9234 bool IsInlinableBarID =
false;
9237 if (isa<ConstantSDNode>(
Op->getOperand(2))) {
9238 BarID = cast<ConstantSDNode>(
Op->getOperand(2))->getSExtValue();
9242 if (IsInlinableBarID) {
9243 Opc = AMDGPU::S_GET_BARRIER_STATE_IMM;
9247 Opc = AMDGPU::S_GET_BARRIER_STATE_M0;
9259 return lowerImage(
Op, ImageDimIntr, DAG,
true);
9267SDValue SITargetLowering::getMemIntrinsicNode(
unsigned Opcode,
const SDLoc &
DL,
9277 bool IsTFE = VTList.
NumVTs == 3;
9280 unsigned NumOpDWords = NumValueDWords + 1;
9285 SDValue Op = getMemIntrinsicNode(Opcode,
DL, OpDWordsVTList, Ops,
9286 OpDWordsVT, OpDWordsMMO, DAG);
9301 (VT == MVT::v3i32 || VT == MVT::v3f32)) {
9307 WidenedMemVT, WidenedMMO);
9317 bool ImageStore)
const {
9352 for (
unsigned I = 0;
I < Elts.
size() / 2;
I += 1) {
9358 if ((NumElements % 2) == 1) {
9360 unsigned I = Elts.
size() / 2;
9376 if (NumElements == 3) {
9397 unsigned IntrinsicID =
Op.getConstantOperandVal(1);
9400 switch (IntrinsicID) {
9401 case Intrinsic::amdgcn_exp_compr: {
9405 "intrinsic not supported on subtarget",
DL.getDebugLoc());
9428 unsigned Opc =
Done->isZero() ? AMDGPU::EXP : AMDGPU::EXP_DONE;
9431 case Intrinsic::amdgcn_s_barrier: {
9434 unsigned WGSize =
ST.getFlatWorkGroupSizes(MF.
getFunction()).second;
9435 if (WGSize <=
ST.getWavefrontSize())
9437 Op.getOperand(0)), 0);
9441 if (
ST.hasSplitBarriers()) {
9446 MVT::Other, K,
Op.getOperand(0)),
9457 case Intrinsic::amdgcn_tbuffer_store: {
9461 VData = handleD16VData(VData, DAG);
9462 unsigned Dfmt =
Op.getConstantOperandVal(8);
9463 unsigned Nfmt =
Op.getConstantOperandVal(9);
9464 unsigned Glc =
Op.getConstantOperandVal(10);
9465 unsigned Slc =
Op.getConstantOperandVal(11);
9483 M->getMemoryVT(),
M->getMemOperand());
9486 case Intrinsic::amdgcn_struct_tbuffer_store:
9487 case Intrinsic::amdgcn_struct_ptr_tbuffer_store: {
9491 VData = handleD16VData(VData, DAG);
9492 SDValue Rsrc = bufferRsrcPtrToVector(
Op.getOperand(3), DAG);
9493 auto Offsets = splitBufferOffsets(
Op.getOperand(5), DAG);
9511 M->getMemoryVT(),
M->getMemOperand());
9514 case Intrinsic::amdgcn_raw_tbuffer_store:
9515 case Intrinsic::amdgcn_raw_ptr_tbuffer_store: {
9519 VData = handleD16VData(VData, DAG);
9520 SDValue Rsrc = bufferRsrcPtrToVector(
Op.getOperand(3), DAG);
9521 auto Offsets = splitBufferOffsets(
Op.getOperand(4), DAG);
9539 M->getMemoryVT(),
M->getMemOperand());
9542 case Intrinsic::amdgcn_buffer_store:
9543 case Intrinsic::amdgcn_buffer_store_format: {
9547 VData = handleD16VData(VData, DAG);
9548 unsigned Glc =
Op.getConstantOperandVal(6);
9549 unsigned Slc =
Op.getConstantOperandVal(7);
9562 setBufferOffsets(
Op.getOperand(5), DAG, &Ops[4]);
9564 unsigned Opc = IntrinsicID == Intrinsic::amdgcn_buffer_store ?
9571 if (VDataType == MVT::i8 || VDataType == MVT::i16)
9572 return handleByteShortBufferStores(DAG, VDataType,
DL, Ops, M);
9575 M->getMemoryVT(),
M->getMemOperand());
9578 case Intrinsic::amdgcn_raw_buffer_store:
9579 case Intrinsic::amdgcn_raw_ptr_buffer_store:
9580 case Intrinsic::amdgcn_raw_buffer_store_format:
9581 case Intrinsic::amdgcn_raw_ptr_buffer_store_format: {
9582 const bool IsFormat =
9583 IntrinsicID == Intrinsic::amdgcn_raw_buffer_store_format ||
9584 IntrinsicID == Intrinsic::amdgcn_raw_ptr_buffer_store_format;
9591 VData = handleD16VData(VData, DAG);
9601 SDValue Rsrc = bufferRsrcPtrToVector(
Op.getOperand(3), DAG);
9602 auto Offsets = splitBufferOffsets(
Op.getOperand(4), DAG);
9622 return handleByteShortBufferStores(DAG, VDataVT,
DL, Ops, M);
9625 M->getMemoryVT(),
M->getMemOperand());
9628 case Intrinsic::amdgcn_struct_buffer_store:
9629 case Intrinsic::amdgcn_struct_ptr_buffer_store:
9630 case Intrinsic::amdgcn_struct_buffer_store_format:
9631 case Intrinsic::amdgcn_struct_ptr_buffer_store_format: {
9632 const bool IsFormat =
9633 IntrinsicID == Intrinsic::amdgcn_struct_buffer_store_format ||
9634 IntrinsicID == Intrinsic::amdgcn_struct_ptr_buffer_store_format;
9642 VData = handleD16VData(VData, DAG);
9652 auto Rsrc = bufferRsrcPtrToVector(
Op.getOperand(3), DAG);
9653 auto Offsets = splitBufferOffsets(
Op.getOperand(5), DAG);
9674 return handleByteShortBufferStores(DAG, VDataType,
DL, Ops, M);
9677 M->getMemoryVT(),
M->getMemOperand());
9679 case Intrinsic::amdgcn_raw_buffer_load_lds:
9680 case Intrinsic::amdgcn_raw_ptr_buffer_load_lds:
9681 case Intrinsic::amdgcn_struct_buffer_load_lds:
9682 case Intrinsic::amdgcn_struct_ptr_buffer_load_lds: {
9686 IntrinsicID == Intrinsic::amdgcn_struct_buffer_load_lds ||
9687 IntrinsicID == Intrinsic::amdgcn_struct_ptr_buffer_load_lds;
9688 unsigned OpOffset = HasVIndex ? 1 : 0;
9689 SDValue VOffset =
Op.getOperand(5 + OpOffset);
9691 unsigned Size =
Op->getConstantOperandVal(4);
9697 Opc = HasVIndex ? HasVOffset ? AMDGPU::BUFFER_LOAD_UBYTE_LDS_BOTHEN
9698 : AMDGPU::BUFFER_LOAD_UBYTE_LDS_IDXEN
9699 : HasVOffset ? AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFEN
9700 : AMDGPU::BUFFER_LOAD_UBYTE_LDS_OFFSET;
9703 Opc = HasVIndex ? HasVOffset ? AMDGPU::BUFFER_LOAD_USHORT_LDS_BOTHEN
9704 : AMDGPU::BUFFER_LOAD_USHORT_LDS_IDXEN
9705 : HasVOffset ? AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFEN
9706 : AMDGPU::BUFFER_LOAD_USHORT_LDS_OFFSET;
9709 Opc = HasVIndex ? HasVOffset ? AMDGPU::BUFFER_LOAD_DWORD_LDS_BOTHEN
9710 : AMDGPU::BUFFER_LOAD_DWORD_LDS_IDXEN
9711 : HasVOffset ? AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFEN
9712 : AMDGPU::BUFFER_LOAD_DWORD_LDS_OFFSET;
9720 if (HasVIndex && HasVOffset)
9726 else if (HasVOffset)
9729 SDValue Rsrc = bufferRsrcPtrToVector(
Op.getOperand(2), DAG);
9733 unsigned Aux =
Op.getConstantOperandVal(8 + OpOffset);
9741 auto *
M = cast<MemSDNode>(
Op);
9768 case Intrinsic::amdgcn_global_load_lds: {
9770 unsigned Size =
Op->getConstantOperandVal(4);
9775 Opc = AMDGPU::GLOBAL_LOAD_LDS_UBYTE;
9778 Opc = AMDGPU::GLOBAL_LOAD_LDS_USHORT;
9781 Opc = AMDGPU::GLOBAL_LOAD_LDS_DWORD;
9785 auto *
M = cast<MemSDNode>(
Op);
9798 if (
LHS->isDivergent())
9802 RHS.getOperand(0).getValueType() == MVT::i32) {
9805 VOffset =
RHS.getOperand(0);
9810 if (!
Addr->isDivergent()) {
9826 LoadPtrI.
Offset =
Op->getConstantOperandVal(5);
9846 case Intrinsic::amdgcn_end_cf:
9848 Op->getOperand(2), Chain), 0);
9849 case Intrinsic::amdgcn_s_barrier_init:
9850 case Intrinsic::amdgcn_s_barrier_join:
9851 case Intrinsic::amdgcn_s_wakeup_barrier: {
9856 bool IsInlinableBarID =
false;
9859 if (isa<ConstantSDNode>(BarOp)) {
9860 BarVal = cast<ConstantSDNode>(BarOp)->getSExtValue();
9864 if (IsInlinableBarID) {
9865 switch (IntrinsicID) {
9868 case Intrinsic::amdgcn_s_barrier_init:
9869 Opc = AMDGPU::S_BARRIER_INIT_IMM;
9871 case Intrinsic::amdgcn_s_barrier_join:
9872 Opc = AMDGPU::S_BARRIER_JOIN_IMM;
9874 case Intrinsic::amdgcn_s_wakeup_barrier:
9875 Opc = AMDGPU::S_WAKEUP_BARRIER_IMM;
9882 switch (IntrinsicID) {
9885 case Intrinsic::amdgcn_s_barrier_init:
9886 Opc = AMDGPU::S_BARRIER_INIT_M0;
9888 case Intrinsic::amdgcn_s_barrier_join:
9889 Opc = AMDGPU::S_BARRIER_JOIN_M0;
9891 case Intrinsic::amdgcn_s_wakeup_barrier:
9892 Opc = AMDGPU::S_WAKEUP_BARRIER_M0;
9897 if (IntrinsicID == Intrinsic::amdgcn_s_barrier_init) {
9903 if (!IsInlinableBarID) {
9908 Op.getOperand(2), M0Val),
9912 }
else if (!IsInlinableBarID) {
9922 return lowerImage(
Op, ImageDimIntr, DAG,
true);
9935std::pair<SDValue, SDValue> SITargetLowering::splitBufferOffsets(
9942 if ((C1 = dyn_cast<ConstantSDNode>(N0)))
9959 unsigned Overflow = ImmOffset & ~MaxImm;
9960 ImmOffset -= Overflow;
9961 if ((int32_t)Overflow < 0) {
9962 Overflow += ImmOffset;
9971 SDValue Ops[] = { N0, OverflowVal };
9986void SITargetLowering::setBufferOffsets(
SDValue CombinedOffset,
9988 Align Alignment)
const {
9991 if (
auto *
C = dyn_cast<ConstantSDNode>(CombinedOffset)) {
9994 if (
TII->splitMUBUFOffset(Imm, SOffset, ImmOffset, Alignment)) {
10005 int Offset = cast<ConstantSDNode>(N1)->getSExtValue();
10007 TII->splitMUBUFOffset(
Offset, SOffset, ImmOffset, Alignment)) {
10024SDValue SITargetLowering::bufferRsrcPtrToVector(
SDValue MaybePointer,
10027 return MaybePointer;
10043 SDValue NumRecords =
Op->getOperand(3);
10046 auto [LowHalf, HighHalf] = DAG.
SplitScalar(Pointer, Loc, MVT::i32, MVT::i32);
10049 std::optional<uint32_t> ConstStride = std::nullopt;
10050 if (
auto *ConstNode = dyn_cast<ConstantSDNode>(Stride))
10051 ConstStride = ConstNode->getZExtValue();
10053 SDValue NewHighHalf = Masked;
10054 if (!ConstStride || *ConstStride != 0) {
10057 ShiftedStride = DAG.
getConstant(*ConstStride << 16, Loc, MVT::i32);
10064 NewHighHalf = DAG.
getNode(
ISD::OR, Loc, MVT::i32, Masked, ShiftedStride);
10068 NewHighHalf, NumRecords, Flags);
10075SITargetLowering::handleByteShortBufferLoads(
SelectionDAG &DAG,
EVT LoadVT,
10096 if (VDataType == MVT::f16)
10100 Ops[1] = BufferStoreExt;
10105 M->getMemOperand());
10130SDValue SITargetLowering::widenLoad(
LoadSDNode *Ld, DAGCombinerInfo &DCI)
const {
10146 if ((MemVT.
isSimple() && !DCI.isAfterLegalizeDAG()) ||
10153 "unexpected vector extload");
10166 "unexpected fp extload");
10184 DCI.AddToWorklist(Cvt.
getNode());
10189 DCI.AddToWorklist(Cvt.
getNode());
10200 if (
Info.isEntryFunction())
10201 return Info.getUserSGPRInfo().hasFlatScratchInit();
10209 EVT MemVT =
Load->getMemoryVT();
10222 EVT RealMemVT = (MemVT == MVT::i1) ? MVT::i8 : MVT::i16;
10225 BasePtr, RealMemVT, MMO);
10255 assert(
Op.getValueType().getVectorElementType() == MVT::i32 &&
10256 "Custom lowering for non-i32 vectors hasn't been implemented.");
10259 unsigned AS =
Load->getAddressSpace();
10278 if (!
Op->isDivergent() && Alignment >=
Align(4) && NumElements < 32) {
10295 Alignment >=
Align(4) && NumElements < 32) {
10310 if (NumElements > 4)
10330 if (NumElements > 2)
10335 if (NumElements > 4)
10347 auto Flags =
Load->getMemOperand()->getFlags();
10349 Load->getAlign(), Flags, &
Fast) &&
10358 MemVT, *
Load->getMemOperand())) {
10368 EVT VT =
Op.getValueType();
10405 EVT VT =
Op.getValueType();
10408 bool AllowInaccurateRcp =
Flags.hasApproximateFuncs() ||
10415 if (!AllowInaccurateRcp && VT != MVT::f16)
10418 if (CLHS->isExactlyValue(1.0)) {
10435 if (CLHS->isExactlyValue(-1.0)) {
10444 if (!AllowInaccurateRcp && (VT != MVT::f16 || !
Flags.hasAllowReciprocal()))
10458 EVT VT =
Op.getValueType();
10461 bool AllowInaccurateDiv =
Flags.hasApproximateFuncs() ||
10463 if (!AllowInaccurateDiv)
10484 return DAG.
getNode(Opcode, SL, VT,
A,
B, Flags);
10497 return DAG.
getNode(Opcode, SL, VTList,
10506 return DAG.
getNode(Opcode, SL, VT, {
A,
B,
C}, Flags);
10519 return DAG.
getNode(Opcode, SL, VTList,
10525 if (
SDValue FastLowered = lowerFastUnsafeFDIV(
Op, DAG))
10526 return FastLowered;
10553 const APFloat K0Val(0x1p+96f);
10556 const APFloat K1Val(0x1p-32f);
10583 assert(ST->hasDenormModeInst() &&
"Requires S_DENORM_MODE");
10584 uint32_t DPDenormModeDefault =
Info->getMode().fpDenormModeDPValue();
10585 uint32_t Mode = SPDenormMode | (DPDenormModeDefault << 2);
10590 if (
SDValue FastLowered = lowerFastUnsafeFDIV(
Op, DAG))
10591 return FastLowered;
10598 Flags.setNoFPExcept(
true);
10615 DenominatorScaled, Flags);
10617 DenominatorScaled, Flags);
10619 using namespace AMDGPU::Hwreg;
10620 const unsigned Denorm32Reg = HwregEncoding::encode(ID_MODE, 4, 2);
10628 const bool HasDynamicDenormals =
10634 if (!PreservesDenormals) {
10642 if (HasDynamicDenormals) {
10646 SavedDenormMode =
SDValue(GetReg, 0);
10654 const SDValue EnableDenormValue =
10663 EnableDenorm = DAG.
getMachineNode(AMDGPU::S_SETREG_B32, SL, BindParamVTs,
10664 {EnableDenormValue,
BitField, Glue});
10677 ApproxRcp, One, NegDivScale0, Flags);
10680 ApproxRcp, Fma0, Flags);
10683 Fma1, Fma1, Flags);
10686 NumeratorScaled,
Mul, Flags);
10689 Fma2, Fma1,
Mul, Fma2, Flags);
10692 NumeratorScaled, Fma3, Flags);
10694 if (!PreservesDenormals) {
10701 Fma4.
getValue(1), DisableDenormValue,
10704 assert(HasDynamicDenormals == (
bool)SavedDenormMode);
10705 const SDValue DisableDenormValue =
10706 HasDynamicDenormals
10711 AMDGPU::S_SETREG_B32, SL, MVT::Other,
10722 {Fma4, Fma1, Fma3, Scale},
Flags);
10728 if (
SDValue FastLowered = lowerFastUnsafeFDIV64(
Op, DAG))
10729 return FastLowered;
10757 NegDivScale0,
Mul, DivScale1);
10789 Fma4, Fma3,
Mul, Scale);
10795 EVT VT =
Op.getValueType();
10797 if (VT == MVT::f32)
10798 return LowerFDIV32(
Op, DAG);
10800 if (VT == MVT::f64)
10801 return LowerFDIV64(
Op, DAG);
10803 if (VT == MVT::f16)
10804 return LowerFDIV16(
Op, DAG);
10813 EVT ResultExpVT =
Op->getValueType(1);
10814 EVT InstrExpVT = VT == MVT::f16 ? MVT::i16 : MVT::i32;
10844 if (VT == MVT::i1) {
10847 Store->getBasePtr(), MVT::i1,
Store->getMemOperand());
10851 Store->getValue().getValueType().getScalarType() == MVT::i32);
10853 unsigned AS =
Store->getAddressSpace();
10872 if (NumElements > 4)
10879 VT, *
Store->getMemOperand()))
10888 if (NumElements > 2)
10892 if (NumElements > 4 ||
10901 auto Flags =
Store->getMemOperand()->getFlags();
10936 MVT VT =
Op.getValueType().getSimpleVT();
11105 EVT VT =
Op.getValueType();
11122 switch (
Op.getOpcode()) {
11148 EVT VT =
Op.getValueType();
11164 DAGCombinerInfo &DCI)
const {
11165 EVT VT =
N->getValueType(0);
11167 if (ScalarVT != MVT::f32 && ScalarVT != MVT::f16)
11174 EVT SrcVT = Src.getValueType();
11180 if (DCI.isAfterLegalizeDAG() && SrcVT == MVT::i32) {
11183 DCI.AddToWorklist(Cvt.
getNode());
11186 if (ScalarVT != MVT::f32) {
11198 DAGCombinerInfo &DCI)
const {
11199 SDValue MagnitudeOp =
N->getOperand(0);
11200 SDValue SignOp =
N->getOperand(1);
11258 unsigned AddrSpace,
11260 DAGCombinerInfo &DCI)
const {
11290 AM.HasBaseReg =
true;
11291 AM.BaseOffs =
Offset.getSExtValue();
11296 EVT VT =
N->getValueType(0);
11302 Flags.setNoUnsignedWrap(
N->getFlags().hasNoUnsignedWrap() &&
11313 switch (
N->getOpcode()) {
11324 DAGCombinerInfo &DCI)
const {
11333 SDValue NewPtr = performSHLPtrCombine(
Ptr.getNode(),
N->getAddressSpace(),
11334 N->getMemoryVT(), DCI);
11338 NewOps[PtrIdx] = NewPtr;
11347 return (Opc ==
ISD::AND && (Val == 0 || Val == 0xffffffff)) ||
11348 (Opc ==
ISD::OR && (Val == 0xffffffff || Val == 0)) ||
11357SDValue SITargetLowering::splitBinaryBitConstantOp(
11358 DAGCombinerInfo &DCI,
11380 if (V.getValueType() != MVT::i1)
11382 switch (V.getOpcode()) {
11401 if (!(
C & 0x000000ff)) ZeroByteMask |= 0x000000ff;
11402 if (!(
C & 0x0000ff00)) ZeroByteMask |= 0x0000ff00;
11403 if (!(
C & 0x00ff0000)) ZeroByteMask |= 0x00ff0000;
11404 if (!(
C & 0xff000000)) ZeroByteMask |= 0xff000000;
11405 uint32_t NonZeroByteMask = ~ZeroByteMask;
11406 if ((NonZeroByteMask &
C) != NonZeroByteMask)
11419 assert(V.getValueSizeInBits() == 32);
11421 if (V.getNumOperands() != 2)
11430 switch (V.getOpcode()) {
11435 return (0x03020100 & ConstMask) | (0x0c0c0c0c & ~ConstMask);
11440 return (0x03020100 & ~ConstMask) | ConstMask;
11447 return uint32_t((0x030201000c0c0c0cull <<
C) >> 32);
11453 return uint32_t(0x0c0c0c0c03020100ull >>
C);
11460 DAGCombinerInfo &DCI)
const {
11461 if (DCI.isBeforeLegalize())
11465 EVT VT =
N->getValueType(0);
11471 if (VT == MVT::i64 && CRHS) {
11477 if (CRHS && VT == MVT::i32) {
11486 if (
auto *CShift = dyn_cast<ConstantSDNode>(
LHS->getOperand(1))) {
11487 unsigned Shift = CShift->getZExtValue();
11489 unsigned Offset = NB + Shift;
11490 if ((
Offset & (Bits - 1)) == 0) {
11493 LHS->getOperand(0),
11508 isa<ConstantSDNode>(
LHS.getOperand(2))) {
11514 Sel = (
LHS.getConstantOperandVal(2) & Sel) | (~Sel & 0x0c0c0c0c);
11529 if (
Y.getOpcode() !=
ISD::FABS ||
Y.getOperand(0) !=
X ||
11534 if (
X !=
LHS.getOperand(1))
11572 (
RHS.getOperand(0) ==
LHS.getOperand(0) &&
11573 LHS.getOperand(0) ==
LHS.getOperand(1))) {
11576 Mask->getZExtValue() & ~OrdMask :
11577 Mask->getZExtValue() & OrdMask;
11585 if (VT == MVT::i32 &&
11598 N->isDivergent() &&
TII->pseudoToMCOpcode(AMDGPU::V_PERM_B32_e64) != -1) {
11601 if (LHSMask != ~0u && RHSMask != ~0u) {
11604 if (LHSMask > RHSMask) {
11611 uint32_t LHSUsedLanes = ~(LHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
11612 uint32_t RHSUsedLanes = ~(RHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
11615 if (!(LHSUsedLanes & RHSUsedLanes) &&
11618 !(LHSUsedLanes == 0x0c0c0000 && RHSUsedLanes == 0x00000c0c)) {
11625 for (
unsigned I = 0;
I < 32;
I += 8) {
11627 if ((LHSMask & ByteSel) == 0x0c || (RHSMask & ByteSel) == 0x0c)
11628 Mask &= (0x0c <<
I) & 0xffffffff;
11637 LHS.getOperand(0),
RHS.getOperand(0),
11686static const std::optional<ByteProvider<SDValue>>
11688 unsigned Depth = 0) {
11691 return std::nullopt;
11693 if (
Op.getValueSizeInBits() < 8)
11694 return std::nullopt;
11696 if (
Op.getValueType().isVector())
11699 switch (
Op->getOpcode()) {
11710 auto *VTSign = cast<VTSDNode>(
Op->getOperand(1));
11711 NarrowVT = VTSign->getVT();
11714 return std::nullopt;
11717 if (SrcIndex >= NarrowByteWidth)
11718 return std::nullopt;
11724 auto ShiftOp = dyn_cast<ConstantSDNode>(
Op->getOperand(1));
11726 return std::nullopt;
11728 uint64_t BitShift = ShiftOp->getZExtValue();
11730 if (BitShift % 8 != 0)
11731 return std::nullopt;
11733 SrcIndex += BitShift / 8;
11751static const std::optional<ByteProvider<SDValue>>
11753 unsigned StartingIndex = 0) {
11757 return std::nullopt;
11759 unsigned BitWidth =
Op.getScalarValueSizeInBits();
11761 return std::nullopt;
11763 return std::nullopt;
11765 bool IsVec =
Op.getValueType().isVector();
11766 switch (
Op.getOpcode()) {
11769 return std::nullopt;
11774 return std::nullopt;
11778 return std::nullopt;
11781 if (!
LHS->isConstantZero() && !
RHS->isConstantZero())
11782 return std::nullopt;
11783 if (!
LHS ||
LHS->isConstantZero())
11785 if (!
RHS ||
RHS->isConstantZero())
11787 return std::nullopt;
11792 return std::nullopt;
11794 auto BitMaskOp = dyn_cast<ConstantSDNode>(
Op->getOperand(1));
11796 return std::nullopt;
11798 uint32_t BitMask = BitMaskOp->getZExtValue();
11802 if ((IndexMask & BitMask) != IndexMask) {
11805 if (IndexMask & BitMask)
11806 return std::nullopt;
11815 return std::nullopt;
11818 auto ShiftOp = dyn_cast<ConstantSDNode>(
Op->getOperand(2));
11819 if (!ShiftOp ||
Op.getValueType().isVector())
11820 return std::nullopt;
11822 uint64_t BitsProvided =
Op.getValueSizeInBits();
11823 if (BitsProvided % 8 != 0)
11824 return std::nullopt;
11826 uint64_t BitShift = ShiftOp->getAPIntValue().urem(BitsProvided);
11828 return std::nullopt;
11830 uint64_t ConcatSizeInBytes = BitsProvided / 4;
11831 uint64_t ByteShift = BitShift / 8;
11833 uint64_t NewIndex = (
Index + ByteShift) % ConcatSizeInBytes;
11834 uint64_t BytesProvided = BitsProvided / 8;
11835 SDValue NextOp =
Op.getOperand(NewIndex >= BytesProvided ? 0 : 1);
11836 NewIndex %= BytesProvided;
11843 return std::nullopt;
11845 auto ShiftOp = dyn_cast<ConstantSDNode>(
Op->getOperand(1));
11847 return std::nullopt;
11849 uint64_t BitShift = ShiftOp->getZExtValue();
11851 return std::nullopt;
11853 auto BitsProvided =
Op.getScalarValueSizeInBits();
11854 if (BitsProvided % 8 != 0)
11855 return std::nullopt;
11857 uint64_t BytesProvided = BitsProvided / 8;
11858 uint64_t ByteShift = BitShift / 8;
11863 return BytesProvided - ByteShift >
Index
11871 return std::nullopt;
11873 auto ShiftOp = dyn_cast<ConstantSDNode>(
Op->getOperand(1));
11875 return std::nullopt;
11877 uint64_t BitShift = ShiftOp->getZExtValue();
11878 if (BitShift % 8 != 0)
11879 return std::nullopt;
11880 uint64_t ByteShift = BitShift / 8;
11886 return Index < ByteShift
11889 Depth + 1, StartingIndex);
11898 return std::nullopt;
11905 auto *VTSign = cast<VTSDNode>(
Op->getOperand(1));
11906 NarrowBitWidth = VTSign->getVT().getSizeInBits();
11908 if (NarrowBitWidth % 8 != 0)
11909 return std::nullopt;
11910 uint64_t NarrowByteWidth = NarrowBitWidth / 8;
11912 if (
Index >= NarrowByteWidth)
11914 ? std::optional<ByteProvider<SDValue>>(
11922 return std::nullopt;
11926 if (NarrowByteWidth >=
Index) {
11931 return std::nullopt;
11938 return std::nullopt;
11942 auto L = cast<LoadSDNode>(
Op.getNode());
11944 unsigned NarrowBitWidth = L->getMemoryVT().getSizeInBits();
11945 if (NarrowBitWidth % 8 != 0)
11946 return std::nullopt;
11947 uint64_t NarrowByteWidth = NarrowBitWidth / 8;
11952 if (
Index >= NarrowByteWidth) {
11954 ? std::optional<ByteProvider<SDValue>>(
11959 if (NarrowByteWidth >
Index) {
11963 return std::nullopt;
11968 return std::nullopt;
11971 Depth + 1, StartingIndex);
11975 auto IdxOp = dyn_cast<ConstantSDNode>(
Op->getOperand(1));
11977 return std::nullopt;
11978 auto VecIdx = IdxOp->getZExtValue();
11979 auto ScalarSize =
Op.getScalarValueSizeInBits();
11980 if (ScalarSize != 32) {
11981 Index = ScalarSize == 8 ? VecIdx : VecIdx * 2 +
Index;
11985 StartingIndex,
Index);
11990 return std::nullopt;
11992 auto PermMask = dyn_cast<ConstantSDNode>(
Op->getOperand(2));
11994 return std::nullopt;
11997 (PermMask->getZExtValue() & (0xFF << (
Index * 8))) >> (
Index * 8);
11998 if (IdxMask > 0x07 && IdxMask != 0x0c)
11999 return std::nullopt;
12001 auto NextOp =
Op.getOperand(IdxMask > 0x03 ? 0 : 1);
12002 auto NextIndex = IdxMask > 0x03 ? IdxMask % 4 : IdxMask;
12004 return IdxMask != 0x0c ?
calculateSrcByte(NextOp, StartingIndex, NextIndex)
12010 return std::nullopt;
12025 return !OpVT.
isVector() && OpVT.getSizeInBits() == 16;
12029 auto ExtType = cast<LoadSDNode>(L)->getExtensionType();
12032 auto MemVT = L->getMemoryVT();
12035 return L->getMemoryVT().getSizeInBits() == 16;
12045 int Low8 = Mask & 0xff;
12046 int Hi8 = (Mask & 0xff00) >> 8;
12048 assert(Low8 < 8 && Hi8 < 8);
12050 bool IsConsecutive = (Hi8 - Low8 == 1);
12055 bool Is16Aligned = !(Low8 % 2);
12057 return IsConsecutive && Is16Aligned;
12065 int Low16 = PermMask & 0xffff;
12066 int Hi16 = (PermMask & 0xffff0000) >> 16;
12076 auto OtherOpIs16Bit = TempOtherOp.getValueSizeInBits() == 16 ||
12078 if (!OtherOpIs16Bit)
12086 unsigned DWordOffset) {
12089 auto TypeSize = Src.getValueSizeInBits().getFixedValue();
12091 assert(Src.getValueSizeInBits().isKnownMultipleOf(8));
12096 if (Src.getValueType().isVector()) {
12097 auto ScalarTySize = Src.getScalarValueSizeInBits();
12098 auto ScalarTy = Src.getValueType().getScalarType();
12099 if (ScalarTySize == 32) {
12103 if (ScalarTySize > 32) {
12106 DAG.
getConstant(DWordOffset / (ScalarTySize / 32), SL, MVT::i32));
12107 auto ShiftVal = 32 * (DWordOffset % (ScalarTySize / 32));
12114 assert(ScalarTySize < 32);
12115 auto NumElements =
TypeSize / ScalarTySize;
12116 auto Trunc32Elements = (ScalarTySize * NumElements) / 32;
12117 auto NormalizedTrunc = Trunc32Elements * 32 / ScalarTySize;
12118 auto NumElementsIn32 = 32 / ScalarTySize;
12119 auto NumAvailElements = DWordOffset < Trunc32Elements
12121 : NumElements - NormalizedTrunc;
12134 auto ShiftVal = 32 * DWordOffset;
12142 [[maybe_unused]]
EVT VT =
N->getValueType(0);
12147 for (
int i = 0; i < 4; i++) {
12149 std::optional<ByteProvider<SDValue>>
P =
12152 if (!
P ||
P->isConstantZero())
12157 if (PermNodes.
size() != 4)
12160 std::pair<unsigned, unsigned> FirstSrc(0, PermNodes[0].SrcOffset / 4);
12161 std::optional<std::pair<unsigned, unsigned>> SecondSrc;
12163 for (
size_t i = 0; i < PermNodes.
size(); i++) {
12164 auto PermOp = PermNodes[i];
12167 int SrcByteAdjust = 4;
12171 if (!PermOp.hasSameSrc(PermNodes[FirstSrc.first]) ||
12172 ((PermOp.SrcOffset / 4) != FirstSrc.second)) {
12174 if (!PermOp.hasSameSrc(PermNodes[SecondSrc->first]) ||
12175 ((PermOp.SrcOffset / 4) != SecondSrc->second))
12179 SecondSrc = {i, PermNodes[i].SrcOffset / 4};
12180 assert(!(PermNodes[SecondSrc->first].Src->getValueSizeInBits() % 8));
12183 assert((PermOp.SrcOffset % 4) + SrcByteAdjust < 8);
12185 PermMask |= ((PermOp.SrcOffset % 4) + SrcByteAdjust) << (i * 8);
12188 SDValue Op = *PermNodes[FirstSrc.first].Src;
12190 assert(
Op.getValueSizeInBits() == 32);
12194 int Low16 = PermMask & 0xffff;
12195 int Hi16 = (PermMask & 0xffff0000) >> 16;
12197 bool WellFormedLow = (Low16 == 0x0504) || (Low16 == 0x0100);
12198 bool WellFormedHi = (Hi16 == 0x0706) || (Hi16 == 0x0302);
12201 if (WellFormedLow && WellFormedHi)
12205 SDValue OtherOp = SecondSrc ? *PermNodes[SecondSrc->first].Src :
Op;
12214 assert(
Op.getValueType().isByteSized() &&
12232 DAGCombinerInfo &DCI)
const {
12237 EVT VT =
N->getValueType(0);
12238 if (VT == MVT::i1) {
12243 if (Src !=
RHS.getOperand(0))
12248 if (!CLHS || !CRHS)
12252 static const uint32_t MaxMask = 0x3ff;
12266 isa<ConstantSDNode>(
LHS.getOperand(2))) {
12271 Sel |=
LHS.getConstantOperandVal(2);
12280 N->isDivergent() &&
TII->pseudoToMCOpcode(AMDGPU::V_PERM_B32_e64) != -1) {
12284 auto usesCombinedOperand = [](
SDNode *OrUse) {
12287 !OrUse->getValueType(0).isVector())
12291 for (
auto VUse : OrUse->uses()) {
12292 if (!VUse->getValueType(0).isVector())
12299 if (VUse->getOpcode() == VectorwiseOp)
12305 if (!
any_of(
N->uses(), usesCombinedOperand))
12311 if (LHSMask != ~0u && RHSMask != ~0u) {
12314 if (LHSMask > RHSMask) {
12321 uint32_t LHSUsedLanes = ~(LHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
12322 uint32_t RHSUsedLanes = ~(RHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
12325 if (!(LHSUsedLanes & RHSUsedLanes) &&
12328 !(LHSUsedLanes == 0x0c0c0000 && RHSUsedLanes == 0x00000c0c)) {
12330 LHSMask &= ~RHSUsedLanes;
12331 RHSMask &= ~LHSUsedLanes;
12333 LHSMask |= LHSUsedLanes & 0x04040404;
12339 LHS.getOperand(0),
RHS.getOperand(0),
12343 if (LHSMask == ~0u || RHSMask == ~0u) {
12349 if (VT != MVT::i64 || DCI.isBeforeLegalizeOps())
12364 if (SrcVT == MVT::i32) {
12370 DCI.AddToWorklist(LowOr.
getNode());
12371 DCI.AddToWorklist(HiBits.
getNode());
12379 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(
N->getOperand(1));
12383 N->getOperand(0), CRHS))
12391 DAGCombinerInfo &DCI)
const {
12392 if (
SDValue RV = reassociateScalarOps(
N, DCI.DAG))
12401 EVT VT =
N->getValueType(0);
12402 if (CRHS && VT == MVT::i64) {
12424 LHS->getOperand(0), FNegLHS, FNegRHS);
12433 DAGCombinerInfo &DCI)
const {
12438 EVT VT =
N->getValueType(0);
12439 if (VT != MVT::i32)
12443 if (Src.getValueType() != MVT::i16)
12450SITargetLowering::performSignExtendInRegCombine(
SDNode *
N,
12451 DAGCombinerInfo &DCI)
const {
12453 auto *VTSign = cast<VTSDNode>(
N->getOperand(1));
12458 VTSign->getVT() == MVT::i8) ||
12460 VTSign->getVT() == MVT::i16))) {
12462 "s_buffer_load_{u8, i8} are supported "
12463 "in GFX12 (or newer) architectures.");
12464 EVT VT = Src.getValueType();
12469 SDVTList ResList = DCI.DAG.getVTList(MVT::i32);
12475 auto *
M = cast<MemSDNode>(Src);
12476 SDValue BufferLoad = DCI.DAG.getMemIntrinsicNode(
12477 Opc,
DL, ResList, Ops,
M->getMemoryVT(),
M->getMemOperand());
12481 VTSign->getVT() == MVT::i8) ||
12483 VTSign->getVT() == MVT::i16)) &&
12485 auto *
M = cast<MemSDNode>(Src);
12497 SDVTList ResList = DCI.DAG.getVTList(MVT::i32,
12498 Src.getOperand(0).getValueType());
12501 SDValue BufferLoadSignExt = DCI.DAG.getMemIntrinsicNode(Opc,
SDLoc(
N),
12503 Ops,
M->getMemoryVT(),
12504 M->getMemOperand());
12505 return DCI.DAG.getMergeValues({BufferLoadSignExt,
12512 DAGCombinerInfo &DCI)
const {
12520 if (
N->getOperand(0).isUndef())
12527 DAGCombinerInfo &DCI)
const {
12528 EVT VT =
N->getValueType(0);
12532 return DCI.DAG.getConstantFP(
12555 unsigned Opcode =
Op.getOpcode();
12559 if (
auto *CFP = dyn_cast<ConstantFPSDNode>(
Op)) {
12560 const auto &
F = CFP->getValueAPF();
12561 if (
F.isNaN() &&
F.isSignaling())
12563 if (!
F.isDenormal())
12626 if (
Op.getValueType() == MVT::i32) {
12631 if (
auto *
RHS = dyn_cast<ConstantSDNode>(
Op.getOperand(1))) {
12632 if (
RHS->getZExtValue() == 0xffff0000) {
12642 return Op.getValueType().getScalarType() != MVT::f16;
12710 if (
Op.getValueType() == MVT::i16) {
12721 unsigned IntrinsicID =
Op.getConstantOperandVal(0);
12723 switch (IntrinsicID) {
12724 case Intrinsic::amdgcn_cvt_pkrtz:
12725 case Intrinsic::amdgcn_cubeid:
12726 case Intrinsic::amdgcn_frexp_mant:
12727 case Intrinsic::amdgcn_fdot2:
12728 case Intrinsic::amdgcn_rcp:
12729 case Intrinsic::amdgcn_rsq:
12730 case Intrinsic::amdgcn_rsq_clamp:
12731 case Intrinsic::amdgcn_rcp_legacy:
12732 case Intrinsic::amdgcn_rsq_legacy:
12733 case Intrinsic::amdgcn_trig_preop:
12734 case Intrinsic::amdgcn_log:
12735 case Intrinsic::amdgcn_exp2:
12736 case Intrinsic::amdgcn_sqrt:
12757 unsigned Opcode =
MI->getOpcode();
12759 if (Opcode == AMDGPU::G_FCANONICALIZE)
12762 std::optional<FPValueAndVReg> FCR;
12765 if (FCR->Value.isSignaling())
12767 if (!FCR->Value.isDenormal())
12778 case AMDGPU::G_FADD:
12779 case AMDGPU::G_FSUB:
12780 case AMDGPU::G_FMUL:
12781 case AMDGPU::G_FCEIL:
12782 case AMDGPU::G_FFLOOR:
12783 case AMDGPU::G_FRINT:
12784 case AMDGPU::G_FNEARBYINT:
12785 case AMDGPU::G_INTRINSIC_FPTRUNC_ROUND:
12786 case AMDGPU::G_INTRINSIC_TRUNC:
12787 case AMDGPU::G_INTRINSIC_ROUNDEVEN:
12788 case AMDGPU::G_FMA:
12789 case AMDGPU::G_FMAD:
12790 case AMDGPU::G_FSQRT:
12791 case AMDGPU::G_FDIV:
12792 case AMDGPU::G_FREM:
12793 case AMDGPU::G_FPOW:
12794 case AMDGPU::G_FPEXT:
12795 case AMDGPU::G_FLOG:
12796 case AMDGPU::G_FLOG2:
12797 case AMDGPU::G_FLOG10:
12798 case AMDGPU::G_FPTRUNC:
12799 case AMDGPU::G_AMDGPU_RCP_IFLAG:
12800 case AMDGPU::G_AMDGPU_CVT_F32_UBYTE0:
12801 case AMDGPU::G_AMDGPU_CVT_F32_UBYTE1:
12802 case AMDGPU::G_AMDGPU_CVT_F32_UBYTE2:
12803 case AMDGPU::G_AMDGPU_CVT_F32_UBYTE3:
12805 case AMDGPU::G_FNEG:
12806 case AMDGPU::G_FABS:
12807 case AMDGPU::G_FCOPYSIGN:
12809 case AMDGPU::G_FMINNUM:
12810 case AMDGPU::G_FMAXNUM:
12811 case AMDGPU::G_FMINNUM_IEEE:
12812 case AMDGPU::G_FMAXNUM_IEEE:
12813 case AMDGPU::G_FMINIMUM:
12814 case AMDGPU::G_FMAXIMUM: {
12822 case AMDGPU::G_BUILD_VECTOR:
12827 case AMDGPU::G_INTRINSIC:
12828 case AMDGPU::G_INTRINSIC_CONVERGENT:
12830 case Intrinsic::amdgcn_fmul_legacy:
12831 case Intrinsic::amdgcn_fmad_ftz:
12832 case Intrinsic::amdgcn_sqrt:
12833 case Intrinsic::amdgcn_fmed3:
12834 case Intrinsic::amdgcn_sin:
12835 case Intrinsic::amdgcn_cos:
12836 case Intrinsic::amdgcn_log:
12837 case Intrinsic::amdgcn_exp2:
12838 case Intrinsic::amdgcn_log_clamp:
12839 case Intrinsic::amdgcn_rcp:
12840 case Intrinsic::amdgcn_rcp_legacy:
12841 case Intrinsic::amdgcn_rsq:
12842 case Intrinsic::amdgcn_rsq_clamp:
12843 case Intrinsic::amdgcn_rsq_legacy:
12844 case Intrinsic::amdgcn_div_scale:
12845 case Intrinsic::amdgcn_div_fmas:
12846 case Intrinsic::amdgcn_div_fixup:
12847 case Intrinsic::amdgcn_fract:
12848 case Intrinsic::amdgcn_cvt_pkrtz:
12849 case Intrinsic::amdgcn_cubeid:
12850 case Intrinsic::amdgcn_cubema:
12851 case Intrinsic::amdgcn_cubesc:
12852 case Intrinsic::amdgcn_cubetc:
12853 case Intrinsic::amdgcn_frexp_mant:
12854 case Intrinsic::amdgcn_fdot2:
12855 case Intrinsic::amdgcn_trig_preop:
12870SDValue SITargetLowering::getCanonicalConstantFP(
12873 if (
C.isDenormal()) {
12887 if (
C.isSignaling()) {
12906 return Op.isUndef() || isa<ConstantFPSDNode>(
Op);
12909SDValue SITargetLowering::performFCanonicalizeCombine(
12911 DAGCombinerInfo &DCI)
const {
12914 EVT VT =
N->getValueType(0);
12923 EVT VT =
N->getValueType(0);
12924 return getCanonicalConstantFP(DAG,
SDLoc(
N), VT, CFP->getValueAPF());
12940 EVT EltVT =
Lo.getValueType();
12943 for (
unsigned I = 0;
I != 2; ++
I) {
12946 NewElts[
I] = getCanonicalConstantFP(DAG, SL, EltVT,
12947 CFP->getValueAPF());
12948 }
else if (
Op.isUndef()) {
12960 if (isa<ConstantFPSDNode>(NewElts[1]))
12961 NewElts[0] = isa<ConstantFPSDNode>(NewElts[1]) ?
12966 NewElts[1] = isa<ConstantFPSDNode>(NewElts[0]) ?
13017 if (!MinK || !MaxK)
13030 if (VT == MVT::i32 || (VT == MVT::i16 && Subtarget->
hasMed3_16()))
13031 return DAG.
getNode(Med3Opc, SL, VT, Src, MaxVal, MinVal);
13073 if (
Info->getMode().DX10Clamp) {
13082 if (VT == MVT::f32 || (VT == MVT::f16 && Subtarget->
hasMed3_16())) {
13104 DAGCombinerInfo &DCI)
const {
13107 EVT VT =
N->getValueType(0);
13108 unsigned Opc =
N->getOpcode();
13117 (VT == MVT::i32 || VT == MVT::f32 ||
13118 ((VT == MVT::f16 || VT == MVT::i16) && Subtarget->
hasMin3Max3_16()))) {
13125 N->getValueType(0),
13138 N->getValueType(0),
13148 if (
SDValue Med3 = performIntMed3ImmCombine(
13153 if (
SDValue Med3 = performIntMed3ImmCombine(
13159 if (
SDValue Med3 = performIntMed3ImmCombine(
13164 if (
SDValue Med3 = performIntMed3ImmCombine(
13174 (VT == MVT::f32 || VT == MVT::f64 ||
13178 if (
SDValue Res = performFPMed3ImmCombine(DAG,
SDLoc(
N), Op0, Op1))
13189 return (CA->isExactlyValue(0.0) && CB->isExactlyValue(1.0)) ||
13190 (CA->isExactlyValue(1.0) && CB->isExactlyValue(0.0));
13199 DAGCombinerInfo &DCI)
const {
13200 EVT VT =
N->getValueType(0);
13223 if (
Info->getMode().DX10Clamp) {
13226 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
13229 if (isa<ConstantFPSDNode>(Src1) && !isa<ConstantFPSDNode>(Src2))
13232 if (isa<ConstantFPSDNode>(Src0) && !isa<ConstantFPSDNode>(Src1))
13243 DAGCombinerInfo &DCI)
const {
13247 return DCI.DAG.getUNDEF(
N->getValueType(0));
13255 bool IsDivergentIdx,
13260 unsigned VecSize = EltSize * NumElem;
13263 if (VecSize <= 64 && EltSize < 32)
13272 if (IsDivergentIdx)
13276 unsigned NumInsts = NumElem +
13277 ((EltSize + 31) / 32) * NumElem ;
13282 return NumInsts <= 16;
13286 return NumInsts <= 15;
13291 if (isa<ConstantSDNode>(
Idx))
13304SDValue SITargetLowering::performExtractVectorEltCombine(
13305 SDNode *
N, DAGCombinerInfo &DCI)
const {
13311 EVT ResVT =
N->getValueType(0);
13330 if (Vec.
hasOneUse() && DCI.isBeforeLegalize() && VecEltVT == ResVT) {
13358 DCI.AddToWorklist(Elt0.
getNode());
13359 DCI.AddToWorklist(Elt1.
getNode());
13381 if (!DCI.isBeforeLegalize())
13387 auto *
Idx = dyn_cast<ConstantSDNode>(
N->getOperand(1));
13388 if (isa<MemSDNode>(Vec) && VecEltSize <= 16 && VecEltVT.
isByteSized() &&
13389 VecSize > 32 && VecSize % 32 == 0 &&
Idx) {
13392 unsigned BitIndex =
Idx->getZExtValue() * VecEltSize;
13393 unsigned EltIdx = BitIndex / 32;
13394 unsigned LeftoverBitIdx = BitIndex % 32;
13398 DCI.AddToWorklist(Cast.
getNode());
13402 DCI.AddToWorklist(Elt.
getNode());
13405 DCI.AddToWorklist(Srl.
getNode());
13409 DCI.AddToWorklist(Trunc.
getNode());
13411 if (VecEltVT == ResVT) {
13423SITargetLowering::performInsertVectorEltCombine(
SDNode *
N,
13424 DAGCombinerInfo &DCI)
const {
13438 EVT IdxVT =
Idx.getValueType();
13455 Src.getOperand(0).getValueType() == MVT::f16) {
13456 return Src.getOperand(0);
13459 if (
auto *CFP = dyn_cast<ConstantFPSDNode>(Src)) {
13460 APFloat Val = CFP->getValueAPF();
13461 bool LosesInfo =
true;
13471 DAGCombinerInfo &DCI)
const {
13473 "combine only useful on gfx8");
13475 SDValue TruncSrc =
N->getOperand(0);
13476 EVT VT =
N->getValueType(0);
13477 if (VT != MVT::f16)
13515unsigned SITargetLowering::getFusedOpcode(
const SelectionDAG &DAG,
13517 const SDNode *N1)
const {
13522 if (((VT == MVT::f32 &&
13524 (VT == MVT::f16 && Subtarget->
hasMadF16() &&
13544 EVT VT =
N->getValueType(0);
13545 if (VT != MVT::i32 && VT != MVT::i64)
13551 unsigned Opc =
N->getOpcode();
13574 return DAG.
getNode(Opc, SL, VT, Add1, Op2);
13596 DAGCombinerInfo &DCI)
const {
13600 EVT VT =
N->getValueType(0);
13610 if (!
N->isDivergent() && Subtarget->
hasSMulHi())
13614 if (NumBits <= 32 || NumBits > 64)
13626 unsigned NumUsers = 0;
13651 bool MulSignedLo =
false;
13652 if (!MulLHSUnsigned32 || !MulRHSUnsigned32) {
13661 if (VT != MVT::i64) {
13684 getMad64_32(DAG, SL, MVT::i64, MulLHSLo, MulRHSLo, AddRHS, MulSignedLo);
13686 if (!MulSignedLo && (!MulLHSUnsigned32 || !MulRHSUnsigned32)) {
13688 std::tie(AccumLo, AccumHi) = DAG.
SplitScalar(Accum, SL, MVT::i32, MVT::i32);
13690 if (!MulLHSUnsigned32) {
13697 if (!MulRHSUnsigned32) {
13708 if (VT != MVT::i64)
13715static std::optional<ByteProvider<SDValue>>
13718 if (!Byte0 || Byte0->isConstantZero()) {
13719 return std::nullopt;
13722 if (Byte1 && !Byte1->isConstantZero()) {
13723 return std::nullopt;
13729 unsigned FirstCs =
First & 0x0c0c0c0c;
13730 unsigned SecondCs = Second & 0x0c0c0c0c;
13731 unsigned FirstNoCs =
First & ~0x0c0c0c0c;
13732 unsigned SecondNoCs = Second & ~0x0c0c0c0c;
13734 assert((FirstCs & 0xFF) | (SecondCs & 0xFF));
13735 assert((FirstCs & 0xFF00) | (SecondCs & 0xFF00));
13736 assert((FirstCs & 0xFF0000) | (SecondCs & 0xFF0000));
13737 assert((FirstCs & 0xFF000000) | (SecondCs & 0xFF000000));
13739 return (FirstNoCs | SecondNoCs) | (FirstCs & SecondCs);
13763 for (
int BPI = 0; BPI < 2; BPI++) {
13766 BPP = {Src1, Src0};
13768 unsigned ZeroMask = 0x0c0c0c0c;
13769 unsigned FMask = 0xFF << (8 * (3 - Step));
13771 unsigned FirstMask =
13772 (BPP.first.SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask);
13773 unsigned SecondMask =
13774 (BPP.second.SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask);
13778 int FirstGroup = -1;
13779 for (
int I = 0;
I < 2;
I++) {
13781 auto MatchesFirst = [&BPP](
DotSrc &IterElt) {
13782 return IterElt.SrcOp == *BPP.first.Src &&
13783 (IterElt.DWordOffset == (BPP.first.SrcOffset / 4));
13793 if (FirstGroup != -1) {
13795 auto MatchesSecond = [&BPP](
DotSrc &IterElt) {
13796 return IterElt.SrcOp == *BPP.second.Src &&
13797 (IterElt.DWordOffset == (BPP.second.SrcOffset / 4));
13803 Srcs.
push_back({*BPP.second.Src, SecondMask, BPP.second.SrcOffset / 4});
13811 unsigned ZeroMask = 0x0c0c0c0c;
13812 unsigned FMask = 0xFF << (8 * (3 - Step));
13816 ((Src0.
SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask)),
13820 ((Src1.
SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask)),
13831 if (Srcs.
size() == 1) {
13832 auto Elt = Srcs.
begin();
13836 if (Elt->PermMask == 0x3020100)
13843 auto FirstElt = Srcs.
begin();
13844 auto SecondElt = std::next(FirstElt);
13851 auto FirstMask = FirstElt->PermMask;
13852 auto SecondMask = SecondElt->PermMask;
13854 unsigned FirstCs = FirstMask & 0x0c0c0c0c;
13855 unsigned FirstPlusFour = FirstMask | 0x04040404;
13858 FirstMask = (FirstPlusFour & 0x0F0F0F0F) | FirstCs;
13870 FirstElt = std::next(SecondElt);
13871 if (FirstElt == Srcs.
end())
13874 SecondElt = std::next(FirstElt);
13877 if (SecondElt == Srcs.
end()) {
13883 DAG.
getConstant(FirstElt->PermMask, SL, MVT::i32)));
13889 return Perms.
size() == 2
13895 for (
auto &[EntryVal, EntryMask, EntryOffset] : Srcs) {
13896 EntryMask = EntryMask >> ((4 - ChainLength) * 8);
13897 auto ZeroMask = ChainLength == 2 ? 0x0c0c0000 : 0x0c000000;
13898 EntryMask += ZeroMask;
13903 auto Opcode =
Op.getOpcode();
13909static std::optional<bool>
13920 bool S0IsSigned = Known0.countMinLeadingOnes() > 0;
13923 bool S1IsSigned = Known1.countMinLeadingOnes() > 0;
13925 assert(!(S0IsUnsigned && S0IsSigned));
13926 assert(!(S1IsUnsigned && S1IsSigned));
13934 if ((S0IsUnsigned && S1IsUnsigned) || (S0IsSigned && S1IsSigned))
13940 if ((S0IsUnsigned && S1IsSigned) || (S0IsSigned && S1IsUnsigned))
13941 return std::nullopt;
13953 if ((S0IsSigned && !(S1IsSigned || S1IsUnsigned)) ||
13954 ((S1IsSigned && !(S0IsSigned || S0IsUnsigned))))
13959 if ((!(S1IsSigned || S1IsUnsigned) && !(S0IsSigned || S0IsUnsigned)))
13965 if ((S0IsUnsigned && !(S1IsSigned || S1IsUnsigned)) ||
13966 ((S1IsUnsigned && !(S0IsSigned || S0IsUnsigned))))
13967 return std::nullopt;
13973 DAGCombinerInfo &DCI)
const {
13975 EVT VT =
N->getValueType(0);
13982 if (
SDValue Folded = tryFoldToMad64_32(
N, DCI))
13987 if (
SDValue V = reassociateScalarOps(
N, DAG)) {
13994 std::optional<bool> IsSigned;
14000 int ChainLength = 0;
14001 for (
int I = 0;
I < 4;
I++) {
14002 auto MulIdx =
isMul(LHS) ? 0 :
isMul(RHS) ? 1 : -1;
14005 auto Src0 =
handleMulOperand(TempNode->getOperand(MulIdx)->getOperand(0));
14008 auto Src1 =
handleMulOperand(TempNode->getOperand(MulIdx)->getOperand(1));
14013 TempNode->getOperand(MulIdx), *Src0, *Src1,
14014 TempNode->getOperand(MulIdx)->getOperand(0),
14015 TempNode->getOperand(MulIdx)->getOperand(1), DAG);
14019 IsSigned = *IterIsSigned;
14020 if (*IterIsSigned != *IsSigned)
14023 auto AddIdx = 1 - MulIdx;
14026 if (
I == 2 &&
isMul(TempNode->getOperand(AddIdx))) {
14027 Src2s.
push_back(TempNode->getOperand(AddIdx));
14037 TempNode->getOperand(AddIdx), *Src0, *Src1,
14038 TempNode->getOperand(AddIdx)->getOperand(0),
14039 TempNode->getOperand(AddIdx)->getOperand(1), DAG);
14043 if (*IterIsSigned != *IsSigned)
14047 ChainLength =
I + 2;
14051 TempNode = TempNode->getOperand(AddIdx);
14053 ChainLength =
I + 1;
14054 if (TempNode->getNumOperands() < 2)
14056 LHS = TempNode->getOperand(0);
14057 RHS = TempNode->getOperand(1);
14060 if (ChainLength < 2)
14066 if (ChainLength < 4) {
14076 bool UseOriginalSrc =
false;
14077 if (ChainLength == 4 && Src0s.
size() == 1 && Src1s.
size() == 1 &&
14078 Src0s.
begin()->PermMask == Src1s.
begin()->PermMask &&
14079 Src0s.
begin()->SrcOp.getValueSizeInBits() >= 32 &&
14080 Src1s.
begin()->SrcOp.getValueSizeInBits() >= 32) {
14082 auto Src0Mask = Src0s.
begin()->PermMask;
14083 SrcBytes.
push_back(Src0Mask & 0xFF000000);
14084 bool UniqueEntries =
true;
14085 for (
auto I = 1;
I < 4;
I++) {
14086 auto NextByte = Src0Mask & (0xFF << ((3 -
I) * 8));
14089 UniqueEntries =
false;
14095 if (UniqueEntries) {
14096 UseOriginalSrc =
true;
14098 auto FirstElt = Src0s.
begin();
14102 auto SecondElt = Src1s.
begin();
14104 SecondElt->DWordOffset);
14113 if (!UseOriginalSrc) {
14120 DAG.
getExtOrTrunc(*IsSigned, Src2s[ChainLength - 1], SL, MVT::i32);
14123 : Intrinsic::amdgcn_udot4,
14133 if (VT != MVT::i32 || !DCI.isAfterLegalizeDAG())
14138 unsigned Opc =
LHS.getOpcode();
14143 Opc =
RHS.getOpcode();
14149 auto Cond =
RHS.getOperand(0);
14157 return DAG.
getNode(Opc, SL, VTList, Args);
14171 DAGCombinerInfo &DCI)
const {
14173 EVT VT =
N->getValueType(0);
14175 if (VT != MVT::i32)
14184 unsigned Opc =
RHS.getOpcode();
14190 auto Cond =
RHS.getOperand(0);
14198 return DAG.
getNode(Opc, SL, VTList, Args);
14212SDValue SITargetLowering::performAddCarrySubCarryCombine(
SDNode *
N,
14213 DAGCombinerInfo &DCI)
const {
14215 if (
N->getValueType(0) != MVT::i32)
14226 unsigned LHSOpc =
LHS.getOpcode();
14227 unsigned Opc =
N->getOpcode();
14237 DAGCombinerInfo &DCI)
const {
14242 EVT VT =
N->getValueType(0);
14254 if (
A ==
LHS.getOperand(1)) {
14255 unsigned FusedOp = getFusedOpcode(DAG,
N,
LHS.getNode());
14256 if (FusedOp != 0) {
14258 return DAG.
getNode(FusedOp, SL, VT,
A, Two, RHS);
14266 if (
A ==
RHS.getOperand(1)) {
14267 unsigned FusedOp = getFusedOpcode(DAG,
N,
RHS.getNode());
14268 if (FusedOp != 0) {
14270 return DAG.
getNode(FusedOp, SL, VT,
A, Two, LHS);
14279 DAGCombinerInfo &DCI)
const {
14285 EVT VT =
N->getValueType(0);
14298 if (
A ==
LHS.getOperand(1)) {
14299 unsigned FusedOp = getFusedOpcode(DAG,
N,
LHS.getNode());
14304 return DAG.
getNode(FusedOp, SL, VT,
A, Two, NegRHS);
14313 if (
A ==
RHS.getOperand(1)) {
14314 unsigned FusedOp = getFusedOpcode(DAG,
N,
RHS.getNode());
14317 return DAG.
getNode(FusedOp, SL, VT,
A, NegTwo, LHS);
14326 DAGCombinerInfo &DCI)
const {
14329 EVT VT =
N->getValueType(0);
14343 bool IsNegative =
false;
14344 if (CLHS->isExactlyValue(1.0) ||
14345 (IsNegative = CLHS->isExactlyValue(-1.0))) {
14361 DAGCombinerInfo &DCI)
const {
14363 EVT VT =
N->getValueType(0);
14385 (
N->getFlags().hasAllowContract() &&
14386 FMA->getFlags().hasAllowContract())) {
14420 if (Vec1 == Vec2 || Vec3 == Vec4)
14426 if ((Vec1 == Vec3 && Vec2 == Vec4) ||
14427 (Vec1 == Vec4 && Vec2 == Vec3)) {
14436 DAGCombinerInfo &DCI)
const {
14442 EVT VT =
LHS.getValueType();
14445 auto CRHS = dyn_cast<ConstantSDNode>(RHS);
14447 CRHS = dyn_cast<ConstantSDNode>(LHS);
14471 return LHS.getOperand(0);
14477 isa<ConstantSDNode>(
LHS.getOperand(1)) &&
14478 isa<ConstantSDNode>(
LHS.getOperand(2)) &&
14479 LHS.getConstantOperandVal(1) !=
LHS.getConstantOperandVal(2) &&
14486 const APInt &CT =
LHS.getConstantOperandAPInt(1);
14487 const APInt &CF =
LHS.getConstantOperandAPInt(2);
14495 return LHS.getOperand(0);
14499 if (VT != MVT::f32 && VT != MVT::f64 &&
14532 DAGCombinerInfo &DCI)
const {
14550 if (
auto *
C = dyn_cast<ConstantSDNode>(Shift.
getOperand(1))) {
14554 unsigned ShiftOffset = 8 *
Offset;
14556 ShiftOffset -=
C->getZExtValue();
14558 ShiftOffset +=
C->getZExtValue();
14560 if (ShiftOffset < 32 && (ShiftOffset % 8) == 0) {
14562 MVT::f32, Shifted);
14573 DCI.AddToWorklist(
N);
14580 return DAG.
getNode(
N->getOpcode(), SL, MVT::f32, DemandedSrc);
14586 DAGCombinerInfo &DCI)
const {
14596 return DCI.DAG.getConstantFP(Zero,
SDLoc(
N),
N->getValueType(0));
14599 APFloat One(
F.getSemantics(),
"1.0");
14601 return DCI.DAG.getConstantFP(One,
SDLoc(
N),
N->getValueType(0));
14611 switch (
N->getOpcode()) {
14613 return performAddCombine(
N, DCI);
14615 return performSubCombine(
N, DCI);
14618 return performAddCarrySubCarryCombine(
N, DCI);
14620 return performFAddCombine(
N, DCI);
14622 return performFSubCombine(
N, DCI);
14624 return performFDivCombine(
N, DCI);
14626 return performSetCCCombine(
N, DCI);
14639 return performMinMaxCombine(
N, DCI);
14641 return performFMACombine(
N, DCI);
14643 return performAndCombine(
N, DCI);
14645 return performOrCombine(
N, DCI);
14648 if (
N->getValueType(0) == MVT::i32 &&
N->isDivergent() &&
14649 TII->pseudoToMCOpcode(AMDGPU::V_PERM_B32_e64) != -1) {
14655 return performXorCombine(
N, DCI);
14657 return performZeroExtendCombine(
N, DCI);
14659 return performSignExtendInRegCombine(
N , DCI);
14661 return performClassCombine(
N, DCI);
14663 return performFCanonicalizeCombine(
N, DCI);
14665 return performRcpCombine(
N, DCI);
14680 return performUCharToFloatCombine(
N, DCI);
14682 return performFCopySignCombine(
N, DCI);
14687 return performCvtF32UByteNCombine(
N, DCI);
14689 return performFMed3Combine(
N, DCI);
14691 return performCvtPkRTZCombine(
N, DCI);
14693 return performClampCombine(
N, DCI);
14696 EVT VT =
N->getValueType(0);
14699 if (VT == MVT::v2i16 || VT == MVT::v2f16 || VT == MVT::v2bf16) {
14702 EVT EltVT = Src.getValueType();
14703 if (EltVT != MVT::i16)
14713 return performExtractVectorEltCombine(
N, DCI);
14715 return performInsertVectorEltCombine(
N, DCI);
14717 return performFPRoundCombine(
N, DCI);
14719 if (
SDValue Widened = widenLoad(cast<LoadSDNode>(
N), DCI))
14725 if (
MemSDNode *MemNode = dyn_cast<MemSDNode>(
N))
14726 return performMemSDNodeCombine(MemNode, DCI);
14739 default:
return ~0u;
14740 case AMDGPU::sub0:
return 0;
14741 case AMDGPU::sub1:
return 1;
14742 case AMDGPU::sub2:
return 2;
14743 case AMDGPU::sub3:
return 3;
14744 case AMDGPU::sub4:
return 4;
14751 unsigned Opcode =
Node->getMachineOpcode();
14755 if (D16Idx >= 0 &&
Node->getConstantOperandVal(D16Idx))
14761 unsigned OldDmask =
Node->getConstantOperandVal(DmaskIdx);
14762 unsigned NewDmask = 0;
14765 bool UsesTFC = ((int(TFEIdx) >= 0 &&
Node->getConstantOperandVal(TFEIdx)) ||
14766 (
int(LWEIdx) >= 0 &&
Node->getConstantOperandVal(LWEIdx)))
14769 unsigned TFCLane = 0;
14770 bool HasChain =
Node->getNumValues() > 1;
14772 if (OldDmask == 0) {
14780 TFCLane = OldBitsSet;
14788 if (
I.getUse().getResNo() != 0)
14792 if (!
I->isMachineOpcode() ||
14793 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
14805 if (UsesTFC && Lane == TFCLane) {
14810 for (
unsigned i = 0, Dmask = OldDmask; (i <= Lane) && (Dmask != 0); i++) {
14812 Dmask &= ~(1 << Comp);
14820 NewDmask |= 1 << Comp;
14825 bool NoChannels = !NewDmask;
14832 if (OldBitsSet == 1)
14838 if (NewDmask == OldDmask)
14847 unsigned NewChannels = BitsSet + UsesTFC;
14851 assert(NewOpcode != -1 &&
14852 NewOpcode !=
static_cast<int>(
Node->getMachineOpcode()) &&
14853 "failed to find equivalent MIMG op");
14861 MVT SVT =
Node->getValueType(0).getVectorElementType().getSimpleVT();
14863 MVT ResultVT = NewChannels == 1 ?
14865 NewChannels == 5 ? 8 : NewChannels);
14879 if (NewChannels == 1) {
14889 for (
unsigned i = 0,
Idx = AMDGPU::sub0; i < 5; ++i) {
14894 if (i || !NoChannels)
14899 if (NewUser !=
User) {
14907 case AMDGPU::sub0:
Idx = AMDGPU::sub1;
break;
14908 case AMDGPU::sub1:
Idx = AMDGPU::sub2;
break;
14909 case AMDGPU::sub2:
Idx = AMDGPU::sub3;
break;
14910 case AMDGPU::sub3:
Idx = AMDGPU::sub4;
break;
14920 Op =
Op.getOperand(0);
14922 return isa<FrameIndexSDNode>(
Op);
14931 RegisterSDNode *DestReg = cast<RegisterSDNode>(Node->getOperand(1));
14932 SDValue SrcVal = Node->getOperand(2);
14940 MRI.createVirtualRegister(&AMDGPU::VReg_1RegClass), MVT::i1);
14942 SDNode *Glued = Node->getGluedNode();
14944 = DAG.
getCopyToReg(Node->getOperand(0), SL, VReg, SrcVal,
14951 return ToResultReg.
getNode();
14956 for (
unsigned i = 0; i < Node->getNumOperands(); ++i) {
14964 Node->getOperand(i).getValueType(),
14965 Node->getOperand(i)), 0));
14976 unsigned Opcode = Node->getMachineOpcode();
14978 if (
TII->isImage(Opcode) && !
TII->get(Opcode).mayStore() &&
14979 !
TII->isGather4(Opcode) &&
14981 return adjustWritemask(Node, DAG);
14984 if (Opcode == AMDGPU::INSERT_SUBREG ||
14985 Opcode == AMDGPU::REG_SEQUENCE) {
14991 case AMDGPU::V_DIV_SCALE_F32_e64:
14992 case AMDGPU::V_DIV_SCALE_F64_e64: {
14996 SDValue Src0 = Node->getOperand(1);
14997 SDValue Src1 = Node->getOperand(3);
14998 SDValue Src2 = Node->getOperand(5);
15002 (Src0 == Src1 || Src0 == Src2))
15059 unsigned InitIdx = 0;
15061 if (
TII->isImage(
MI)) {
15069 unsigned TFEVal = TFE ? TFE->
getImm() : 0;
15070 unsigned LWEVal = LWE ? LWE->
getImm() : 0;
15071 unsigned D16Val = D16 ? D16->getImm() : 0;
15073 if (!TFEVal && !LWEVal)
15084 assert(MO_Dmask &&
"Expected dmask operand in instruction");
15086 unsigned dmask = MO_Dmask->
getImm();
15093 InitIdx = D16Val && Packed ? ((ActiveLanes + 1) >> 1) + 1 : ActiveLanes + 1;
15099 TRI.getRegSizeInBits(*
TII->getOpRegClass(
MI, DstIdx)) / 32;
15100 if (DstSize < InitIdx)
15103 InitIdx =
TRI.getRegSizeInBits(*
TII->getOpRegClass(
MI, DstIdx)) / 32;
15111 Register PrevDst =
MRI.cloneVirtualRegister(
MI.getOperand(DstIdx).getReg());
15112 unsigned NewDst = 0;
15121 for (; SizeLeft; SizeLeft--, CurrIdx++) {
15122 NewDst =
MRI.createVirtualRegister(
TII->getOpRegClass(
MI, DstIdx));
15140 MI.tieOperands(DstIdx,
MI.getNumOperands() - 1);
15153 if (
TII->isVOP3(
MI.getOpcode())) {
15155 TII->legalizeOperandsVOP3(
MRI,
MI);
15160 if (!
MI.getDesc().operands().empty()) {
15161 unsigned Opc =
MI.getOpcode();
15162 bool HasAGPRs =
Info->mayNeedAGPRs();
15170 if ((
I == Src2Idx) && (HasAGPRs))
15173 if (!
Op.isReg() || !
Op.getReg().isVirtual())
15175 auto *RC =
TRI->getRegClassForReg(
MRI,
Op.getReg());
15176 if (!
TRI->hasAGPRs(RC))
15178 auto *Src =
MRI.getUniqueVRegDef(
Op.getReg());
15179 if (!Src || !Src->isCopy() ||
15180 !
TRI->isSGPRReg(
MRI, Src->getOperand(1).getReg()))
15182 auto *NewRC =
TRI->getEquivalentVGPRClass(RC);
15186 MRI.setRegClass(
Op.getReg(), NewRC);
15193 if (
auto *Src2 =
TII->getNamedOperand(
MI, AMDGPU::OpName::src2)) {
15194 if (Src2->isReg() && Src2->getReg().isVirtual()) {
15195 auto *RC =
TRI->getRegClassForReg(
MRI, Src2->getReg());
15196 if (
TRI->isVectorSuperClass(RC)) {
15197 auto *NewRC =
TRI->getEquivalentAGPRClass(RC);
15198 MRI.setRegClass(Src2->getReg(), NewRC);
15199 if (Src2->isTied())
15200 MRI.setRegClass(
MI.getOperand(0).getReg(), NewRC);
15209 if (
TII->isImage(
MI))
15210 TII->enforceOperandRCAlignment(
MI, AMDGPU::OpName::vaddr);
15236 MVT::v2i32, Ops0), 0);
15266 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
15288std::pair<unsigned, const TargetRegisterClass *>
15295 if (Constraint.
size() == 1) {
15297 switch (Constraint[0]) {
15304 RC = &AMDGPU::SReg_32RegClass;
15307 RC = &AMDGPU::SGPR_64RegClass;
15312 return std::pair(0U,
nullptr);
15319 RC = &AMDGPU::VGPR_32RegClass;
15324 return std::pair(0U,
nullptr);
15333 RC = &AMDGPU::AGPR_32RegClass;
15338 return std::pair(0U,
nullptr);
15347 return std::pair(0U, RC);
15352 if (
RegName.consume_front(
"v")) {
15353 RC = &AMDGPU::VGPR_32RegClass;
15354 }
else if (
RegName.consume_front(
"s")) {
15355 RC = &AMDGPU::SGPR_32RegClass;
15356 }
else if (
RegName.consume_front(
"a")) {
15357 RC = &AMDGPU::AGPR_32RegClass;
15362 if (
RegName.consume_front(
"[")) {
15372 RC =
TRI->getVGPRClassForBitWidth(Width);
15374 RC =
TRI->getSGPRClassForBitWidth(Width);
15376 RC =
TRI->getAGPRClassForBitWidth(Width);
15378 Reg =
TRI->getMatchingSuperReg(Reg, AMDGPU::sub0, RC);
15379 return std::pair(Reg, RC);
15384 if (!
Failed && Idx < RC->getNumRegs())
15392 Ret.second =
TRI->getPhysRegBaseClass(Ret.first);
15398 if (Constraint.
size() == 1) {
15399 switch (Constraint[0]) {
15408 }
else if (Constraint ==
"DA" ||
15409 Constraint ==
"DB") {
15417 if (Constraint.
size() == 1) {
15418 switch (Constraint[0]) {
15434 Val = Val & maskTrailingOnes<uint64_t>(
Size);
15441 std::vector<SDValue> &Ops,
15456 unsigned Size =
Op.getScalarValueSizeInBits();
15464 Val =
C->getSExtValue();
15468 Val =
C->getValueAPF().bitcastToAPInt().getSExtValue();
15474 if (
Op.getOperand(0).isUndef() ||
Op.getOperand(1).isUndef())
15477 Val =
C->getSExtValue();
15481 Val =
C->getValueAPF().bitcastToAPInt().getSExtValue();
15491 if (Constraint.
size() == 1) {
15492 switch (Constraint[0]) {
15496 return isInt<16>(Val);
15500 return isInt<32>(Val);
15507 }
else if (Constraint.
size() == 2) {
15508 if (Constraint ==
"DA") {
15509 int64_t HiBits =
static_cast<int32_t
>(Val >> 32);
15510 int64_t LoBits =
static_cast<int32_t
>(Val);
15514 if (Constraint ==
"DB") {
15522 unsigned MaxSize)
const {
15523 unsigned Size = std::min<unsigned>(
Op.getScalarValueSizeInBits(), MaxSize);
15526 MVT VT =
Op.getSimpleValueType();
15551 switch (UnalignedClassID) {
15552 case AMDGPU::VReg_64RegClassID:
15553 return AMDGPU::VReg_64_Align2RegClassID;
15554 case AMDGPU::VReg_96RegClassID:
15555 return AMDGPU::VReg_96_Align2RegClassID;
15556 case AMDGPU::VReg_128RegClassID:
15557 return AMDGPU::VReg_128_Align2RegClassID;
15558 case AMDGPU::VReg_160RegClassID:
15559 return AMDGPU::VReg_160_Align2RegClassID;
15560 case AMDGPU::VReg_192RegClassID:
15561 return AMDGPU::VReg_192_Align2RegClassID;
15562 case AMDGPU::VReg_224RegClassID:
15563 return AMDGPU::VReg_224_Align2RegClassID;
15564 case AMDGPU::VReg_256RegClassID:
15565 return AMDGPU::VReg_256_Align2RegClassID;
15566 case AMDGPU::VReg_288RegClassID:
15567 return AMDGPU::VReg_288_Align2RegClassID;
15568 case AMDGPU::VReg_320RegClassID:
15569 return AMDGPU::VReg_320_Align2RegClassID;
15570 case AMDGPU::VReg_352RegClassID:
15571 return AMDGPU::VReg_352_Align2RegClassID;
15572 case AMDGPU::VReg_384RegClassID:
15573 return AMDGPU::VReg_384_Align2RegClassID;
15574 case AMDGPU::VReg_512RegClassID:
15575 return AMDGPU::VReg_512_Align2RegClassID;
15576 case AMDGPU::VReg_1024RegClassID:
15577 return AMDGPU::VReg_1024_Align2RegClassID;
15578 case AMDGPU::AReg_64RegClassID:
15579 return AMDGPU::AReg_64_Align2RegClassID;
15580 case AMDGPU::AReg_96RegClassID:
15581 return AMDGPU::AReg_96_Align2RegClassID;
15582 case AMDGPU::AReg_128RegClassID:
15583 return AMDGPU::AReg_128_Align2RegClassID;
15584 case AMDGPU::AReg_160RegClassID:
15585 return AMDGPU::AReg_160_Align2RegClassID;
15586 case AMDGPU::AReg_192RegClassID:
15587 return AMDGPU::AReg_192_Align2RegClassID;
15588 case AMDGPU::AReg_256RegClassID:
15589 return AMDGPU::AReg_256_Align2RegClassID;
15590 case AMDGPU::AReg_512RegClassID:
15591 return AMDGPU::AReg_512_Align2RegClassID;
15592 case AMDGPU::AReg_1024RegClassID:
15593 return AMDGPU::AReg_1024_Align2RegClassID;
15609 if (
Info->isEntryFunction()) {
15616 unsigned MaxNumSGPRs = ST.getMaxNumSGPRs(MF);
15618 ? AMDGPU::SGPR_32RegClass.getRegister(MaxNumSGPRs - 1)
15619 :
TRI->getAlignedHighSGPRForRC(MF, 2,
15620 &AMDGPU::SGPR_64RegClass);
15621 Info->setSGPRForEXECCopy(SReg);
15624 Info->getStackPtrOffsetReg()));
15625 if (
Info->getStackPtrOffsetReg() != AMDGPU::SP_REG)
15626 MRI.replaceRegWith(AMDGPU::SP_REG,
Info->getStackPtrOffsetReg());
15630 if (
Info->getScratchRSrcReg() != AMDGPU::PRIVATE_RSRC_REG)
15631 MRI.replaceRegWith(AMDGPU::PRIVATE_RSRC_REG,
Info->getScratchRSrcReg());
15633 if (
Info->getFrameOffsetReg() != AMDGPU::FP_REG)
15634 MRI.replaceRegWith(AMDGPU::FP_REG,
Info->getFrameOffsetReg());
15636 Info->limitOccupancy(MF);
15638 if (ST.isWave32() && !MF.
empty()) {
15639 for (
auto &
MBB : MF) {
15640 for (
auto &
MI :
MBB) {
15641 TII->fixImplicitOperands(
MI);
15651 if (ST.needsAlignedVGPRs()) {
15652 for (
unsigned I = 0, E =
MRI.getNumVirtRegs();
I != E; ++
I) {
15658 if (NewClassID != -1)
15659 MRI.setRegClass(Reg,
TRI->getRegClass(NewClassID));
15668 const APInt &DemandedElts,
15670 unsigned Depth)
const {
15672 unsigned Opc =
Op.getOpcode();
15675 unsigned IID =
Op.getConstantOperandVal(0);
15677 case Intrinsic::amdgcn_mbcnt_lo:
15678 case Intrinsic::amdgcn_mbcnt_hi: {
15685 unsigned MaxActiveBits = std::max(Src1ValBits, ST.getWavefrontSizeLog2());
15687 MaxActiveBits += Src1ValBits ? 1 : 0;
15688 unsigned Size =
Op.getValueType().getSizeInBits();
15689 if (MaxActiveBits <
Size)
15698 Op, Known, DemandedElts, DAG,
Depth);
15713 unsigned MaxValue =
15722 switch (
MI->getOpcode()) {
15723 case AMDGPU::G_INTRINSIC:
15724 case AMDGPU::G_INTRINSIC_CONVERGENT: {
15726 case Intrinsic::amdgcn_workitem_id_x:
15729 case Intrinsic::amdgcn_workitem_id_y:
15732 case Intrinsic::amdgcn_workitem_id_z:
15735 case Intrinsic::amdgcn_mbcnt_lo:
15736 case Intrinsic::amdgcn_mbcnt_hi: {
15738 unsigned Size =
MRI.getType(R).getSizeInBits();
15742 case Intrinsic::amdgcn_groupstaticsize: {
15753 case AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE:
15756 case AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT:
15759 case AMDGPU::G_AMDGPU_SMED3:
15760 case AMDGPU::G_AMDGPU_UMED3: {
15761 auto [Dst, Src0, Src1, Src2] =
MI->getFirst4Regs();
15788 unsigned Depth)
const {
15790 if (
auto *GI = dyn_cast<GIntrinsic>(
MI)) {
15796 if (
MaybeAlign RetAlign = Attrs.getRetAlignment())
15823 if (Header->getAlignment() != PrefAlign)
15824 return Header->getAlignment();
15826 unsigned LoopSize = 0;
15834 LoopSize +=
TII->getInstSizeInBytes(
MI);
15835 if (LoopSize > 192)
15840 if (LoopSize <= 64)
15843 if (LoopSize <= 128)
15844 return CacheLineAlign;
15850 auto I = Exit->getFirstNonDebugInstr();
15851 if (
I != Exit->end() &&
I->getOpcode() == AMDGPU::S_INST_PREFETCH)
15852 return CacheLineAlign;
15861 if (PreTerm == Pre->
begin() ||
15862 std::prev(PreTerm)->getOpcode() != AMDGPU::S_INST_PREFETCH)
15866 auto ExitHead = Exit->getFirstNonDebugInstr();
15867 if (ExitHead == Exit->end() ||
15868 ExitHead->getOpcode() != AMDGPU::S_INST_PREFETCH)
15873 return CacheLineAlign;
15881 N =
N->getOperand(0).getNode();
15892 switch (
N->getOpcode()) {
15900 if (Reg.isPhysical() ||
MRI.isLiveIn(Reg))
15901 return !
TRI->isSGPRReg(
MRI, Reg);
15907 return !
TRI->isSGPRReg(
MRI, Reg);
15911 unsigned AS = L->getAddressSpace();
15945 if (
auto *
A = dyn_cast<AtomicSDNode>(
N)) {
15947 return A->readMem() &&
A->writeMem();
15982 unsigned Depth)
const {
15987 if (
Info->getMode().DX10Clamp)
16000static bool fpModeMatchesGlobalFPAtomicMode(
const AtomicRMWInst *RMW) {
16014 return F->getFnAttribute(
"amdgpu-unsafe-fp-atomics").getValueAsString() !=
16027 <<
"Hardware instruction generated for atomic "
16029 <<
" operation at memory scope " << MemScope;
16047 bool HasSystemScope =
16106 if (HasSystemScope)
16155 if (HasSystemScope)
16192 if (RC == &AMDGPU::VReg_1RegClass && !isDivergent)
16194 : &AMDGPU::SReg_32RegClass;
16195 if (!
TRI->isSGPRClass(RC) && !isDivergent)
16196 return TRI->getEquivalentSGPRClass(RC);
16197 else if (
TRI->isSGPRClass(RC) && isDivergent)
16198 return TRI->getEquivalentVGPRClass(RC);
16210 unsigned WaveSize) {
16215 if (!
IT ||
IT->getBitWidth() != WaveSize)
16218 if (!isa<Instruction>(V))
16220 if (!Visited.
insert(V).second)
16222 bool Result =
false;
16223 for (
const auto *U : V->users()) {
16224 if (
const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(U)) {
16225 if (V == U->getOperand(1)) {
16226 switch (Intrinsic->getIntrinsicID()) {
16230 case Intrinsic::amdgcn_if_break:
16231 case Intrinsic::amdgcn_if:
16232 case Intrinsic::amdgcn_else:
16237 if (V == U->getOperand(0)) {
16238 switch (Intrinsic->getIntrinsicID()) {
16242 case Intrinsic::amdgcn_end_cf:
16243 case Intrinsic::amdgcn_loop:
16249 Result =
hasCFUser(U, Visited, WaveSize);
16258 const Value *V)
const {
16259 if (
const CallInst *CI = dyn_cast<CallInst>(V)) {
16260 if (CI->isInlineAsm()) {
16269 for (
auto &TC : TargetConstraints) {
16273 SIRI, TC.ConstraintCode, TC.ConstraintVT).second;
16286 for (;
I != E; ++
I) {
16287 if (
MemSDNode *M = dyn_cast<MemSDNode>(*
I)) {
16310 return MRI.hasOneNonDBGUse(N0);
16317 if (
I.getMetadata(
"amdgpu.noclobber"))
16319 if (
I.getMetadata(
"amdgpu.last.use"))
16329 if (!Def->isMachineOpcode())
16340 PhysReg = AMDGPU::SCC;
16342 TRI->getMinimalPhysRegClass(PhysReg, Def->getSimpleValueType(ResNo));
16356 "this cannot be replaced with add");
16362 "target should have atomic fadd instructions");
16365 "generic atomicrmw expansion only supports FP32 operand in flat "
16439 for (
auto &
P : MDs)
16450 {
Addr},
nullptr,
"is.shared");
16451 Builder.
CreateCondBr(IsShared, SharedBB, CheckPrivateBB);
16456 Value *LoadedShared = CreateNewAtomicRMW(Builder, CastToLocal, Val);
16461 Intrinsic::amdgcn_is_private, {}, {
Addr},
nullptr,
"is.private");
16467 Value *LoadedPrivate =
16468 Builder.
CreateLoad(ValTy, CastToPrivate,
"loaded.private");
16476 Value *LoadedGlobal = CreateNewAtomicRMW(Builder, CastToGlobal, Val);
static bool isMul(MachineInstr *MI)
unsigned const MachineRegisterInfo * MRI
static unsigned getIntrinsicID(const SDNode *N)
static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls)
Return true if the calling convention is one that we can guarantee TCO for.
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static constexpr std::pair< ImplicitArgumentMask, StringLiteral > ImplicitAttrs[]
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
static bool parseTexFail(uint64_t TexFailCtrl, bool &TFE, bool &LWE, bool &IsTexFail)
static void packImage16bitOpsToDwords(MachineIRBuilder &B, MachineInstr &MI, SmallVectorImpl< Register > &PackedAddrs, unsigned ArgOffset, const AMDGPU::ImageDimIntrinsicInfo *Intr, bool IsA16, bool IsG16)
Turn a set of s16 typed registers in AddrRegs into a dword sized vector with s16 typed elements.
static bool isKnownNonNull(Register Val, MachineRegisterInfo &MRI, const AMDGPUTargetMachine &TM, unsigned AddrSpace)
Return true if the value is a known valid address, such that a null check is not necessary.
Provides AMDGPU specific target descriptions.
The AMDGPU TargetMachine interface definition for hw codegen targets.
This file implements a class to represent arbitrary precision integral constant values and operations...
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate any type of IT block"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow complex IT blocks")))
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
#define LLVM_ATTRIBUTE_UNUSED
static std::optional< SDByteProvider > calculateByteProvider(SDValue Op, unsigned Index, unsigned Depth, std::optional< uint64_t > VectorIndex, unsigned StartingIndex=0)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static bool isSigned(unsigned int Opcode)
Utilities for dealing with flags related to floating point properties and mode controls.
AMD GCN specific subclass of TargetSubtarget.
Provides analysis for querying information about KnownBits during GISel passes.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
static bool isUndef(ArrayRef< int > Mask)
iv Induction Variable Users
static const unsigned MaxDepth
Contains matchers for matching SSA Machine Instructions.
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
static void r0(uint32_t &A, uint32_t &B, uint32_t &C, uint32_t &D, uint32_t &E, int I, uint32_t *Buf)
static void r3(uint32_t &A, uint32_t &B, uint32_t &C, uint32_t &D, uint32_t &E, int I, uint32_t *Buf)
static void r2(uint32_t &A, uint32_t &B, uint32_t &C, uint32_t &D, uint32_t &E, int I, uint32_t *Buf)
static void r1(uint32_t &A, uint32_t &B, uint32_t &C, uint32_t &D, uint32_t &E, int I, uint32_t *Buf)
#define FP_DENORM_FLUSH_NONE
#define FP_DENORM_FLUSH_IN_FLUSH_OUT
static void reservePrivateMemoryRegs(const TargetMachine &TM, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info)
static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT, const SDLoc &DL, SelectionDAG &DAG, bool Unpacked)
static MachineBasicBlock * emitIndirectSrc(MachineInstr &MI, MachineBasicBlock &MBB, const GCNSubtarget &ST)
static bool denormalModeIsFlushAllF64F16(const MachineFunction &MF)
static EVT memVTFromLoadIntrData(Type *Ty, unsigned MaxNumLanes)
static std::pair< unsigned, int > computeIndirectRegAndOffset(const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, unsigned VecReg, int Offset)
static bool denormalModeIsFlushAllF32(const MachineFunction &MF)
static bool addresses16Bits(int Mask)
static bool isClampZeroToOne(SDValue A, SDValue B)
static unsigned findFirstFreeSGPR(CCState &CCInfo)
static uint32_t getPermuteMask(SDValue V)
static int getAlignedAGPRClassID(unsigned UnalignedClassID)
static void processPSInputArgs(SmallVectorImpl< ISD::InputArg > &Splits, CallingConv::ID CallConv, ArrayRef< ISD::InputArg > Ins, BitVector &Skipped, FunctionType *FType, SIMachineFunctionInfo *Info)
static SDValue selectSOffset(SDValue SOffset, SelectionDAG &DAG, const GCNSubtarget *Subtarget)
static SDValue getLoadExtOrTrunc(SelectionDAG &DAG, ISD::LoadExtType ExtType, SDValue Op, const SDLoc &SL, EVT VT)
static void fixMasks(SmallVectorImpl< DotSrc > &Srcs, unsigned ChainLength)
static SDValue strictFPExtFromF16(SelectionDAG &DAG, SDValue Src)
Return the source of an fp_extend from f16 to f32, or a converted FP constant.
static bool bitOpWithConstantIsReducible(unsigned Opc, uint32_t Val)
static cl::opt< bool > DisableLoopAlignment("amdgpu-disable-loop-alignment", cl::desc("Do not align and prefetch loops"), cl::init(false))
static SDValue getDWordFromOffset(SelectionDAG &DAG, SDLoc SL, SDValue Src, unsigned DWordOffset)
static MachineBasicBlock::iterator loadM0FromVGPR(const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineInstr &MI, unsigned InitResultReg, unsigned PhiReg, int Offset, bool UseGPRIdxMode, Register &SGPRIdxReg)
static bool isImmConstraint(StringRef Constraint)
static SDValue padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT, SDValue Src, int ExtraElts)
static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG)
static bool hasCFUser(const Value *V, SmallPtrSet< const Value *, 16 > &Visited, unsigned WaveSize)
static OptimizationRemark emitAtomicRMWLegalRemark(const AtomicRMWInst *RMW)
static EVT memVTFromLoadIntrReturn(Type *Ty, unsigned MaxNumLanes)
static unsigned SubIdx2Lane(unsigned Idx)
Helper function for adjustWritemask.
static bool addressMayBeAccessedAsPrivate(const MachineMemOperand *MMO, const SIMachineFunctionInfo &Info)
static MachineBasicBlock * lowerWaveReduce(MachineInstr &MI, MachineBasicBlock &BB, const GCNSubtarget &ST, unsigned Opc)
static bool elementPairIsContiguous(ArrayRef< int > Mask, int Elt)
static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo, const TargetRegisterClass *RC, unsigned NumArgRegs)
static SDValue getMad64_32(SelectionDAG &DAG, const SDLoc &SL, EVT VT, SDValue N0, SDValue N1, SDValue N2, bool Signed)
static SDValue resolveSources(SelectionDAG &DAG, SDLoc SL, SmallVectorImpl< DotSrc > &Srcs, bool IsSigned, bool IsAny)
static bool hasNon16BitAccesses(uint64_t PermMask, SDValue &Op, SDValue &OtherOp)
static void placeSources(ByteProvider< SDValue > &Src0, ByteProvider< SDValue > &Src1, SmallVectorImpl< DotSrc > &Src0s, SmallVectorImpl< DotSrc > &Src1s, int Step)
bool unsafeFPAtomicsDisabled(Function *F)
static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop(const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, const DebugLoc &DL, const MachineOperand &Idx, unsigned InitReg, unsigned ResultReg, unsigned PhiReg, unsigned InitSaveExecReg, int Offset, bool UseGPRIdxMode, Register &SGPRIdxReg)
static SDValue matchPERM(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static bool isFrameIndexOp(SDValue Op)
static ConstantFPSDNode * getSplatConstantFP(SDValue Op)
static void allocateSGPR32Input(CCState &CCInfo, ArgDescriptor &Arg)
static bool isExtendedFrom16Bits(SDValue &Operand)
static std::optional< bool > checkDot4MulSignedness(const SDValue &N, ByteProvider< SDValue > &Src0, ByteProvider< SDValue > &Src1, const SDValue &S0Op, const SDValue &S1Op, const SelectionDAG &DAG)
static bool vectorEltWillFoldAway(SDValue Op)
static SDValue getSPDenormModeValue(uint32_t SPDenormMode, SelectionDAG &DAG, const SIMachineFunctionInfo *Info, const GCNSubtarget *ST)
static uint32_t getConstantPermuteMask(uint32_t C)
static MachineBasicBlock * emitIndirectDst(MachineInstr &MI, MachineBasicBlock &MBB, const GCNSubtarget &ST)
static void setM0ToIndexFromSGPR(const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineInstr &MI, int Offset)
static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask=~0u, ArgDescriptor Arg=ArgDescriptor())
static std::pair< MachineBasicBlock *, MachineBasicBlock * > splitBlockForLoop(MachineInstr &MI, MachineBasicBlock &MBB, bool InstInLoop)
static unsigned getBasePtrIndex(const MemSDNode *N)
MemSDNode::getBasePtr() does not work for intrinsics, which needs to offset by the chain and intrinsi...
static void knownBitsForWorkitemID(const GCNSubtarget &ST, GISelKnownBits &KB, KnownBits &Known, unsigned Dim)
static LLVM_ATTRIBUTE_UNUSED bool isCopyFromRegOfInlineAsm(const SDNode *N)
static void allocateFixedSGPRInputImpl(CCState &CCInfo, const TargetRegisterClass *RC, MCRegister Reg)
static SDValue constructRetValue(SelectionDAG &DAG, MachineSDNode *Result, ArrayRef< EVT > ResultTypes, bool IsTexFail, bool Unpacked, bool IsD16, int DMaskPop, int NumVDataDwords, bool IsAtomicPacked16Bit, const SDLoc &DL)
static std::optional< ByteProvider< SDValue > > handleMulOperand(const SDValue &MulOperand)
static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG)
static Register getIndirectSGPRIdx(const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineInstr &MI, int Offset)
static SDValue emitNonHSAIntrinsicError(SelectionDAG &DAG, const SDLoc &DL, EVT VT)
static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc)
static unsigned getIdxEn(SDValue VIndex)
static SDValue lowerBALLOTIntrinsic(const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG)
static SDValue buildSMovImm32(SelectionDAG &DAG, const SDLoc &DL, uint64_t Val)
static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL, ArrayRef< SDValue > Elts)
static SDNode * findUser(SDValue Value, unsigned Opcode)
Helper function for LowerBRCOND.
static unsigned addPermMasks(unsigned First, unsigned Second)
static uint64_t clearUnusedBits(uint64_t Val, unsigned Size)
static SDValue getFPTernOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, EVT VT, SDValue A, SDValue B, SDValue C, SDValue GlueChain, SDNodeFlags Flags)
static SDValue emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL, EVT VT)
static SDValue getFPBinOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, EVT VT, SDValue A, SDValue B, SDValue GlueChain, SDNodeFlags Flags)
static SDValue buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV, const SDLoc &DL, int64_t Offset, EVT PtrVT, unsigned GAFlags=SIInstrInfo::MO_NONE)
static cl::opt< bool > UseDivergentRegisterIndexing("amdgpu-use-divergent-register-indexing", cl::Hidden, cl::desc("Use indirect register addressing for divergent indexes"), cl::init(false))
static const std::optional< ByteProvider< SDValue > > calculateSrcByte(const SDValue Op, uint64_t DestByte, uint64_t SrcIndex=0, unsigned Depth=0)
static void allocateSGPR64Input(CCState &CCInfo, ArgDescriptor &Arg)
SI DAG Lowering interface definition.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static constexpr int Concat[]
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
void setFuncArgInfo(const Function &F, const AMDGPUFunctionArgInfo &ArgInfo)
static bool isUniformMMO(const MachineMemOperand *MMO)
static std::optional< uint32_t > getLDSKernelIdMetadata(const Function &F)
uint32_t getLDSSize() const
void setUsesDynamicLDS(bool DynLDS)
void setDynLDSAlign(const Function &F, const GlobalVariable &GV)
bool isEntryFunction() const
bool hasMadMacF32Insts() const
bool useRealTrue16Insts() const
Return true if real (non-fake) variants of True16 instructions using 16-bit registers should be code-...
unsigned getMaxWorkitemID(const Function &Kernel, unsigned Dimension) const
Return the maximum workitem ID value in the function, for the given (0, 1, 2) dimension.
bool hasMadMixInsts() const
unsigned getWavefrontSizeLog2() const
bool has16BitInsts() const
bool isAmdHsaOrMesa(const Function &F) const
bool hasFastFMAF32() const
bool hasTrigReducedRange() const
unsigned getWavefrontSize() const
bool hasInv2PiInlineImm() const
bool hasVOP3PInsts() const
static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG)
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types.
SDValue storeStackInputValue(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain, SDValue ArgVal, int64_t Offset) const
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
SDValue lowerUnhandledCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals, StringRef Reason) const
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, MachineFrameInfo &MFI, int ClobberedFI) const
static bool needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src, SDNodeFlags Flags)
uint32_t getImplicitParameterOffset(const MachineFunction &MF, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
SDValue loadInputValue(SelectionDAG &DAG, const TargetRegisterClass *RC, EVT VT, const SDLoc &SL, const ArgDescriptor &Arg) const
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT, const SDLoc &SL, bool RawReg=false) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
Selects the correct CCAssignFn for a given CallingConvention value.
static bool allUsesHaveSourceMods(const SDNode *N, unsigned CostThreshold=4)
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG)
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
static bool allowApproxFunc(const SelectionDAG &DAG, SDNodeFlags Flags)
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const
static bool shouldFoldFNegIntoSrc(SDNode *FNeg, SDValue FNegSrc)
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Widen a suitably aligned v3 load.
static APFloat getQNaN(const fltSemantics &Sem, bool Negative=false, const APInt *payload=nullptr)
Factory for QNaN values.
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
APInt bitcastToAPInt() const
static APFloat getLargest(const fltSemantics &Sem, bool Negative=false)
Returns the largest finite number in the given semantics.
static APFloat getInf(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Infinity.
static APFloat getZero(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Zero.
Class for arbitrary precision integers.
void setHighBits(unsigned hiBits)
Set the top hiBits bits.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
bool isSignMask() const
Check if the APInt's value is returned by getSignMask.
unsigned countr_zero() const
Count the number of trailing zero bits.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
bool sge(const APInt &RHS) const
Signed greater or equal comparison.
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
An instruction that atomically checks whether a specified value is in a memory location,...
unsigned getPointerAddressSpace() const
Returns the address space of the pointer operand.
an instruction that atomically reads a memory location, combines it with another value,...
Align getAlign() const
Return the alignment of the memory that is being allocated by the instruction.
BinOp
This enumeration lists the possible modifications atomicrmw can make.
@ Min
*p = old <signed v ? old : v
@ Max
*p = old >signed v ? old : v
@ UMin
*p = old <unsigned v ? old : v
@ FMin
*p = minnum(old, v) minnum matches the behavior of llvm.minnum.
@ UMax
*p = old >unsigned v ? old : v
@ FMax
*p = maxnum(old, v) maxnum matches the behavior of llvm.maxnum.
Value * getPointerOperand()
void setOperation(BinOp Operation)
BinOp getOperation() const
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this rmw instruction.
static StringRef getOperationName(BinOp Op)
AtomicOrdering getOrdering() const
Returns the ordering constraint of this rmw instruction.
unsigned getPointerAddressSpace() const
Returns the address space of the pointer operand.
This is an SDNode representing atomic operations.
bool isCompareAndSwap() const
Returns true if this SDNode represents cmpxchg atomic operation, false otherwise.
MemoryEffects getMemoryEffects() const
Returns memory effects of the function.
LLVM Basic Block Representation.
static BasicBlock * Create(LLVMContext &Context, const Twine &Name="", Function *Parent=nullptr, BasicBlock *InsertBefore=nullptr)
Creates a new BasicBlock.
BasicBlock * splitBasicBlock(iterator I, const Twine &BBName="", bool Before=false)
Split the basic block into two basic blocks at the specified instruction.
const Function * getParent() const
Return the enclosing method, or null if none.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Represents known origin of an individual byte in combine pattern.
static ByteProvider getConstantZero()
static ByteProvider getSrc(std::optional< ISelOp > Val, int64_t ByteOffset, int64_t VectorOffset)
std::optional< ISelOp > Src
CCState - This class holds information needed while lowering arguments and return values.
MachineFunction & getMachineFunction() const
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
static bool resultsCompatible(CallingConv::ID CalleeCC, CallingConv::ID CallerCC, MachineFunction &MF, LLVMContext &C, const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn CalleeFn, CCAssignFn CallerFn)
Returns true if the results of the two calling conventions are compatible.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
bool isAllocated(MCRegister Reg) const
isAllocated - Return true if the specified register (or an alias) is allocated.
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
int64_t getLocMemOffset() const
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation or the function signa...
bool hasFnAttr(Attribute::AttrKind Kind) const
Determine whether this call has the given attribute.
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
Value * getArgOperand(unsigned i) const
unsigned arg_size() const
This class represents a function call, abstracting a target machine's calling convention.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
bool isFPPredicate() const
bool isIntPredicate() const
const APFloat & getValueAPF() const
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
bool isNegative() const
Return true if the value is negative.
bool isInfinity() const
Return true if the value is an infinity.
This is the shared class of boolean and integer constants.
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
uint64_t getZExtValue() const
const APInt & getAPIntValue() const
This is an important base class in LLVM.
bool isNullValue() const
Return true if this is the value that would be returned by getNullValue.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Diagnostic information for unsupported feature in backend.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Register DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
const Value * getValueFromVirtualReg(Register Vreg)
This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence to get the Value correspondi...
Class to represent function types.
Type * getParamType(unsigned i) const
Parameter type accessors.
FunctionType * getFunctionType() const
Returns the FunctionType for me.
iterator_range< arg_iterator > args()
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
DenormalMode getDenormalMode(const fltSemantics &FPType) const
Returns the denormal handling type for the default rounding mode of the function.
bool hasD16Images() const
bool hasImageStoreD16Bug() const
bool hasUsableDivScaleConditionOutput() const
Condition output from div_scale is usable.
bool hasUsableDSOffset() const
True if the offset field of DS instructions works as expected.
bool hasDot7Insts() const
bool hasApertureRegs() const
bool hasFlatInstOffsets() const
bool hasCompressedExport() const
Return true if the target's EXP instruction has the COMPR flag, which affects the meaning of the EN (...
bool hasGFX90AInsts() const
bool hasBCNT(unsigned Size) const
bool hasMultiDwordFlatScratchAddressing() const
bool hasArchitectedSGPRs() const
bool hasDenormModeInst() const
bool hasPrivEnabledTrap2NopBug() const
bool hasUnalignedDSAccessEnabled() const
const SIInstrInfo * getInstrInfo() const override
bool hasDot1Insts() const
bool hasAtomicFaddRtnInsts() const
Align getStackAlignment() const
bool hasScalarSubwordLoads() const
bool enableFlatScratch() const
bool hasDwordx3LoadStores() const
bool hasFlatScrRegister() const
bool supportsGetDoorbellID() const
bool hasFlatAtomicFaddF32Inst() const
bool hasKernargPreload() const
const SIRegisterInfo * getRegisterInfo() const override
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const
bool hasLDSMisalignedBug() const
bool hasUserSGPRInit16Bug() const
TrapHandlerAbi getTrapHandlerAbi() const
const SIFrameLowering * getFrameLowering() const override
bool hasUnalignedScratchAccess() const
bool hasRestrictedSOffset() const
bool hasMin3Max3_16() const
bool hasGFX10_AEncoding() const
bool hasPackedFP32Ops() const
bool hasGFX940Insts() const
bool hasFullRate64Ops() const
bool isTrapHandlerEnabled() const
bool hasLDSFPAtomicAddF64() const
bool hasFlatGlobalInsts() const
bool getScalarizeGlobalBehavior() const
bool hasScalarSMulU64() const
unsigned getKnownHighZeroBitsForFrameIndex() const
Return the number of high bits known to be zero for a frame index.
bool hasShaderCyclesHiLoRegisters() const
bool hasNSAEncoding() const
bool hasSMemRealTime() const
bool usePRTStrictNull() const
bool hasUnalignedBufferAccessEnabled() const
unsigned getMaxPrivateElementSize(bool ForBufferRSrc=false) const
bool hasImageGather4D16Bug() const
bool supportsMinMaxDenormModes() const
bool hasAtomicFaddInsts() const
unsigned getNSAMaxSize(bool HasSampler=false) const
bool hasAtomicFaddNoRtnInsts() const
bool hasScalarDwordx3Loads() const
bool hasLDSFPAtomicAddF32() const
bool haveRoundOpsF64() const
Have v_trunc_f64, v_ceil_f64, v_rndne_f64.
bool hasDot8Insts() const
bool hasDS96AndDS128() const
bool useFlatForGlobal() const
Generation getGeneration() const
bool hasScalarAddSub64() const
bool hasUnpackedD16VMem() const
bool hasIEEEMinMax() const
bool hasFmaMixInsts() const
bool hasPackedTID() const
bool hasAddNoCarry() const
bool hasGWSAutoReplay() const
bool hasKernargSegmentPtr() const
bool hasDispatchID() const
bool hasPrivateSegmentBuffer() const
unsigned getNumFreeUserSGPRs()
bool hasImplicitBufferPtr() const
bool hasDispatchPtr() const
bool hasFlatScratchInit() const
virtual void computeKnownBitsImpl(Register R, KnownBits &Known, const APInt &DemandedElts, unsigned Depth=0)
const MachineFunction & getMachineFunction() const
int64_t getOffset() const
unsigned getAddressSpace() const
const GlobalValue * getGlobal() const
bool hasExternalLinkage() const
unsigned getAddressSpace() const
Module * getParent()
Get the module that this global value is contained inside of...
Type * getValueType() const
LoadInst * CreateAlignedLoad(Type *Ty, Value *Ptr, MaybeAlign Align, const char *Name)
Value * CreateFAdd(Value *L, Value *R, const Twine &Name="", MDNode *FPMD=nullptr)
CallInst * CreateIntrinsic(Intrinsic::ID ID, ArrayRef< Type * > Types, ArrayRef< Value * > Args, Instruction *FMFSource=nullptr, const Twine &Name="")
Create a call to intrinsic ID with Args, mangled using Types.
BasicBlock::iterator GetInsertPoint() const
BasicBlock * GetInsertBlock() const
PHINode * CreatePHI(Type *Ty, unsigned NumReservedValues, const Twine &Name="")
BranchInst * CreateCondBr(Value *Cond, BasicBlock *True, BasicBlock *False, MDNode *BranchWeights=nullptr, MDNode *Unpredictable=nullptr)
Create a conditional 'br Cond, TrueDest, FalseDest' instruction.
LoadInst * CreateLoad(Type *Ty, Value *Ptr, const char *Name)
Provided to resolve 'CreateLoad(Ty, Ptr, "...")' correctly, instead of converting the string to 'bool...
LLVMContext & getContext() const
StoreInst * CreateStore(Value *Val, Value *Ptr, bool isVolatile=false)
AtomicRMWInst * CreateAtomicRMW(AtomicRMWInst::BinOp Op, Value *Ptr, Value *Val, MaybeAlign Align, AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System)
BranchInst * CreateBr(BasicBlock *Dest)
Create an unconditional 'br label X' instruction.
void SetInsertPoint(BasicBlock *TheBB)
This specifies that created instructions should be appended to the end of the specified block.
Value * CreateAddrSpaceCast(Value *V, Type *DestTy, const Twine &Name="")
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
const BasicBlock * getParent() const
InstListType::iterator eraseFromParent()
This method unlinks 'this' from the containing basic block and deletes it.
const Function * getFunction() const
Return the function this instruction belongs to.
void setMetadata(unsigned KindID, MDNode *Node)
Set the metadata of the specified kind to the specified node.
void getAllMetadata(SmallVectorImpl< std::pair< unsigned, MDNode * > > &MDs) const
Get all metadata attached to this Instruction.
void copyMetadata(const Instruction &SrcInst, ArrayRef< unsigned > WL=ArrayRef< unsigned >())
Copy metadata from SrcInst to this instruction.
Class to represent integer types.
A wrapper class for inspecting calls to intrinsic functions.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr LLT changeElementSize(unsigned NewEltSize) const
If this type is a vector, return a vector with the same number of elements but the new element size.
This is an important class for using LLVM in a threaded context.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
SyncScope::ID getOrInsertSyncScopeID(StringRef SSN)
getOrInsertSyncScopeID - Maps synchronization scope name to synchronization scope ID.
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
An instruction for reading from memory.
unsigned getPointerAddressSpace() const
Returns the address space of the pointer operand.
void setAtomic(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System)
Sets the ordering constraint and the synchronization scope ID of this load instruction.
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Describe properties that are true of each instruction in the target description file.
bool isCompare() const
Return true if this instruction is a comparison.
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
Wrapper class representing physical registers. Should be passed by value.
Helper class for constructing bundles of MachineInstrs.
MachineBasicBlock::instr_iterator begin() const
Return an iterator to the first bundled instruction.
uint64_t getScalarSizeInBits() const
bool bitsLE(MVT VT) const
Return true if this has no more bits than VT.
unsigned getVectorNumElements() const
bool isVector() const
Return true if this is a vector value type.
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
bool bitsLT(MVT VT) const
Return true if this has less bits than VT.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
static MVT getVectorVT(MVT VT, unsigned NumElements)
static MVT getIntegerVT(unsigned BitWidth)
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
MachineBasicBlock * splitAt(MachineInstr &SplitInst, bool UpdateLiveIns=true, LiveIntervals *LIS=nullptr)
Split a basic block into 2 pieces at SplitPoint.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Align getAlignment() const
Return alignment of the basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool hasCalls() const
Return true if the current function has any function calls.
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
bool hasStackObjects() const
Return true if there are any stack objects in this function.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
DenormalMode getDenormalMode(const fltSemantics &FPType) const
Returns the denormal handling type for the default rounding mode of the function.
void push_back(MachineBasicBlock *MBB)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Representation of each machine instruction.
const MachineOperand & getOperand(unsigned i) const
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
const MachinePointerInfo & getPointerInfo() const
Flags getFlags() const
Return the raw flags of the source value,.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
void setIsUndef(bool Val=true)
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
unsigned getAddressSpace() const
Return the address space for the associated pointer.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
bool onlyWritesMemory() const
Whether this function only (at most) writes memory.
bool doesNotAccessMemory() const
Whether this function accesses no memory.
bool onlyReadsMemory() const
Whether this function only (at most) reads memory.
A Module instance is used to store all the information related to an LLVM module.
void addIncoming(Value *V, BasicBlock *BB)
Add an incoming value to the end of the PHI list.
AnalysisType & getAnalysis() const
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information ...
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
static PoisonValue * get(Type *T)
Static factory methods - Return an 'poison' object of the specified type.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
const DebugLoc & getDebugLoc() const
This class provides iterator support for SDUse operands that use a specific SDNode.
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool hasOneUse() const
Return true if there is exactly one use of this node.
SDNodeFlags getFlags() const
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
const SDValue & getOperand(unsigned Num) const
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
static use_iterator use_end()
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
bool isMachineOpcode() const
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned getMachineOpcode() const
unsigned getOpcode() const
static unsigned getMaxMUBUFImmOffset(const GCNSubtarget &ST)
static unsigned getDSShaderTypeValue(const MachineFunction &MF)
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
bool hasWorkGroupIDZ() const
SIModeRegisterDefaults getMode() const
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const
unsigned getBytesInStackArgArea() const
const AMDGPUGWSResourcePseudoSourceValue * getGWSPSV(const AMDGPUTargetMachine &TM)
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
static LLVM_READONLY const TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)
static bool isVGPRClass(const TargetRegisterClass *RC)
static bool isSGPRClass(const TargetRegisterClass *RC)
static bool isAGPRClass(const TargetRegisterClass *RC)
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const
bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) const override
Allows the target to handle physreg-carried dependency in target-specific way.
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
bool requiresUniformRegister(MachineFunction &MF, const Value *V) const override
Allows target to decide about the register class of the specific value that is live outside the defin...
bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override
Returns true if be combined with to form an ISD::FMAD.
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
void bundleInstWithWaitcnt(MachineInstr &MI) const
Insert MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
MVT getPointerTy(const DataLayout &DL, unsigned AS) const override
Map address space 7 to MVT::v5i32 because that's its in-memory representation.
bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
SDNode * legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
bool allowsMisalignedMemoryAccessesImpl(unsigned Size, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) const
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const
const GCNSubtarget * getSubtarget() const
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
bool shouldEmitGOTReloc(const GlobalValue *GV) const
bool isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const
void CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const override
SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const
SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const
void allocateSpecialInputSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
void allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const
SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const
bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override
void allocateHSAUserSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent) const override
Return the register class that should be used for the specified value type.
void AddMemOpInit(MachineInstr &MI) const
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
bool isLegalGlobalAddressingMode(const AddrMode &AM) const
void computeKnownBitsForFrameIndex(int FrameIdx, KnownBits &Known, const MachineFunction &MF) const override
Determine which of the bits of FrameIndex FIOp are known to be 0.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const
bool isShuffleMaskLegal(ArrayRef< int >, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
LLT getPreferredShiftAmountTy(LLT Ty) const override
Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool isMemOpUniform(const SDNode *N) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
void allocateSpecialInputVGPRsFixed(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments in fixed registers.
LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
MachineBasicBlock * emitGWSMemViolTestLoop(MachineInstr &MI, MachineBasicBlock *BB) const
bool checkAsmConstraintValA(SDValue Op, uint64_t Val, unsigned MaxSize=64) const
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool shouldEmitFixup(const GlobalValue *GV) const
MachineBasicBlock * splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) const
bool hasMemSDNodeUser(SDNode *N) const
bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const override
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const
SDValue LowerCallResult(SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation input to an Opcode operation is free (for instance,...
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
void allocateSpecialInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments at the end of allocated user arguments.
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
static bool isNonGlobalAddrSpace(unsigned AS)
MachineSDNode * buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multiplied by the ...
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
bool mayBeEmittedAsTailCall(const CallInst *) const override
Return true if the target may be able emit the call instruction as a tail call.
void passSpecialInputs(CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl< std::pair< unsigned, SDValue > > &RegsToPass, SmallVectorImpl< SDValue > &MemOpChains, SDValue Chain) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool checkAsmConstraintVal(SDValue Op, StringRef Constraint, uint64_t Val) const
void emitExpandAtomicRMW(AtomicRMWInst *AI) const override
Perform a atomicrmw expansion using a target-specific way.
static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, bool IsDivergentIdx, const GCNSubtarget *Subtarget)
Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be expanded into a set of cmp...
bool shouldUseLDSConstAddress(const GlobalValue *GV) const
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) const override
LLT handling variant.
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const
SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI)
bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
bool shouldEmitPCReloc(const GlobalValue *GV) const
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
void allocateSpecialEntryInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
void allocatePreloadKernArgSGPRs(CCState &CCInfo, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ISD::InputArg > &Ins, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &MF, unsigned IntrinsicID) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const
bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const override
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine the known alignment for the pointer value R.
MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override
Similarly, the in-memory representation of a p7 is {p8, i32}, aka v8i32 when padding is added.
void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT, unsigned Opcode)
Convert Op, which must be of integer type, to the integer type VT, by either any/sign/zero-extending ...
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
bool isKnownNeverSNaN(SDValue Op, unsigned Depth=0) const
SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
Return an AddrSpaceCastSDNode.
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
const Pass * getPass() const
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
Append the extracted elements from Start to Count out of the vector Op in Args.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
bool haveNoCommonBitsSet(SDValue A, SDValue B) const
Return true if A and B have no common bits set.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
std::pair< SDValue, SDValue > SplitVectorOperand(const SDNode *N, unsigned OpNo)
Split the node's operand with EXTRACT_SUBVECTOR and return the low/high part.
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
const TargetLowering & getTargetLoweringInfo() const
std::pair< EVT, EVT > GetSplitDestVTs(const EVT &VT) const
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not neces...
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getBitcastedAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
const DataLayout & getDataLayout() const
SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
Creates a new TokenFactor containing Vals.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
const TargetMachine & getTarget() const
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isKnownNeverNaN(SDValue Op, bool SNaN=false, unsigned Depth=0) const
Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op)
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue getCondCode(ISD::CondCode Cond)
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset)
Create an add instruction with appropriate flags when used for addressing some offset of an object.
LLVMContext * getContext() const
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL, bool LegalTypes=true)
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
int getMaskElt(unsigned Idx) const
ArrayRef< int > getMask() const
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
iterator insert(iterator I, T &&Elt)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
This class is used to represent ISD::STORE nodes.
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
StringRef - Represent a constant reference to a string, i.e.
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
constexpr size_t size() const
size - Get the string size.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Information about stack frame layout on the target.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
StackDirection getStackGrowthDirection() const
getStackGrowthDirection - Return the direction the stack grows
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const TargetMachine & getTargetMachine() const
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
void setHasExtractBitsInsn(bool hasExtractInsn=true)
Tells the code generator that the target has BitExtract instructions.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual void computeKnownBitsForFrameIndex(int FIOp, KnownBits &Known, const MachineFunction &MF) const
Determine which of the bits of FrameIndex FIOp are known to be 0.
SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const
std::vector< AsmOperandInfo > AsmOperandInfoVector
SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) const
More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contri...
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
std::pair< SDValue, SDValue > expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is 'desirable' to us...
std::pair< SDValue, SDValue > scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Turn load of vector type into a load of the individual elements.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
Look at Op.
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo,...
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const
Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
Primary interface to the complete machine description for the target machine.
const Triple & getTargetTriple() const
bool shouldAssumeDSOLocal(const GlobalValue *GV) const
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
unsigned getID() const
Return the register class ID number.
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
iterator begin() const
begin/end - Return all of the registers in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
OSType getOS() const
Get the parsed operating system type of this triple.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
const fltSemantics & getFltSemantics() const
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
bool isSized(SmallPtrSetImpl< Type * > *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
bool isFunctionTy() const
True if this is an instance of FunctionType.
static IntegerType * getInt32Ty(LLVMContext &C)
bool isIntegerTy() const
True if this is an instance of IntegerType.
bool isVoidTy() const
Return true if this is 'void'.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
A Use represents the edge between a Value definition and its users.
Value * getOperand(unsigned i) const
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
bool hasOneUse() const
Return true if there is exactly one use of this value.
void replaceAllUsesWith(Value *V)
Change all uses of this to point to a new Value.
LLVMContext & getContext() const
All values hold a context through their type.
iterator_range< use_iterator > uses()
void takeName(Value *V)
Transfer the name from V to this value.
constexpr bool isZero() const
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
@ BUFFER_STRIDED_POINTER
Address space for 192-bit fat buffer pointers with an additional index.
@ REGION_ADDRESS
Address space for region memory. (GDS)
@ LOCAL_ADDRESS
Address space for local memory.
@ STREAMOUT_REGISTER
Internal address spaces. Can be freely renumbered.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
@ FLAT_ADDRESS
Address space for flat memory.
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
@ BUFFER_FAT_POINTER
Address space for 160-bit buffer fat pointers.
@ PRIVATE_ADDRESS
Address space for private memory.
@ BUFFER_RESOURCE
Address space for 128-bit buffer resources.
@ BUFFER_ATOMIC_COND_SUB_U32
@ TBUFFER_LOAD_FORMAT_D16
@ BUFFER_ATOMIC_FADD_BF16
@ TBUFFER_STORE_FORMAT_D16
@ BUFFER_STORE_FORMAT_D16
@ CLAMP
CLAMP value between 0.0 and 1.0.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi)
LLVM_READONLY const MIMGG16MappingInfo * getMIMGG16MappingInfo(unsigned G)
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isFlatGlobalAddrSpace(unsigned AS)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool isGFX12Plus(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
LLVM_READNONE bool isKernel(CallingConv::ID CC)
bool isGFX11(const MCSubtargetInfo &STI)
bool isCompute(CallingConv::ID cc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
bool isChainCC(CallingConv::ID CC)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
bool getMUBUFTfe(unsigned Opc)
bool isGFX11Plus(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV2F16(uint32_t Literal)
bool isShader(CallingConv::ID cc)
bool isGFX10Plus(const MCSubtargetInfo &STI)
LLVM_READONLY int getVOPe64(uint16_t Opcode)
std::optional< unsigned > getInlineEncodingV2I16(uint32_t Literal)
bool isExtendedGlobalAddrSpace(unsigned AS)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfo(unsigned DimEnum)
std::optional< unsigned > getInlineEncodingV2BF16(uint32_t Literal)
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
const ImageDimIntrinsicInfo * getImageDimIntrinsicInfo(unsigned Intr)
bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
const RsrcIntrinsic * lookupRsrcIntrinsic(unsigned Intr)
bool isGraphics(CallingConv::ID cc)
const uint64_t FltRoundConversionTable
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
@ MaxID
The highest possible ID. Must be some 2^k - 1.
@ AMDGPU_Gfx
Used for AMD graphics targets.
@ AMDGPU_CS_ChainPreserve
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_CS_Chain
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ SET_FPENV
Sets the current floating-point environment.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ BSWAP
Byte Swap and Counting operators.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ FADD
Simple binary floating point operators.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SIGN_EXTEND
Conversion operators.
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ READSTEADYCOUNTER
READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
@ BR
Control flow instructions. These all have token chains.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ UNDEF
UNDEF - An undefined node.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ GET_ROUNDING
Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest, ties to even 2 Round to ...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ GET_FPMODE
Reads the current dynamic floating-point control modes.
@ GET_FPENV
Gets the current floating-point environment.
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ SMULO
Same for multiplication.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
@ BF16_TO_FP
BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions and truncation for bfloat16.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
@ INLINEASM
INLINEASM - Represents an inline asm block.
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ BRCOND
BRCOND - Conditional branch.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
StringRef getName(ID id)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
GFCstOrSplatGFCstMatch m_GFCstOrSplat(std::optional< FPValueAndVReg > &FPValReg)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
@ System
Synchronized with respect to all concurrently executing threads.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred)
getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition ...
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
int64_t maxIntN(int64_t N)
Gets the maximum value for a N-bit signed integer.
int popcount(T Value) noexcept
Count the number of set bits in a value.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
SDValue peekThroughBitcasts(SDValue V)
Return the non-bitcasted source operand of V if it exists.
testing::Matcher< const detail::ErrorHolder & > Failed()
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
ConstantFPSDNode * isConstOrConstSplatFP(SDValue N, bool AllowUndefs=false)
Returns the SDNode if it is a constant splat BuildVector or constant float.
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
bool isReleaseOrStronger(AtomicOrdering AO)
static const MachineMemOperand::Flags MONoClobber
Mark the MMO of a uniform load if there are no potentially clobbering stores on any path from the sta...
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
int countl_zero(T Val)
Count number of 0's from the most significant bit to the least stopping at the first 1.
bool isBoolSGPR(SDValue V)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred)
getFCmpCondCode - Return the ISD condition code corresponding to the given LLVM IR floating-point con...
constexpr uint32_t Lo_32(uint64_t Value)
Return the low 32 bits of a 64 bit value.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
unsigned getUndefRegState(bool B)
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
@ Or
Bitwise or logical OR of integers.
@ Mul
Product of integers.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
DWARFExpression::Operation Op
@ TowardPositive
roundTowardPositive.
@ TowardNegative
roundTowardNegative.
unsigned M0(unsigned Val)
int64_t minIntN(int64_t N)
Gets the minimum value for a N-bit signed integer.
ConstantSDNode * isConstOrConstSplat(SDValue N, bool AllowUndefs=false, bool AllowTruncation=false)
Returns the SDNode if it is a constant splat BuildVector or constant int.
constexpr unsigned BitWidth
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
static const MachineMemOperand::Flags MOLastUse
Mark the MMO of a load as the last use.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
ArgDescriptor WorkItemIDZ
ArgDescriptor WorkItemIDY
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(PreloadedValue Value) const
ArgDescriptor WorkItemIDX
static constexpr uint64_t encode(Fields... Values)
static std::tuple< typename Fields::ValueType... > decode(uint64_t Encoded)
static const fltSemantics & IEEEsingle() LLVM_READNONE
static constexpr roundingMode rmNearestTiesToEven
static const fltSemantics & IEEEhalf() LLVM_READNONE
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
static ArgDescriptor createStack(unsigned Offset, unsigned Mask=~0u)
MCRegister getRegister() const
static ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask)
static ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Helper struct shared between Function Specialization and SCCP Solver.
Represent subnormal handling kind for floating point instruction inputs and outputs.
@ Dynamic
Denormals have unknown treatment.
static constexpr DenormalMode getPreserveSign()
static constexpr DenormalMode getIEEE()
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
EVT changeTypeToInteger() const
Return the type converted to an equivalently sized integer or vector with integer element type.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isByteSized() const
Return true if the bit size is a multiple of 8.
uint64_t getScalarSizeInBits() const
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
TypeSize getStoreSizeInBits() const
Return the number of bits overwritten by a store of the specified value type.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool bitsEq(EVT VT) const
Return true if this has the same number of bits as VT.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isInteger() const
Return true if this is an integer or a vector integer type.
unsigned getPointerAddrSpace() const
unsigned getByValSize() const
bool isUnknown() const
Returns true if we don't know any bits.
void resetAll()
Resets the known state of all bits.
unsigned countMaxActiveBits() const
Returns the maximum number of bits needed to represent all possible unsigned values with these known ...
unsigned countMinLeadingZeros() const
Returns the minimum number of leading zero bits.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
int64_t Offset
Offset - This is an offset from the base Value*.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
These are IR-level optimization flags that may be propagated to SDNodes.
bool hasNoUnsignedWrap() const
bool hasAllowContract() const
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...
This structure contains all information that is necessary for lowering calls.
SDValue ConvergenceControlToken
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
bool isBeforeLegalize() const