LLVM API Documentation
00001 //===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the Sparc implementation of the TargetInstrInfo class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #ifndef SPARCINSTRUCTIONINFO_H 00015 #define SPARCINSTRUCTIONINFO_H 00016 00017 #include "SparcRegisterInfo.h" 00018 #include "llvm/Target/TargetInstrInfo.h" 00019 00020 #define GET_INSTRINFO_HEADER 00021 #include "SparcGenInstrInfo.inc" 00022 00023 namespace llvm { 00024 00025 /// SPII - This namespace holds all of the target specific flags that 00026 /// instruction info tracks. 00027 /// 00028 namespace SPII { 00029 enum { 00030 Pseudo = (1<<0), 00031 Load = (1<<1), 00032 Store = (1<<2), 00033 DelaySlot = (1<<3) 00034 }; 00035 } 00036 00037 class SparcInstrInfo : public SparcGenInstrInfo { 00038 const SparcRegisterInfo RI; 00039 const SparcSubtarget& Subtarget; 00040 public: 00041 explicit SparcInstrInfo(SparcSubtarget &ST); 00042 00043 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 00044 /// such, whenever a client has an instance of instruction info, it should 00045 /// always be able to get register info as well (through this method). 00046 /// 00047 virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; } 00048 00049 /// isLoadFromStackSlot - If the specified machine instruction is a direct 00050 /// load from a stack slot, return the virtual or physical register number of 00051 /// the destination along with the FrameIndex of the loaded stack slot. If 00052 /// not, return 0. This predicate must return 0 if the instruction has 00053 /// any side effects other than loading from the stack slot. 00054 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 00055 int &FrameIndex) const; 00056 00057 /// isStoreToStackSlot - If the specified machine instruction is a direct 00058 /// store to a stack slot, return the virtual or physical register number of 00059 /// the source reg along with the FrameIndex of the loaded stack slot. If 00060 /// not, return 0. This predicate must return 0 if the instruction has 00061 /// any side effects other than storing to the stack slot. 00062 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 00063 int &FrameIndex) const; 00064 00065 /// emitFrameIndexDebugValue - Emit a target-dependent form of 00066 /// DBG_VALUE encoding the address of a frame index. 00067 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 00068 int FrameIx, 00069 uint64_t Offset, 00070 const MDNode *MDPtr, 00071 DebugLoc dl) const; 00072 00073 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 00074 MachineBasicBlock *&FBB, 00075 SmallVectorImpl<MachineOperand> &Cond, 00076 bool AllowModify = false) const ; 00077 00078 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 00079 00080 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 00081 MachineBasicBlock *FBB, 00082 const SmallVectorImpl<MachineOperand> &Cond, 00083 DebugLoc DL) const; 00084 00085 virtual void copyPhysReg(MachineBasicBlock &MBB, 00086 MachineBasicBlock::iterator I, DebugLoc DL, 00087 unsigned DestReg, unsigned SrcReg, 00088 bool KillSrc) const; 00089 00090 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 00091 MachineBasicBlock::iterator MBBI, 00092 unsigned SrcReg, bool isKill, int FrameIndex, 00093 const TargetRegisterClass *RC, 00094 const TargetRegisterInfo *TRI) const; 00095 00096 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 00097 MachineBasicBlock::iterator MBBI, 00098 unsigned DestReg, int FrameIndex, 00099 const TargetRegisterClass *RC, 00100 const TargetRegisterInfo *TRI) const; 00101 00102 unsigned getGlobalBaseReg(MachineFunction *MF) const; 00103 }; 00104 00105 } 00106 00107 #endif