LLVM API Documentation

NVPTXISelLowering.cpp
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00001 //
00002 //                     The LLVM Compiler Infrastructure
00003 //
00004 // This file is distributed under the University of Illinois Open Source
00005 // License. See LICENSE.TXT for details.
00006 //
00007 //===----------------------------------------------------------------------===//
00008 //
00009 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
00010 // selection DAG.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "NVPTXISelLowering.h"
00015 #include "NVPTX.h"
00016 #include "NVPTXTargetMachine.h"
00017 #include "NVPTXTargetObjectFile.h"
00018 #include "NVPTXUtilities.h"
00019 #include "llvm/CodeGen/Analysis.h"
00020 #include "llvm/CodeGen/MachineFrameInfo.h"
00021 #include "llvm/CodeGen/MachineFunction.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineRegisterInfo.h"
00024 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
00025 #include "llvm/IR/CallSite.h"
00026 #include "llvm/IR/DerivedTypes.h"
00027 #include "llvm/IR/Function.h"
00028 #include "llvm/IR/GlobalValue.h"
00029 #include "llvm/IR/IntrinsicInst.h"
00030 #include "llvm/IR/Intrinsics.h"
00031 #include "llvm/IR/Module.h"
00032 #include "llvm/MC/MCSectionELF.h"
00033 #include "llvm/Support/CommandLine.h"
00034 #include "llvm/Support/Debug.h"
00035 #include "llvm/Support/ErrorHandling.h"
00036 #include "llvm/Support/MathExtras.h"
00037 #include "llvm/Support/raw_ostream.h"
00038 #include <sstream>
00039 
00040 #undef DEBUG_TYPE
00041 #define DEBUG_TYPE "nvptx-lower"
00042 
00043 using namespace llvm;
00044 
00045 static unsigned int uniqueCallSite = 0;
00046 
00047 static cl::opt<bool> sched4reg(
00048     "nvptx-sched4reg",
00049     cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
00050 
00051 static cl::opt<unsigned>
00052 FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
00053                     cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
00054                              " 1: do it  2: do it aggressively"),
00055                     cl::init(2));
00056 
00057 static bool IsPTXVectorType(MVT VT) {
00058   switch (VT.SimpleTy) {
00059   default:
00060     return false;
00061   case MVT::v2i1:
00062   case MVT::v4i1:
00063   case MVT::v2i8:
00064   case MVT::v4i8:
00065   case MVT::v2i16:
00066   case MVT::v4i16:
00067   case MVT::v2i32:
00068   case MVT::v4i32:
00069   case MVT::v2i64:
00070   case MVT::v2f32:
00071   case MVT::v4f32:
00072   case MVT::v2f64:
00073     return true;
00074   }
00075 }
00076 
00077 /// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
00078 /// EVTs that compose it.  Unlike ComputeValueVTs, this will break apart vectors
00079 /// into their primitive components.
00080 /// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
00081 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
00082 /// LowerCall, and LowerReturn.
00083 static void ComputePTXValueVTs(const TargetLowering &TLI, Type *Ty,
00084                                SmallVectorImpl<EVT> &ValueVTs,
00085                                SmallVectorImpl<uint64_t> *Offsets = nullptr,
00086                                uint64_t StartingOffset = 0) {
00087   SmallVector<EVT, 16> TempVTs;
00088   SmallVector<uint64_t, 16> TempOffsets;
00089 
00090   ComputeValueVTs(TLI, Ty, TempVTs, &TempOffsets, StartingOffset);
00091   for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
00092     EVT VT = TempVTs[i];
00093     uint64_t Off = TempOffsets[i];
00094     if (VT.isVector())
00095       for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
00096         ValueVTs.push_back(VT.getVectorElementType());
00097         if (Offsets)
00098           Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
00099       }
00100     else {
00101       ValueVTs.push_back(VT);
00102       if (Offsets)
00103         Offsets->push_back(Off);
00104     }
00105   }
00106 }
00107 
00108 // NVPTXTargetLowering Constructor.
00109 NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
00110                                          const NVPTXSubtarget &STI)
00111     : TargetLowering(TM), nvTM(&TM), STI(STI) {
00112 
00113   // always lower memset, memcpy, and memmove intrinsics to load/store
00114   // instructions, rather
00115   // then generating calls to memset, mempcy or memmove.
00116   MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
00117   MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
00118   MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
00119 
00120   setBooleanContents(ZeroOrNegativeOneBooleanContent);
00121   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
00122 
00123   // Jump is Expensive. Don't create extra control flow for 'and', 'or'
00124   // condition branches.
00125   setJumpIsExpensive(true);
00126 
00127   // By default, use the Source scheduling
00128   if (sched4reg)
00129     setSchedulingPreference(Sched::RegPressure);
00130   else
00131     setSchedulingPreference(Sched::Source);
00132 
00133   addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
00134   addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
00135   addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
00136   addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
00137   addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
00138   addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
00139 
00140   // Operations not directly supported by NVPTX.
00141   setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
00142   setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
00143   setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
00144   setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
00145   setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
00146   setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
00147   setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
00148   setOperationAction(ISD::BR_CC, MVT::f32, Expand);
00149   setOperationAction(ISD::BR_CC, MVT::f64, Expand);
00150   setOperationAction(ISD::BR_CC, MVT::i1, Expand);
00151   setOperationAction(ISD::BR_CC, MVT::i8, Expand);
00152   setOperationAction(ISD::BR_CC, MVT::i16, Expand);
00153   setOperationAction(ISD::BR_CC, MVT::i32, Expand);
00154   setOperationAction(ISD::BR_CC, MVT::i64, Expand);
00155   // Some SIGN_EXTEND_INREG can be done using cvt instruction.
00156   // For others we will expand to a SHL/SRA pair.
00157   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
00158   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
00159   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
00160   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
00161   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
00162 
00163   setOperationAction(ISD::SHL_PARTS, MVT::i32  , Custom);
00164   setOperationAction(ISD::SRA_PARTS, MVT::i32  , Custom);
00165   setOperationAction(ISD::SRL_PARTS, MVT::i32  , Custom);
00166   setOperationAction(ISD::SHL_PARTS, MVT::i64  , Custom);
00167   setOperationAction(ISD::SRA_PARTS, MVT::i64  , Custom);
00168   setOperationAction(ISD::SRL_PARTS, MVT::i64  , Custom);
00169 
00170   if (STI.hasROT64()) {
00171     setOperationAction(ISD::ROTL, MVT::i64, Legal);
00172     setOperationAction(ISD::ROTR, MVT::i64, Legal);
00173   } else {
00174     setOperationAction(ISD::ROTL, MVT::i64, Expand);
00175     setOperationAction(ISD::ROTR, MVT::i64, Expand);
00176   }
00177   if (STI.hasROT32()) {
00178     setOperationAction(ISD::ROTL, MVT::i32, Legal);
00179     setOperationAction(ISD::ROTR, MVT::i32, Legal);
00180   } else {
00181     setOperationAction(ISD::ROTL, MVT::i32, Expand);
00182     setOperationAction(ISD::ROTR, MVT::i32, Expand);
00183   }
00184 
00185   setOperationAction(ISD::ROTL, MVT::i16, Expand);
00186   setOperationAction(ISD::ROTR, MVT::i16, Expand);
00187   setOperationAction(ISD::ROTL, MVT::i8, Expand);
00188   setOperationAction(ISD::ROTR, MVT::i8, Expand);
00189   setOperationAction(ISD::BSWAP, MVT::i16, Expand);
00190   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
00191   setOperationAction(ISD::BSWAP, MVT::i64, Expand);
00192 
00193   // Indirect branch is not supported.
00194   // This also disables Jump Table creation.
00195   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
00196   setOperationAction(ISD::BRIND, MVT::Other, Expand);
00197 
00198   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
00199   setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
00200 
00201   // We want to legalize constant related memmove and memcopy
00202   // intrinsics.
00203   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
00204 
00205   // Turn FP extload into load/fextend
00206   setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
00207   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
00208   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
00209   // Turn FP truncstore into trunc + store.
00210   setTruncStoreAction(MVT::f32, MVT::f16, Expand);
00211   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
00212   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
00213 
00214   // PTX does not support load / store predicate registers
00215   setOperationAction(ISD::LOAD, MVT::i1, Custom);
00216   setOperationAction(ISD::STORE, MVT::i1, Custom);
00217 
00218   for (MVT VT : MVT::integer_valuetypes()) {
00219     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
00220     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
00221     setTruncStoreAction(VT, MVT::i1, Expand);
00222   }
00223 
00224   // This is legal in NVPTX
00225   setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
00226   setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
00227 
00228   // TRAP can be lowered to PTX trap
00229   setOperationAction(ISD::TRAP, MVT::Other, Legal);
00230 
00231   setOperationAction(ISD::ADDC, MVT::i64, Expand);
00232   setOperationAction(ISD::ADDE, MVT::i64, Expand);
00233 
00234   // Register custom handling for vector loads/stores
00235   for (MVT VT : MVT::vector_valuetypes()) {
00236     if (IsPTXVectorType(VT)) {
00237       setOperationAction(ISD::LOAD, VT, Custom);
00238       setOperationAction(ISD::STORE, VT, Custom);
00239       setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
00240     }
00241   }
00242 
00243   // Custom handling for i8 intrinsics
00244   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
00245 
00246   setOperationAction(ISD::CTLZ, MVT::i16, Legal);
00247   setOperationAction(ISD::CTLZ, MVT::i32, Legal);
00248   setOperationAction(ISD::CTLZ, MVT::i64, Legal);
00249   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
00250   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
00251   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
00252   setOperationAction(ISD::CTTZ, MVT::i16, Expand);
00253   setOperationAction(ISD::CTTZ, MVT::i32, Expand);
00254   setOperationAction(ISD::CTTZ, MVT::i64, Expand);
00255   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
00256   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
00257   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
00258   setOperationAction(ISD::CTPOP, MVT::i16, Legal);
00259   setOperationAction(ISD::CTPOP, MVT::i32, Legal);
00260   setOperationAction(ISD::CTPOP, MVT::i64, Legal);
00261 
00262   // PTX does not directly support SELP of i1, so promote to i32 first
00263   setOperationAction(ISD::SELECT, MVT::i1, Custom);
00264 
00265   // We have some custom DAG combine patterns for these nodes
00266   setTargetDAGCombine(ISD::ADD);
00267   setTargetDAGCombine(ISD::AND);
00268   setTargetDAGCombine(ISD::FADD);
00269   setTargetDAGCombine(ISD::MUL);
00270   setTargetDAGCombine(ISD::SHL);
00271 
00272   // Now deduce the information based on the above mentioned
00273   // actions
00274   computeRegisterProperties();
00275 }
00276 
00277 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
00278   switch (Opcode) {
00279   default:
00280     return nullptr;
00281   case NVPTXISD::CALL:
00282     return "NVPTXISD::CALL";
00283   case NVPTXISD::RET_FLAG:
00284     return "NVPTXISD::RET_FLAG";
00285   case NVPTXISD::Wrapper:
00286     return "NVPTXISD::Wrapper";
00287   case NVPTXISD::DeclareParam:
00288     return "NVPTXISD::DeclareParam";
00289   case NVPTXISD::DeclareScalarParam:
00290     return "NVPTXISD::DeclareScalarParam";
00291   case NVPTXISD::DeclareRet:
00292     return "NVPTXISD::DeclareRet";
00293   case NVPTXISD::DeclareRetParam:
00294     return "NVPTXISD::DeclareRetParam";
00295   case NVPTXISD::PrintCall:
00296     return "NVPTXISD::PrintCall";
00297   case NVPTXISD::LoadParam:
00298     return "NVPTXISD::LoadParam";
00299   case NVPTXISD::LoadParamV2:
00300     return "NVPTXISD::LoadParamV2";
00301   case NVPTXISD::LoadParamV4:
00302     return "NVPTXISD::LoadParamV4";
00303   case NVPTXISD::StoreParam:
00304     return "NVPTXISD::StoreParam";
00305   case NVPTXISD::StoreParamV2:
00306     return "NVPTXISD::StoreParamV2";
00307   case NVPTXISD::StoreParamV4:
00308     return "NVPTXISD::StoreParamV4";
00309   case NVPTXISD::StoreParamS32:
00310     return "NVPTXISD::StoreParamS32";
00311   case NVPTXISD::StoreParamU32:
00312     return "NVPTXISD::StoreParamU32";
00313   case NVPTXISD::CallArgBegin:
00314     return "NVPTXISD::CallArgBegin";
00315   case NVPTXISD::CallArg:
00316     return "NVPTXISD::CallArg";
00317   case NVPTXISD::LastCallArg:
00318     return "NVPTXISD::LastCallArg";
00319   case NVPTXISD::CallArgEnd:
00320     return "NVPTXISD::CallArgEnd";
00321   case NVPTXISD::CallVoid:
00322     return "NVPTXISD::CallVoid";
00323   case NVPTXISD::CallVal:
00324     return "NVPTXISD::CallVal";
00325   case NVPTXISD::CallSymbol:
00326     return "NVPTXISD::CallSymbol";
00327   case NVPTXISD::Prototype:
00328     return "NVPTXISD::Prototype";
00329   case NVPTXISD::MoveParam:
00330     return "NVPTXISD::MoveParam";
00331   case NVPTXISD::StoreRetval:
00332     return "NVPTXISD::StoreRetval";
00333   case NVPTXISD::StoreRetvalV2:
00334     return "NVPTXISD::StoreRetvalV2";
00335   case NVPTXISD::StoreRetvalV4:
00336     return "NVPTXISD::StoreRetvalV4";
00337   case NVPTXISD::PseudoUseParam:
00338     return "NVPTXISD::PseudoUseParam";
00339   case NVPTXISD::RETURN:
00340     return "NVPTXISD::RETURN";
00341   case NVPTXISD::CallSeqBegin:
00342     return "NVPTXISD::CallSeqBegin";
00343   case NVPTXISD::CallSeqEnd:
00344     return "NVPTXISD::CallSeqEnd";
00345   case NVPTXISD::CallPrototype:
00346     return "NVPTXISD::CallPrototype";
00347   case NVPTXISD::LoadV2:
00348     return "NVPTXISD::LoadV2";
00349   case NVPTXISD::LoadV4:
00350     return "NVPTXISD::LoadV4";
00351   case NVPTXISD::LDGV2:
00352     return "NVPTXISD::LDGV2";
00353   case NVPTXISD::LDGV4:
00354     return "NVPTXISD::LDGV4";
00355   case NVPTXISD::LDUV2:
00356     return "NVPTXISD::LDUV2";
00357   case NVPTXISD::LDUV4:
00358     return "NVPTXISD::LDUV4";
00359   case NVPTXISD::StoreV2:
00360     return "NVPTXISD::StoreV2";
00361   case NVPTXISD::StoreV4:
00362     return "NVPTXISD::StoreV4";
00363   case NVPTXISD::FUN_SHFL_CLAMP:
00364     return "NVPTXISD::FUN_SHFL_CLAMP";
00365   case NVPTXISD::FUN_SHFR_CLAMP:
00366     return "NVPTXISD::FUN_SHFR_CLAMP";
00367   case NVPTXISD::IMAD:
00368     return "NVPTXISD::IMAD";
00369   case NVPTXISD::MUL_WIDE_SIGNED:
00370     return "NVPTXISD::MUL_WIDE_SIGNED";
00371   case NVPTXISD::MUL_WIDE_UNSIGNED:
00372     return "NVPTXISD::MUL_WIDE_UNSIGNED";
00373   case NVPTXISD::Tex1DFloatS32:        return "NVPTXISD::Tex1DFloatS32";
00374   case NVPTXISD::Tex1DFloatFloat:      return "NVPTXISD::Tex1DFloatFloat";
00375   case NVPTXISD::Tex1DFloatFloatLevel:
00376     return "NVPTXISD::Tex1DFloatFloatLevel";
00377   case NVPTXISD::Tex1DFloatFloatGrad:
00378     return "NVPTXISD::Tex1DFloatFloatGrad";
00379   case NVPTXISD::Tex1DS32S32:          return "NVPTXISD::Tex1DS32S32";
00380   case NVPTXISD::Tex1DS32Float:        return "NVPTXISD::Tex1DS32Float";
00381   case NVPTXISD::Tex1DS32FloatLevel:
00382     return "NVPTXISD::Tex1DS32FloatLevel";
00383   case NVPTXISD::Tex1DS32FloatGrad:
00384     return "NVPTXISD::Tex1DS32FloatGrad";
00385   case NVPTXISD::Tex1DU32S32:          return "NVPTXISD::Tex1DU32S32";
00386   case NVPTXISD::Tex1DU32Float:        return "NVPTXISD::Tex1DU32Float";
00387   case NVPTXISD::Tex1DU32FloatLevel:
00388     return "NVPTXISD::Tex1DU32FloatLevel";
00389   case NVPTXISD::Tex1DU32FloatGrad:
00390     return "NVPTXISD::Tex1DU32FloatGrad";
00391   case NVPTXISD::Tex1DArrayFloatS32:   return "NVPTXISD::Tex1DArrayFloatS32";
00392   case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
00393   case NVPTXISD::Tex1DArrayFloatFloatLevel:
00394     return "NVPTXISD::Tex1DArrayFloatFloatLevel";
00395   case NVPTXISD::Tex1DArrayFloatFloatGrad:
00396     return "NVPTXISD::Tex1DArrayFloatFloatGrad";
00397   case NVPTXISD::Tex1DArrayS32S32:     return "NVPTXISD::Tex1DArrayS32S32";
00398   case NVPTXISD::Tex1DArrayS32Float:   return "NVPTXISD::Tex1DArrayS32Float";
00399   case NVPTXISD::Tex1DArrayS32FloatLevel:
00400     return "NVPTXISD::Tex1DArrayS32FloatLevel";
00401   case NVPTXISD::Tex1DArrayS32FloatGrad:
00402     return "NVPTXISD::Tex1DArrayS32FloatGrad";
00403   case NVPTXISD::Tex1DArrayU32S32:     return "NVPTXISD::Tex1DArrayU32S32";
00404   case NVPTXISD::Tex1DArrayU32Float:   return "NVPTXISD::Tex1DArrayU32Float";
00405   case NVPTXISD::Tex1DArrayU32FloatLevel:
00406     return "NVPTXISD::Tex1DArrayU32FloatLevel";
00407   case NVPTXISD::Tex1DArrayU32FloatGrad:
00408     return "NVPTXISD::Tex1DArrayU32FloatGrad";
00409   case NVPTXISD::Tex2DFloatS32:        return "NVPTXISD::Tex2DFloatS32";
00410   case NVPTXISD::Tex2DFloatFloat:      return "NVPTXISD::Tex2DFloatFloat";
00411   case NVPTXISD::Tex2DFloatFloatLevel:
00412     return "NVPTXISD::Tex2DFloatFloatLevel";
00413   case NVPTXISD::Tex2DFloatFloatGrad:
00414     return "NVPTXISD::Tex2DFloatFloatGrad";
00415   case NVPTXISD::Tex2DS32S32:          return "NVPTXISD::Tex2DS32S32";
00416   case NVPTXISD::Tex2DS32Float:        return "NVPTXISD::Tex2DS32Float";
00417   case NVPTXISD::Tex2DS32FloatLevel:
00418     return "NVPTXISD::Tex2DS32FloatLevel";
00419   case NVPTXISD::Tex2DS32FloatGrad:
00420     return "NVPTXISD::Tex2DS32FloatGrad";
00421   case NVPTXISD::Tex2DU32S32:          return "NVPTXISD::Tex2DU32S32";
00422   case NVPTXISD::Tex2DU32Float:        return "NVPTXISD::Tex2DU32Float";
00423   case NVPTXISD::Tex2DU32FloatLevel:
00424     return "NVPTXISD::Tex2DU32FloatLevel";
00425   case NVPTXISD::Tex2DU32FloatGrad:
00426     return "NVPTXISD::Tex2DU32FloatGrad";
00427   case NVPTXISD::Tex2DArrayFloatS32:   return "NVPTXISD::Tex2DArrayFloatS32";
00428   case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
00429   case NVPTXISD::Tex2DArrayFloatFloatLevel:
00430     return "NVPTXISD::Tex2DArrayFloatFloatLevel";
00431   case NVPTXISD::Tex2DArrayFloatFloatGrad:
00432     return "NVPTXISD::Tex2DArrayFloatFloatGrad";
00433   case NVPTXISD::Tex2DArrayS32S32:     return "NVPTXISD::Tex2DArrayS32S32";
00434   case NVPTXISD::Tex2DArrayS32Float:   return "NVPTXISD::Tex2DArrayS32Float";
00435   case NVPTXISD::Tex2DArrayS32FloatLevel:
00436     return "NVPTXISD::Tex2DArrayS32FloatLevel";
00437   case NVPTXISD::Tex2DArrayS32FloatGrad:
00438     return "NVPTXISD::Tex2DArrayS32FloatGrad";
00439   case NVPTXISD::Tex2DArrayU32S32:     return "NVPTXISD::Tex2DArrayU32S32";
00440   case NVPTXISD::Tex2DArrayU32Float:   return "NVPTXISD::Tex2DArrayU32Float";
00441   case NVPTXISD::Tex2DArrayU32FloatLevel:
00442     return "NVPTXISD::Tex2DArrayU32FloatLevel";
00443   case NVPTXISD::Tex2DArrayU32FloatGrad:
00444     return "NVPTXISD::Tex2DArrayU32FloatGrad";
00445   case NVPTXISD::Tex3DFloatS32:        return "NVPTXISD::Tex3DFloatS32";
00446   case NVPTXISD::Tex3DFloatFloat:      return "NVPTXISD::Tex3DFloatFloat";
00447   case NVPTXISD::Tex3DFloatFloatLevel:
00448     return "NVPTXISD::Tex3DFloatFloatLevel";
00449   case NVPTXISD::Tex3DFloatFloatGrad:
00450     return "NVPTXISD::Tex3DFloatFloatGrad";
00451   case NVPTXISD::Tex3DS32S32:          return "NVPTXISD::Tex3DS32S32";
00452   case NVPTXISD::Tex3DS32Float:        return "NVPTXISD::Tex3DS32Float";
00453   case NVPTXISD::Tex3DS32FloatLevel:
00454     return "NVPTXISD::Tex3DS32FloatLevel";
00455   case NVPTXISD::Tex3DS32FloatGrad:
00456     return "NVPTXISD::Tex3DS32FloatGrad";
00457   case NVPTXISD::Tex3DU32S32:          return "NVPTXISD::Tex3DU32S32";
00458   case NVPTXISD::Tex3DU32Float:        return "NVPTXISD::Tex3DU32Float";
00459   case NVPTXISD::Tex3DU32FloatLevel:
00460     return "NVPTXISD::Tex3DU32FloatLevel";
00461   case NVPTXISD::Tex3DU32FloatGrad:
00462     return "NVPTXISD::Tex3DU32FloatGrad";
00463   case NVPTXISD::TexCubeFloatFloat:      return "NVPTXISD::TexCubeFloatFloat";
00464   case NVPTXISD::TexCubeFloatFloatLevel:
00465     return "NVPTXISD::TexCubeFloatFloatLevel";
00466   case NVPTXISD::TexCubeS32Float:        return "NVPTXISD::TexCubeS32Float";
00467   case NVPTXISD::TexCubeS32FloatLevel:
00468     return "NVPTXISD::TexCubeS32FloatLevel";
00469   case NVPTXISD::TexCubeU32Float:        return "NVPTXISD::TexCubeU32Float";
00470   case NVPTXISD::TexCubeU32FloatLevel:
00471     return "NVPTXISD::TexCubeU32FloatLevel";
00472   case NVPTXISD::TexCubeArrayFloatFloat:
00473     return "NVPTXISD::TexCubeArrayFloatFloat";
00474   case NVPTXISD::TexCubeArrayFloatFloatLevel:
00475     return "NVPTXISD::TexCubeArrayFloatFloatLevel";
00476   case NVPTXISD::TexCubeArrayS32Float:
00477     return "NVPTXISD::TexCubeArrayS32Float";
00478   case NVPTXISD::TexCubeArrayS32FloatLevel:
00479     return "NVPTXISD::TexCubeArrayS32FloatLevel";
00480   case NVPTXISD::TexCubeArrayU32Float:
00481     return "NVPTXISD::TexCubeArrayU32Float";
00482   case NVPTXISD::TexCubeArrayU32FloatLevel:
00483     return "NVPTXISD::TexCubeArrayU32FloatLevel";
00484   case NVPTXISD::Tld4R2DFloatFloat:
00485     return "NVPTXISD::Tld4R2DFloatFloat";
00486   case NVPTXISD::Tld4G2DFloatFloat:
00487     return "NVPTXISD::Tld4G2DFloatFloat";
00488   case NVPTXISD::Tld4B2DFloatFloat:
00489     return "NVPTXISD::Tld4B2DFloatFloat";
00490   case NVPTXISD::Tld4A2DFloatFloat:
00491     return "NVPTXISD::Tld4A2DFloatFloat";
00492   case NVPTXISD::Tld4R2DS64Float:
00493     return "NVPTXISD::Tld4R2DS64Float";
00494   case NVPTXISD::Tld4G2DS64Float:
00495     return "NVPTXISD::Tld4G2DS64Float";
00496   case NVPTXISD::Tld4B2DS64Float:
00497     return "NVPTXISD::Tld4B2DS64Float";
00498   case NVPTXISD::Tld4A2DS64Float:
00499     return "NVPTXISD::Tld4A2DS64Float";
00500   case NVPTXISD::Tld4R2DU64Float:
00501     return "NVPTXISD::Tld4R2DU64Float";
00502   case NVPTXISD::Tld4G2DU64Float:
00503     return "NVPTXISD::Tld4G2DU64Float";
00504   case NVPTXISD::Tld4B2DU64Float:
00505     return "NVPTXISD::Tld4B2DU64Float";
00506   case NVPTXISD::Tld4A2DU64Float:
00507     return "NVPTXISD::Tld4A2DU64Float";
00508 
00509   case NVPTXISD::TexUnified1DFloatS32:
00510     return "NVPTXISD::TexUnified1DFloatS32";
00511   case NVPTXISD::TexUnified1DFloatFloat:
00512     return "NVPTXISD::TexUnified1DFloatFloat";
00513   case NVPTXISD::TexUnified1DFloatFloatLevel:
00514     return "NVPTXISD::TexUnified1DFloatFloatLevel";
00515   case NVPTXISD::TexUnified1DFloatFloatGrad:
00516     return "NVPTXISD::TexUnified1DFloatFloatGrad";
00517   case NVPTXISD::TexUnified1DS32S32:
00518     return "NVPTXISD::TexUnified1DS32S32";
00519   case NVPTXISD::TexUnified1DS32Float:
00520     return "NVPTXISD::TexUnified1DS32Float";
00521   case NVPTXISD::TexUnified1DS32FloatLevel:
00522     return "NVPTXISD::TexUnified1DS32FloatLevel";
00523   case NVPTXISD::TexUnified1DS32FloatGrad:
00524     return "NVPTXISD::TexUnified1DS32FloatGrad";
00525   case NVPTXISD::TexUnified1DU32S32:
00526     return "NVPTXISD::TexUnified1DU32S32";
00527   case NVPTXISD::TexUnified1DU32Float:
00528     return "NVPTXISD::TexUnified1DU32Float";
00529   case NVPTXISD::TexUnified1DU32FloatLevel:
00530     return "NVPTXISD::TexUnified1DU32FloatLevel";
00531   case NVPTXISD::TexUnified1DU32FloatGrad:
00532     return "NVPTXISD::TexUnified1DU32FloatGrad";
00533   case NVPTXISD::TexUnified1DArrayFloatS32:
00534     return "NVPTXISD::TexUnified1DArrayFloatS32";
00535   case NVPTXISD::TexUnified1DArrayFloatFloat:
00536     return "NVPTXISD::TexUnified1DArrayFloatFloat";
00537   case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
00538     return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
00539   case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
00540     return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
00541   case NVPTXISD::TexUnified1DArrayS32S32:
00542     return "NVPTXISD::TexUnified1DArrayS32S32";
00543   case NVPTXISD::TexUnified1DArrayS32Float:
00544     return "NVPTXISD::TexUnified1DArrayS32Float";
00545   case NVPTXISD::TexUnified1DArrayS32FloatLevel:
00546     return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
00547   case NVPTXISD::TexUnified1DArrayS32FloatGrad:
00548     return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
00549   case NVPTXISD::TexUnified1DArrayU32S32:
00550     return "NVPTXISD::TexUnified1DArrayU32S32";
00551   case NVPTXISD::TexUnified1DArrayU32Float:
00552     return "NVPTXISD::TexUnified1DArrayU32Float";
00553   case NVPTXISD::TexUnified1DArrayU32FloatLevel:
00554     return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
00555   case NVPTXISD::TexUnified1DArrayU32FloatGrad:
00556     return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
00557   case NVPTXISD::TexUnified2DFloatS32:
00558     return "NVPTXISD::TexUnified2DFloatS32";
00559   case NVPTXISD::TexUnified2DFloatFloat:
00560     return "NVPTXISD::TexUnified2DFloatFloat";
00561   case NVPTXISD::TexUnified2DFloatFloatLevel:
00562     return "NVPTXISD::TexUnified2DFloatFloatLevel";
00563   case NVPTXISD::TexUnified2DFloatFloatGrad:
00564     return "NVPTXISD::TexUnified2DFloatFloatGrad";
00565   case NVPTXISD::TexUnified2DS32S32:
00566     return "NVPTXISD::TexUnified2DS32S32";
00567   case NVPTXISD::TexUnified2DS32Float:
00568     return "NVPTXISD::TexUnified2DS32Float";
00569   case NVPTXISD::TexUnified2DS32FloatLevel:
00570     return "NVPTXISD::TexUnified2DS32FloatLevel";
00571   case NVPTXISD::TexUnified2DS32FloatGrad:
00572     return "NVPTXISD::TexUnified2DS32FloatGrad";
00573   case NVPTXISD::TexUnified2DU32S32:
00574     return "NVPTXISD::TexUnified2DU32S32";
00575   case NVPTXISD::TexUnified2DU32Float:
00576     return "NVPTXISD::TexUnified2DU32Float";
00577   case NVPTXISD::TexUnified2DU32FloatLevel:
00578     return "NVPTXISD::TexUnified2DU32FloatLevel";
00579   case NVPTXISD::TexUnified2DU32FloatGrad:
00580     return "NVPTXISD::TexUnified2DU32FloatGrad";
00581   case NVPTXISD::TexUnified2DArrayFloatS32:
00582     return "NVPTXISD::TexUnified2DArrayFloatS32";
00583   case NVPTXISD::TexUnified2DArrayFloatFloat:
00584     return "NVPTXISD::TexUnified2DArrayFloatFloat";
00585   case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
00586     return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
00587   case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
00588     return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
00589   case NVPTXISD::TexUnified2DArrayS32S32:
00590     return "NVPTXISD::TexUnified2DArrayS32S32";
00591   case NVPTXISD::TexUnified2DArrayS32Float:
00592     return "NVPTXISD::TexUnified2DArrayS32Float";
00593   case NVPTXISD::TexUnified2DArrayS32FloatLevel:
00594     return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
00595   case NVPTXISD::TexUnified2DArrayS32FloatGrad:
00596     return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
00597   case NVPTXISD::TexUnified2DArrayU32S32:
00598     return "NVPTXISD::TexUnified2DArrayU32S32";
00599   case NVPTXISD::TexUnified2DArrayU32Float:
00600     return "NVPTXISD::TexUnified2DArrayU32Float";
00601   case NVPTXISD::TexUnified2DArrayU32FloatLevel:
00602     return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
00603   case NVPTXISD::TexUnified2DArrayU32FloatGrad:
00604     return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
00605   case NVPTXISD::TexUnified3DFloatS32:
00606     return "NVPTXISD::TexUnified3DFloatS32";
00607   case NVPTXISD::TexUnified3DFloatFloat:
00608     return "NVPTXISD::TexUnified3DFloatFloat";
00609   case NVPTXISD::TexUnified3DFloatFloatLevel:
00610     return "NVPTXISD::TexUnified3DFloatFloatLevel";
00611   case NVPTXISD::TexUnified3DFloatFloatGrad:
00612     return "NVPTXISD::TexUnified3DFloatFloatGrad";
00613   case NVPTXISD::TexUnified3DS32S32:
00614     return "NVPTXISD::TexUnified3DS32S32";
00615   case NVPTXISD::TexUnified3DS32Float:
00616     return "NVPTXISD::TexUnified3DS32Float";
00617   case NVPTXISD::TexUnified3DS32FloatLevel:
00618     return "NVPTXISD::TexUnified3DS32FloatLevel";
00619   case NVPTXISD::TexUnified3DS32FloatGrad:
00620     return "NVPTXISD::TexUnified3DS32FloatGrad";
00621   case NVPTXISD::TexUnified3DU32S32:
00622     return "NVPTXISD::TexUnified3DU32S32";
00623   case NVPTXISD::TexUnified3DU32Float:
00624     return "NVPTXISD::TexUnified3DU32Float";
00625   case NVPTXISD::TexUnified3DU32FloatLevel:
00626     return "NVPTXISD::TexUnified3DU32FloatLevel";
00627   case NVPTXISD::TexUnified3DU32FloatGrad:
00628     return "NVPTXISD::TexUnified3DU32FloatGrad";
00629   case NVPTXISD::TexUnifiedCubeFloatFloat:
00630     return "NVPTXISD::TexUnifiedCubeFloatFloat";
00631   case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
00632     return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
00633   case NVPTXISD::TexUnifiedCubeS32Float:
00634     return "NVPTXISD::TexUnifiedCubeS32Float";
00635   case NVPTXISD::TexUnifiedCubeS32FloatLevel:
00636     return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
00637   case NVPTXISD::TexUnifiedCubeU32Float:
00638     return "NVPTXISD::TexUnifiedCubeU32Float";
00639   case NVPTXISD::TexUnifiedCubeU32FloatLevel:
00640     return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
00641   case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
00642     return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
00643   case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
00644     return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
00645   case NVPTXISD::TexUnifiedCubeArrayS32Float:
00646     return "NVPTXISD::TexUnifiedCubeArrayS32Float";
00647   case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
00648     return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
00649   case NVPTXISD::TexUnifiedCubeArrayU32Float:
00650     return "NVPTXISD::TexUnifiedCubeArrayU32Float";
00651   case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
00652     return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
00653   case NVPTXISD::Tld4UnifiedR2DFloatFloat:
00654     return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
00655   case NVPTXISD::Tld4UnifiedG2DFloatFloat:
00656     return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
00657   case NVPTXISD::Tld4UnifiedB2DFloatFloat:
00658     return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
00659   case NVPTXISD::Tld4UnifiedA2DFloatFloat:
00660     return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
00661   case NVPTXISD::Tld4UnifiedR2DS64Float:
00662     return "NVPTXISD::Tld4UnifiedR2DS64Float";
00663   case NVPTXISD::Tld4UnifiedG2DS64Float:
00664     return "NVPTXISD::Tld4UnifiedG2DS64Float";
00665   case NVPTXISD::Tld4UnifiedB2DS64Float:
00666     return "NVPTXISD::Tld4UnifiedB2DS64Float";
00667   case NVPTXISD::Tld4UnifiedA2DS64Float:
00668     return "NVPTXISD::Tld4UnifiedA2DS64Float";
00669   case NVPTXISD::Tld4UnifiedR2DU64Float:
00670     return "NVPTXISD::Tld4UnifiedR2DU64Float";
00671   case NVPTXISD::Tld4UnifiedG2DU64Float:
00672     return "NVPTXISD::Tld4UnifiedG2DU64Float";
00673   case NVPTXISD::Tld4UnifiedB2DU64Float:
00674     return "NVPTXISD::Tld4UnifiedB2DU64Float";
00675   case NVPTXISD::Tld4UnifiedA2DU64Float:
00676     return "NVPTXISD::Tld4UnifiedA2DU64Float";
00677 
00678   case NVPTXISD::Suld1DI8Clamp:          return "NVPTXISD::Suld1DI8Clamp";
00679   case NVPTXISD::Suld1DI16Clamp:         return "NVPTXISD::Suld1DI16Clamp";
00680   case NVPTXISD::Suld1DI32Clamp:         return "NVPTXISD::Suld1DI32Clamp";
00681   case NVPTXISD::Suld1DI64Clamp:         return "NVPTXISD::Suld1DI64Clamp";
00682   case NVPTXISD::Suld1DV2I8Clamp:        return "NVPTXISD::Suld1DV2I8Clamp";
00683   case NVPTXISD::Suld1DV2I16Clamp:       return "NVPTXISD::Suld1DV2I16Clamp";
00684   case NVPTXISD::Suld1DV2I32Clamp:       return "NVPTXISD::Suld1DV2I32Clamp";
00685   case NVPTXISD::Suld1DV2I64Clamp:       return "NVPTXISD::Suld1DV2I64Clamp";
00686   case NVPTXISD::Suld1DV4I8Clamp:        return "NVPTXISD::Suld1DV4I8Clamp";
00687   case NVPTXISD::Suld1DV4I16Clamp:       return "NVPTXISD::Suld1DV4I16Clamp";
00688   case NVPTXISD::Suld1DV4I32Clamp:       return "NVPTXISD::Suld1DV4I32Clamp";
00689 
00690   case NVPTXISD::Suld1DArrayI8Clamp:   return "NVPTXISD::Suld1DArrayI8Clamp";
00691   case NVPTXISD::Suld1DArrayI16Clamp:  return "NVPTXISD::Suld1DArrayI16Clamp";
00692   case NVPTXISD::Suld1DArrayI32Clamp:  return "NVPTXISD::Suld1DArrayI32Clamp";
00693   case NVPTXISD::Suld1DArrayI64Clamp:  return "NVPTXISD::Suld1DArrayI64Clamp";
00694   case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
00695   case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
00696   case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
00697   case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
00698   case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
00699   case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
00700   case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
00701 
00702   case NVPTXISD::Suld2DI8Clamp:          return "NVPTXISD::Suld2DI8Clamp";
00703   case NVPTXISD::Suld2DI16Clamp:         return "NVPTXISD::Suld2DI16Clamp";
00704   case NVPTXISD::Suld2DI32Clamp:         return "NVPTXISD::Suld2DI32Clamp";
00705   case NVPTXISD::Suld2DI64Clamp:         return "NVPTXISD::Suld2DI64Clamp";
00706   case NVPTXISD::Suld2DV2I8Clamp:        return "NVPTXISD::Suld2DV2I8Clamp";
00707   case NVPTXISD::Suld2DV2I16Clamp:       return "NVPTXISD::Suld2DV2I16Clamp";
00708   case NVPTXISD::Suld2DV2I32Clamp:       return "NVPTXISD::Suld2DV2I32Clamp";
00709   case NVPTXISD::Suld2DV2I64Clamp:       return "NVPTXISD::Suld2DV2I64Clamp";
00710   case NVPTXISD::Suld2DV4I8Clamp:        return "NVPTXISD::Suld2DV4I8Clamp";
00711   case NVPTXISD::Suld2DV4I16Clamp:       return "NVPTXISD::Suld2DV4I16Clamp";
00712   case NVPTXISD::Suld2DV4I32Clamp:       return "NVPTXISD::Suld2DV4I32Clamp";
00713 
00714   case NVPTXISD::Suld2DArrayI8Clamp:   return "NVPTXISD::Suld2DArrayI8Clamp";
00715   case NVPTXISD::Suld2DArrayI16Clamp:  return "NVPTXISD::Suld2DArrayI16Clamp";
00716   case NVPTXISD::Suld2DArrayI32Clamp:  return "NVPTXISD::Suld2DArrayI32Clamp";
00717   case NVPTXISD::Suld2DArrayI64Clamp:  return "NVPTXISD::Suld2DArrayI64Clamp";
00718   case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
00719   case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
00720   case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
00721   case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
00722   case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
00723   case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
00724   case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
00725 
00726   case NVPTXISD::Suld3DI8Clamp:          return "NVPTXISD::Suld3DI8Clamp";
00727   case NVPTXISD::Suld3DI16Clamp:         return "NVPTXISD::Suld3DI16Clamp";
00728   case NVPTXISD::Suld3DI32Clamp:         return "NVPTXISD::Suld3DI32Clamp";
00729   case NVPTXISD::Suld3DI64Clamp:         return "NVPTXISD::Suld3DI64Clamp";
00730   case NVPTXISD::Suld3DV2I8Clamp:        return "NVPTXISD::Suld3DV2I8Clamp";
00731   case NVPTXISD::Suld3DV2I16Clamp:       return "NVPTXISD::Suld3DV2I16Clamp";
00732   case NVPTXISD::Suld3DV2I32Clamp:       return "NVPTXISD::Suld3DV2I32Clamp";
00733   case NVPTXISD::Suld3DV2I64Clamp:       return "NVPTXISD::Suld3DV2I64Clamp";
00734   case NVPTXISD::Suld3DV4I8Clamp:        return "NVPTXISD::Suld3DV4I8Clamp";
00735   case NVPTXISD::Suld3DV4I16Clamp:       return "NVPTXISD::Suld3DV4I16Clamp";
00736   case NVPTXISD::Suld3DV4I32Clamp:       return "NVPTXISD::Suld3DV4I32Clamp";
00737 
00738   case NVPTXISD::Suld1DI8Trap:          return "NVPTXISD::Suld1DI8Trap";
00739   case NVPTXISD::Suld1DI16Trap:         return "NVPTXISD::Suld1DI16Trap";
00740   case NVPTXISD::Suld1DI32Trap:         return "NVPTXISD::Suld1DI32Trap";
00741   case NVPTXISD::Suld1DI64Trap:         return "NVPTXISD::Suld1DI64Trap";
00742   case NVPTXISD::Suld1DV2I8Trap:        return "NVPTXISD::Suld1DV2I8Trap";
00743   case NVPTXISD::Suld1DV2I16Trap:       return "NVPTXISD::Suld1DV2I16Trap";
00744   case NVPTXISD::Suld1DV2I32Trap:       return "NVPTXISD::Suld1DV2I32Trap";
00745   case NVPTXISD::Suld1DV2I64Trap:       return "NVPTXISD::Suld1DV2I64Trap";
00746   case NVPTXISD::Suld1DV4I8Trap:        return "NVPTXISD::Suld1DV4I8Trap";
00747   case NVPTXISD::Suld1DV4I16Trap:       return "NVPTXISD::Suld1DV4I16Trap";
00748   case NVPTXISD::Suld1DV4I32Trap:       return "NVPTXISD::Suld1DV4I32Trap";
00749 
00750   case NVPTXISD::Suld1DArrayI8Trap:     return "NVPTXISD::Suld1DArrayI8Trap";
00751   case NVPTXISD::Suld1DArrayI16Trap:    return "NVPTXISD::Suld1DArrayI16Trap";
00752   case NVPTXISD::Suld1DArrayI32Trap:    return "NVPTXISD::Suld1DArrayI32Trap";
00753   case NVPTXISD::Suld1DArrayI64Trap:    return "NVPTXISD::Suld1DArrayI64Trap";
00754   case NVPTXISD::Suld1DArrayV2I8Trap:   return "NVPTXISD::Suld1DArrayV2I8Trap";
00755   case NVPTXISD::Suld1DArrayV2I16Trap:  return "NVPTXISD::Suld1DArrayV2I16Trap";
00756   case NVPTXISD::Suld1DArrayV2I32Trap:  return "NVPTXISD::Suld1DArrayV2I32Trap";
00757   case NVPTXISD::Suld1DArrayV2I64Trap:  return "NVPTXISD::Suld1DArrayV2I64Trap";
00758   case NVPTXISD::Suld1DArrayV4I8Trap:   return "NVPTXISD::Suld1DArrayV4I8Trap";
00759   case NVPTXISD::Suld1DArrayV4I16Trap:  return "NVPTXISD::Suld1DArrayV4I16Trap";
00760   case NVPTXISD::Suld1DArrayV4I32Trap:  return "NVPTXISD::Suld1DArrayV4I32Trap";
00761 
00762   case NVPTXISD::Suld2DI8Trap:          return "NVPTXISD::Suld2DI8Trap";
00763   case NVPTXISD::Suld2DI16Trap:         return "NVPTXISD::Suld2DI16Trap";
00764   case NVPTXISD::Suld2DI32Trap:         return "NVPTXISD::Suld2DI32Trap";
00765   case NVPTXISD::Suld2DI64Trap:         return "NVPTXISD::Suld2DI64Trap";
00766   case NVPTXISD::Suld2DV2I8Trap:        return "NVPTXISD::Suld2DV2I8Trap";
00767   case NVPTXISD::Suld2DV2I16Trap:       return "NVPTXISD::Suld2DV2I16Trap";
00768   case NVPTXISD::Suld2DV2I32Trap:       return "NVPTXISD::Suld2DV2I32Trap";
00769   case NVPTXISD::Suld2DV2I64Trap:       return "NVPTXISD::Suld2DV2I64Trap";
00770   case NVPTXISD::Suld2DV4I8Trap:        return "NVPTXISD::Suld2DV4I8Trap";
00771   case NVPTXISD::Suld2DV4I16Trap:       return "NVPTXISD::Suld2DV4I16Trap";
00772   case NVPTXISD::Suld2DV4I32Trap:       return "NVPTXISD::Suld2DV4I32Trap";
00773 
00774   case NVPTXISD::Suld2DArrayI8Trap:     return "NVPTXISD::Suld2DArrayI8Trap";
00775   case NVPTXISD::Suld2DArrayI16Trap:    return "NVPTXISD::Suld2DArrayI16Trap";
00776   case NVPTXISD::Suld2DArrayI32Trap:    return "NVPTXISD::Suld2DArrayI32Trap";
00777   case NVPTXISD::Suld2DArrayI64Trap:    return "NVPTXISD::Suld2DArrayI64Trap";
00778   case NVPTXISD::Suld2DArrayV2I8Trap:   return "NVPTXISD::Suld2DArrayV2I8Trap";
00779   case NVPTXISD::Suld2DArrayV2I16Trap:  return "NVPTXISD::Suld2DArrayV2I16Trap";
00780   case NVPTXISD::Suld2DArrayV2I32Trap:  return "NVPTXISD::Suld2DArrayV2I32Trap";
00781   case NVPTXISD::Suld2DArrayV2I64Trap:  return "NVPTXISD::Suld2DArrayV2I64Trap";
00782   case NVPTXISD::Suld2DArrayV4I8Trap:   return "NVPTXISD::Suld2DArrayV4I8Trap";
00783   case NVPTXISD::Suld2DArrayV4I16Trap:  return "NVPTXISD::Suld2DArrayV4I16Trap";
00784   case NVPTXISD::Suld2DArrayV4I32Trap:  return "NVPTXISD::Suld2DArrayV4I32Trap";
00785 
00786   case NVPTXISD::Suld3DI8Trap:          return "NVPTXISD::Suld3DI8Trap";
00787   case NVPTXISD::Suld3DI16Trap:         return "NVPTXISD::Suld3DI16Trap";
00788   case NVPTXISD::Suld3DI32Trap:         return "NVPTXISD::Suld3DI32Trap";
00789   case NVPTXISD::Suld3DI64Trap:         return "NVPTXISD::Suld3DI64Trap";
00790   case NVPTXISD::Suld3DV2I8Trap:        return "NVPTXISD::Suld3DV2I8Trap";
00791   case NVPTXISD::Suld3DV2I16Trap:       return "NVPTXISD::Suld3DV2I16Trap";
00792   case NVPTXISD::Suld3DV2I32Trap:       return "NVPTXISD::Suld3DV2I32Trap";
00793   case NVPTXISD::Suld3DV2I64Trap:       return "NVPTXISD::Suld3DV2I64Trap";
00794   case NVPTXISD::Suld3DV4I8Trap:        return "NVPTXISD::Suld3DV4I8Trap";
00795   case NVPTXISD::Suld3DV4I16Trap:       return "NVPTXISD::Suld3DV4I16Trap";
00796   case NVPTXISD::Suld3DV4I32Trap:       return "NVPTXISD::Suld3DV4I32Trap";
00797 
00798   case NVPTXISD::Suld1DI8Zero:          return "NVPTXISD::Suld1DI8Zero";
00799   case NVPTXISD::Suld1DI16Zero:         return "NVPTXISD::Suld1DI16Zero";
00800   case NVPTXISD::Suld1DI32Zero:         return "NVPTXISD::Suld1DI32Zero";
00801   case NVPTXISD::Suld1DI64Zero:         return "NVPTXISD::Suld1DI64Zero";
00802   case NVPTXISD::Suld1DV2I8Zero:        return "NVPTXISD::Suld1DV2I8Zero";
00803   case NVPTXISD::Suld1DV2I16Zero:       return "NVPTXISD::Suld1DV2I16Zero";
00804   case NVPTXISD::Suld1DV2I32Zero:       return "NVPTXISD::Suld1DV2I32Zero";
00805   case NVPTXISD::Suld1DV2I64Zero:       return "NVPTXISD::Suld1DV2I64Zero";
00806   case NVPTXISD::Suld1DV4I8Zero:        return "NVPTXISD::Suld1DV4I8Zero";
00807   case NVPTXISD::Suld1DV4I16Zero:       return "NVPTXISD::Suld1DV4I16Zero";
00808   case NVPTXISD::Suld1DV4I32Zero:       return "NVPTXISD::Suld1DV4I32Zero";
00809 
00810   case NVPTXISD::Suld1DArrayI8Zero:     return "NVPTXISD::Suld1DArrayI8Zero";
00811   case NVPTXISD::Suld1DArrayI16Zero:    return "NVPTXISD::Suld1DArrayI16Zero";
00812   case NVPTXISD::Suld1DArrayI32Zero:    return "NVPTXISD::Suld1DArrayI32Zero";
00813   case NVPTXISD::Suld1DArrayI64Zero:    return "NVPTXISD::Suld1DArrayI64Zero";
00814   case NVPTXISD::Suld1DArrayV2I8Zero:   return "NVPTXISD::Suld1DArrayV2I8Zero";
00815   case NVPTXISD::Suld1DArrayV2I16Zero:  return "NVPTXISD::Suld1DArrayV2I16Zero";
00816   case NVPTXISD::Suld1DArrayV2I32Zero:  return "NVPTXISD::Suld1DArrayV2I32Zero";
00817   case NVPTXISD::Suld1DArrayV2I64Zero:  return "NVPTXISD::Suld1DArrayV2I64Zero";
00818   case NVPTXISD::Suld1DArrayV4I8Zero:   return "NVPTXISD::Suld1DArrayV4I8Zero";
00819   case NVPTXISD::Suld1DArrayV4I16Zero:  return "NVPTXISD::Suld1DArrayV4I16Zero";
00820   case NVPTXISD::Suld1DArrayV4I32Zero:  return "NVPTXISD::Suld1DArrayV4I32Zero";
00821 
00822   case NVPTXISD::Suld2DI8Zero:          return "NVPTXISD::Suld2DI8Zero";
00823   case NVPTXISD::Suld2DI16Zero:         return "NVPTXISD::Suld2DI16Zero";
00824   case NVPTXISD::Suld2DI32Zero:         return "NVPTXISD::Suld2DI32Zero";
00825   case NVPTXISD::Suld2DI64Zero:         return "NVPTXISD::Suld2DI64Zero";
00826   case NVPTXISD::Suld2DV2I8Zero:        return "NVPTXISD::Suld2DV2I8Zero";
00827   case NVPTXISD::Suld2DV2I16Zero:       return "NVPTXISD::Suld2DV2I16Zero";
00828   case NVPTXISD::Suld2DV2I32Zero:       return "NVPTXISD::Suld2DV2I32Zero";
00829   case NVPTXISD::Suld2DV2I64Zero:       return "NVPTXISD::Suld2DV2I64Zero";
00830   case NVPTXISD::Suld2DV4I8Zero:        return "NVPTXISD::Suld2DV4I8Zero";
00831   case NVPTXISD::Suld2DV4I16Zero:       return "NVPTXISD::Suld2DV4I16Zero";
00832   case NVPTXISD::Suld2DV4I32Zero:       return "NVPTXISD::Suld2DV4I32Zero";
00833 
00834   case NVPTXISD::Suld2DArrayI8Zero:     return "NVPTXISD::Suld2DArrayI8Zero";
00835   case NVPTXISD::Suld2DArrayI16Zero:    return "NVPTXISD::Suld2DArrayI16Zero";
00836   case NVPTXISD::Suld2DArrayI32Zero:    return "NVPTXISD::Suld2DArrayI32Zero";
00837   case NVPTXISD::Suld2DArrayI64Zero:    return "NVPTXISD::Suld2DArrayI64Zero";
00838   case NVPTXISD::Suld2DArrayV2I8Zero:   return "NVPTXISD::Suld2DArrayV2I8Zero";
00839   case NVPTXISD::Suld2DArrayV2I16Zero:  return "NVPTXISD::Suld2DArrayV2I16Zero";
00840   case NVPTXISD::Suld2DArrayV2I32Zero:  return "NVPTXISD::Suld2DArrayV2I32Zero";
00841   case NVPTXISD::Suld2DArrayV2I64Zero:  return "NVPTXISD::Suld2DArrayV2I64Zero";
00842   case NVPTXISD::Suld2DArrayV4I8Zero:   return "NVPTXISD::Suld2DArrayV4I8Zero";
00843   case NVPTXISD::Suld2DArrayV4I16Zero:  return "NVPTXISD::Suld2DArrayV4I16Zero";
00844   case NVPTXISD::Suld2DArrayV4I32Zero:  return "NVPTXISD::Suld2DArrayV4I32Zero";
00845 
00846   case NVPTXISD::Suld3DI8Zero:          return "NVPTXISD::Suld3DI8Zero";
00847   case NVPTXISD::Suld3DI16Zero:         return "NVPTXISD::Suld3DI16Zero";
00848   case NVPTXISD::Suld3DI32Zero:         return "NVPTXISD::Suld3DI32Zero";
00849   case NVPTXISD::Suld3DI64Zero:         return "NVPTXISD::Suld3DI64Zero";
00850   case NVPTXISD::Suld3DV2I8Zero:        return "NVPTXISD::Suld3DV2I8Zero";
00851   case NVPTXISD::Suld3DV2I16Zero:       return "NVPTXISD::Suld3DV2I16Zero";
00852   case NVPTXISD::Suld3DV2I32Zero:       return "NVPTXISD::Suld3DV2I32Zero";
00853   case NVPTXISD::Suld3DV2I64Zero:       return "NVPTXISD::Suld3DV2I64Zero";
00854   case NVPTXISD::Suld3DV4I8Zero:        return "NVPTXISD::Suld3DV4I8Zero";
00855   case NVPTXISD::Suld3DV4I16Zero:       return "NVPTXISD::Suld3DV4I16Zero";
00856   case NVPTXISD::Suld3DV4I32Zero:       return "NVPTXISD::Suld3DV4I32Zero";
00857   }
00858 }
00859 
00860 TargetLoweringBase::LegalizeTypeAction
00861 NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
00862   if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
00863     return TypeSplitVector;
00864 
00865   return TargetLoweringBase::getPreferredVectorAction(VT);
00866 }
00867 
00868 SDValue
00869 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
00870   SDLoc dl(Op);
00871   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
00872   Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
00873   return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
00874 }
00875 
00876 std::string
00877 NVPTXTargetLowering::getPrototype(Type *retTy, const ArgListTy &Args,
00878                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
00879                                   unsigned retAlignment,
00880                                   const ImmutableCallSite *CS) const {
00881 
00882   bool isABI = (STI.getSmVersion() >= 20);
00883   assert(isABI && "Non-ABI compilation is not supported");
00884   if (!isABI)
00885     return "";
00886 
00887   std::stringstream O;
00888   O << "prototype_" << uniqueCallSite << " : .callprototype ";
00889 
00890   if (retTy->getTypeID() == Type::VoidTyID) {
00891     O << "()";
00892   } else {
00893     O << "(";
00894     if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
00895       unsigned size = 0;
00896       if (const IntegerType *ITy = dyn_cast<IntegerType>(retTy)) {
00897         size = ITy->getBitWidth();
00898         if (size < 32)
00899           size = 32;
00900       } else {
00901         assert(retTy->isFloatingPointTy() &&
00902                "Floating point type expected here");
00903         size = retTy->getPrimitiveSizeInBits();
00904       }
00905 
00906       O << ".param .b" << size << " _";
00907     } else if (isa<PointerType>(retTy)) {
00908       O << ".param .b" << getPointerTy().getSizeInBits() << " _";
00909     } else if ((retTy->getTypeID() == Type::StructTyID) ||
00910                isa<VectorType>(retTy)) {
00911       O << ".param .align "
00912         << retAlignment
00913         << " .b8 _["
00914         << getDataLayout()->getTypeAllocSize(retTy) << "]";
00915     } else {
00916       llvm_unreachable("Unknown return type");
00917     }
00918     O << ") ";
00919   }
00920   O << "_ (";
00921 
00922   bool first = true;
00923   MVT thePointerTy = getPointerTy();
00924 
00925   unsigned OIdx = 0;
00926   for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
00927     Type *Ty = Args[i].Ty;
00928     if (!first) {
00929       O << ", ";
00930     }
00931     first = false;
00932 
00933     if (Outs[OIdx].Flags.isByVal() == false) {
00934       if (Ty->isAggregateType() || Ty->isVectorTy()) {
00935         unsigned align = 0;
00936         const CallInst *CallI = cast<CallInst>(CS->getInstruction());
00937         const DataLayout *TD = getDataLayout();
00938         // +1 because index 0 is reserved for return type alignment
00939         if (!llvm::getAlign(*CallI, i + 1, align))
00940           align = TD->getABITypeAlignment(Ty);
00941         unsigned sz = TD->getTypeAllocSize(Ty);
00942         O << ".param .align " << align << " .b8 ";
00943         O << "_";
00944         O << "[" << sz << "]";
00945         // update the index for Outs
00946         SmallVector<EVT, 16> vtparts;
00947         ComputeValueVTs(*this, Ty, vtparts);
00948         if (unsigned len = vtparts.size())
00949           OIdx += len - 1;
00950         continue;
00951       }
00952        // i8 types in IR will be i16 types in SDAG
00953       assert((getValueType(Ty) == Outs[OIdx].VT ||
00954              (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
00955              "type mismatch between callee prototype and arguments");
00956       // scalar type
00957       unsigned sz = 0;
00958       if (isa<IntegerType>(Ty)) {
00959         sz = cast<IntegerType>(Ty)->getBitWidth();
00960         if (sz < 32)
00961           sz = 32;
00962       } else if (isa<PointerType>(Ty))
00963         sz = thePointerTy.getSizeInBits();
00964       else
00965         sz = Ty->getPrimitiveSizeInBits();
00966       O << ".param .b" << sz << " ";
00967       O << "_";
00968       continue;
00969     }
00970     const PointerType *PTy = dyn_cast<PointerType>(Ty);
00971     assert(PTy && "Param with byval attribute should be a pointer type");
00972     Type *ETy = PTy->getElementType();
00973 
00974     unsigned align = Outs[OIdx].Flags.getByValAlign();
00975     unsigned sz = getDataLayout()->getTypeAllocSize(ETy);
00976     O << ".param .align " << align << " .b8 ";
00977     O << "_";
00978     O << "[" << sz << "]";
00979   }
00980   O << ");";
00981   return O.str();
00982 }
00983 
00984 unsigned
00985 NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
00986                                           const ImmutableCallSite *CS,
00987                                           Type *Ty,
00988                                           unsigned Idx) const {
00989   const DataLayout *TD = getDataLayout();
00990   unsigned Align = 0;
00991   const Value *DirectCallee = CS->getCalledFunction();
00992 
00993   if (!DirectCallee) {
00994     // We don't have a direct function symbol, but that may be because of
00995     // constant cast instructions in the call.
00996     const Instruction *CalleeI = CS->getInstruction();
00997     assert(CalleeI && "Call target is not a function or derived value?");
00998 
00999     // With bitcast'd call targets, the instruction will be the call
01000     if (isa<CallInst>(CalleeI)) {
01001       // Check if we have call alignment metadata
01002       if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
01003         return Align;
01004 
01005       const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
01006       // Ignore any bitcast instructions
01007       while(isa<ConstantExpr>(CalleeV)) {
01008         const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
01009         if (!CE->isCast())
01010           break;
01011         // Look through the bitcast
01012         CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
01013       }
01014 
01015       // We have now looked past all of the bitcasts.  Do we finally have a
01016       // Function?
01017       if (isa<Function>(CalleeV))
01018         DirectCallee = CalleeV;
01019     }
01020   }
01021 
01022   // Check for function alignment information if we found that the
01023   // ultimate target is a Function
01024   if (DirectCallee)
01025     if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
01026       return Align;
01027 
01028   // Call is indirect or alignment information is not available, fall back to
01029   // the ABI type alignment
01030   return TD->getABITypeAlignment(Ty);
01031 }
01032 
01033 SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
01034                                        SmallVectorImpl<SDValue> &InVals) const {
01035   SelectionDAG &DAG = CLI.DAG;
01036   SDLoc dl = CLI.DL;
01037   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
01038   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
01039   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
01040   SDValue Chain = CLI.Chain;
01041   SDValue Callee = CLI.Callee;
01042   bool &isTailCall = CLI.IsTailCall;
01043   ArgListTy &Args = CLI.getArgs();
01044   Type *retTy = CLI.RetTy;
01045   ImmutableCallSite *CS = CLI.CS;
01046 
01047   bool isABI = (STI.getSmVersion() >= 20);
01048   assert(isABI && "Non-ABI compilation is not supported");
01049   if (!isABI)
01050     return Chain;
01051   const DataLayout *TD = getDataLayout();
01052   MachineFunction &MF = DAG.getMachineFunction();
01053   const Function *F = MF.getFunction();
01054 
01055   SDValue tempChain = Chain;
01056   Chain =
01057       DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
01058                            dl);
01059   SDValue InFlag = Chain.getValue(1);
01060 
01061   unsigned paramCount = 0;
01062   // Args.size() and Outs.size() need not match.
01063   // Outs.size() will be larger
01064   //   * if there is an aggregate argument with multiple fields (each field
01065   //     showing up separately in Outs)
01066   //   * if there is a vector argument with more than typical vector-length
01067   //     elements (generally if more than 4) where each vector element is
01068   //     individually present in Outs.
01069   // So a different index should be used for indexing into Outs/OutVals.
01070   // See similar issue in LowerFormalArguments.
01071   unsigned OIdx = 0;
01072   // Declare the .params or .reg need to pass values
01073   // to the function
01074   for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
01075     EVT VT = Outs[OIdx].VT;
01076     Type *Ty = Args[i].Ty;
01077 
01078     if (Outs[OIdx].Flags.isByVal() == false) {
01079       if (Ty->isAggregateType()) {
01080         // aggregate
01081         SmallVector<EVT, 16> vtparts;
01082         SmallVector<uint64_t, 16> Offsets;
01083         ComputePTXValueVTs(*this, Ty, vtparts, &Offsets, 0);
01084 
01085         unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
01086         // declare .param .align <align> .b8 .param<n>[<size>];
01087         unsigned sz = TD->getTypeAllocSize(Ty);
01088         SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01089         SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
01090                                       DAG.getConstant(paramCount, MVT::i32),
01091                                       DAG.getConstant(sz, MVT::i32), InFlag };
01092         Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
01093                             DeclareParamOps);
01094         InFlag = Chain.getValue(1);
01095         for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
01096           EVT elemtype = vtparts[j];
01097           unsigned ArgAlign = GreatestCommonDivisor64(align, Offsets[j]);
01098           if (elemtype.isInteger() && (sz < 8))
01099             sz = 8;
01100           SDValue StVal = OutVals[OIdx];
01101           if (elemtype.getSizeInBits() < 16) {
01102             StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
01103           }
01104           SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01105           SDValue CopyParamOps[] = { Chain,
01106                                      DAG.getConstant(paramCount, MVT::i32),
01107                                      DAG.getConstant(Offsets[j], MVT::i32),
01108                                      StVal, InFlag };
01109           Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
01110                                           CopyParamVTs, CopyParamOps,
01111                                           elemtype, MachinePointerInfo(),
01112                                           ArgAlign);
01113           InFlag = Chain.getValue(1);
01114           ++OIdx;
01115         }
01116         if (vtparts.size() > 0)
01117           --OIdx;
01118         ++paramCount;
01119         continue;
01120       }
01121       if (Ty->isVectorTy()) {
01122         EVT ObjectVT = getValueType(Ty);
01123         unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
01124         // declare .param .align <align> .b8 .param<n>[<size>];
01125         unsigned sz = TD->getTypeAllocSize(Ty);
01126         SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01127         SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
01128                                       DAG.getConstant(paramCount, MVT::i32),
01129                                       DAG.getConstant(sz, MVT::i32), InFlag };
01130         Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
01131                             DeclareParamOps);
01132         InFlag = Chain.getValue(1);
01133         unsigned NumElts = ObjectVT.getVectorNumElements();
01134         EVT EltVT = ObjectVT.getVectorElementType();
01135         EVT MemVT = EltVT;
01136         bool NeedExtend = false;
01137         if (EltVT.getSizeInBits() < 16) {
01138           NeedExtend = true;
01139           EltVT = MVT::i16;
01140         }
01141 
01142         // V1 store
01143         if (NumElts == 1) {
01144           SDValue Elt = OutVals[OIdx++];
01145           if (NeedExtend)
01146             Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
01147 
01148           SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01149           SDValue CopyParamOps[] = { Chain,
01150                                      DAG.getConstant(paramCount, MVT::i32),
01151                                      DAG.getConstant(0, MVT::i32), Elt,
01152                                      InFlag };
01153           Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
01154                                           CopyParamVTs, CopyParamOps,
01155                                           MemVT, MachinePointerInfo());
01156           InFlag = Chain.getValue(1);
01157         } else if (NumElts == 2) {
01158           SDValue Elt0 = OutVals[OIdx++];
01159           SDValue Elt1 = OutVals[OIdx++];
01160           if (NeedExtend) {
01161             Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
01162             Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
01163           }
01164 
01165           SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01166           SDValue CopyParamOps[] = { Chain,
01167                                      DAG.getConstant(paramCount, MVT::i32),
01168                                      DAG.getConstant(0, MVT::i32), Elt0, Elt1,
01169                                      InFlag };
01170           Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
01171                                           CopyParamVTs, CopyParamOps,
01172                                           MemVT, MachinePointerInfo());
01173           InFlag = Chain.getValue(1);
01174         } else {
01175           unsigned curOffset = 0;
01176           // V4 stores
01177           // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
01178           // the
01179           // vector will be expanded to a power of 2 elements, so we know we can
01180           // always round up to the next multiple of 4 when creating the vector
01181           // stores.
01182           // e.g.  4 elem => 1 st.v4
01183           //       6 elem => 2 st.v4
01184           //       8 elem => 2 st.v4
01185           //      11 elem => 3 st.v4
01186           unsigned VecSize = 4;
01187           if (EltVT.getSizeInBits() == 64)
01188             VecSize = 2;
01189 
01190           // This is potentially only part of a vector, so assume all elements
01191           // are packed together.
01192           unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
01193 
01194           for (unsigned i = 0; i < NumElts; i += VecSize) {
01195             // Get values
01196             SDValue StoreVal;
01197             SmallVector<SDValue, 8> Ops;
01198             Ops.push_back(Chain);
01199             Ops.push_back(DAG.getConstant(paramCount, MVT::i32));
01200             Ops.push_back(DAG.getConstant(curOffset, MVT::i32));
01201 
01202             unsigned Opc = NVPTXISD::StoreParamV2;
01203 
01204             StoreVal = OutVals[OIdx++];
01205             if (NeedExtend)
01206               StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
01207             Ops.push_back(StoreVal);
01208 
01209             if (i + 1 < NumElts) {
01210               StoreVal = OutVals[OIdx++];
01211               if (NeedExtend)
01212                 StoreVal =
01213                     DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
01214             } else {
01215               StoreVal = DAG.getUNDEF(EltVT);
01216             }
01217             Ops.push_back(StoreVal);
01218 
01219             if (VecSize == 4) {
01220               Opc = NVPTXISD::StoreParamV4;
01221               if (i + 2 < NumElts) {
01222                 StoreVal = OutVals[OIdx++];
01223                 if (NeedExtend)
01224                   StoreVal =
01225                       DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
01226               } else {
01227                 StoreVal = DAG.getUNDEF(EltVT);
01228               }
01229               Ops.push_back(StoreVal);
01230 
01231               if (i + 3 < NumElts) {
01232                 StoreVal = OutVals[OIdx++];
01233                 if (NeedExtend)
01234                   StoreVal =
01235                       DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
01236               } else {
01237                 StoreVal = DAG.getUNDEF(EltVT);
01238               }
01239               Ops.push_back(StoreVal);
01240             }
01241 
01242             Ops.push_back(InFlag);
01243 
01244             SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01245             Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
01246                                             MemVT, MachinePointerInfo());
01247             InFlag = Chain.getValue(1);
01248             curOffset += PerStoreOffset;
01249           }
01250         }
01251         ++paramCount;
01252         --OIdx;
01253         continue;
01254       }
01255       // Plain scalar
01256       // for ABI,    declare .param .b<size> .param<n>;
01257       unsigned sz = VT.getSizeInBits();
01258       bool needExtend = false;
01259       if (VT.isInteger()) {
01260         if (sz < 16)
01261           needExtend = true;
01262         if (sz < 32)
01263           sz = 32;
01264       }
01265       SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01266       SDValue DeclareParamOps[] = { Chain,
01267                                     DAG.getConstant(paramCount, MVT::i32),
01268                                     DAG.getConstant(sz, MVT::i32),
01269                                     DAG.getConstant(0, MVT::i32), InFlag };
01270       Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
01271                           DeclareParamOps);
01272       InFlag = Chain.getValue(1);
01273       SDValue OutV = OutVals[OIdx];
01274       if (needExtend) {
01275         // zext/sext i1 to i16
01276         unsigned opc = ISD::ZERO_EXTEND;
01277         if (Outs[OIdx].Flags.isSExt())
01278           opc = ISD::SIGN_EXTEND;
01279         OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
01280       }
01281       SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01282       SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
01283                                  DAG.getConstant(0, MVT::i32), OutV, InFlag };
01284 
01285       unsigned opcode = NVPTXISD::StoreParam;
01286       if (Outs[OIdx].Flags.isZExt())
01287         opcode = NVPTXISD::StoreParamU32;
01288       else if (Outs[OIdx].Flags.isSExt())
01289         opcode = NVPTXISD::StoreParamS32;
01290       Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
01291                                       VT, MachinePointerInfo());
01292 
01293       InFlag = Chain.getValue(1);
01294       ++paramCount;
01295       continue;
01296     }
01297     // struct or vector
01298     SmallVector<EVT, 16> vtparts;
01299     SmallVector<uint64_t, 16> Offsets;
01300     const PointerType *PTy = dyn_cast<PointerType>(Args[i].Ty);
01301     assert(PTy && "Type of a byval parameter should be pointer");
01302     ComputePTXValueVTs(*this, PTy->getElementType(), vtparts, &Offsets, 0);
01303 
01304     // declare .param .align <align> .b8 .param<n>[<size>];
01305     unsigned sz = Outs[OIdx].Flags.getByValSize();
01306     SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01307     unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
01308     // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
01309     // so we don't need to worry about natural alignment or not.
01310     // See TargetLowering::LowerCallTo().
01311     SDValue DeclareParamOps[] = {
01312       Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), MVT::i32),
01313       DAG.getConstant(paramCount, MVT::i32), DAG.getConstant(sz, MVT::i32),
01314       InFlag
01315     };
01316     Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
01317                         DeclareParamOps);
01318     InFlag = Chain.getValue(1);
01319     for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
01320       EVT elemtype = vtparts[j];
01321       int curOffset = Offsets[j];
01322       unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
01323       SDValue srcAddr =
01324           DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[OIdx],
01325                       DAG.getConstant(curOffset, getPointerTy()));
01326       SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
01327                                    MachinePointerInfo(), false, false, false,
01328                                    PartAlign);
01329       if (elemtype.getSizeInBits() < 16) {
01330         theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
01331       }
01332       SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01333       SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
01334                                  DAG.getConstant(curOffset, MVT::i32), theVal,
01335                                  InFlag };
01336       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
01337                                       CopyParamOps, elemtype,
01338                                       MachinePointerInfo());
01339 
01340       InFlag = Chain.getValue(1);
01341     }
01342     ++paramCount;
01343   }
01344 
01345   GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
01346   unsigned retAlignment = 0;
01347 
01348   // Handle Result
01349   if (Ins.size() > 0) {
01350     SmallVector<EVT, 16> resvtparts;
01351     ComputeValueVTs(*this, retTy, resvtparts);
01352 
01353     // Declare
01354     //  .param .align 16 .b8 retval0[<size-in-bytes>], or
01355     //  .param .b<size-in-bits> retval0
01356     unsigned resultsz = TD->getTypeAllocSizeInBits(retTy);
01357     // Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
01358     // these three types to match the logic in
01359     // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
01360     // Plus, this behavior is consistent with nvcc's.
01361     if (retTy->isFloatingPointTy() || retTy->isIntegerTy() ||
01362         retTy->isPointerTy()) {
01363       // Scalar needs to be at least 32bit wide
01364       if (resultsz < 32)
01365         resultsz = 32;
01366       SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01367       SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, MVT::i32),
01368                                   DAG.getConstant(resultsz, MVT::i32),
01369                                   DAG.getConstant(0, MVT::i32), InFlag };
01370       Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
01371                           DeclareRetOps);
01372       InFlag = Chain.getValue(1);
01373     } else {
01374       retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
01375       SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01376       SDValue DeclareRetOps[] = { Chain,
01377                                   DAG.getConstant(retAlignment, MVT::i32),
01378                                   DAG.getConstant(resultsz / 8, MVT::i32),
01379                                   DAG.getConstant(0, MVT::i32), InFlag };
01380       Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
01381                           DeclareRetOps);
01382       InFlag = Chain.getValue(1);
01383     }
01384   }
01385 
01386   if (!Func) {
01387     // This is indirect function call case : PTX requires a prototype of the
01388     // form
01389     // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
01390     // to be emitted, and the label has to used as the last arg of call
01391     // instruction.
01392     // The prototype is embedded in a string and put as the operand for a
01393     // CallPrototype SDNode which will print out to the value of the string.
01394     SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01395     std::string Proto = getPrototype(retTy, Args, Outs, retAlignment, CS);
01396     const char *ProtoStr =
01397       nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
01398     SDValue ProtoOps[] = {
01399       Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
01400     };
01401     Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
01402     InFlag = Chain.getValue(1);
01403   }
01404   // Op to just print "call"
01405   SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01406   SDValue PrintCallOps[] = {
01407     Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, MVT::i32), InFlag
01408   };
01409   Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
01410                       dl, PrintCallVTs, PrintCallOps);
01411   InFlag = Chain.getValue(1);
01412 
01413   // Ops to print out the function name
01414   SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01415   SDValue CallVoidOps[] = { Chain, Callee, InFlag };
01416   Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
01417   InFlag = Chain.getValue(1);
01418 
01419   // Ops to print out the param list
01420   SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01421   SDValue CallArgBeginOps[] = { Chain, InFlag };
01422   Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
01423                       CallArgBeginOps);
01424   InFlag = Chain.getValue(1);
01425 
01426   for (unsigned i = 0, e = paramCount; i != e; ++i) {
01427     unsigned opcode;
01428     if (i == (e - 1))
01429       opcode = NVPTXISD::LastCallArg;
01430     else
01431       opcode = NVPTXISD::CallArg;
01432     SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01433     SDValue CallArgOps[] = { Chain, DAG.getConstant(1, MVT::i32),
01434                              DAG.getConstant(i, MVT::i32), InFlag };
01435     Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
01436     InFlag = Chain.getValue(1);
01437   }
01438   SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01439   SDValue CallArgEndOps[] = { Chain, DAG.getConstant(Func ? 1 : 0, MVT::i32),
01440                               InFlag };
01441   Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
01442   InFlag = Chain.getValue(1);
01443 
01444   if (!Func) {
01445     SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01446     SDValue PrototypeOps[] = { Chain, DAG.getConstant(uniqueCallSite, MVT::i32),
01447                                InFlag };
01448     Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
01449     InFlag = Chain.getValue(1);
01450   }
01451 
01452   // Generate loads from param memory/moves from registers for result
01453   if (Ins.size() > 0) {
01454     if (retTy && retTy->isVectorTy()) {
01455       EVT ObjectVT = getValueType(retTy);
01456       unsigned NumElts = ObjectVT.getVectorNumElements();
01457       EVT EltVT = ObjectVT.getVectorElementType();
01458       assert(STI.getTargetLowering()->getNumRegisters(F->getContext(),
01459                                                       ObjectVT) == NumElts &&
01460              "Vector was not scalarized");
01461       unsigned sz = EltVT.getSizeInBits();
01462       bool needTruncate = sz < 8 ? true : false;
01463 
01464       if (NumElts == 1) {
01465         // Just a simple load
01466         SmallVector<EVT, 4> LoadRetVTs;
01467         if (EltVT == MVT::i1 || EltVT == MVT::i8) {
01468           // If loading i1/i8 result, generate
01469           //   load.b8 i16
01470           //   if i1
01471           //   trunc i16 to i1
01472           LoadRetVTs.push_back(MVT::i16);
01473         } else
01474           LoadRetVTs.push_back(EltVT);
01475         LoadRetVTs.push_back(MVT::Other);
01476         LoadRetVTs.push_back(MVT::Glue);
01477         SmallVector<SDValue, 4> LoadRetOps;
01478         LoadRetOps.push_back(Chain);
01479         LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
01480         LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
01481         LoadRetOps.push_back(InFlag);
01482         SDValue retval = DAG.getMemIntrinsicNode(
01483             NVPTXISD::LoadParam, dl,
01484             DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
01485         Chain = retval.getValue(1);
01486         InFlag = retval.getValue(2);
01487         SDValue Ret0 = retval;
01488         if (needTruncate)
01489           Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
01490         InVals.push_back(Ret0);
01491       } else if (NumElts == 2) {
01492         // LoadV2
01493         SmallVector<EVT, 4> LoadRetVTs;
01494         if (EltVT == MVT::i1 || EltVT == MVT::i8) {
01495           // If loading i1/i8 result, generate
01496           //   load.b8 i16
01497           //   if i1
01498           //   trunc i16 to i1
01499           LoadRetVTs.push_back(MVT::i16);
01500           LoadRetVTs.push_back(MVT::i16);
01501         } else {
01502           LoadRetVTs.push_back(EltVT);
01503           LoadRetVTs.push_back(EltVT);
01504         }
01505         LoadRetVTs.push_back(MVT::Other);
01506         LoadRetVTs.push_back(MVT::Glue);
01507         SmallVector<SDValue, 4> LoadRetOps;
01508         LoadRetOps.push_back(Chain);
01509         LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
01510         LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
01511         LoadRetOps.push_back(InFlag);
01512         SDValue retval = DAG.getMemIntrinsicNode(
01513             NVPTXISD::LoadParamV2, dl,
01514             DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
01515         Chain = retval.getValue(2);
01516         InFlag = retval.getValue(3);
01517         SDValue Ret0 = retval.getValue(0);
01518         SDValue Ret1 = retval.getValue(1);
01519         if (needTruncate) {
01520           Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
01521           InVals.push_back(Ret0);
01522           Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
01523           InVals.push_back(Ret1);
01524         } else {
01525           InVals.push_back(Ret0);
01526           InVals.push_back(Ret1);
01527         }
01528       } else {
01529         // Split into N LoadV4
01530         unsigned Ofst = 0;
01531         unsigned VecSize = 4;
01532         unsigned Opc = NVPTXISD::LoadParamV4;
01533         if (EltVT.getSizeInBits() == 64) {
01534           VecSize = 2;
01535           Opc = NVPTXISD::LoadParamV2;
01536         }
01537         EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
01538         for (unsigned i = 0; i < NumElts; i += VecSize) {
01539           SmallVector<EVT, 8> LoadRetVTs;
01540           if (EltVT == MVT::i1 || EltVT == MVT::i8) {
01541             // If loading i1/i8 result, generate
01542             //   load.b8 i16
01543             //   if i1
01544             //   trunc i16 to i1
01545             for (unsigned j = 0; j < VecSize; ++j)
01546               LoadRetVTs.push_back(MVT::i16);
01547           } else {
01548             for (unsigned j = 0; j < VecSize; ++j)
01549               LoadRetVTs.push_back(EltVT);
01550           }
01551           LoadRetVTs.push_back(MVT::Other);
01552           LoadRetVTs.push_back(MVT::Glue);
01553           SmallVector<SDValue, 4> LoadRetOps;
01554           LoadRetOps.push_back(Chain);
01555           LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
01556           LoadRetOps.push_back(DAG.getConstant(Ofst, MVT::i32));
01557           LoadRetOps.push_back(InFlag);
01558           SDValue retval = DAG.getMemIntrinsicNode(
01559               Opc, dl, DAG.getVTList(LoadRetVTs),
01560               LoadRetOps, EltVT, MachinePointerInfo());
01561           if (VecSize == 2) {
01562             Chain = retval.getValue(2);
01563             InFlag = retval.getValue(3);
01564           } else {
01565             Chain = retval.getValue(4);
01566             InFlag = retval.getValue(5);
01567           }
01568 
01569           for (unsigned j = 0; j < VecSize; ++j) {
01570             if (i + j >= NumElts)
01571               break;
01572             SDValue Elt = retval.getValue(j);
01573             if (needTruncate)
01574               Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
01575             InVals.push_back(Elt);
01576           }
01577           Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
01578         }
01579       }
01580     } else {
01581       SmallVector<EVT, 16> VTs;
01582       SmallVector<uint64_t, 16> Offsets;
01583       ComputePTXValueVTs(*this, retTy, VTs, &Offsets, 0);
01584       assert(VTs.size() == Ins.size() && "Bad value decomposition");
01585       unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0);
01586       for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
01587         unsigned sz = VTs[i].getSizeInBits();
01588         unsigned AlignI = GreatestCommonDivisor64(RetAlign, Offsets[i]);
01589         bool needTruncate = sz < 8 ? true : false;
01590         if (VTs[i].isInteger() && (sz < 8))
01591           sz = 8;
01592 
01593         SmallVector<EVT, 4> LoadRetVTs;
01594         EVT TheLoadType = VTs[i];
01595         if (retTy->isIntegerTy() &&
01596             TD->getTypeAllocSizeInBits(retTy) < 32) {
01597           // This is for integer types only, and specifically not for
01598           // aggregates.
01599           LoadRetVTs.push_back(MVT::i32);
01600           TheLoadType = MVT::i32;
01601         } else if (sz < 16) {
01602           // If loading i1/i8 result, generate
01603           //   load i8 (-> i16)
01604           //   trunc i16 to i1/i8
01605           LoadRetVTs.push_back(MVT::i16);
01606         } else
01607           LoadRetVTs.push_back(Ins[i].VT);
01608         LoadRetVTs.push_back(MVT::Other);
01609         LoadRetVTs.push_back(MVT::Glue);
01610 
01611         SmallVector<SDValue, 4> LoadRetOps;
01612         LoadRetOps.push_back(Chain);
01613         LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
01614         LoadRetOps.push_back(DAG.getConstant(Offsets[i], MVT::i32));
01615         LoadRetOps.push_back(InFlag);
01616         SDValue retval = DAG.getMemIntrinsicNode(
01617             NVPTXISD::LoadParam, dl,
01618             DAG.getVTList(LoadRetVTs), LoadRetOps,
01619             TheLoadType, MachinePointerInfo(), AlignI);
01620         Chain = retval.getValue(1);
01621         InFlag = retval.getValue(2);
01622         SDValue Ret0 = retval.getValue(0);
01623         if (needTruncate)
01624           Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
01625         InVals.push_back(Ret0);
01626       }
01627     }
01628   }
01629 
01630   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
01631                              DAG.getIntPtrConstant(uniqueCallSite + 1, true),
01632                              InFlag, dl);
01633   uniqueCallSite++;
01634 
01635   // set isTailCall to false for now, until we figure out how to express
01636   // tail call optimization in PTX
01637   isTailCall = false;
01638   return Chain;
01639 }
01640 
01641 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
01642 // (see LegalizeDAG.cpp). This is slow and uses local memory.
01643 // We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
01644 SDValue
01645 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
01646   SDNode *Node = Op.getNode();
01647   SDLoc dl(Node);
01648   SmallVector<SDValue, 8> Ops;
01649   unsigned NumOperands = Node->getNumOperands();
01650   for (unsigned i = 0; i < NumOperands; ++i) {
01651     SDValue SubOp = Node->getOperand(i);
01652     EVT VVT = SubOp.getNode()->getValueType(0);
01653     EVT EltVT = VVT.getVectorElementType();
01654     unsigned NumSubElem = VVT.getVectorNumElements();
01655     for (unsigned j = 0; j < NumSubElem; ++j) {
01656       Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
01657                                 DAG.getIntPtrConstant(j)));
01658     }
01659   }
01660   return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
01661 }
01662 
01663 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
01664 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
01665 ///    amount, or
01666 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
01667 ///    amount.
01668 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
01669                                                   SelectionDAG &DAG) const {
01670   assert(Op.getNumOperands() == 3 && "Not a double-shift!");
01671   assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
01672 
01673   EVT VT = Op.getValueType();
01674   unsigned VTBits = VT.getSizeInBits();
01675   SDLoc dl(Op);
01676   SDValue ShOpLo = Op.getOperand(0);
01677   SDValue ShOpHi = Op.getOperand(1);
01678   SDValue ShAmt  = Op.getOperand(2);
01679   unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
01680 
01681   if (VTBits == 32 && STI.getSmVersion() >= 35) {
01682 
01683     // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
01684     // {dHi, dLo} = {aHi, aLo} >> Amt
01685     //   dHi = aHi >> Amt
01686     //   dLo = shf.r.clamp aLo, aHi, Amt
01687 
01688     SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
01689     SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
01690                              ShAmt);
01691 
01692     SDValue Ops[2] = { Lo, Hi };
01693     return DAG.getMergeValues(Ops, dl);
01694   }
01695   else {
01696 
01697     // {dHi, dLo} = {aHi, aLo} >> Amt
01698     // - if (Amt>=size) then
01699     //      dLo = aHi >> (Amt-size)
01700     //      dHi = aHi >> Amt (this is either all 0 or all 1)
01701     //   else
01702     //      dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
01703     //      dHi = aHi >> Amt
01704 
01705     SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
01706                                    DAG.getConstant(VTBits, MVT::i32), ShAmt);
01707     SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
01708     SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
01709                                      DAG.getConstant(VTBits, MVT::i32));
01710     SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
01711     SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
01712     SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
01713 
01714     SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
01715                                DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
01716     SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
01717     SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
01718 
01719     SDValue Ops[2] = { Lo, Hi };
01720     return DAG.getMergeValues(Ops, dl);
01721   }
01722 }
01723 
01724 /// LowerShiftLeftParts - Lower SHL_PARTS, which
01725 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
01726 ///    amount, or
01727 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
01728 ///    amount.
01729 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
01730                                                  SelectionDAG &DAG) const {
01731   assert(Op.getNumOperands() == 3 && "Not a double-shift!");
01732   assert(Op.getOpcode() == ISD::SHL_PARTS);
01733 
01734   EVT VT = Op.getValueType();
01735   unsigned VTBits = VT.getSizeInBits();
01736   SDLoc dl(Op);
01737   SDValue ShOpLo = Op.getOperand(0);
01738   SDValue ShOpHi = Op.getOperand(1);
01739   SDValue ShAmt  = Op.getOperand(2);
01740 
01741   if (VTBits == 32 && STI.getSmVersion() >= 35) {
01742 
01743     // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
01744     // {dHi, dLo} = {aHi, aLo} << Amt
01745     //   dHi = shf.l.clamp aLo, aHi, Amt
01746     //   dLo = aLo << Amt
01747 
01748     SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
01749                              ShAmt);
01750     SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
01751 
01752     SDValue Ops[2] = { Lo, Hi };
01753     return DAG.getMergeValues(Ops, dl);
01754   }
01755   else {
01756 
01757     // {dHi, dLo} = {aHi, aLo} << Amt
01758     // - if (Amt>=size) then
01759     //      dLo = aLo << Amt (all 0)
01760     //      dLo = aLo << (Amt-size)
01761     //   else
01762     //      dLo = aLo << Amt
01763     //      dHi = (aHi << Amt) | (aLo >> (size-Amt))
01764 
01765     SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
01766                                    DAG.getConstant(VTBits, MVT::i32), ShAmt);
01767     SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
01768     SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
01769                                      DAG.getConstant(VTBits, MVT::i32));
01770     SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
01771     SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
01772     SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
01773 
01774     SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
01775                                DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
01776     SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
01777     SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
01778 
01779     SDValue Ops[2] = { Lo, Hi };
01780     return DAG.getMergeValues(Ops, dl);
01781   }
01782 }
01783 
01784 SDValue
01785 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
01786   switch (Op.getOpcode()) {
01787   case ISD::RETURNADDR:
01788     return SDValue();
01789   case ISD::FRAMEADDR:
01790     return SDValue();
01791   case ISD::GlobalAddress:
01792     return LowerGlobalAddress(Op, DAG);
01793   case ISD::INTRINSIC_W_CHAIN:
01794     return Op;
01795   case ISD::BUILD_VECTOR:
01796   case ISD::EXTRACT_SUBVECTOR:
01797     return Op;
01798   case ISD::CONCAT_VECTORS:
01799     return LowerCONCAT_VECTORS(Op, DAG);
01800   case ISD::STORE:
01801     return LowerSTORE(Op, DAG);
01802   case ISD::LOAD:
01803     return LowerLOAD(Op, DAG);
01804   case ISD::SHL_PARTS:
01805     return LowerShiftLeftParts(Op, DAG);
01806   case ISD::SRA_PARTS:
01807   case ISD::SRL_PARTS:
01808     return LowerShiftRightParts(Op, DAG);
01809   case ISD::SELECT:
01810     return LowerSelect(Op, DAG);
01811   default:
01812     llvm_unreachable("Custom lowering not defined for operation");
01813   }
01814 }
01815 
01816 SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
01817   SDValue Op0 = Op->getOperand(0);
01818   SDValue Op1 = Op->getOperand(1);
01819   SDValue Op2 = Op->getOperand(2);
01820   SDLoc DL(Op.getNode());
01821 
01822   assert(Op.getValueType() == MVT::i1 && "Custom lowering enabled only for i1");
01823 
01824   Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
01825   Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
01826   SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
01827   SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select);
01828 
01829   return Trunc;
01830 }
01831 
01832 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
01833   if (Op.getValueType() == MVT::i1)
01834     return LowerLOADi1(Op, DAG);
01835   else
01836     return SDValue();
01837 }
01838 
01839 // v = ld i1* addr
01840 //   =>
01841 // v1 = ld i8* addr (-> i16)
01842 // v = trunc i16 to i1
01843 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
01844   SDNode *Node = Op.getNode();
01845   LoadSDNode *LD = cast<LoadSDNode>(Node);
01846   SDLoc dl(Node);
01847   assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
01848   assert(Node->getValueType(0) == MVT::i1 &&
01849          "Custom lowering for i1 load only");
01850   SDValue newLD =
01851       DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
01852                   LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
01853                   LD->isInvariant(), LD->getAlignment());
01854   SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
01855   // The legalizer (the caller) is expecting two values from the legalized
01856   // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
01857   // in LegalizeDAG.cpp which also uses MergeValues.
01858   SDValue Ops[] = { result, LD->getChain() };
01859   return DAG.getMergeValues(Ops, dl);
01860 }
01861 
01862 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
01863   EVT ValVT = Op.getOperand(1).getValueType();
01864   if (ValVT == MVT::i1)
01865     return LowerSTOREi1(Op, DAG);
01866   else if (ValVT.isVector())
01867     return LowerSTOREVector(Op, DAG);
01868   else
01869     return SDValue();
01870 }
01871 
01872 SDValue
01873 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
01874   SDNode *N = Op.getNode();
01875   SDValue Val = N->getOperand(1);
01876   SDLoc DL(N);
01877   EVT ValVT = Val.getValueType();
01878 
01879   if (ValVT.isVector()) {
01880     // We only handle "native" vector sizes for now, e.g. <4 x double> is not
01881     // legal.  We can (and should) split that into 2 stores of <2 x double> here
01882     // but I'm leaving that as a TODO for now.
01883     if (!ValVT.isSimple())
01884       return SDValue();
01885     switch (ValVT.getSimpleVT().SimpleTy) {
01886     default:
01887       return SDValue();
01888     case MVT::v2i8:
01889     case MVT::v2i16:
01890     case MVT::v2i32:
01891     case MVT::v2i64:
01892     case MVT::v2f32:
01893     case MVT::v2f64:
01894     case MVT::v4i8:
01895     case MVT::v4i16:
01896     case MVT::v4i32:
01897     case MVT::v4f32:
01898       // This is a "native" vector type
01899       break;
01900     }
01901 
01902     MemSDNode *MemSD = cast<MemSDNode>(N);
01903     const DataLayout *TD = getDataLayout();
01904 
01905     unsigned Align = MemSD->getAlignment();
01906     unsigned PrefAlign =
01907       TD->getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
01908     if (Align < PrefAlign) {
01909       // This store is not sufficiently aligned, so bail out and let this vector
01910       // store be scalarized.  Note that we may still be able to emit smaller
01911       // vector stores.  For example, if we are storing a <4 x float> with an
01912       // alignment of 8, this check will fail but the legalizer will try again
01913       // with 2 x <2 x float>, which will succeed with an alignment of 8.
01914       return SDValue();
01915     }
01916 
01917     unsigned Opcode = 0;
01918     EVT EltVT = ValVT.getVectorElementType();
01919     unsigned NumElts = ValVT.getVectorNumElements();
01920 
01921     // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
01922     // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
01923     // stored type to i16 and propagate the "real" type as the memory type.
01924     bool NeedExt = false;
01925     if (EltVT.getSizeInBits() < 16)
01926       NeedExt = true;
01927 
01928     switch (NumElts) {
01929     default:
01930       return SDValue();
01931     case 2:
01932       Opcode = NVPTXISD::StoreV2;
01933       break;
01934     case 4: {
01935       Opcode = NVPTXISD::StoreV4;
01936       break;
01937     }
01938     }
01939 
01940     SmallVector<SDValue, 8> Ops;
01941 
01942     // First is the chain
01943     Ops.push_back(N->getOperand(0));
01944 
01945     // Then the split values
01946     for (unsigned i = 0; i < NumElts; ++i) {
01947       SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
01948                                    DAG.getIntPtrConstant(i));
01949       if (NeedExt)
01950         ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
01951       Ops.push_back(ExtVal);
01952     }
01953 
01954     // Then any remaining arguments
01955     for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
01956       Ops.push_back(N->getOperand(i));
01957     }
01958 
01959     SDValue NewSt = DAG.getMemIntrinsicNode(
01960         Opcode, DL, DAG.getVTList(MVT::Other), Ops,
01961         MemSD->getMemoryVT(), MemSD->getMemOperand());
01962 
01963     //return DCI.CombineTo(N, NewSt, true);
01964     return NewSt;
01965   }
01966 
01967   return SDValue();
01968 }
01969 
01970 // st i1 v, addr
01971 //    =>
01972 // v1 = zxt v to i16
01973 // st.u8 i16, addr
01974 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
01975   SDNode *Node = Op.getNode();
01976   SDLoc dl(Node);
01977   StoreSDNode *ST = cast<StoreSDNode>(Node);
01978   SDValue Tmp1 = ST->getChain();
01979   SDValue Tmp2 = ST->getBasePtr();
01980   SDValue Tmp3 = ST->getValue();
01981   assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
01982   unsigned Alignment = ST->getAlignment();
01983   bool isVolatile = ST->isVolatile();
01984   bool isNonTemporal = ST->isNonTemporal();
01985   Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
01986   SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
01987                                      ST->getPointerInfo(), MVT::i8, isNonTemporal,
01988                                      isVolatile, Alignment);
01989   return Result;
01990 }
01991 
01992 SDValue NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname,
01993                                         int idx, EVT v) const {
01994   std::string *name = nvTM->getManagedStrPool()->getManagedString(inname);
01995   std::stringstream suffix;
01996   suffix << idx;
01997   *name += suffix.str();
01998   return DAG.getTargetExternalSymbol(name->c_str(), v);
01999 }
02000 
02001 SDValue
02002 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
02003   std::string ParamSym;
02004   raw_string_ostream ParamStr(ParamSym);
02005 
02006   ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
02007   ParamStr.flush();
02008 
02009   std::string *SavedStr =
02010     nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
02011   return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
02012 }
02013 
02014 SDValue NVPTXTargetLowering::getParamHelpSymbol(SelectionDAG &DAG, int idx) {
02015   return getExtSymb(DAG, ".HLPPARAM", idx);
02016 }
02017 
02018 // Check to see if the kernel argument is image*_t or sampler_t
02019 
02020 bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
02021   static const char *const specialTypes[] = { "struct._image2d_t",
02022                                               "struct._image3d_t",
02023                                               "struct._sampler_t" };
02024 
02025   const Type *Ty = arg->getType();
02026   const PointerType *PTy = dyn_cast<PointerType>(Ty);
02027 
02028   if (!PTy)
02029     return false;
02030 
02031   if (!context)
02032     return false;
02033 
02034   const StructType *STy = dyn_cast<StructType>(PTy->getElementType());
02035   const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
02036 
02037   for (int i = 0, e = array_lengthof(specialTypes); i != e; ++i)
02038     if (TypeName == specialTypes[i])
02039       return true;
02040 
02041   return false;
02042 }
02043 
02044 SDValue NVPTXTargetLowering::LowerFormalArguments(
02045     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
02046     const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
02047     SmallVectorImpl<SDValue> &InVals) const {
02048   MachineFunction &MF = DAG.getMachineFunction();
02049   const DataLayout *TD = getDataLayout();
02050 
02051   const Function *F = MF.getFunction();
02052   const AttributeSet &PAL = F->getAttributes();
02053   const TargetLowering *TLI = STI.getTargetLowering();
02054 
02055   SDValue Root = DAG.getRoot();
02056   std::vector<SDValue> OutChains;
02057 
02058   bool isKernel = llvm::isKernelFunction(*F);
02059   bool isABI = (STI.getSmVersion() >= 20);
02060   assert(isABI && "Non-ABI compilation is not supported");
02061   if (!isABI)
02062     return Chain;
02063 
02064   std::vector<Type *> argTypes;
02065   std::vector<const Argument *> theArgs;
02066   for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
02067        I != E; ++I) {
02068     theArgs.push_back(I);
02069     argTypes.push_back(I->getType());
02070   }
02071   // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
02072   // Ins.size() will be larger
02073   //   * if there is an aggregate argument with multiple fields (each field
02074   //     showing up separately in Ins)
02075   //   * if there is a vector argument with more than typical vector-length
02076   //     elements (generally if more than 4) where each vector element is
02077   //     individually present in Ins.
02078   // So a different index should be used for indexing into Ins.
02079   // See similar issue in LowerCall.
02080   unsigned InsIdx = 0;
02081 
02082   int idx = 0;
02083   for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
02084     Type *Ty = argTypes[i];
02085 
02086     // If the kernel argument is image*_t or sampler_t, convert it to
02087     // a i32 constant holding the parameter position. This can later
02088     // matched in the AsmPrinter to output the correct mangled name.
02089     if (isImageOrSamplerVal(
02090             theArgs[i],
02091             (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
02092                                      : nullptr))) {
02093       assert(isKernel && "Only kernels can have image/sampler params");
02094       InVals.push_back(DAG.getConstant(i + 1, MVT::i32));
02095       continue;
02096     }
02097 
02098     if (theArgs[i]->use_empty()) {
02099       // argument is dead
02100       if (Ty->isAggregateType()) {
02101         SmallVector<EVT, 16> vtparts;
02102 
02103         ComputePTXValueVTs(*this, Ty, vtparts);
02104         assert(vtparts.size() > 0 && "empty aggregate type not expected");
02105         for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
02106              ++parti) {
02107           InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
02108           ++InsIdx;
02109         }
02110         if (vtparts.size() > 0)
02111           --InsIdx;
02112         continue;
02113       }
02114       if (Ty->isVectorTy()) {
02115         EVT ObjectVT = getValueType(Ty);
02116         unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
02117         for (unsigned parti = 0; parti < NumRegs; ++parti) {
02118           InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
02119           ++InsIdx;
02120         }
02121         if (NumRegs > 0)
02122           --InsIdx;
02123         continue;
02124       }
02125       InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
02126       continue;
02127     }
02128 
02129     // In the following cases, assign a node order of "idx+1"
02130     // to newly created nodes. The SDNodes for params have to
02131     // appear in the same order as their order of appearance
02132     // in the original function. "idx+1" holds that order.
02133     if (PAL.hasAttribute(i + 1, Attribute::ByVal) == false) {
02134       if (Ty->isAggregateType()) {
02135         SmallVector<EVT, 16> vtparts;
02136         SmallVector<uint64_t, 16> offsets;
02137 
02138         // NOTE: Here, we lose the ability to issue vector loads for vectors
02139         // that are a part of a struct.  This should be investigated in the
02140         // future.
02141         ComputePTXValueVTs(*this, Ty, vtparts, &offsets, 0);
02142         assert(vtparts.size() > 0 && "empty aggregate type not expected");
02143         bool aggregateIsPacked = false;
02144         if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
02145           aggregateIsPacked = STy->isPacked();
02146 
02147         SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
02148         for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
02149              ++parti) {
02150           EVT partVT = vtparts[parti];
02151           Value *srcValue = Constant::getNullValue(
02152               PointerType::get(partVT.getTypeForEVT(F->getContext()),
02153                                llvm::ADDRESS_SPACE_PARAM));
02154           SDValue srcAddr =
02155               DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
02156                           DAG.getConstant(offsets[parti], getPointerTy()));
02157           unsigned partAlign =
02158               aggregateIsPacked ? 1
02159                                 : TD->getABITypeAlignment(
02160                                       partVT.getTypeForEVT(F->getContext()));
02161           SDValue p;
02162           if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
02163             ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? 
02164                                      ISD::SEXTLOAD : ISD::ZEXTLOAD;
02165             p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
02166                                MachinePointerInfo(srcValue), partVT, false,
02167                                false, false, partAlign);
02168           } else {
02169             p = DAG.getLoad(partVT, dl, Root, srcAddr,
02170                             MachinePointerInfo(srcValue), false, false, false,
02171                             partAlign);
02172           }
02173           if (p.getNode())
02174             p.getNode()->setIROrder(idx + 1);
02175           InVals.push_back(p);
02176           ++InsIdx;
02177         }
02178         if (vtparts.size() > 0)
02179           --InsIdx;
02180         continue;
02181       }
02182       if (Ty->isVectorTy()) {
02183         EVT ObjectVT = getValueType(Ty);
02184         SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
02185         unsigned NumElts = ObjectVT.getVectorNumElements();
02186         assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
02187                "Vector was not scalarized");
02188         EVT EltVT = ObjectVT.getVectorElementType();
02189 
02190         // V1 load
02191         // f32 = load ...
02192         if (NumElts == 1) {
02193           // We only have one element, so just directly load it
02194           Value *SrcValue = Constant::getNullValue(PointerType::get(
02195               EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
02196           SDValue P = DAG.getLoad(
02197               EltVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false,
02198               false, true,
02199               TD->getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
02200           if (P.getNode())
02201             P.getNode()->setIROrder(idx + 1);
02202 
02203           if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
02204             P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
02205           InVals.push_back(P);
02206           ++InsIdx;
02207         } else if (NumElts == 2) {
02208           // V2 load
02209           // f32,f32 = load ...
02210           EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
02211           Value *SrcValue = Constant::getNullValue(PointerType::get(
02212               VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
02213           SDValue P = DAG.getLoad(
02214               VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false,
02215               false, true,
02216               TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
02217           if (P.getNode())
02218             P.getNode()->setIROrder(idx + 1);
02219 
02220           SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
02221                                      DAG.getIntPtrConstant(0));
02222           SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
02223                                      DAG.getIntPtrConstant(1));
02224 
02225           if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
02226             Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
02227             Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
02228           }
02229 
02230           InVals.push_back(Elt0);
02231           InVals.push_back(Elt1);
02232           InsIdx += 2;
02233         } else {
02234           // V4 loads
02235           // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
02236           // the
02237           // vector will be expanded to a power of 2 elements, so we know we can
02238           // always round up to the next multiple of 4 when creating the vector
02239           // loads.
02240           // e.g.  4 elem => 1 ld.v4
02241           //       6 elem => 2 ld.v4
02242           //       8 elem => 2 ld.v4
02243           //      11 elem => 3 ld.v4
02244           unsigned VecSize = 4;
02245           if (EltVT.getSizeInBits() == 64) {
02246             VecSize = 2;
02247           }
02248           EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
02249           unsigned Ofst = 0;
02250           for (unsigned i = 0; i < NumElts; i += VecSize) {
02251             Value *SrcValue = Constant::getNullValue(
02252                 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
02253                                  llvm::ADDRESS_SPACE_PARAM));
02254             SDValue SrcAddr =
02255                 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
02256                             DAG.getConstant(Ofst, getPointerTy()));
02257             SDValue P = DAG.getLoad(
02258                 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
02259                 false, true,
02260                 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
02261             if (P.getNode())
02262               P.getNode()->setIROrder(idx + 1);
02263 
02264             for (unsigned j = 0; j < VecSize; ++j) {
02265               if (i + j >= NumElts)
02266                 break;
02267               SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
02268                                         DAG.getIntPtrConstant(j));
02269               if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
02270                 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
02271               InVals.push_back(Elt);
02272             }
02273             Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
02274           }
02275           InsIdx += NumElts;
02276         }
02277 
02278         if (NumElts > 0)
02279           --InsIdx;
02280         continue;
02281       }
02282       // A plain scalar.
02283       EVT ObjectVT = getValueType(Ty);
02284       // If ABI, load from the param symbol
02285       SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
02286       Value *srcValue = Constant::getNullValue(PointerType::get(
02287           ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
02288       SDValue p;
02289        if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
02290         ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? 
02291                                        ISD::SEXTLOAD : ISD::ZEXTLOAD;
02292         p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg,
02293                            MachinePointerInfo(srcValue), ObjectVT, false, false,
02294                            false,
02295         TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
02296       } else {
02297         p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg,
02298                         MachinePointerInfo(srcValue), false, false, false,
02299         TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
02300       }
02301       if (p.getNode())
02302         p.getNode()->setIROrder(idx + 1);
02303       InVals.push_back(p);
02304       continue;
02305     }
02306 
02307     // Param has ByVal attribute
02308     // Return MoveParam(param symbol).
02309     // Ideally, the param symbol can be returned directly,
02310     // but when SDNode builder decides to use it in a CopyToReg(),
02311     // machine instruction fails because TargetExternalSymbol
02312     // (not lowered) is target dependent, and CopyToReg assumes
02313     // the source is lowered.
02314     EVT ObjectVT = getValueType(Ty);
02315     assert(ObjectVT == Ins[InsIdx].VT &&
02316            "Ins type did not match function type");
02317     SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
02318     SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
02319     if (p.getNode())
02320       p.getNode()->setIROrder(idx + 1);
02321     if (isKernel)
02322       InVals.push_back(p);
02323     else {
02324       SDValue p2 = DAG.getNode(
02325           ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
02326           DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, MVT::i32), p);
02327       InVals.push_back(p2);
02328     }
02329   }
02330 
02331   // Clang will check explicit VarArg and issue error if any. However, Clang
02332   // will let code with
02333   // implicit var arg like f() pass. See bug 617733.
02334   // We treat this case as if the arg list is empty.
02335   // if (F.isVarArg()) {
02336   // assert(0 && "VarArg not supported yet!");
02337   //}
02338 
02339   if (!OutChains.empty())
02340     DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
02341 
02342   return Chain;
02343 }
02344 
02345 
02346 SDValue
02347 NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
02348                                  bool isVarArg,
02349                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
02350                                  const SmallVectorImpl<SDValue> &OutVals,
02351                                  SDLoc dl, SelectionDAG &DAG) const {
02352   MachineFunction &MF = DAG.getMachineFunction();
02353   const Function *F = MF.getFunction();
02354   Type *RetTy = F->getReturnType();
02355   const DataLayout *TD = getDataLayout();
02356 
02357   bool isABI = (STI.getSmVersion() >= 20);
02358   assert(isABI && "Non-ABI compilation is not supported");
02359   if (!isABI)
02360     return Chain;
02361 
02362   if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
02363     // If we have a vector type, the OutVals array will be the scalarized
02364     // components and we have combine them into 1 or more vector stores.
02365     unsigned NumElts = VTy->getNumElements();
02366     assert(NumElts == Outs.size() && "Bad scalarization of return value");
02367 
02368     // const_cast can be removed in later LLVM versions
02369     EVT EltVT = getValueType(RetTy).getVectorElementType();
02370     bool NeedExtend = false;
02371     if (EltVT.getSizeInBits() < 16)
02372       NeedExtend = true;
02373 
02374     // V1 store
02375     if (NumElts == 1) {
02376       SDValue StoreVal = OutVals[0];
02377       // We only have one element, so just directly store it
02378       if (NeedExtend)
02379         StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
02380       SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal };
02381       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
02382                                       DAG.getVTList(MVT::Other), Ops,
02383                                       EltVT, MachinePointerInfo());
02384 
02385     } else if (NumElts == 2) {
02386       // V2 store
02387       SDValue StoreVal0 = OutVals[0];
02388       SDValue StoreVal1 = OutVals[1];
02389 
02390       if (NeedExtend) {
02391         StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
02392         StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
02393       }
02394 
02395       SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal0,
02396                         StoreVal1 };
02397       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
02398                                       DAG.getVTList(MVT::Other), Ops,
02399                                       EltVT, MachinePointerInfo());
02400     } else {
02401       // V4 stores
02402       // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
02403       // vector will be expanded to a power of 2 elements, so we know we can
02404       // always round up to the next multiple of 4 when creating the vector
02405       // stores.
02406       // e.g.  4 elem => 1 st.v4
02407       //       6 elem => 2 st.v4
02408       //       8 elem => 2 st.v4
02409       //      11 elem => 3 st.v4
02410 
02411       unsigned VecSize = 4;
02412       if (OutVals[0].getValueType().getSizeInBits() == 64)
02413         VecSize = 2;
02414 
02415       unsigned Offset = 0;
02416 
02417       EVT VecVT =
02418           EVT::getVectorVT(F->getContext(), EltVT, VecSize);
02419       unsigned PerStoreOffset =
02420           TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
02421 
02422       for (unsigned i = 0; i < NumElts; i += VecSize) {
02423         // Get values
02424         SDValue StoreVal;
02425         SmallVector<SDValue, 8> Ops;
02426         Ops.push_back(Chain);
02427         Ops.push_back(DAG.getConstant(Offset, MVT::i32));
02428         unsigned Opc = NVPTXISD::StoreRetvalV2;
02429         EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
02430 
02431         StoreVal = OutVals[i];
02432         if (NeedExtend)
02433           StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
02434         Ops.push_back(StoreVal);
02435 
02436         if (i + 1 < NumElts) {
02437           StoreVal = OutVals[i + 1];
02438           if (NeedExtend)
02439             StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
02440         } else {
02441           StoreVal = DAG.getUNDEF(ExtendedVT);
02442         }
02443         Ops.push_back(StoreVal);
02444 
02445         if (VecSize == 4) {
02446           Opc = NVPTXISD::StoreRetvalV4;
02447           if (i + 2 < NumElts) {
02448             StoreVal = OutVals[i + 2];
02449             if (NeedExtend)
02450               StoreVal =
02451                   DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
02452           } else {
02453             StoreVal = DAG.getUNDEF(ExtendedVT);
02454           }
02455           Ops.push_back(StoreVal);
02456 
02457           if (i + 3 < NumElts) {
02458             StoreVal = OutVals[i + 3];
02459             if (NeedExtend)
02460               StoreVal =
02461                   DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
02462           } else {
02463             StoreVal = DAG.getUNDEF(ExtendedVT);
02464           }
02465           Ops.push_back(StoreVal);
02466         }
02467 
02468         // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
02469         Chain =
02470             DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
02471                                     EltVT, MachinePointerInfo());
02472         Offset += PerStoreOffset;
02473       }
02474     }
02475   } else {
02476     SmallVector<EVT, 16> ValVTs;
02477     SmallVector<uint64_t, 16> Offsets;
02478     ComputePTXValueVTs(*this, RetTy, ValVTs, &Offsets, 0);
02479     assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
02480 
02481     for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
02482       SDValue theVal = OutVals[i];
02483       EVT TheValType = theVal.getValueType();
02484       unsigned numElems = 1;
02485       if (TheValType.isVector())
02486         numElems = TheValType.getVectorNumElements();
02487       for (unsigned j = 0, je = numElems; j != je; ++j) {
02488         SDValue TmpVal = theVal;
02489         if (TheValType.isVector())
02490           TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
02491                                TheValType.getVectorElementType(), TmpVal,
02492                                DAG.getIntPtrConstant(j));
02493         EVT TheStoreType = ValVTs[i];
02494         if (RetTy->isIntegerTy() &&
02495             TD->getTypeAllocSizeInBits(RetTy) < 32) {
02496           // The following zero-extension is for integer types only, and
02497           // specifically not for aggregates.
02498           TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
02499           TheStoreType = MVT::i32;
02500         }
02501         else if (TmpVal.getValueType().getSizeInBits() < 16)
02502           TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
02503 
02504         SDValue Ops[] = {
02505           Chain,
02506           DAG.getConstant(Offsets[i], MVT::i32),
02507           TmpVal };
02508         Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
02509                                         DAG.getVTList(MVT::Other), Ops,
02510                                         TheStoreType,
02511                                         MachinePointerInfo());
02512       }
02513     }
02514   }
02515 
02516   return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
02517 }
02518 
02519 
02520 void NVPTXTargetLowering::LowerAsmOperandForConstraint(
02521     SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
02522     SelectionDAG &DAG) const {
02523   if (Constraint.length() > 1)
02524     return;
02525   else
02526     TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
02527 }
02528 
02529 // NVPTX suuport vector of legal types of any length in Intrinsics because the
02530 // NVPTX specific type legalizer
02531 // will legalize them to the PTX supported length.
02532 bool NVPTXTargetLowering::isTypeSupportedInIntrinsic(MVT VT) const {
02533   if (isTypeLegal(VT))
02534     return true;
02535   if (VT.isVector()) {
02536     MVT eVT = VT.getVectorElementType();
02537     if (isTypeLegal(eVT))
02538       return true;
02539   }
02540   return false;
02541 }
02542 
02543 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
02544   switch (Intrinsic) {
02545   default:
02546     return 0;
02547 
02548   case Intrinsic::nvvm_tex_1d_v4f32_s32:
02549     return NVPTXISD::Tex1DFloatS32;
02550   case Intrinsic::nvvm_tex_1d_v4f32_f32:
02551     return NVPTXISD::Tex1DFloatFloat;
02552   case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
02553     return NVPTXISD::Tex1DFloatFloatLevel;
02554   case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
02555     return NVPTXISD::Tex1DFloatFloatGrad;
02556   case Intrinsic::nvvm_tex_1d_v4s32_s32:
02557     return NVPTXISD::Tex1DS32S32;
02558   case Intrinsic::nvvm_tex_1d_v4s32_f32:
02559     return NVPTXISD::Tex1DS32Float;
02560   case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
02561     return NVPTXISD::Tex1DS32FloatLevel;
02562   case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
02563     return NVPTXISD::Tex1DS32FloatGrad;
02564   case Intrinsic::nvvm_tex_1d_v4u32_s32:
02565     return NVPTXISD::Tex1DU32S32;
02566   case Intrinsic::nvvm_tex_1d_v4u32_f32:
02567     return NVPTXISD::Tex1DU32Float;
02568   case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
02569     return NVPTXISD::Tex1DU32FloatLevel;
02570   case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
02571     return NVPTXISD::Tex1DU32FloatGrad;
02572 
02573   case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
02574     return NVPTXISD::Tex1DArrayFloatS32;
02575   case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
02576     return NVPTXISD::Tex1DArrayFloatFloat;
02577   case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
02578     return NVPTXISD::Tex1DArrayFloatFloatLevel;
02579   case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
02580     return NVPTXISD::Tex1DArrayFloatFloatGrad;
02581   case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
02582     return NVPTXISD::Tex1DArrayS32S32;
02583   case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
02584     return NVPTXISD::Tex1DArrayS32Float;
02585   case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
02586     return NVPTXISD::Tex1DArrayS32FloatLevel;
02587   case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
02588     return NVPTXISD::Tex1DArrayS32FloatGrad;
02589   case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
02590     return NVPTXISD::Tex1DArrayU32S32;
02591   case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
02592     return NVPTXISD::Tex1DArrayU32Float;
02593   case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
02594     return NVPTXISD::Tex1DArrayU32FloatLevel;
02595   case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
02596     return NVPTXISD::Tex1DArrayU32FloatGrad;
02597 
02598   case Intrinsic::nvvm_tex_2d_v4f32_s32:
02599     return NVPTXISD::Tex2DFloatS32;
02600   case Intrinsic::nvvm_tex_2d_v4f32_f32:
02601     return NVPTXISD::Tex2DFloatFloat;
02602   case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
02603     return NVPTXISD::Tex2DFloatFloatLevel;
02604   case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
02605     return NVPTXISD::Tex2DFloatFloatGrad;
02606   case Intrinsic::nvvm_tex_2d_v4s32_s32:
02607     return NVPTXISD::Tex2DS32S32;
02608   case Intrinsic::nvvm_tex_2d_v4s32_f32:
02609     return NVPTXISD::Tex2DS32Float;
02610   case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
02611     return NVPTXISD::Tex2DS32FloatLevel;
02612   case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
02613     return NVPTXISD::Tex2DS32FloatGrad;
02614   case Intrinsic::nvvm_tex_2d_v4u32_s32:
02615     return NVPTXISD::Tex2DU32S32;
02616   case Intrinsic::nvvm_tex_2d_v4u32_f32:
02617     return NVPTXISD::Tex2DU32Float;
02618   case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
02619     return NVPTXISD::Tex2DU32FloatLevel;
02620   case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
02621     return NVPTXISD::Tex2DU32FloatGrad;
02622 
02623   case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
02624     return NVPTXISD::Tex2DArrayFloatS32;
02625   case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
02626     return NVPTXISD::Tex2DArrayFloatFloat;
02627   case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
02628     return NVPTXISD::Tex2DArrayFloatFloatLevel;
02629   case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
02630     return NVPTXISD::Tex2DArrayFloatFloatGrad;
02631   case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
02632     return NVPTXISD::Tex2DArrayS32S32;
02633   case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
02634     return NVPTXISD::Tex2DArrayS32Float;
02635   case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
02636     return NVPTXISD::Tex2DArrayS32FloatLevel;
02637   case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
02638     return NVPTXISD::Tex2DArrayS32FloatGrad;
02639   case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
02640     return NVPTXISD::Tex2DArrayU32S32;
02641   case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
02642     return NVPTXISD::Tex2DArrayU32Float;
02643   case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
02644     return NVPTXISD::Tex2DArrayU32FloatLevel;
02645   case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
02646     return NVPTXISD::Tex2DArrayU32FloatGrad;
02647 
02648   case Intrinsic::nvvm_tex_3d_v4f32_s32:
02649     return NVPTXISD::Tex3DFloatS32;
02650   case Intrinsic::nvvm_tex_3d_v4f32_f32:
02651     return NVPTXISD::Tex3DFloatFloat;
02652   case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
02653     return NVPTXISD::Tex3DFloatFloatLevel;
02654   case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
02655     return NVPTXISD::Tex3DFloatFloatGrad;
02656   case Intrinsic::nvvm_tex_3d_v4s32_s32:
02657     return NVPTXISD::Tex3DS32S32;
02658   case Intrinsic::nvvm_tex_3d_v4s32_f32:
02659     return NVPTXISD::Tex3DS32Float;
02660   case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
02661     return NVPTXISD::Tex3DS32FloatLevel;
02662   case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
02663     return NVPTXISD::Tex3DS32FloatGrad;
02664   case Intrinsic::nvvm_tex_3d_v4u32_s32:
02665     return NVPTXISD::Tex3DU32S32;
02666   case Intrinsic::nvvm_tex_3d_v4u32_f32:
02667     return NVPTXISD::Tex3DU32Float;
02668   case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
02669     return NVPTXISD::Tex3DU32FloatLevel;
02670   case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
02671     return NVPTXISD::Tex3DU32FloatGrad;
02672 
02673   case Intrinsic::nvvm_tex_cube_v4f32_f32:
02674     return NVPTXISD::TexCubeFloatFloat;
02675   case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
02676     return NVPTXISD::TexCubeFloatFloatLevel;
02677   case Intrinsic::nvvm_tex_cube_v4s32_f32:
02678     return NVPTXISD::TexCubeS32Float;
02679   case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
02680     return NVPTXISD::TexCubeS32FloatLevel;
02681   case Intrinsic::nvvm_tex_cube_v4u32_f32:
02682     return NVPTXISD::TexCubeU32Float;
02683   case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
02684     return NVPTXISD::TexCubeU32FloatLevel;
02685 
02686   case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
02687     return NVPTXISD::TexCubeArrayFloatFloat;
02688   case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
02689     return NVPTXISD::TexCubeArrayFloatFloatLevel;
02690   case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
02691     return NVPTXISD::TexCubeArrayS32Float;
02692   case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
02693     return NVPTXISD::TexCubeArrayS32FloatLevel;
02694   case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
02695     return NVPTXISD::TexCubeArrayU32Float;
02696   case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
02697     return NVPTXISD::TexCubeArrayU32FloatLevel;
02698 
02699   case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
02700     return NVPTXISD::Tld4R2DFloatFloat;
02701   case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
02702     return NVPTXISD::Tld4G2DFloatFloat;
02703   case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
02704     return NVPTXISD::Tld4B2DFloatFloat;
02705   case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
02706     return NVPTXISD::Tld4A2DFloatFloat;
02707   case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
02708     return NVPTXISD::Tld4R2DS64Float;
02709   case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
02710     return NVPTXISD::Tld4G2DS64Float;
02711   case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
02712     return NVPTXISD::Tld4B2DS64Float;
02713   case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
02714     return NVPTXISD::Tld4A2DS64Float;
02715   case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
02716     return NVPTXISD::Tld4R2DU64Float;
02717   case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
02718     return NVPTXISD::Tld4G2DU64Float;
02719   case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
02720     return NVPTXISD::Tld4B2DU64Float;
02721   case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
02722     return NVPTXISD::Tld4A2DU64Float;
02723 
02724   case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
02725     return NVPTXISD::TexUnified1DFloatS32;
02726   case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
02727     return NVPTXISD::TexUnified1DFloatFloat;
02728   case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
02729     return NVPTXISD::TexUnified1DFloatFloatLevel;
02730   case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
02731     return NVPTXISD::TexUnified1DFloatFloatGrad;
02732   case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
02733     return NVPTXISD::TexUnified1DS32S32;
02734   case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
02735     return NVPTXISD::TexUnified1DS32Float;
02736   case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
02737     return NVPTXISD::TexUnified1DS32FloatLevel;
02738   case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
02739     return NVPTXISD::TexUnified1DS32FloatGrad;
02740   case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
02741     return NVPTXISD::TexUnified1DU32S32;
02742   case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
02743     return NVPTXISD::TexUnified1DU32Float;
02744   case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
02745     return NVPTXISD::TexUnified1DU32FloatLevel;
02746   case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
02747     return NVPTXISD::TexUnified1DU32FloatGrad;
02748 
02749   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
02750     return NVPTXISD::TexUnified1DArrayFloatS32;
02751   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
02752     return NVPTXISD::TexUnified1DArrayFloatFloat;
02753   case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
02754     return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
02755   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
02756     return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
02757   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
02758     return NVPTXISD::TexUnified1DArrayS32S32;
02759   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
02760     return NVPTXISD::TexUnified1DArrayS32Float;
02761   case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
02762     return NVPTXISD::TexUnified1DArrayS32FloatLevel;
02763   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
02764     return NVPTXISD::TexUnified1DArrayS32FloatGrad;
02765   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
02766     return NVPTXISD::TexUnified1DArrayU32S32;
02767   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
02768     return NVPTXISD::TexUnified1DArrayU32Float;
02769   case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
02770     return NVPTXISD::TexUnified1DArrayU32FloatLevel;
02771   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
02772     return NVPTXISD::TexUnified1DArrayU32FloatGrad;
02773 
02774   case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
02775     return NVPTXISD::TexUnified2DFloatS32;
02776   case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
02777     return NVPTXISD::TexUnified2DFloatFloat;
02778   case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
02779     return NVPTXISD::TexUnified2DFloatFloatLevel;
02780   case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
02781     return NVPTXISD::TexUnified2DFloatFloatGrad;
02782   case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
02783     return NVPTXISD::TexUnified2DS32S32;
02784   case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
02785     return NVPTXISD::TexUnified2DS32Float;
02786   case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
02787     return NVPTXISD::TexUnified2DS32FloatLevel;
02788   case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
02789     return NVPTXISD::TexUnified2DS32FloatGrad;
02790   case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
02791     return NVPTXISD::TexUnified2DU32S32;
02792   case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
02793     return NVPTXISD::TexUnified2DU32Float;
02794   case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
02795     return NVPTXISD::TexUnified2DU32FloatLevel;
02796   case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
02797     return NVPTXISD::TexUnified2DU32FloatGrad;
02798 
02799   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
02800     return NVPTXISD::TexUnified2DArrayFloatS32;
02801   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
02802     return NVPTXISD::TexUnified2DArrayFloatFloat;
02803   case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
02804     return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
02805   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
02806     return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
02807   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
02808     return NVPTXISD::TexUnified2DArrayS32S32;
02809   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
02810     return NVPTXISD::TexUnified2DArrayS32Float;
02811   case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
02812     return NVPTXISD::TexUnified2DArrayS32FloatLevel;
02813   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
02814     return NVPTXISD::TexUnified2DArrayS32FloatGrad;
02815   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
02816     return NVPTXISD::TexUnified2DArrayU32S32;
02817   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
02818     return NVPTXISD::TexUnified2DArrayU32Float;
02819   case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
02820     return NVPTXISD::TexUnified2DArrayU32FloatLevel;
02821   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
02822     return NVPTXISD::TexUnified2DArrayU32FloatGrad;
02823 
02824   case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
02825     return NVPTXISD::TexUnified3DFloatS32;
02826   case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
02827     return NVPTXISD::TexUnified3DFloatFloat;
02828   case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
02829     return NVPTXISD::TexUnified3DFloatFloatLevel;
02830   case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
02831     return NVPTXISD::TexUnified3DFloatFloatGrad;
02832   case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
02833     return NVPTXISD::TexUnified3DS32S32;
02834   case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
02835     return NVPTXISD::TexUnified3DS32Float;
02836   case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
02837     return NVPTXISD::TexUnified3DS32FloatLevel;
02838   case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
02839     return NVPTXISD::TexUnified3DS32FloatGrad;
02840   case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
02841     return NVPTXISD::TexUnified3DU32S32;
02842   case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
02843     return NVPTXISD::TexUnified3DU32Float;
02844   case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
02845     return NVPTXISD::TexUnified3DU32FloatLevel;
02846   case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
02847     return NVPTXISD::TexUnified3DU32FloatGrad;
02848 
02849   case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
02850     return NVPTXISD::TexUnifiedCubeFloatFloat;
02851   case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
02852     return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
02853   case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
02854     return NVPTXISD::TexUnifiedCubeS32Float;
02855   case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
02856     return NVPTXISD::TexUnifiedCubeS32FloatLevel;
02857   case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
02858     return NVPTXISD::TexUnifiedCubeU32Float;
02859   case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
02860     return NVPTXISD::TexUnifiedCubeU32FloatLevel;
02861 
02862   case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
02863     return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
02864   case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
02865     return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
02866   case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
02867     return NVPTXISD::TexUnifiedCubeArrayS32Float;
02868   case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
02869     return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
02870   case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
02871     return NVPTXISD::TexUnifiedCubeArrayU32Float;
02872   case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
02873     return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
02874 
02875   case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
02876     return NVPTXISD::Tld4UnifiedR2DFloatFloat;
02877   case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
02878     return NVPTXISD::Tld4UnifiedG2DFloatFloat;
02879   case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
02880     return NVPTXISD::Tld4UnifiedB2DFloatFloat;
02881   case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
02882     return NVPTXISD::Tld4UnifiedA2DFloatFloat;
02883   case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
02884     return NVPTXISD::Tld4UnifiedR2DS64Float;
02885   case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
02886     return NVPTXISD::Tld4UnifiedG2DS64Float;
02887   case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
02888     return NVPTXISD::Tld4UnifiedB2DS64Float;
02889   case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
02890     return NVPTXISD::Tld4UnifiedA2DS64Float;
02891   case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
02892     return NVPTXISD::Tld4UnifiedR2DU64Float;
02893   case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
02894     return NVPTXISD::Tld4UnifiedG2DU64Float;
02895   case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
02896     return NVPTXISD::Tld4UnifiedB2DU64Float;
02897   case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
02898     return NVPTXISD::Tld4UnifiedA2DU64Float;
02899   }
02900 }
02901 
02902 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
02903   switch (Intrinsic) {
02904   default:
02905     return 0;
02906   case Intrinsic::nvvm_suld_1d_i8_clamp:
02907     return NVPTXISD::Suld1DI8Clamp;
02908   case Intrinsic::nvvm_suld_1d_i16_clamp:
02909     return NVPTXISD::Suld1DI16Clamp;
02910   case Intrinsic::nvvm_suld_1d_i32_clamp:
02911     return NVPTXISD::Suld1DI32Clamp;
02912   case Intrinsic::nvvm_suld_1d_i64_clamp:
02913     return NVPTXISD::Suld1DI64Clamp;
02914   case Intrinsic::nvvm_suld_1d_v2i8_clamp:
02915     return NVPTXISD::Suld1DV2I8Clamp;
02916   case Intrinsic::nvvm_suld_1d_v2i16_clamp:
02917     return NVPTXISD::Suld1DV2I16Clamp;
02918   case Intrinsic::nvvm_suld_1d_v2i32_clamp:
02919     return NVPTXISD::Suld1DV2I32Clamp;
02920   case Intrinsic::nvvm_suld_1d_v2i64_clamp:
02921     return NVPTXISD::Suld1DV2I64Clamp;
02922   case Intrinsic::nvvm_suld_1d_v4i8_clamp:
02923     return NVPTXISD::Suld1DV4I8Clamp;
02924   case Intrinsic::nvvm_suld_1d_v4i16_clamp:
02925     return NVPTXISD::Suld1DV4I16Clamp;
02926   case Intrinsic::nvvm_suld_1d_v4i32_clamp:
02927     return NVPTXISD::Suld1DV4I32Clamp;
02928   case Intrinsic::nvvm_suld_1d_array_i8_clamp:
02929     return NVPTXISD::Suld1DArrayI8Clamp;
02930   case Intrinsic::nvvm_suld_1d_array_i16_clamp:
02931     return NVPTXISD::Suld1DArrayI16Clamp;
02932   case Intrinsic::nvvm_suld_1d_array_i32_clamp:
02933     return NVPTXISD::Suld1DArrayI32Clamp;
02934   case Intrinsic::nvvm_suld_1d_array_i64_clamp:
02935     return NVPTXISD::Suld1DArrayI64Clamp;
02936   case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
02937     return NVPTXISD::Suld1DArrayV2I8Clamp;
02938   case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
02939     return NVPTXISD::Suld1DArrayV2I16Clamp;
02940   case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
02941     return NVPTXISD::Suld1DArrayV2I32Clamp;
02942   case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
02943     return NVPTXISD::Suld1DArrayV2I64Clamp;
02944   case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
02945     return NVPTXISD::Suld1DArrayV4I8Clamp;
02946   case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
02947     return NVPTXISD::Suld1DArrayV4I16Clamp;
02948   case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
02949     return NVPTXISD::Suld1DArrayV4I32Clamp;
02950   case Intrinsic::nvvm_suld_2d_i8_clamp:
02951     return NVPTXISD::Suld2DI8Clamp;
02952   case Intrinsic::nvvm_suld_2d_i16_clamp:
02953     return NVPTXISD::Suld2DI16Clamp;
02954   case Intrinsic::nvvm_suld_2d_i32_clamp:
02955     return NVPTXISD::Suld2DI32Clamp;
02956   case Intrinsic::nvvm_suld_2d_i64_clamp:
02957     return NVPTXISD::Suld2DI64Clamp;
02958   case Intrinsic::nvvm_suld_2d_v2i8_clamp:
02959     return NVPTXISD::Suld2DV2I8Clamp;
02960   case Intrinsic::nvvm_suld_2d_v2i16_clamp:
02961     return NVPTXISD::Suld2DV2I16Clamp;
02962   case Intrinsic::nvvm_suld_2d_v2i32_clamp:
02963     return NVPTXISD::Suld2DV2I32Clamp;
02964   case Intrinsic::nvvm_suld_2d_v2i64_clamp:
02965     return NVPTXISD::Suld2DV2I64Clamp;
02966   case Intrinsic::nvvm_suld_2d_v4i8_clamp:
02967     return NVPTXISD::Suld2DV4I8Clamp;
02968   case Intrinsic::nvvm_suld_2d_v4i16_clamp:
02969     return NVPTXISD::Suld2DV4I16Clamp;
02970   case Intrinsic::nvvm_suld_2d_v4i32_clamp:
02971     return NVPTXISD::Suld2DV4I32Clamp;
02972   case Intrinsic::nvvm_suld_2d_array_i8_clamp:
02973     return NVPTXISD::Suld2DArrayI8Clamp;
02974   case Intrinsic::nvvm_suld_2d_array_i16_clamp:
02975     return NVPTXISD::Suld2DArrayI16Clamp;
02976   case Intrinsic::nvvm_suld_2d_array_i32_clamp:
02977     return NVPTXISD::Suld2DArrayI32Clamp;
02978   case Intrinsic::nvvm_suld_2d_array_i64_clamp:
02979     return NVPTXISD::Suld2DArrayI64Clamp;
02980   case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
02981     return NVPTXISD::Suld2DArrayV2I8Clamp;
02982   case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
02983     return NVPTXISD::Suld2DArrayV2I16Clamp;
02984   case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
02985     return NVPTXISD::Suld2DArrayV2I32Clamp;
02986   case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
02987     return NVPTXISD::Suld2DArrayV2I64Clamp;
02988   case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
02989     return NVPTXISD::Suld2DArrayV4I8Clamp;
02990   case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
02991     return NVPTXISD::Suld2DArrayV4I16Clamp;
02992   case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
02993     return NVPTXISD::Suld2DArrayV4I32Clamp;
02994   case Intrinsic::nvvm_suld_3d_i8_clamp:
02995     return NVPTXISD::Suld3DI8Clamp;
02996   case Intrinsic::nvvm_suld_3d_i16_clamp:
02997     return NVPTXISD::Suld3DI16Clamp;
02998   case Intrinsic::nvvm_suld_3d_i32_clamp:
02999     return NVPTXISD::Suld3DI32Clamp;
03000   case Intrinsic::nvvm_suld_3d_i64_clamp:
03001     return NVPTXISD::Suld3DI64Clamp;
03002   case Intrinsic::nvvm_suld_3d_v2i8_clamp:
03003     return NVPTXISD::Suld3DV2I8Clamp;
03004   case Intrinsic::nvvm_suld_3d_v2i16_clamp:
03005     return NVPTXISD::Suld3DV2I16Clamp;
03006   case Intrinsic::nvvm_suld_3d_v2i32_clamp:
03007     return NVPTXISD::Suld3DV2I32Clamp;
03008   case Intrinsic::nvvm_suld_3d_v2i64_clamp:
03009     return NVPTXISD::Suld3DV2I64Clamp;
03010   case Intrinsic::nvvm_suld_3d_v4i8_clamp:
03011     return NVPTXISD::Suld3DV4I8Clamp;
03012   case Intrinsic::nvvm_suld_3d_v4i16_clamp:
03013     return NVPTXISD::Suld3DV4I16Clamp;
03014   case Intrinsic::nvvm_suld_3d_v4i32_clamp:
03015     return NVPTXISD::Suld3DV4I32Clamp;
03016   case Intrinsic::nvvm_suld_1d_i8_trap:
03017     return NVPTXISD::Suld1DI8Trap;
03018   case Intrinsic::nvvm_suld_1d_i16_trap:
03019     return NVPTXISD::Suld1DI16Trap;
03020   case Intrinsic::nvvm_suld_1d_i32_trap:
03021     return NVPTXISD::Suld1DI32Trap;
03022   case Intrinsic::nvvm_suld_1d_i64_trap:
03023     return NVPTXISD::Suld1DI64Trap;
03024   case Intrinsic::nvvm_suld_1d_v2i8_trap:
03025     return NVPTXISD::Suld1DV2I8Trap;
03026   case Intrinsic::nvvm_suld_1d_v2i16_trap:
03027     return NVPTXISD::Suld1DV2I16Trap;
03028   case Intrinsic::nvvm_suld_1d_v2i32_trap:
03029     return NVPTXISD::Suld1DV2I32Trap;
03030   case Intrinsic::nvvm_suld_1d_v2i64_trap:
03031     return NVPTXISD::Suld1DV2I64Trap;
03032   case Intrinsic::nvvm_suld_1d_v4i8_trap:
03033     return NVPTXISD::Suld1DV4I8Trap;
03034   case Intrinsic::nvvm_suld_1d_v4i16_trap:
03035     return NVPTXISD::Suld1DV4I16Trap;
03036   case Intrinsic::nvvm_suld_1d_v4i32_trap:
03037     return NVPTXISD::Suld1DV4I32Trap;
03038   case Intrinsic::nvvm_suld_1d_array_i8_trap:
03039     return NVPTXISD::Suld1DArrayI8Trap;
03040   case Intrinsic::nvvm_suld_1d_array_i16_trap:
03041     return NVPTXISD::Suld1DArrayI16Trap;
03042   case Intrinsic::nvvm_suld_1d_array_i32_trap:
03043     return NVPTXISD::Suld1DArrayI32Trap;
03044   case Intrinsic::nvvm_suld_1d_array_i64_trap:
03045     return NVPTXISD::Suld1DArrayI64Trap;
03046   case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
03047     return NVPTXISD::Suld1DArrayV2I8Trap;
03048   case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
03049     return NVPTXISD::Suld1DArrayV2I16Trap;
03050   case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
03051     return NVPTXISD::Suld1DArrayV2I32Trap;
03052   case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
03053     return NVPTXISD::Suld1DArrayV2I64Trap;
03054   case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
03055     return NVPTXISD::Suld1DArrayV4I8Trap;
03056   case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
03057     return NVPTXISD::Suld1DArrayV4I16Trap;
03058   case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
03059     return NVPTXISD::Suld1DArrayV4I32Trap;
03060   case Intrinsic::nvvm_suld_2d_i8_trap:
03061     return NVPTXISD::Suld2DI8Trap;
03062   case Intrinsic::nvvm_suld_2d_i16_trap:
03063     return NVPTXISD::Suld2DI16Trap;
03064   case Intrinsic::nvvm_suld_2d_i32_trap:
03065     return NVPTXISD::Suld2DI32Trap;
03066   case Intrinsic::nvvm_suld_2d_i64_trap:
03067     return NVPTXISD::Suld2DI64Trap;
03068   case Intrinsic::nvvm_suld_2d_v2i8_trap:
03069     return NVPTXISD::Suld2DV2I8Trap;
03070   case Intrinsic::nvvm_suld_2d_v2i16_trap:
03071     return NVPTXISD::Suld2DV2I16Trap;
03072   case Intrinsic::nvvm_suld_2d_v2i32_trap:
03073     return NVPTXISD::Suld2DV2I32Trap;
03074   case Intrinsic::nvvm_suld_2d_v2i64_trap:
03075     return NVPTXISD::Suld2DV2I64Trap;
03076   case Intrinsic::nvvm_suld_2d_v4i8_trap:
03077     return NVPTXISD::Suld2DV4I8Trap;
03078   case Intrinsic::nvvm_suld_2d_v4i16_trap:
03079     return NVPTXISD::Suld2DV4I16Trap;
03080   case Intrinsic::nvvm_suld_2d_v4i32_trap:
03081     return NVPTXISD::Suld2DV4I32Trap;
03082   case Intrinsic::nvvm_suld_2d_array_i8_trap:
03083     return NVPTXISD::Suld2DArrayI8Trap;
03084   case Intrinsic::nvvm_suld_2d_array_i16_trap:
03085     return NVPTXISD::Suld2DArrayI16Trap;
03086   case Intrinsic::nvvm_suld_2d_array_i32_trap:
03087     return NVPTXISD::Suld2DArrayI32Trap;
03088   case Intrinsic::nvvm_suld_2d_array_i64_trap:
03089     return NVPTXISD::Suld2DArrayI64Trap;
03090   case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
03091     return NVPTXISD::Suld2DArrayV2I8Trap;
03092   case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
03093     return NVPTXISD::Suld2DArrayV2I16Trap;
03094   case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
03095     return NVPTXISD::Suld2DArrayV2I32Trap;
03096   case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
03097     return NVPTXISD::Suld2DArrayV2I64Trap;
03098   case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
03099     return NVPTXISD::Suld2DArrayV4I8Trap;
03100   case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
03101     return NVPTXISD::Suld2DArrayV4I16Trap;
03102   case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
03103     return NVPTXISD::Suld2DArrayV4I32Trap;
03104   case Intrinsic::nvvm_suld_3d_i8_trap:
03105     return NVPTXISD::Suld3DI8Trap;
03106   case Intrinsic::nvvm_suld_3d_i16_trap:
03107     return NVPTXISD::Suld3DI16Trap;
03108   case Intrinsic::nvvm_suld_3d_i32_trap:
03109     return NVPTXISD::Suld3DI32Trap;
03110   case Intrinsic::nvvm_suld_3d_i64_trap:
03111     return NVPTXISD::Suld3DI64Trap;
03112   case Intrinsic::nvvm_suld_3d_v2i8_trap:
03113     return NVPTXISD::Suld3DV2I8Trap;
03114   case Intrinsic::nvvm_suld_3d_v2i16_trap:
03115     return NVPTXISD::Suld3DV2I16Trap;
03116   case Intrinsic::nvvm_suld_3d_v2i32_trap:
03117     return NVPTXISD::Suld3DV2I32Trap;
03118   case Intrinsic::nvvm_suld_3d_v2i64_trap:
03119     return NVPTXISD::Suld3DV2I64Trap;
03120   case Intrinsic::nvvm_suld_3d_v4i8_trap:
03121     return NVPTXISD::Suld3DV4I8Trap;
03122   case Intrinsic::nvvm_suld_3d_v4i16_trap:
03123     return NVPTXISD::Suld3DV4I16Trap;
03124   case Intrinsic::nvvm_suld_3d_v4i32_trap:
03125     return NVPTXISD::Suld3DV4I32Trap;
03126   case Intrinsic::nvvm_suld_1d_i8_zero:
03127     return NVPTXISD::Suld1DI8Zero;
03128   case Intrinsic::nvvm_suld_1d_i16_zero:
03129     return NVPTXISD::Suld1DI16Zero;
03130   case Intrinsic::nvvm_suld_1d_i32_zero:
03131     return NVPTXISD::Suld1DI32Zero;
03132   case Intrinsic::nvvm_suld_1d_i64_zero:
03133     return NVPTXISD::Suld1DI64Zero;
03134   case Intrinsic::nvvm_suld_1d_v2i8_zero:
03135     return NVPTXISD::Suld1DV2I8Zero;
03136   case Intrinsic::nvvm_suld_1d_v2i16_zero:
03137     return NVPTXISD::Suld1DV2I16Zero;
03138   case Intrinsic::nvvm_suld_1d_v2i32_zero:
03139     return NVPTXISD::Suld1DV2I32Zero;
03140   case Intrinsic::nvvm_suld_1d_v2i64_zero:
03141     return NVPTXISD::Suld1DV2I64Zero;
03142   case Intrinsic::nvvm_suld_1d_v4i8_zero:
03143     return NVPTXISD::Suld1DV4I8Zero;
03144   case Intrinsic::nvvm_suld_1d_v4i16_zero:
03145     return NVPTXISD::Suld1DV4I16Zero;
03146   case Intrinsic::nvvm_suld_1d_v4i32_zero:
03147     return NVPTXISD::Suld1DV4I32Zero;
03148   case Intrinsic::nvvm_suld_1d_array_i8_zero:
03149     return NVPTXISD::Suld1DArrayI8Zero;
03150   case Intrinsic::nvvm_suld_1d_array_i16_zero:
03151     return NVPTXISD::Suld1DArrayI16Zero;
03152   case Intrinsic::nvvm_suld_1d_array_i32_zero:
03153     return NVPTXISD::Suld1DArrayI32Zero;
03154   case Intrinsic::nvvm_suld_1d_array_i64_zero:
03155     return NVPTXISD::Suld1DArrayI64Zero;
03156   case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
03157     return NVPTXISD::Suld1DArrayV2I8Zero;
03158   case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
03159     return NVPTXISD::Suld1DArrayV2I16Zero;
03160   case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
03161     return NVPTXISD::Suld1DArrayV2I32Zero;
03162   case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
03163     return NVPTXISD::Suld1DArrayV2I64Zero;
03164   case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
03165     return NVPTXISD::Suld1DArrayV4I8Zero;
03166   case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
03167     return NVPTXISD::Suld1DArrayV4I16Zero;
03168   case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
03169     return NVPTXISD::Suld1DArrayV4I32Zero;
03170   case Intrinsic::nvvm_suld_2d_i8_zero:
03171     return NVPTXISD::Suld2DI8Zero;
03172   case Intrinsic::nvvm_suld_2d_i16_zero:
03173     return NVPTXISD::Suld2DI16Zero;
03174   case Intrinsic::nvvm_suld_2d_i32_zero:
03175     return NVPTXISD::Suld2DI32Zero;
03176   case Intrinsic::nvvm_suld_2d_i64_zero:
03177     return NVPTXISD::Suld2DI64Zero;
03178   case Intrinsic::nvvm_suld_2d_v2i8_zero:
03179     return NVPTXISD::Suld2DV2I8Zero;
03180   case Intrinsic::nvvm_suld_2d_v2i16_zero:
03181     return NVPTXISD::Suld2DV2I16Zero;
03182   case Intrinsic::nvvm_suld_2d_v2i32_zero:
03183     return NVPTXISD::Suld2DV2I32Zero;
03184   case Intrinsic::nvvm_suld_2d_v2i64_zero:
03185     return NVPTXISD::Suld2DV2I64Zero;
03186   case Intrinsic::nvvm_suld_2d_v4i8_zero:
03187     return NVPTXISD::Suld2DV4I8Zero;
03188   case Intrinsic::nvvm_suld_2d_v4i16_zero:
03189     return NVPTXISD::Suld2DV4I16Zero;
03190   case Intrinsic::nvvm_suld_2d_v4i32_zero:
03191     return NVPTXISD::Suld2DV4I32Zero;
03192   case Intrinsic::nvvm_suld_2d_array_i8_zero:
03193     return NVPTXISD::Suld2DArrayI8Zero;
03194   case Intrinsic::nvvm_suld_2d_array_i16_zero:
03195     return NVPTXISD::Suld2DArrayI16Zero;
03196   case Intrinsic::nvvm_suld_2d_array_i32_zero:
03197     return NVPTXISD::Suld2DArrayI32Zero;
03198   case Intrinsic::nvvm_suld_2d_array_i64_zero:
03199     return NVPTXISD::Suld2DArrayI64Zero;
03200   case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
03201     return NVPTXISD::Suld2DArrayV2I8Zero;
03202   case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
03203     return NVPTXISD::Suld2DArrayV2I16Zero;
03204   case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
03205     return NVPTXISD::Suld2DArrayV2I32Zero;
03206   case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
03207     return NVPTXISD::Suld2DArrayV2I64Zero;
03208   case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
03209     return NVPTXISD::Suld2DArrayV4I8Zero;
03210   case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
03211     return NVPTXISD::Suld2DArrayV4I16Zero;
03212   case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
03213     return NVPTXISD::Suld2DArrayV4I32Zero;
03214   case Intrinsic::nvvm_suld_3d_i8_zero:
03215     return NVPTXISD::Suld3DI8Zero;
03216   case Intrinsic::nvvm_suld_3d_i16_zero:
03217     return NVPTXISD::Suld3DI16Zero;
03218   case Intrinsic::nvvm_suld_3d_i32_zero:
03219     return NVPTXISD::Suld3DI32Zero;
03220   case Intrinsic::nvvm_suld_3d_i64_zero:
03221     return NVPTXISD::Suld3DI64Zero;
03222   case Intrinsic::nvvm_suld_3d_v2i8_zero:
03223     return NVPTXISD::Suld3DV2I8Zero;
03224   case Intrinsic::nvvm_suld_3d_v2i16_zero:
03225     return NVPTXISD::Suld3DV2I16Zero;
03226   case Intrinsic::nvvm_suld_3d_v2i32_zero:
03227     return NVPTXISD::Suld3DV2I32Zero;
03228   case Intrinsic::nvvm_suld_3d_v2i64_zero:
03229     return NVPTXISD::Suld3DV2I64Zero;
03230   case Intrinsic::nvvm_suld_3d_v4i8_zero:
03231     return NVPTXISD::Suld3DV4I8Zero;
03232   case Intrinsic::nvvm_suld_3d_v4i16_zero:
03233     return NVPTXISD::Suld3DV4I16Zero;
03234   case Intrinsic::nvvm_suld_3d_v4i32_zero:
03235     return NVPTXISD::Suld3DV4I32Zero;
03236   }
03237 }
03238 
03239 // llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
03240 // TgtMemIntrinsic
03241 // because we need the information that is only available in the "Value" type
03242 // of destination
03243 // pointer. In particular, the address space information.
03244 bool NVPTXTargetLowering::getTgtMemIntrinsic(
03245     IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
03246   switch (Intrinsic) {
03247   default:
03248     return false;
03249 
03250   case Intrinsic::nvvm_atomic_load_add_f32:
03251     Info.opc = ISD::INTRINSIC_W_CHAIN;
03252     Info.memVT = MVT::f32;
03253     Info.ptrVal = I.getArgOperand(0);
03254     Info.offset = 0;
03255     Info.vol = 0;
03256     Info.readMem = true;
03257     Info.writeMem = true;
03258     Info.align = 0;
03259     return true;
03260 
03261   case Intrinsic::nvvm_atomic_load_inc_32:
03262   case Intrinsic::nvvm_atomic_load_dec_32:
03263     Info.opc = ISD::INTRINSIC_W_CHAIN;
03264     Info.memVT = MVT::i32;
03265     Info.ptrVal = I.getArgOperand(0);
03266     Info.offset = 0;
03267     Info.vol = 0;
03268     Info.readMem = true;
03269     Info.writeMem = true;
03270     Info.align = 0;
03271     return true;
03272 
03273   case Intrinsic::nvvm_ldu_global_i:
03274   case Intrinsic::nvvm_ldu_global_f:
03275   case Intrinsic::nvvm_ldu_global_p: {
03276 
03277     Info.opc = ISD::INTRINSIC_W_CHAIN;
03278     if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
03279       Info.memVT = getValueType(I.getType());
03280     else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
03281       Info.memVT = getPointerTy();
03282     else
03283       Info.memVT = getValueType(I.getType());
03284     Info.ptrVal = I.getArgOperand(0);
03285     Info.offset = 0;
03286     Info.vol = 0;
03287     Info.readMem = true;
03288     Info.writeMem = false;
03289     Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
03290 
03291     return true;
03292   }
03293   case Intrinsic::nvvm_ldg_global_i:
03294   case Intrinsic::nvvm_ldg_global_f:
03295   case Intrinsic::nvvm_ldg_global_p: {
03296 
03297     Info.opc = ISD::INTRINSIC_W_CHAIN;
03298     if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
03299       Info.memVT = getValueType(I.getType());
03300     else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
03301       Info.memVT = getPointerTy();
03302     else
03303       Info.memVT = getValueType(I.getType());
03304     Info.ptrVal = I.getArgOperand(0);
03305     Info.offset = 0;
03306     Info.vol = 0;
03307     Info.readMem = true;
03308     Info.writeMem = false;
03309     Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
03310 
03311     return true;
03312   }
03313 
03314   case Intrinsic::nvvm_tex_1d_v4f32_s32:
03315   case Intrinsic::nvvm_tex_1d_v4f32_f32:
03316   case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
03317   case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
03318   case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
03319   case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
03320   case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
03321   case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
03322   case Intrinsic::nvvm_tex_2d_v4f32_s32:
03323   case Intrinsic::nvvm_tex_2d_v4f32_f32:
03324   case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
03325   case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
03326   case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
03327   case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
03328   case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
03329   case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
03330   case Intrinsic::nvvm_tex_3d_v4f32_s32:
03331   case Intrinsic::nvvm_tex_3d_v4f32_f32:
03332   case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
03333   case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
03334   case Intrinsic::nvvm_tex_cube_v4f32_f32:
03335   case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
03336   case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
03337   case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
03338   case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
03339   case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
03340   case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
03341   case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
03342   case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
03343   case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
03344   case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
03345   case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
03346   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
03347   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
03348   case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
03349   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
03350   case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
03351   case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
03352   case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
03353   case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
03354   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
03355   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
03356   case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
03357   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
03358   case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
03359   case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
03360   case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
03361   case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
03362   case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
03363   case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
03364   case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
03365   case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
03366   case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
03367   case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
03368   case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
03369   case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32: {
03370     Info.opc = getOpcForTextureInstr(Intrinsic);
03371     Info.memVT = MVT::v4f32;
03372     Info.ptrVal = nullptr;
03373     Info.offset = 0;
03374     Info.vol = 0;
03375     Info.readMem = true;
03376     Info.writeMem = false;
03377     Info.align = 16;
03378     return true;
03379   }
03380   case Intrinsic::nvvm_tex_1d_v4s32_s32:
03381   case Intrinsic::nvvm_tex_1d_v4s32_f32:
03382   case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
03383   case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
03384   case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
03385   case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
03386   case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
03387   case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
03388   case Intrinsic::nvvm_tex_2d_v4s32_s32:
03389   case Intrinsic::nvvm_tex_2d_v4s32_f32:
03390   case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
03391   case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
03392   case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
03393   case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
03394   case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
03395   case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
03396   case Intrinsic::nvvm_tex_3d_v4s32_s32:
03397   case Intrinsic::nvvm_tex_3d_v4s32_f32:
03398   case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
03399   case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
03400   case Intrinsic::nvvm_tex_cube_v4s32_f32:
03401   case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
03402   case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
03403   case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
03404   case Intrinsic::nvvm_tex_cube_v4u32_f32:
03405   case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
03406   case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
03407   case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
03408   case Intrinsic::nvvm_tex_1d_v4u32_s32:
03409   case Intrinsic::nvvm_tex_1d_v4u32_f32:
03410   case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
03411   case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
03412   case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
03413   case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
03414   case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
03415   case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
03416   case Intrinsic::nvvm_tex_2d_v4u32_s32:
03417   case Intrinsic::nvvm_tex_2d_v4u32_f32:
03418   case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
03419   case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
03420   case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
03421   case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
03422   case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
03423   case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
03424   case Intrinsic::nvvm_tex_3d_v4u32_s32:
03425   case Intrinsic::nvvm_tex_3d_v4u32_f32:
03426   case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
03427   case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
03428   case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
03429   case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
03430   case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
03431   case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
03432   case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
03433   case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
03434   case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
03435   case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
03436   case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
03437   case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
03438   case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
03439   case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
03440   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
03441   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
03442   case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
03443   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
03444   case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
03445   case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
03446   case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
03447   case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
03448   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
03449   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
03450   case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
03451   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
03452   case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
03453   case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
03454   case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
03455   case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
03456   case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
03457   case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
03458   case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
03459   case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
03460   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
03461   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
03462   case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
03463   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
03464   case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
03465   case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
03466   case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
03467   case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
03468   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
03469   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
03470   case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
03471   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
03472   case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
03473   case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
03474   case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
03475   case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
03476   case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
03477   case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
03478   case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
03479   case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
03480   case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
03481   case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
03482   case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
03483   case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
03484   case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
03485   case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
03486   case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
03487   case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
03488   case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
03489   case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
03490   case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
03491   case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32: {
03492     Info.opc = getOpcForTextureInstr(Intrinsic);
03493     Info.memVT = MVT::v4i32;
03494     Info.ptrVal = nullptr;
03495     Info.offset = 0;
03496     Info.vol = 0;
03497     Info.readMem = true;
03498     Info.writeMem = false;
03499     Info.align = 16;
03500     return true;
03501   }
03502   case Intrinsic::nvvm_suld_1d_i8_clamp:
03503   case Intrinsic::nvvm_suld_1d_v2i8_clamp:
03504   case Intrinsic::nvvm_suld_1d_v4i8_clamp:
03505   case Intrinsic::nvvm_suld_1d_array_i8_clamp:
03506   case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
03507   case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
03508   case Intrinsic::nvvm_suld_2d_i8_clamp:
03509   case Intrinsic::nvvm_suld_2d_v2i8_clamp:
03510   case Intrinsic::nvvm_suld_2d_v4i8_clamp:
03511   case Intrinsic::nvvm_suld_2d_array_i8_clamp:
03512   case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
03513   case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
03514   case Intrinsic::nvvm_suld_3d_i8_clamp:
03515   case Intrinsic::nvvm_suld_3d_v2i8_clamp:
03516   case Intrinsic::nvvm_suld_3d_v4i8_clamp:
03517   case Intrinsic::nvvm_suld_1d_i8_trap:
03518   case Intrinsic::nvvm_suld_1d_v2i8_trap:
03519   case Intrinsic::nvvm_suld_1d_v4i8_trap:
03520   case Intrinsic::nvvm_suld_1d_array_i8_trap:
03521   case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
03522   case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
03523   case Intrinsic::nvvm_suld_2d_i8_trap:
03524   case Intrinsic::nvvm_suld_2d_v2i8_trap:
03525   case Intrinsic::nvvm_suld_2d_v4i8_trap:
03526   case Intrinsic::nvvm_suld_2d_array_i8_trap:
03527   case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
03528   case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
03529   case Intrinsic::nvvm_suld_3d_i8_trap:
03530   case Intrinsic::nvvm_suld_3d_v2i8_trap:
03531   case Intrinsic::nvvm_suld_3d_v4i8_trap:
03532   case Intrinsic::nvvm_suld_1d_i8_zero:
03533   case Intrinsic::nvvm_suld_1d_v2i8_zero:
03534   case Intrinsic::nvvm_suld_1d_v4i8_zero:
03535   case Intrinsic::nvvm_suld_1d_array_i8_zero:
03536   case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
03537   case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
03538   case Intrinsic::nvvm_suld_2d_i8_zero:
03539   case Intrinsic::nvvm_suld_2d_v2i8_zero:
03540   case Intrinsic::nvvm_suld_2d_v4i8_zero:
03541   case Intrinsic::nvvm_suld_2d_array_i8_zero:
03542   case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
03543   case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
03544   case Intrinsic::nvvm_suld_3d_i8_zero:
03545   case Intrinsic::nvvm_suld_3d_v2i8_zero:
03546   case Intrinsic::nvvm_suld_3d_v4i8_zero: {
03547     Info.opc = getOpcForSurfaceInstr(Intrinsic);
03548     Info.memVT = MVT::i8;
03549     Info.ptrVal = nullptr;
03550     Info.offset = 0;
03551     Info.vol = 0;
03552     Info.readMem = true;
03553     Info.writeMem = false;
03554     Info.align = 16;
03555     return true;
03556   }
03557   case Intrinsic::nvvm_suld_1d_i16_clamp:
03558   case Intrinsic::nvvm_suld_1d_v2i16_clamp:
03559   case Intrinsic::nvvm_suld_1d_v4i16_clamp:
03560   case Intrinsic::nvvm_suld_1d_array_i16_clamp:
03561   case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
03562   case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
03563   case Intrinsic::nvvm_suld_2d_i16_clamp:
03564   case Intrinsic::nvvm_suld_2d_v2i16_clamp:
03565   case Intrinsic::nvvm_suld_2d_v4i16_clamp:
03566   case Intrinsic::nvvm_suld_2d_array_i16_clamp:
03567   case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
03568   case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
03569   case Intrinsic::nvvm_suld_3d_i16_clamp:
03570   case Intrinsic::nvvm_suld_3d_v2i16_clamp:
03571   case Intrinsic::nvvm_suld_3d_v4i16_clamp:
03572   case Intrinsic::nvvm_suld_1d_i16_trap:
03573   case Intrinsic::nvvm_suld_1d_v2i16_trap:
03574   case Intrinsic::nvvm_suld_1d_v4i16_trap:
03575   case Intrinsic::nvvm_suld_1d_array_i16_trap:
03576   case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
03577   case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
03578   case Intrinsic::nvvm_suld_2d_i16_trap:
03579   case Intrinsic::nvvm_suld_2d_v2i16_trap:
03580   case Intrinsic::nvvm_suld_2d_v4i16_trap:
03581   case Intrinsic::nvvm_suld_2d_array_i16_trap:
03582   case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
03583   case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
03584   case Intrinsic::nvvm_suld_3d_i16_trap:
03585   case Intrinsic::nvvm_suld_3d_v2i16_trap:
03586   case Intrinsic::nvvm_suld_3d_v4i16_trap:
03587   case Intrinsic::nvvm_suld_1d_i16_zero:
03588   case Intrinsic::nvvm_suld_1d_v2i16_zero:
03589   case Intrinsic::nvvm_suld_1d_v4i16_zero:
03590   case Intrinsic::nvvm_suld_1d_array_i16_zero:
03591   case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
03592   case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
03593   case Intrinsic::nvvm_suld_2d_i16_zero:
03594   case Intrinsic::nvvm_suld_2d_v2i16_zero:
03595   case Intrinsic::nvvm_suld_2d_v4i16_zero:
03596   case Intrinsic::nvvm_suld_2d_array_i16_zero:
03597   case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
03598   case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
03599   case Intrinsic::nvvm_suld_3d_i16_zero:
03600   case Intrinsic::nvvm_suld_3d_v2i16_zero:
03601   case Intrinsic::nvvm_suld_3d_v4i16_zero: {
03602     Info.opc = getOpcForSurfaceInstr(Intrinsic);
03603     Info.memVT = MVT::i16;
03604     Info.ptrVal = nullptr;
03605     Info.offset = 0;
03606     Info.vol = 0;
03607     Info.readMem = true;
03608     Info.writeMem = false;
03609     Info.align = 16;
03610     return true;
03611   }
03612   case Intrinsic::nvvm_suld_1d_i32_clamp:
03613   case Intrinsic::nvvm_suld_1d_v2i32_clamp:
03614   case Intrinsic::nvvm_suld_1d_v4i32_clamp:
03615   case Intrinsic::nvvm_suld_1d_array_i32_clamp:
03616   case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
03617   case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
03618   case Intrinsic::nvvm_suld_2d_i32_clamp:
03619   case Intrinsic::nvvm_suld_2d_v2i32_clamp:
03620   case Intrinsic::nvvm_suld_2d_v4i32_clamp:
03621   case Intrinsic::nvvm_suld_2d_array_i32_clamp:
03622   case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
03623   case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
03624   case Intrinsic::nvvm_suld_3d_i32_clamp:
03625   case Intrinsic::nvvm_suld_3d_v2i32_clamp:
03626   case Intrinsic::nvvm_suld_3d_v4i32_clamp:
03627   case Intrinsic::nvvm_suld_1d_i32_trap:
03628   case Intrinsic::nvvm_suld_1d_v2i32_trap:
03629   case Intrinsic::nvvm_suld_1d_v4i32_trap:
03630   case Intrinsic::nvvm_suld_1d_array_i32_trap:
03631   case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
03632   case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
03633   case Intrinsic::nvvm_suld_2d_i32_trap:
03634   case Intrinsic::nvvm_suld_2d_v2i32_trap:
03635   case Intrinsic::nvvm_suld_2d_v4i32_trap:
03636   case Intrinsic::nvvm_suld_2d_array_i32_trap:
03637   case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
03638   case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
03639   case Intrinsic::nvvm_suld_3d_i32_trap:
03640   case Intrinsic::nvvm_suld_3d_v2i32_trap:
03641   case Intrinsic::nvvm_suld_3d_v4i32_trap:
03642   case Intrinsic::nvvm_suld_1d_i32_zero:
03643   case Intrinsic::nvvm_suld_1d_v2i32_zero:
03644   case Intrinsic::nvvm_suld_1d_v4i32_zero:
03645   case Intrinsic::nvvm_suld_1d_array_i32_zero:
03646   case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
03647   case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
03648   case Intrinsic::nvvm_suld_2d_i32_zero:
03649   case Intrinsic::nvvm_suld_2d_v2i32_zero:
03650   case Intrinsic::nvvm_suld_2d_v4i32_zero:
03651   case Intrinsic::nvvm_suld_2d_array_i32_zero:
03652   case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
03653   case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
03654   case Intrinsic::nvvm_suld_3d_i32_zero:
03655   case Intrinsic::nvvm_suld_3d_v2i32_zero:
03656   case Intrinsic::nvvm_suld_3d_v4i32_zero: {
03657     Info.opc = getOpcForSurfaceInstr(Intrinsic);
03658     Info.memVT = MVT::i32;
03659     Info.ptrVal = nullptr;
03660     Info.offset = 0;
03661     Info.vol = 0;
03662     Info.readMem = true;
03663     Info.writeMem = false;
03664     Info.align = 16;
03665     return true;
03666   }
03667   case Intrinsic::nvvm_suld_1d_i64_clamp:
03668   case Intrinsic::nvvm_suld_1d_v2i64_clamp:
03669   case Intrinsic::nvvm_suld_1d_array_i64_clamp:
03670   case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
03671   case Intrinsic::nvvm_suld_2d_i64_clamp:
03672   case Intrinsic::nvvm_suld_2d_v2i64_clamp:
03673   case Intrinsic::nvvm_suld_2d_array_i64_clamp:
03674   case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
03675   case Intrinsic::nvvm_suld_3d_i64_clamp:
03676   case Intrinsic::nvvm_suld_3d_v2i64_clamp:
03677   case Intrinsic::nvvm_suld_1d_i64_trap:
03678   case Intrinsic::nvvm_suld_1d_v2i64_trap:
03679   case Intrinsic::nvvm_suld_1d_array_i64_trap:
03680   case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
03681   case Intrinsic::nvvm_suld_2d_i64_trap:
03682   case Intrinsic::nvvm_suld_2d_v2i64_trap:
03683   case Intrinsic::nvvm_suld_2d_array_i64_trap:
03684   case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
03685   case Intrinsic::nvvm_suld_3d_i64_trap:
03686   case Intrinsic::nvvm_suld_3d_v2i64_trap:
03687   case Intrinsic::nvvm_suld_1d_i64_zero:
03688   case Intrinsic::nvvm_suld_1d_v2i64_zero:
03689   case Intrinsic::nvvm_suld_1d_array_i64_zero:
03690   case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
03691   case Intrinsic::nvvm_suld_2d_i64_zero:
03692   case Intrinsic::nvvm_suld_2d_v2i64_zero:
03693   case Intrinsic::nvvm_suld_2d_array_i64_zero:
03694   case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
03695   case Intrinsic::nvvm_suld_3d_i64_zero:
03696   case Intrinsic::nvvm_suld_3d_v2i64_zero: {
03697     Info.opc = getOpcForSurfaceInstr(Intrinsic);
03698     Info.memVT = MVT::i64;
03699     Info.ptrVal = nullptr;
03700     Info.offset = 0;
03701     Info.vol = 0;
03702     Info.readMem = true;
03703     Info.writeMem = false;
03704     Info.align = 16;
03705     return true;
03706   }
03707   }
03708   return false;
03709 }
03710 
03711 /// isLegalAddressingMode - Return true if the addressing mode represented
03712 /// by AM is legal for this target, for a load/store of the specified type.
03713 /// Used to guide target specific optimizations, like loop strength reduction
03714 /// (LoopStrengthReduce.cpp) and memory optimization for address mode
03715 /// (CodeGenPrepare.cpp)
03716 bool NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM,
03717                                                 Type *Ty) const {
03718 
03719   // AddrMode - This represents an addressing mode of:
03720   //    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
03721   //
03722   // The legal address modes are
03723   // - [avar]
03724   // - [areg]
03725   // - [areg+immoff]
03726   // - [immAddr]
03727 
03728   if (AM.BaseGV) {
03729     if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
03730       return false;
03731     return true;
03732   }
03733 
03734   switch (AM.Scale) {
03735   case 0: // "r", "r+i" or "i" is allowed
03736     break;
03737   case 1:
03738     if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
03739       return false;
03740     // Otherwise we have r+i.
03741     break;
03742   default:
03743     // No scale > 1 is allowed
03744     return false;
03745   }
03746   return true;
03747 }
03748 
03749 //===----------------------------------------------------------------------===//
03750 //                         NVPTX Inline Assembly Support
03751 //===----------------------------------------------------------------------===//
03752 
03753 /// getConstraintType - Given a constraint letter, return the type of
03754 /// constraint it is for this target.
03755 NVPTXTargetLowering::ConstraintType
03756 NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
03757   if (Constraint.size() == 1) {
03758     switch (Constraint[0]) {
03759     default:
03760       break;
03761     case 'b':
03762     case 'r':
03763     case 'h':
03764     case 'c':
03765     case 'l':
03766     case 'f':
03767     case 'd':
03768     case '0':
03769     case 'N':
03770       return C_RegisterClass;
03771     }
03772   }
03773   return TargetLowering::getConstraintType(Constraint);
03774 }
03775 
03776 std::pair<unsigned, const TargetRegisterClass *>
03777 NVPTXTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
03778                                                   MVT VT) const {
03779   if (Constraint.size() == 1) {
03780     switch (Constraint[0]) {
03781     case 'b':
03782       return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
03783     case 'c':
03784       return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
03785     case 'h':
03786       return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
03787     case 'r':
03788       return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
03789     case 'l':
03790     case 'N':
03791       return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
03792     case 'f':
03793       return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
03794     case 'd':
03795       return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
03796     }
03797   }
03798   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
03799 }
03800 
03801 /// getFunctionAlignment - Return the Log2 alignment of this function.
03802 unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
03803   return 4;
03804 }
03805 
03806 //===----------------------------------------------------------------------===//
03807 //                         NVPTX DAG Combining
03808 //===----------------------------------------------------------------------===//
03809 
03810 bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
03811                                    CodeGenOpt::Level OptLevel) const {
03812   const Function *F = MF.getFunction();
03813   const TargetOptions &TO = MF.getTarget().Options;
03814 
03815   // Always honor command-line argument
03816   if (FMAContractLevelOpt.getNumOccurrences() > 0) {
03817     return FMAContractLevelOpt > 0;
03818   } else if (OptLevel == 0) {
03819     // Do not contract if we're not optimizing the code
03820     return false;
03821   } else if (TO.AllowFPOpFusion == FPOpFusion::Fast || TO.UnsafeFPMath) {
03822     // Honor TargetOptions flags that explicitly say fusion is okay
03823     return true;
03824   } else if (F->hasFnAttribute("unsafe-fp-math")) {
03825     // Check for unsafe-fp-math=true coming from Clang
03826     Attribute Attr = F->getFnAttribute("unsafe-fp-math");
03827     StringRef Val = Attr.getValueAsString();
03828     if (Val == "true")
03829       return true;
03830   }
03831 
03832   // We did not have a clear indication that fusion is allowed, so assume not
03833   return false;
03834 }
03835 
03836 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
03837 /// operands N0 and N1.  This is a helper for PerformADDCombine that is
03838 /// called with the default operands, and if that fails, with commuted
03839 /// operands.
03840 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
03841                                            TargetLowering::DAGCombinerInfo &DCI,
03842                                              const NVPTXSubtarget &Subtarget,
03843                                              CodeGenOpt::Level OptLevel) {
03844   SelectionDAG  &DAG = DCI.DAG;
03845   // Skip non-integer, non-scalar case
03846   EVT VT=N0.getValueType();
03847   if (VT.isVector())
03848     return SDValue();
03849 
03850   // fold (add (mul a, b), c) -> (mad a, b, c)
03851   //
03852   if (N0.getOpcode() == ISD::MUL) {
03853     assert (VT.isInteger());
03854     // For integer:
03855     // Since integer multiply-add costs the same as integer multiply
03856     // but is more costly than integer add, do the fusion only when
03857     // the mul is only used in the add.
03858     if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
03859         !N0.getNode()->hasOneUse())
03860       return SDValue();
03861 
03862     // Do the folding
03863     return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
03864                        N0.getOperand(0), N0.getOperand(1), N1);
03865   }
03866   else if (N0.getOpcode() == ISD::FMUL) {
03867     if (VT == MVT::f32 || VT == MVT::f64) {
03868       const auto *TLI = static_cast<const NVPTXTargetLowering *>(
03869           &DAG.getTargetLoweringInfo());
03870       if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
03871         return SDValue();
03872 
03873       // For floating point:
03874       // Do the fusion only when the mul has less than 5 uses and all
03875       // are add.
03876       // The heuristic is that if a use is not an add, then that use
03877       // cannot be fused into fma, therefore mul is still needed anyway.
03878       // If there are more than 4 uses, even if they are all add, fusing
03879       // them will increase register pressue.
03880       //
03881       int numUses = 0;
03882       int nonAddCount = 0;
03883       for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
03884            UE = N0.getNode()->use_end();
03885            UI != UE; ++UI) {
03886         numUses++;
03887         SDNode *User = *UI;
03888         if (User->getOpcode() != ISD::FADD)
03889           ++nonAddCount;
03890       }
03891       if (numUses >= 5)
03892         return SDValue();
03893       if (nonAddCount) {
03894         int orderNo = N->getIROrder();
03895         int orderNo2 = N0.getNode()->getIROrder();
03896         // simple heuristics here for considering potential register
03897         // pressure, the logics here is that the differnce are used
03898         // to measure the distance between def and use, the longer distance
03899         // more likely cause register pressure.
03900         if (orderNo - orderNo2 < 500)
03901           return SDValue();
03902 
03903         // Now, check if at least one of the FMUL's operands is live beyond the node N,
03904         // which guarantees that the FMA will not increase register pressure at node N.
03905         bool opIsLive = false;
03906         const SDNode *left = N0.getOperand(0).getNode();
03907         const SDNode *right = N0.getOperand(1).getNode();
03908 
03909         if (dyn_cast<ConstantSDNode>(left) || dyn_cast<ConstantSDNode>(right))
03910           opIsLive = true;
03911 
03912         if (!opIsLive)
03913           for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
03914             SDNode *User = *UI;
03915             int orderNo3 = User->getIROrder();
03916             if (orderNo3 > orderNo) {
03917               opIsLive = true;
03918               break;
03919             }
03920           }
03921 
03922         if (!opIsLive)
03923           for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
03924             SDNode *User = *UI;
03925             int orderNo3 = User->getIROrder();
03926             if (orderNo3 > orderNo) {
03927               opIsLive = true;
03928               break;
03929             }
03930           }
03931 
03932         if (!opIsLive)
03933           return SDValue();
03934       }
03935 
03936       return DAG.getNode(ISD::FMA, SDLoc(N), VT,
03937                          N0.getOperand(0), N0.getOperand(1), N1);
03938     }
03939   }
03940 
03941   return SDValue();
03942 }
03943 
03944 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
03945 ///
03946 static SDValue PerformADDCombine(SDNode *N,
03947                                  TargetLowering::DAGCombinerInfo &DCI,
03948                                  const NVPTXSubtarget &Subtarget,
03949                                  CodeGenOpt::Level OptLevel) {
03950   SDValue N0 = N->getOperand(0);
03951   SDValue N1 = N->getOperand(1);
03952 
03953   // First try with the default operand order.
03954   SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
03955                                                  OptLevel);
03956   if (Result.getNode())
03957     return Result;
03958 
03959   // If that didn't work, try again with the operands commuted.
03960   return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
03961 }
03962 
03963 static SDValue PerformANDCombine(SDNode *N,
03964                                  TargetLowering::DAGCombinerInfo &DCI) {
03965   // The type legalizer turns a vector load of i8 values into a zextload to i16
03966   // registers, optionally ANY_EXTENDs it (if target type is integer),
03967   // and ANDs off the high 8 bits. Since we turn this load into a
03968   // target-specific DAG node, the DAG combiner fails to eliminate these AND
03969   // nodes. Do that here.
03970   SDValue Val = N->getOperand(0);
03971   SDValue Mask = N->getOperand(1);
03972 
03973   if (isa<ConstantSDNode>(Val)) {
03974     std::swap(Val, Mask);
03975   }
03976 
03977   SDValue AExt;
03978   // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
03979   if (Val.getOpcode() == ISD::ANY_EXTEND) {
03980     AExt = Val;
03981     Val = Val->getOperand(0);
03982   }
03983 
03984   if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
03985     Val = Val->getOperand(0);
03986   }
03987 
03988   if (Val->getOpcode() == NVPTXISD::LoadV2 ||
03989       Val->getOpcode() == NVPTXISD::LoadV4) {
03990     ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
03991     if (!MaskCnst) {
03992       // Not an AND with a constant
03993       return SDValue();
03994     }
03995 
03996     uint64_t MaskVal = MaskCnst->getZExtValue();
03997     if (MaskVal != 0xff) {
03998       // Not an AND that chops off top 8 bits
03999       return SDValue();
04000     }
04001 
04002     MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
04003     if (!Mem) {
04004       // Not a MemSDNode?!?
04005       return SDValue();
04006     }
04007 
04008     EVT MemVT = Mem->getMemoryVT();
04009     if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
04010       // We only handle the i8 case
04011       return SDValue();
04012     }
04013 
04014     unsigned ExtType =
04015       cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
04016         getZExtValue();
04017     if (ExtType == ISD::SEXTLOAD) {
04018       // If for some reason the load is a sextload, the and is needed to zero
04019       // out the high 8 bits
04020       return SDValue();
04021     }
04022 
04023     bool AddTo = false;
04024     if (AExt.getNode() != 0) {
04025       // Re-insert the ext as a zext.
04026       Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
04027                             AExt.getValueType(), Val);
04028       AddTo = true;
04029     }
04030 
04031     // If we get here, the AND is unnecessary.  Just replace it with the load
04032     DCI.CombineTo(N, Val, AddTo);
04033   }
04034 
04035   return SDValue();
04036 }
04037 
04038 enum OperandSignedness {
04039   Signed = 0,
04040   Unsigned,
04041   Unknown
04042 };
04043 
04044 /// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
04045 /// that can be demoted to \p OptSize bits without loss of information. The
04046 /// signedness of the operand, if determinable, is placed in \p S.
04047 static bool IsMulWideOperandDemotable(SDValue Op,
04048                                       unsigned OptSize,
04049                                       OperandSignedness &S) {
04050   S = Unknown;
04051 
04052   if (Op.getOpcode() == ISD::SIGN_EXTEND ||
04053       Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
04054     EVT OrigVT = Op.getOperand(0).getValueType();
04055     if (OrigVT.getSizeInBits() <= OptSize) {
04056       S = Signed;
04057       return true;
04058     }
04059   } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
04060     EVT OrigVT = Op.getOperand(0).getValueType();
04061     if (OrigVT.getSizeInBits() <= OptSize) {
04062       S = Unsigned;
04063       return true;
04064     }
04065   }
04066 
04067   return false;
04068 }
04069 
04070 /// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
04071 /// be demoted to \p OptSize bits without loss of information. If the operands
04072 /// contain a constant, it should appear as the RHS operand. The signedness of
04073 /// the operands is placed in \p IsSigned.
04074 static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
04075                                         unsigned OptSize,
04076                                         bool &IsSigned) {
04077 
04078   OperandSignedness LHSSign;
04079 
04080   // The LHS operand must be a demotable op
04081   if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
04082     return false;
04083 
04084   // We should have been able to determine the signedness from the LHS
04085   if (LHSSign == Unknown)
04086     return false;
04087 
04088   IsSigned = (LHSSign == Signed);
04089 
04090   // The RHS can be a demotable op or a constant
04091   if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
04092     APInt Val = CI->getAPIntValue();
04093     if (LHSSign == Unsigned) {
04094       if (Val.isIntN(OptSize)) {
04095         return true;
04096       }
04097       return false;
04098     } else {
04099       if (Val.isSignedIntN(OptSize)) {
04100         return true;
04101       }
04102       return false;
04103     }
04104   } else {
04105     OperandSignedness RHSSign;
04106     if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
04107       return false;
04108 
04109     if (LHSSign != RHSSign)
04110       return false;
04111 
04112     return true;
04113   }
04114 }
04115 
04116 /// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
04117 /// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
04118 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
04119 /// amount.
04120 static SDValue TryMULWIDECombine(SDNode *N,
04121                                  TargetLowering::DAGCombinerInfo &DCI) {
04122   EVT MulType = N->getValueType(0);
04123   if (MulType != MVT::i32 && MulType != MVT::i64) {
04124     return SDValue();
04125   }
04126 
04127   unsigned OptSize = MulType.getSizeInBits() >> 1;
04128   SDValue LHS = N->getOperand(0);
04129   SDValue RHS = N->getOperand(1);
04130 
04131   // Canonicalize the multiply so the constant (if any) is on the right
04132   if (N->getOpcode() == ISD::MUL) {
04133     if (isa<ConstantSDNode>(LHS)) {
04134       std::swap(LHS, RHS);
04135     }
04136   }
04137 
04138   // If we have a SHL, determine the actual multiply amount
04139   if (N->getOpcode() == ISD::SHL) {
04140     ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
04141     if (!ShlRHS) {
04142       return SDValue();
04143     }
04144 
04145     APInt ShiftAmt = ShlRHS->getAPIntValue();
04146     unsigned BitWidth = MulType.getSizeInBits();
04147     if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
04148       APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
04149       RHS = DCI.DAG.getConstant(MulVal, MulType);
04150     } else {
04151       return SDValue();
04152     }
04153   }
04154 
04155   bool Signed;
04156   // Verify that our operands are demotable
04157   if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
04158     return SDValue();
04159   }
04160 
04161   EVT DemotedVT;
04162   if (MulType == MVT::i32) {
04163     DemotedVT = MVT::i16;
04164   } else {
04165     DemotedVT = MVT::i32;
04166   }
04167 
04168   // Truncate the operands to the correct size. Note that these are just for
04169   // type consistency and will (likely) be eliminated in later phases.
04170   SDValue TruncLHS =
04171     DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, LHS);
04172   SDValue TruncRHS =
04173     DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, RHS);
04174 
04175   unsigned Opc;
04176   if (Signed) {
04177     Opc = NVPTXISD::MUL_WIDE_SIGNED;
04178   } else {
04179     Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
04180   }
04181 
04182   return DCI.DAG.getNode(Opc, SDLoc(N), MulType, TruncLHS, TruncRHS);
04183 }
04184 
04185 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
04186 static SDValue PerformMULCombine(SDNode *N,
04187                                  TargetLowering::DAGCombinerInfo &DCI,
04188                                  CodeGenOpt::Level OptLevel) {
04189   if (OptLevel > 0) {
04190     // Try mul.wide combining at OptLevel > 0
04191     SDValue Ret = TryMULWIDECombine(N, DCI);
04192     if (Ret.getNode())
04193       return Ret;
04194   }
04195 
04196   return SDValue();
04197 }
04198 
04199 /// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
04200 static SDValue PerformSHLCombine(SDNode *N,
04201                                  TargetLowering::DAGCombinerInfo &DCI,
04202                                  CodeGenOpt::Level OptLevel) {
04203   if (OptLevel > 0) {
04204     // Try mul.wide combining at OptLevel > 0
04205     SDValue Ret = TryMULWIDECombine(N, DCI);
04206     if (Ret.getNode())
04207       return Ret;
04208   }
04209 
04210   return SDValue();
04211 }
04212 
04213 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
04214                                                DAGCombinerInfo &DCI) const {
04215   CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
04216   switch (N->getOpcode()) {
04217     default: break;
04218     case ISD::ADD:
04219     case ISD::FADD:
04220       return PerformADDCombine(N, DCI, STI, OptLevel);
04221     case ISD::MUL:
04222       return PerformMULCombine(N, DCI, OptLevel);
04223     case ISD::SHL:
04224       return PerformSHLCombine(N, DCI, OptLevel);
04225     case ISD::AND:
04226       return PerformANDCombine(N, DCI);
04227   }
04228   return SDValue();
04229 }
04230 
04231 /// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
04232 static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
04233                               const DataLayout *TD,
04234                               SmallVectorImpl<SDValue> &Results) {
04235   EVT ResVT = N->getValueType(0);
04236   SDLoc DL(N);
04237 
04238   assert(ResVT.isVector() && "Vector load must have vector type");
04239 
04240   // We only handle "native" vector sizes for now, e.g. <4 x double> is not
04241   // legal.  We can (and should) split that into 2 loads of <2 x double> here
04242   // but I'm leaving that as a TODO for now.
04243   assert(ResVT.isSimple() && "Can only handle simple types");
04244   switch (ResVT.getSimpleVT().SimpleTy) {
04245   default:
04246     return;
04247   case MVT::v2i8:
04248   case MVT::v2i16:
04249   case MVT::v2i32:
04250   case MVT::v2i64:
04251   case MVT::v2f32:
04252   case MVT::v2f64:
04253   case MVT::v4i8:
04254   case MVT::v4i16:
04255   case MVT::v4i32:
04256   case MVT::v4f32:
04257     // This is a "native" vector type
04258     break;
04259   }
04260 
04261   LoadSDNode *LD = cast<LoadSDNode>(N);
04262 
04263   unsigned Align = LD->getAlignment();
04264   unsigned PrefAlign =
04265     TD->getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
04266   if (Align < PrefAlign) {
04267     // This load is not sufficiently aligned, so bail out and let this vector
04268     // load be scalarized.  Note that we may still be able to emit smaller
04269     // vector loads.  For example, if we are loading a <4 x float> with an
04270     // alignment of 8, this check will fail but the legalizer will try again
04271     // with 2 x <2 x float>, which will succeed with an alignment of 8.
04272     return;
04273   }
04274 
04275   EVT EltVT = ResVT.getVectorElementType();
04276   unsigned NumElts = ResVT.getVectorNumElements();
04277 
04278   // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
04279   // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
04280   // loaded type to i16 and propagate the "real" type as the memory type.
04281   bool NeedTrunc = false;
04282   if (EltVT.getSizeInBits() < 16) {
04283     EltVT = MVT::i16;
04284     NeedTrunc = true;
04285   }
04286 
04287   unsigned Opcode = 0;
04288   SDVTList LdResVTs;
04289 
04290   switch (NumElts) {
04291   default:
04292     return;
04293   case 2:
04294     Opcode = NVPTXISD::LoadV2;
04295     LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
04296     break;
04297   case 4: {
04298     Opcode = NVPTXISD::LoadV4;
04299     EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
04300     LdResVTs = DAG.getVTList(ListVTs);
04301     break;
04302   }
04303   }
04304 
04305   SmallVector<SDValue, 8> OtherOps;
04306 
04307   // Copy regular operands
04308   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
04309     OtherOps.push_back(N->getOperand(i));
04310 
04311   // The select routine does not have access to the LoadSDNode instance, so
04312   // pass along the extension information
04313   OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType()));
04314 
04315   SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
04316                                           LD->getMemoryVT(),
04317                                           LD->getMemOperand());
04318 
04319   SmallVector<SDValue, 4> ScalarRes;
04320 
04321   for (unsigned i = 0; i < NumElts; ++i) {
04322     SDValue Res = NewLD.getValue(i);
04323     if (NeedTrunc)
04324       Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
04325     ScalarRes.push_back(Res);
04326   }
04327 
04328   SDValue LoadChain = NewLD.getValue(NumElts);
04329 
04330   SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
04331 
04332   Results.push_back(BuildVec);
04333   Results.push_back(LoadChain);
04334 }
04335 
04336 static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
04337                                      SmallVectorImpl<SDValue> &Results) {
04338   SDValue Chain = N->getOperand(0);
04339   SDValue Intrin = N->getOperand(1);
04340   SDLoc DL(N);
04341 
04342   // Get the intrinsic ID
04343   unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
04344   switch (IntrinNo) {
04345   default:
04346     return;
04347   case Intrinsic::nvvm_ldg_global_i:
04348   case Intrinsic::nvvm_ldg_global_f:
04349   case Intrinsic::nvvm_ldg_global_p:
04350   case Intrinsic::nvvm_ldu_global_i:
04351   case Intrinsic::nvvm_ldu_global_f:
04352   case Intrinsic::nvvm_ldu_global_p: {
04353     EVT ResVT = N->getValueType(0);
04354 
04355     if (ResVT.isVector()) {
04356       // Vector LDG/LDU
04357 
04358       unsigned NumElts = ResVT.getVectorNumElements();
04359       EVT EltVT = ResVT.getVectorElementType();
04360 
04361       // Since LDU/LDG are target nodes, we cannot rely on DAG type
04362       // legalization.
04363       // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
04364       // loaded type to i16 and propagate the "real" type as the memory type.
04365       bool NeedTrunc = false;
04366       if (EltVT.getSizeInBits() < 16) {
04367         EltVT = MVT::i16;
04368         NeedTrunc = true;
04369       }
04370 
04371       unsigned Opcode = 0;
04372       SDVTList LdResVTs;
04373 
04374       switch (NumElts) {
04375       default:
04376         return;
04377       case 2:
04378         switch (IntrinNo) {
04379         default:
04380           return;
04381         case Intrinsic::nvvm_ldg_global_i:
04382         case Intrinsic::nvvm_ldg_global_f:
04383         case Intrinsic::nvvm_ldg_global_p:
04384           Opcode = NVPTXISD::LDGV2;
04385           break;
04386         case Intrinsic::nvvm_ldu_global_i:
04387         case Intrinsic::nvvm_ldu_global_f:
04388         case Intrinsic::nvvm_ldu_global_p:
04389           Opcode = NVPTXISD::LDUV2;
04390           break;
04391         }
04392         LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
04393         break;
04394       case 4: {
04395         switch (IntrinNo) {
04396         default:
04397           return;
04398         case Intrinsic::nvvm_ldg_global_i:
04399         case Intrinsic::nvvm_ldg_global_f:
04400         case Intrinsic::nvvm_ldg_global_p:
04401           Opcode = NVPTXISD::LDGV4;
04402           break;
04403         case Intrinsic::nvvm_ldu_global_i:
04404         case Intrinsic::nvvm_ldu_global_f:
04405         case Intrinsic::nvvm_ldu_global_p:
04406           Opcode = NVPTXISD::LDUV4;
04407           break;
04408         }
04409         EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
04410         LdResVTs = DAG.getVTList(ListVTs);
04411         break;
04412       }
04413       }
04414 
04415       SmallVector<SDValue, 8> OtherOps;
04416 
04417       // Copy regular operands
04418 
04419       OtherOps.push_back(Chain); // Chain
04420                                  // Skip operand 1 (intrinsic ID)
04421       // Others
04422       for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i)
04423         OtherOps.push_back(N->getOperand(i));
04424 
04425       MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
04426 
04427       SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
04428                                               MemSD->getMemoryVT(),
04429                                               MemSD->getMemOperand());
04430 
04431       SmallVector<SDValue, 4> ScalarRes;
04432 
04433       for (unsigned i = 0; i < NumElts; ++i) {
04434         SDValue Res = NewLD.getValue(i);
04435         if (NeedTrunc)
04436           Res =
04437               DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
04438         ScalarRes.push_back(Res);
04439       }
04440 
04441       SDValue LoadChain = NewLD.getValue(NumElts);
04442 
04443       SDValue BuildVec =
04444           DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
04445 
04446       Results.push_back(BuildVec);
04447       Results.push_back(LoadChain);
04448     } else {
04449       // i8 LDG/LDU
04450       assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
04451              "Custom handling of non-i8 ldu/ldg?");
04452 
04453       // Just copy all operands as-is
04454       SmallVector<SDValue, 4> Ops;
04455       for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
04456         Ops.push_back(N->getOperand(i));
04457 
04458       // Force output to i16
04459       SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
04460 
04461       MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
04462 
04463       // We make sure the memory type is i8, which will be used during isel
04464       // to select the proper instruction.
04465       SDValue NewLD =
04466           DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
04467                                   MVT::i8, MemSD->getMemOperand());
04468 
04469       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
04470                                     NewLD.getValue(0)));
04471       Results.push_back(NewLD.getValue(1));
04472     }
04473   }
04474   }
04475 }
04476 
04477 void NVPTXTargetLowering::ReplaceNodeResults(
04478     SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
04479   switch (N->getOpcode()) {
04480   default:
04481     report_fatal_error("Unhandled custom legalization");
04482   case ISD::LOAD:
04483     ReplaceLoadVector(N, DAG, getDataLayout(), Results);
04484     return;
04485   case ISD::INTRINSIC_W_CHAIN:
04486     ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
04487     return;
04488   }
04489 }
04490 
04491 // Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
04492 void NVPTXSection::anchor() {}
04493 
04494 NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
04495   delete TextSection;
04496   delete DataSection;
04497   delete BSSSection;
04498   delete ReadOnlySection;
04499 
04500   delete StaticCtorSection;
04501   delete StaticDtorSection;
04502   delete LSDASection;
04503   delete EHFrameSection;
04504   delete DwarfAbbrevSection;
04505   delete DwarfInfoSection;
04506   delete DwarfLineSection;
04507   delete DwarfFrameSection;
04508   delete DwarfPubTypesSection;
04509   delete DwarfDebugInlineSection;
04510   delete DwarfStrSection;
04511   delete DwarfLocSection;
04512   delete DwarfARangesSection;
04513   delete DwarfRangesSection;
04514   delete DwarfMacroInfoSection;
04515 }
04516 
04517 const MCSection *
04518 NVPTXTargetObjectFile::SelectSectionForGlobal(const GlobalValue *GV,
04519                                               SectionKind Kind, Mangler &Mang,
04520                                               const TargetMachine &TM) const {
04521   return getDataSection();
04522 }