LLVM  mainline
NVPTXISelLowering.cpp
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00001 //
00002 //                     The LLVM Compiler Infrastructure
00003 //
00004 // This file is distributed under the University of Illinois Open Source
00005 // License. See LICENSE.TXT for details.
00006 //
00007 //===----------------------------------------------------------------------===//
00008 //
00009 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
00010 // selection DAG.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "NVPTXISelLowering.h"
00015 #include "NVPTX.h"
00016 #include "NVPTXTargetMachine.h"
00017 #include "NVPTXTargetObjectFile.h"
00018 #include "NVPTXUtilities.h"
00019 #include "llvm/CodeGen/Analysis.h"
00020 #include "llvm/CodeGen/MachineFrameInfo.h"
00021 #include "llvm/CodeGen/MachineFunction.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineRegisterInfo.h"
00024 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
00025 #include "llvm/IR/CallSite.h"
00026 #include "llvm/IR/DerivedTypes.h"
00027 #include "llvm/IR/Function.h"
00028 #include "llvm/IR/GlobalValue.h"
00029 #include "llvm/IR/IntrinsicInst.h"
00030 #include "llvm/IR/Intrinsics.h"
00031 #include "llvm/IR/Module.h"
00032 #include "llvm/MC/MCSectionELF.h"
00033 #include "llvm/Support/CommandLine.h"
00034 #include "llvm/Support/Debug.h"
00035 #include "llvm/Support/ErrorHandling.h"
00036 #include "llvm/Support/MathExtras.h"
00037 #include "llvm/Support/raw_ostream.h"
00038 #include <sstream>
00039 
00040 #undef DEBUG_TYPE
00041 #define DEBUG_TYPE "nvptx-lower"
00042 
00043 using namespace llvm;
00044 
00045 static unsigned int uniqueCallSite = 0;
00046 
00047 static cl::opt<bool> sched4reg(
00048     "nvptx-sched4reg",
00049     cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
00050 
00051 static cl::opt<unsigned>
00052 FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
00053                     cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
00054                              " 1: do it  2: do it aggressively"),
00055                     cl::init(2));
00056 
00057 static bool IsPTXVectorType(MVT VT) {
00058   switch (VT.SimpleTy) {
00059   default:
00060     return false;
00061   case MVT::v2i1:
00062   case MVT::v4i1:
00063   case MVT::v2i8:
00064   case MVT::v4i8:
00065   case MVT::v2i16:
00066   case MVT::v4i16:
00067   case MVT::v2i32:
00068   case MVT::v4i32:
00069   case MVT::v2i64:
00070   case MVT::v2f32:
00071   case MVT::v4f32:
00072   case MVT::v2f64:
00073     return true;
00074   }
00075 }
00076 
00077 /// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
00078 /// EVTs that compose it.  Unlike ComputeValueVTs, this will break apart vectors
00079 /// into their primitive components.
00080 /// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
00081 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
00082 /// LowerCall, and LowerReturn.
00083 static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
00084                                Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
00085                                SmallVectorImpl<uint64_t> *Offsets = nullptr,
00086                                uint64_t StartingOffset = 0) {
00087   SmallVector<EVT, 16> TempVTs;
00088   SmallVector<uint64_t, 16> TempOffsets;
00089 
00090   ComputeValueVTs(TLI, DL, Ty, TempVTs, &TempOffsets, StartingOffset);
00091   for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
00092     EVT VT = TempVTs[i];
00093     uint64_t Off = TempOffsets[i];
00094     if (VT.isVector())
00095       for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
00096         ValueVTs.push_back(VT.getVectorElementType());
00097         if (Offsets)
00098           Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
00099       }
00100     else {
00101       ValueVTs.push_back(VT);
00102       if (Offsets)
00103         Offsets->push_back(Off);
00104     }
00105   }
00106 }
00107 
00108 // NVPTXTargetLowering Constructor.
00109 NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
00110                                          const NVPTXSubtarget &STI)
00111     : TargetLowering(TM), nvTM(&TM), STI(STI) {
00112 
00113   // always lower memset, memcpy, and memmove intrinsics to load/store
00114   // instructions, rather
00115   // then generating calls to memset, mempcy or memmove.
00116   MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
00117   MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
00118   MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
00119 
00120   setBooleanContents(ZeroOrNegativeOneBooleanContent);
00121   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
00122 
00123   // Jump is Expensive. Don't create extra control flow for 'and', 'or'
00124   // condition branches.
00125   setJumpIsExpensive(true);
00126 
00127   // Wide divides are _very_ slow. Try to reduce the width of the divide if
00128   // possible.
00129   addBypassSlowDiv(64, 32);
00130 
00131   // By default, use the Source scheduling
00132   if (sched4reg)
00133     setSchedulingPreference(Sched::RegPressure);
00134   else
00135     setSchedulingPreference(Sched::Source);
00136 
00137   addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
00138   addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
00139   addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
00140   addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
00141   addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
00142   addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
00143 
00144   // Operations not directly supported by NVPTX.
00145   setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
00146   setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
00147   setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
00148   setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
00149   setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
00150   setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
00151   setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
00152   setOperationAction(ISD::BR_CC, MVT::f32, Expand);
00153   setOperationAction(ISD::BR_CC, MVT::f64, Expand);
00154   setOperationAction(ISD::BR_CC, MVT::i1, Expand);
00155   setOperationAction(ISD::BR_CC, MVT::i8, Expand);
00156   setOperationAction(ISD::BR_CC, MVT::i16, Expand);
00157   setOperationAction(ISD::BR_CC, MVT::i32, Expand);
00158   setOperationAction(ISD::BR_CC, MVT::i64, Expand);
00159   // Some SIGN_EXTEND_INREG can be done using cvt instruction.
00160   // For others we will expand to a SHL/SRA pair.
00161   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
00162   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
00163   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
00164   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
00165   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
00166 
00167   setOperationAction(ISD::SHL_PARTS, MVT::i32  , Custom);
00168   setOperationAction(ISD::SRA_PARTS, MVT::i32  , Custom);
00169   setOperationAction(ISD::SRL_PARTS, MVT::i32  , Custom);
00170   setOperationAction(ISD::SHL_PARTS, MVT::i64  , Custom);
00171   setOperationAction(ISD::SRA_PARTS, MVT::i64  , Custom);
00172   setOperationAction(ISD::SRL_PARTS, MVT::i64  , Custom);
00173 
00174   if (STI.hasROT64()) {
00175     setOperationAction(ISD::ROTL, MVT::i64, Legal);
00176     setOperationAction(ISD::ROTR, MVT::i64, Legal);
00177   } else {
00178     setOperationAction(ISD::ROTL, MVT::i64, Expand);
00179     setOperationAction(ISD::ROTR, MVT::i64, Expand);
00180   }
00181   if (STI.hasROT32()) {
00182     setOperationAction(ISD::ROTL, MVT::i32, Legal);
00183     setOperationAction(ISD::ROTR, MVT::i32, Legal);
00184   } else {
00185     setOperationAction(ISD::ROTL, MVT::i32, Expand);
00186     setOperationAction(ISD::ROTR, MVT::i32, Expand);
00187   }
00188 
00189   setOperationAction(ISD::ROTL, MVT::i16, Expand);
00190   setOperationAction(ISD::ROTR, MVT::i16, Expand);
00191   setOperationAction(ISD::ROTL, MVT::i8, Expand);
00192   setOperationAction(ISD::ROTR, MVT::i8, Expand);
00193   setOperationAction(ISD::BSWAP, MVT::i16, Expand);
00194   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
00195   setOperationAction(ISD::BSWAP, MVT::i64, Expand);
00196 
00197   // Indirect branch is not supported.
00198   // This also disables Jump Table creation.
00199   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
00200   setOperationAction(ISD::BRIND, MVT::Other, Expand);
00201 
00202   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
00203   setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
00204 
00205   // We want to legalize constant related memmove and memcopy
00206   // intrinsics.
00207   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
00208 
00209   // Turn FP extload into load/fextend
00210   setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
00211   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
00212   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
00213   setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
00214   setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
00215   setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
00216   setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
00217   setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
00218   setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
00219   // Turn FP truncstore into trunc + store.
00220   // FIXME: vector types should also be expanded
00221   setTruncStoreAction(MVT::f32, MVT::f16, Expand);
00222   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
00223   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
00224 
00225   // PTX does not support load / store predicate registers
00226   setOperationAction(ISD::LOAD, MVT::i1, Custom);
00227   setOperationAction(ISD::STORE, MVT::i1, Custom);
00228 
00229   for (MVT VT : MVT::integer_valuetypes()) {
00230     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
00231     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
00232     setTruncStoreAction(VT, MVT::i1, Expand);
00233   }
00234 
00235   // This is legal in NVPTX
00236   setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
00237   setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
00238 
00239   // TRAP can be lowered to PTX trap
00240   setOperationAction(ISD::TRAP, MVT::Other, Legal);
00241 
00242   setOperationAction(ISD::ADDC, MVT::i64, Expand);
00243   setOperationAction(ISD::ADDE, MVT::i64, Expand);
00244 
00245   // Register custom handling for vector loads/stores
00246   for (MVT VT : MVT::vector_valuetypes()) {
00247     if (IsPTXVectorType(VT)) {
00248       setOperationAction(ISD::LOAD, VT, Custom);
00249       setOperationAction(ISD::STORE, VT, Custom);
00250       setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
00251     }
00252   }
00253 
00254   // Custom handling for i8 intrinsics
00255   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
00256 
00257   setOperationAction(ISD::CTLZ, MVT::i16, Legal);
00258   setOperationAction(ISD::CTLZ, MVT::i32, Legal);
00259   setOperationAction(ISD::CTLZ, MVT::i64, Legal);
00260   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
00261   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
00262   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
00263   setOperationAction(ISD::CTTZ, MVT::i16, Expand);
00264   setOperationAction(ISD::CTTZ, MVT::i32, Expand);
00265   setOperationAction(ISD::CTTZ, MVT::i64, Expand);
00266   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
00267   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
00268   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
00269   setOperationAction(ISD::CTPOP, MVT::i16, Legal);
00270   setOperationAction(ISD::CTPOP, MVT::i32, Legal);
00271   setOperationAction(ISD::CTPOP, MVT::i64, Legal);
00272 
00273   // PTX does not directly support SELP of i1, so promote to i32 first
00274   setOperationAction(ISD::SELECT, MVT::i1, Custom);
00275 
00276   // PTX cannot multiply two i64s in a single instruction.
00277   setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
00278   setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
00279 
00280   // We have some custom DAG combine patterns for these nodes
00281   setTargetDAGCombine(ISD::ADD);
00282   setTargetDAGCombine(ISD::AND);
00283   setTargetDAGCombine(ISD::FADD);
00284   setTargetDAGCombine(ISD::MUL);
00285   setTargetDAGCombine(ISD::SHL);
00286   setTargetDAGCombine(ISD::SELECT);
00287 
00288   // Now deduce the information based on the above mentioned
00289   // actions
00290   computeRegisterProperties(STI.getRegisterInfo());
00291 }
00292 
00293 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
00294   switch ((NVPTXISD::NodeType)Opcode) {
00295   case NVPTXISD::FIRST_NUMBER:
00296     break;
00297   case NVPTXISD::CALL:
00298     return "NVPTXISD::CALL";
00299   case NVPTXISD::RET_FLAG:
00300     return "NVPTXISD::RET_FLAG";
00301   case NVPTXISD::LOAD_PARAM:
00302     return "NVPTXISD::LOAD_PARAM";
00303   case NVPTXISD::Wrapper:
00304     return "NVPTXISD::Wrapper";
00305   case NVPTXISD::DeclareParam:
00306     return "NVPTXISD::DeclareParam";
00307   case NVPTXISD::DeclareScalarParam:
00308     return "NVPTXISD::DeclareScalarParam";
00309   case NVPTXISD::DeclareRet:
00310     return "NVPTXISD::DeclareRet";
00311   case NVPTXISD::DeclareScalarRet:
00312     return "NVPTXISD::DeclareScalarRet";
00313   case NVPTXISD::DeclareRetParam:
00314     return "NVPTXISD::DeclareRetParam";
00315   case NVPTXISD::PrintCall:
00316     return "NVPTXISD::PrintCall";
00317   case NVPTXISD::PrintCallUni:
00318     return "NVPTXISD::PrintCallUni";
00319   case NVPTXISD::LoadParam:
00320     return "NVPTXISD::LoadParam";
00321   case NVPTXISD::LoadParamV2:
00322     return "NVPTXISD::LoadParamV2";
00323   case NVPTXISD::LoadParamV4:
00324     return "NVPTXISD::LoadParamV4";
00325   case NVPTXISD::StoreParam:
00326     return "NVPTXISD::StoreParam";
00327   case NVPTXISD::StoreParamV2:
00328     return "NVPTXISD::StoreParamV2";
00329   case NVPTXISD::StoreParamV4:
00330     return "NVPTXISD::StoreParamV4";
00331   case NVPTXISD::StoreParamS32:
00332     return "NVPTXISD::StoreParamS32";
00333   case NVPTXISD::StoreParamU32:
00334     return "NVPTXISD::StoreParamU32";
00335   case NVPTXISD::CallArgBegin:
00336     return "NVPTXISD::CallArgBegin";
00337   case NVPTXISD::CallArg:
00338     return "NVPTXISD::CallArg";
00339   case NVPTXISD::LastCallArg:
00340     return "NVPTXISD::LastCallArg";
00341   case NVPTXISD::CallArgEnd:
00342     return "NVPTXISD::CallArgEnd";
00343   case NVPTXISD::CallVoid:
00344     return "NVPTXISD::CallVoid";
00345   case NVPTXISD::CallVal:
00346     return "NVPTXISD::CallVal";
00347   case NVPTXISD::CallSymbol:
00348     return "NVPTXISD::CallSymbol";
00349   case NVPTXISD::Prototype:
00350     return "NVPTXISD::Prototype";
00351   case NVPTXISD::MoveParam:
00352     return "NVPTXISD::MoveParam";
00353   case NVPTXISD::StoreRetval:
00354     return "NVPTXISD::StoreRetval";
00355   case NVPTXISD::StoreRetvalV2:
00356     return "NVPTXISD::StoreRetvalV2";
00357   case NVPTXISD::StoreRetvalV4:
00358     return "NVPTXISD::StoreRetvalV4";
00359   case NVPTXISD::PseudoUseParam:
00360     return "NVPTXISD::PseudoUseParam";
00361   case NVPTXISD::RETURN:
00362     return "NVPTXISD::RETURN";
00363   case NVPTXISD::CallSeqBegin:
00364     return "NVPTXISD::CallSeqBegin";
00365   case NVPTXISD::CallSeqEnd:
00366     return "NVPTXISD::CallSeqEnd";
00367   case NVPTXISD::CallPrototype:
00368     return "NVPTXISD::CallPrototype";
00369   case NVPTXISD::LoadV2:
00370     return "NVPTXISD::LoadV2";
00371   case NVPTXISD::LoadV4:
00372     return "NVPTXISD::LoadV4";
00373   case NVPTXISD::LDGV2:
00374     return "NVPTXISD::LDGV2";
00375   case NVPTXISD::LDGV4:
00376     return "NVPTXISD::LDGV4";
00377   case NVPTXISD::LDUV2:
00378     return "NVPTXISD::LDUV2";
00379   case NVPTXISD::LDUV4:
00380     return "NVPTXISD::LDUV4";
00381   case NVPTXISD::StoreV2:
00382     return "NVPTXISD::StoreV2";
00383   case NVPTXISD::StoreV4:
00384     return "NVPTXISD::StoreV4";
00385   case NVPTXISD::FUN_SHFL_CLAMP:
00386     return "NVPTXISD::FUN_SHFL_CLAMP";
00387   case NVPTXISD::FUN_SHFR_CLAMP:
00388     return "NVPTXISD::FUN_SHFR_CLAMP";
00389   case NVPTXISD::IMAD:
00390     return "NVPTXISD::IMAD";
00391   case NVPTXISD::Dummy:
00392     return "NVPTXISD::Dummy";
00393   case NVPTXISD::MUL_WIDE_SIGNED:
00394     return "NVPTXISD::MUL_WIDE_SIGNED";
00395   case NVPTXISD::MUL_WIDE_UNSIGNED:
00396     return "NVPTXISD::MUL_WIDE_UNSIGNED";
00397   case NVPTXISD::Tex1DFloatS32:        return "NVPTXISD::Tex1DFloatS32";
00398   case NVPTXISD::Tex1DFloatFloat:      return "NVPTXISD::Tex1DFloatFloat";
00399   case NVPTXISD::Tex1DFloatFloatLevel:
00400     return "NVPTXISD::Tex1DFloatFloatLevel";
00401   case NVPTXISD::Tex1DFloatFloatGrad:
00402     return "NVPTXISD::Tex1DFloatFloatGrad";
00403   case NVPTXISD::Tex1DS32S32:          return "NVPTXISD::Tex1DS32S32";
00404   case NVPTXISD::Tex1DS32Float:        return "NVPTXISD::Tex1DS32Float";
00405   case NVPTXISD::Tex1DS32FloatLevel:
00406     return "NVPTXISD::Tex1DS32FloatLevel";
00407   case NVPTXISD::Tex1DS32FloatGrad:
00408     return "NVPTXISD::Tex1DS32FloatGrad";
00409   case NVPTXISD::Tex1DU32S32:          return "NVPTXISD::Tex1DU32S32";
00410   case NVPTXISD::Tex1DU32Float:        return "NVPTXISD::Tex1DU32Float";
00411   case NVPTXISD::Tex1DU32FloatLevel:
00412     return "NVPTXISD::Tex1DU32FloatLevel";
00413   case NVPTXISD::Tex1DU32FloatGrad:
00414     return "NVPTXISD::Tex1DU32FloatGrad";
00415   case NVPTXISD::Tex1DArrayFloatS32:   return "NVPTXISD::Tex1DArrayFloatS32";
00416   case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
00417   case NVPTXISD::Tex1DArrayFloatFloatLevel:
00418     return "NVPTXISD::Tex1DArrayFloatFloatLevel";
00419   case NVPTXISD::Tex1DArrayFloatFloatGrad:
00420     return "NVPTXISD::Tex1DArrayFloatFloatGrad";
00421   case NVPTXISD::Tex1DArrayS32S32:     return "NVPTXISD::Tex1DArrayS32S32";
00422   case NVPTXISD::Tex1DArrayS32Float:   return "NVPTXISD::Tex1DArrayS32Float";
00423   case NVPTXISD::Tex1DArrayS32FloatLevel:
00424     return "NVPTXISD::Tex1DArrayS32FloatLevel";
00425   case NVPTXISD::Tex1DArrayS32FloatGrad:
00426     return "NVPTXISD::Tex1DArrayS32FloatGrad";
00427   case NVPTXISD::Tex1DArrayU32S32:     return "NVPTXISD::Tex1DArrayU32S32";
00428   case NVPTXISD::Tex1DArrayU32Float:   return "NVPTXISD::Tex1DArrayU32Float";
00429   case NVPTXISD::Tex1DArrayU32FloatLevel:
00430     return "NVPTXISD::Tex1DArrayU32FloatLevel";
00431   case NVPTXISD::Tex1DArrayU32FloatGrad:
00432     return "NVPTXISD::Tex1DArrayU32FloatGrad";
00433   case NVPTXISD::Tex2DFloatS32:        return "NVPTXISD::Tex2DFloatS32";
00434   case NVPTXISD::Tex2DFloatFloat:      return "NVPTXISD::Tex2DFloatFloat";
00435   case NVPTXISD::Tex2DFloatFloatLevel:
00436     return "NVPTXISD::Tex2DFloatFloatLevel";
00437   case NVPTXISD::Tex2DFloatFloatGrad:
00438     return "NVPTXISD::Tex2DFloatFloatGrad";
00439   case NVPTXISD::Tex2DS32S32:          return "NVPTXISD::Tex2DS32S32";
00440   case NVPTXISD::Tex2DS32Float:        return "NVPTXISD::Tex2DS32Float";
00441   case NVPTXISD::Tex2DS32FloatLevel:
00442     return "NVPTXISD::Tex2DS32FloatLevel";
00443   case NVPTXISD::Tex2DS32FloatGrad:
00444     return "NVPTXISD::Tex2DS32FloatGrad";
00445   case NVPTXISD::Tex2DU32S32:          return "NVPTXISD::Tex2DU32S32";
00446   case NVPTXISD::Tex2DU32Float:        return "NVPTXISD::Tex2DU32Float";
00447   case NVPTXISD::Tex2DU32FloatLevel:
00448     return "NVPTXISD::Tex2DU32FloatLevel";
00449   case NVPTXISD::Tex2DU32FloatGrad:
00450     return "NVPTXISD::Tex2DU32FloatGrad";
00451   case NVPTXISD::Tex2DArrayFloatS32:   return "NVPTXISD::Tex2DArrayFloatS32";
00452   case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
00453   case NVPTXISD::Tex2DArrayFloatFloatLevel:
00454     return "NVPTXISD::Tex2DArrayFloatFloatLevel";
00455   case NVPTXISD::Tex2DArrayFloatFloatGrad:
00456     return "NVPTXISD::Tex2DArrayFloatFloatGrad";
00457   case NVPTXISD::Tex2DArrayS32S32:     return "NVPTXISD::Tex2DArrayS32S32";
00458   case NVPTXISD::Tex2DArrayS32Float:   return "NVPTXISD::Tex2DArrayS32Float";
00459   case NVPTXISD::Tex2DArrayS32FloatLevel:
00460     return "NVPTXISD::Tex2DArrayS32FloatLevel";
00461   case NVPTXISD::Tex2DArrayS32FloatGrad:
00462     return "NVPTXISD::Tex2DArrayS32FloatGrad";
00463   case NVPTXISD::Tex2DArrayU32S32:     return "NVPTXISD::Tex2DArrayU32S32";
00464   case NVPTXISD::Tex2DArrayU32Float:   return "NVPTXISD::Tex2DArrayU32Float";
00465   case NVPTXISD::Tex2DArrayU32FloatLevel:
00466     return "NVPTXISD::Tex2DArrayU32FloatLevel";
00467   case NVPTXISD::Tex2DArrayU32FloatGrad:
00468     return "NVPTXISD::Tex2DArrayU32FloatGrad";
00469   case NVPTXISD::Tex3DFloatS32:        return "NVPTXISD::Tex3DFloatS32";
00470   case NVPTXISD::Tex3DFloatFloat:      return "NVPTXISD::Tex3DFloatFloat";
00471   case NVPTXISD::Tex3DFloatFloatLevel:
00472     return "NVPTXISD::Tex3DFloatFloatLevel";
00473   case NVPTXISD::Tex3DFloatFloatGrad:
00474     return "NVPTXISD::Tex3DFloatFloatGrad";
00475   case NVPTXISD::Tex3DS32S32:          return "NVPTXISD::Tex3DS32S32";
00476   case NVPTXISD::Tex3DS32Float:        return "NVPTXISD::Tex3DS32Float";
00477   case NVPTXISD::Tex3DS32FloatLevel:
00478     return "NVPTXISD::Tex3DS32FloatLevel";
00479   case NVPTXISD::Tex3DS32FloatGrad:
00480     return "NVPTXISD::Tex3DS32FloatGrad";
00481   case NVPTXISD::Tex3DU32S32:          return "NVPTXISD::Tex3DU32S32";
00482   case NVPTXISD::Tex3DU32Float:        return "NVPTXISD::Tex3DU32Float";
00483   case NVPTXISD::Tex3DU32FloatLevel:
00484     return "NVPTXISD::Tex3DU32FloatLevel";
00485   case NVPTXISD::Tex3DU32FloatGrad:
00486     return "NVPTXISD::Tex3DU32FloatGrad";
00487   case NVPTXISD::TexCubeFloatFloat:      return "NVPTXISD::TexCubeFloatFloat";
00488   case NVPTXISD::TexCubeFloatFloatLevel:
00489     return "NVPTXISD::TexCubeFloatFloatLevel";
00490   case NVPTXISD::TexCubeS32Float:        return "NVPTXISD::TexCubeS32Float";
00491   case NVPTXISD::TexCubeS32FloatLevel:
00492     return "NVPTXISD::TexCubeS32FloatLevel";
00493   case NVPTXISD::TexCubeU32Float:        return "NVPTXISD::TexCubeU32Float";
00494   case NVPTXISD::TexCubeU32FloatLevel:
00495     return "NVPTXISD::TexCubeU32FloatLevel";
00496   case NVPTXISD::TexCubeArrayFloatFloat:
00497     return "NVPTXISD::TexCubeArrayFloatFloat";
00498   case NVPTXISD::TexCubeArrayFloatFloatLevel:
00499     return "NVPTXISD::TexCubeArrayFloatFloatLevel";
00500   case NVPTXISD::TexCubeArrayS32Float:
00501     return "NVPTXISD::TexCubeArrayS32Float";
00502   case NVPTXISD::TexCubeArrayS32FloatLevel:
00503     return "NVPTXISD::TexCubeArrayS32FloatLevel";
00504   case NVPTXISD::TexCubeArrayU32Float:
00505     return "NVPTXISD::TexCubeArrayU32Float";
00506   case NVPTXISD::TexCubeArrayU32FloatLevel:
00507     return "NVPTXISD::TexCubeArrayU32FloatLevel";
00508   case NVPTXISD::Tld4R2DFloatFloat:
00509     return "NVPTXISD::Tld4R2DFloatFloat";
00510   case NVPTXISD::Tld4G2DFloatFloat:
00511     return "NVPTXISD::Tld4G2DFloatFloat";
00512   case NVPTXISD::Tld4B2DFloatFloat:
00513     return "NVPTXISD::Tld4B2DFloatFloat";
00514   case NVPTXISD::Tld4A2DFloatFloat:
00515     return "NVPTXISD::Tld4A2DFloatFloat";
00516   case NVPTXISD::Tld4R2DS64Float:
00517     return "NVPTXISD::Tld4R2DS64Float";
00518   case NVPTXISD::Tld4G2DS64Float:
00519     return "NVPTXISD::Tld4G2DS64Float";
00520   case NVPTXISD::Tld4B2DS64Float:
00521     return "NVPTXISD::Tld4B2DS64Float";
00522   case NVPTXISD::Tld4A2DS64Float:
00523     return "NVPTXISD::Tld4A2DS64Float";
00524   case NVPTXISD::Tld4R2DU64Float:
00525     return "NVPTXISD::Tld4R2DU64Float";
00526   case NVPTXISD::Tld4G2DU64Float:
00527     return "NVPTXISD::Tld4G2DU64Float";
00528   case NVPTXISD::Tld4B2DU64Float:
00529     return "NVPTXISD::Tld4B2DU64Float";
00530   case NVPTXISD::Tld4A2DU64Float:
00531     return "NVPTXISD::Tld4A2DU64Float";
00532 
00533   case NVPTXISD::TexUnified1DFloatS32:
00534     return "NVPTXISD::TexUnified1DFloatS32";
00535   case NVPTXISD::TexUnified1DFloatFloat:
00536     return "NVPTXISD::TexUnified1DFloatFloat";
00537   case NVPTXISD::TexUnified1DFloatFloatLevel:
00538     return "NVPTXISD::TexUnified1DFloatFloatLevel";
00539   case NVPTXISD::TexUnified1DFloatFloatGrad:
00540     return "NVPTXISD::TexUnified1DFloatFloatGrad";
00541   case NVPTXISD::TexUnified1DS32S32:
00542     return "NVPTXISD::TexUnified1DS32S32";
00543   case NVPTXISD::TexUnified1DS32Float:
00544     return "NVPTXISD::TexUnified1DS32Float";
00545   case NVPTXISD::TexUnified1DS32FloatLevel:
00546     return "NVPTXISD::TexUnified1DS32FloatLevel";
00547   case NVPTXISD::TexUnified1DS32FloatGrad:
00548     return "NVPTXISD::TexUnified1DS32FloatGrad";
00549   case NVPTXISD::TexUnified1DU32S32:
00550     return "NVPTXISD::TexUnified1DU32S32";
00551   case NVPTXISD::TexUnified1DU32Float:
00552     return "NVPTXISD::TexUnified1DU32Float";
00553   case NVPTXISD::TexUnified1DU32FloatLevel:
00554     return "NVPTXISD::TexUnified1DU32FloatLevel";
00555   case NVPTXISD::TexUnified1DU32FloatGrad:
00556     return "NVPTXISD::TexUnified1DU32FloatGrad";
00557   case NVPTXISD::TexUnified1DArrayFloatS32:
00558     return "NVPTXISD::TexUnified1DArrayFloatS32";
00559   case NVPTXISD::TexUnified1DArrayFloatFloat:
00560     return "NVPTXISD::TexUnified1DArrayFloatFloat";
00561   case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
00562     return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
00563   case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
00564     return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
00565   case NVPTXISD::TexUnified1DArrayS32S32:
00566     return "NVPTXISD::TexUnified1DArrayS32S32";
00567   case NVPTXISD::TexUnified1DArrayS32Float:
00568     return "NVPTXISD::TexUnified1DArrayS32Float";
00569   case NVPTXISD::TexUnified1DArrayS32FloatLevel:
00570     return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
00571   case NVPTXISD::TexUnified1DArrayS32FloatGrad:
00572     return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
00573   case NVPTXISD::TexUnified1DArrayU32S32:
00574     return "NVPTXISD::TexUnified1DArrayU32S32";
00575   case NVPTXISD::TexUnified1DArrayU32Float:
00576     return "NVPTXISD::TexUnified1DArrayU32Float";
00577   case NVPTXISD::TexUnified1DArrayU32FloatLevel:
00578     return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
00579   case NVPTXISD::TexUnified1DArrayU32FloatGrad:
00580     return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
00581   case NVPTXISD::TexUnified2DFloatS32:
00582     return "NVPTXISD::TexUnified2DFloatS32";
00583   case NVPTXISD::TexUnified2DFloatFloat:
00584     return "NVPTXISD::TexUnified2DFloatFloat";
00585   case NVPTXISD::TexUnified2DFloatFloatLevel:
00586     return "NVPTXISD::TexUnified2DFloatFloatLevel";
00587   case NVPTXISD::TexUnified2DFloatFloatGrad:
00588     return "NVPTXISD::TexUnified2DFloatFloatGrad";
00589   case NVPTXISD::TexUnified2DS32S32:
00590     return "NVPTXISD::TexUnified2DS32S32";
00591   case NVPTXISD::TexUnified2DS32Float:
00592     return "NVPTXISD::TexUnified2DS32Float";
00593   case NVPTXISD::TexUnified2DS32FloatLevel:
00594     return "NVPTXISD::TexUnified2DS32FloatLevel";
00595   case NVPTXISD::TexUnified2DS32FloatGrad:
00596     return "NVPTXISD::TexUnified2DS32FloatGrad";
00597   case NVPTXISD::TexUnified2DU32S32:
00598     return "NVPTXISD::TexUnified2DU32S32";
00599   case NVPTXISD::TexUnified2DU32Float:
00600     return "NVPTXISD::TexUnified2DU32Float";
00601   case NVPTXISD::TexUnified2DU32FloatLevel:
00602     return "NVPTXISD::TexUnified2DU32FloatLevel";
00603   case NVPTXISD::TexUnified2DU32FloatGrad:
00604     return "NVPTXISD::TexUnified2DU32FloatGrad";
00605   case NVPTXISD::TexUnified2DArrayFloatS32:
00606     return "NVPTXISD::TexUnified2DArrayFloatS32";
00607   case NVPTXISD::TexUnified2DArrayFloatFloat:
00608     return "NVPTXISD::TexUnified2DArrayFloatFloat";
00609   case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
00610     return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
00611   case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
00612     return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
00613   case NVPTXISD::TexUnified2DArrayS32S32:
00614     return "NVPTXISD::TexUnified2DArrayS32S32";
00615   case NVPTXISD::TexUnified2DArrayS32Float:
00616     return "NVPTXISD::TexUnified2DArrayS32Float";
00617   case NVPTXISD::TexUnified2DArrayS32FloatLevel:
00618     return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
00619   case NVPTXISD::TexUnified2DArrayS32FloatGrad:
00620     return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
00621   case NVPTXISD::TexUnified2DArrayU32S32:
00622     return "NVPTXISD::TexUnified2DArrayU32S32";
00623   case NVPTXISD::TexUnified2DArrayU32Float:
00624     return "NVPTXISD::TexUnified2DArrayU32Float";
00625   case NVPTXISD::TexUnified2DArrayU32FloatLevel:
00626     return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
00627   case NVPTXISD::TexUnified2DArrayU32FloatGrad:
00628     return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
00629   case NVPTXISD::TexUnified3DFloatS32:
00630     return "NVPTXISD::TexUnified3DFloatS32";
00631   case NVPTXISD::TexUnified3DFloatFloat:
00632     return "NVPTXISD::TexUnified3DFloatFloat";
00633   case NVPTXISD::TexUnified3DFloatFloatLevel:
00634     return "NVPTXISD::TexUnified3DFloatFloatLevel";
00635   case NVPTXISD::TexUnified3DFloatFloatGrad:
00636     return "NVPTXISD::TexUnified3DFloatFloatGrad";
00637   case NVPTXISD::TexUnified3DS32S32:
00638     return "NVPTXISD::TexUnified3DS32S32";
00639   case NVPTXISD::TexUnified3DS32Float:
00640     return "NVPTXISD::TexUnified3DS32Float";
00641   case NVPTXISD::TexUnified3DS32FloatLevel:
00642     return "NVPTXISD::TexUnified3DS32FloatLevel";
00643   case NVPTXISD::TexUnified3DS32FloatGrad:
00644     return "NVPTXISD::TexUnified3DS32FloatGrad";
00645   case NVPTXISD::TexUnified3DU32S32:
00646     return "NVPTXISD::TexUnified3DU32S32";
00647   case NVPTXISD::TexUnified3DU32Float:
00648     return "NVPTXISD::TexUnified3DU32Float";
00649   case NVPTXISD::TexUnified3DU32FloatLevel:
00650     return "NVPTXISD::TexUnified3DU32FloatLevel";
00651   case NVPTXISD::TexUnified3DU32FloatGrad:
00652     return "NVPTXISD::TexUnified3DU32FloatGrad";
00653   case NVPTXISD::TexUnifiedCubeFloatFloat:
00654     return "NVPTXISD::TexUnifiedCubeFloatFloat";
00655   case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
00656     return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
00657   case NVPTXISD::TexUnifiedCubeS32Float:
00658     return "NVPTXISD::TexUnifiedCubeS32Float";
00659   case NVPTXISD::TexUnifiedCubeS32FloatLevel:
00660     return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
00661   case NVPTXISD::TexUnifiedCubeU32Float:
00662     return "NVPTXISD::TexUnifiedCubeU32Float";
00663   case NVPTXISD::TexUnifiedCubeU32FloatLevel:
00664     return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
00665   case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
00666     return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
00667   case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
00668     return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
00669   case NVPTXISD::TexUnifiedCubeArrayS32Float:
00670     return "NVPTXISD::TexUnifiedCubeArrayS32Float";
00671   case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
00672     return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
00673   case NVPTXISD::TexUnifiedCubeArrayU32Float:
00674     return "NVPTXISD::TexUnifiedCubeArrayU32Float";
00675   case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
00676     return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
00677   case NVPTXISD::Tld4UnifiedR2DFloatFloat:
00678     return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
00679   case NVPTXISD::Tld4UnifiedG2DFloatFloat:
00680     return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
00681   case NVPTXISD::Tld4UnifiedB2DFloatFloat:
00682     return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
00683   case NVPTXISD::Tld4UnifiedA2DFloatFloat:
00684     return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
00685   case NVPTXISD::Tld4UnifiedR2DS64Float:
00686     return "NVPTXISD::Tld4UnifiedR2DS64Float";
00687   case NVPTXISD::Tld4UnifiedG2DS64Float:
00688     return "NVPTXISD::Tld4UnifiedG2DS64Float";
00689   case NVPTXISD::Tld4UnifiedB2DS64Float:
00690     return "NVPTXISD::Tld4UnifiedB2DS64Float";
00691   case NVPTXISD::Tld4UnifiedA2DS64Float:
00692     return "NVPTXISD::Tld4UnifiedA2DS64Float";
00693   case NVPTXISD::Tld4UnifiedR2DU64Float:
00694     return "NVPTXISD::Tld4UnifiedR2DU64Float";
00695   case NVPTXISD::Tld4UnifiedG2DU64Float:
00696     return "NVPTXISD::Tld4UnifiedG2DU64Float";
00697   case NVPTXISD::Tld4UnifiedB2DU64Float:
00698     return "NVPTXISD::Tld4UnifiedB2DU64Float";
00699   case NVPTXISD::Tld4UnifiedA2DU64Float:
00700     return "NVPTXISD::Tld4UnifiedA2DU64Float";
00701 
00702   case NVPTXISD::Suld1DI8Clamp:          return "NVPTXISD::Suld1DI8Clamp";
00703   case NVPTXISD::Suld1DI16Clamp:         return "NVPTXISD::Suld1DI16Clamp";
00704   case NVPTXISD::Suld1DI32Clamp:         return "NVPTXISD::Suld1DI32Clamp";
00705   case NVPTXISD::Suld1DI64Clamp:         return "NVPTXISD::Suld1DI64Clamp";
00706   case NVPTXISD::Suld1DV2I8Clamp:        return "NVPTXISD::Suld1DV2I8Clamp";
00707   case NVPTXISD::Suld1DV2I16Clamp:       return "NVPTXISD::Suld1DV2I16Clamp";
00708   case NVPTXISD::Suld1DV2I32Clamp:       return "NVPTXISD::Suld1DV2I32Clamp";
00709   case NVPTXISD::Suld1DV2I64Clamp:       return "NVPTXISD::Suld1DV2I64Clamp";
00710   case NVPTXISD::Suld1DV4I8Clamp:        return "NVPTXISD::Suld1DV4I8Clamp";
00711   case NVPTXISD::Suld1DV4I16Clamp:       return "NVPTXISD::Suld1DV4I16Clamp";
00712   case NVPTXISD::Suld1DV4I32Clamp:       return "NVPTXISD::Suld1DV4I32Clamp";
00713 
00714   case NVPTXISD::Suld1DArrayI8Clamp:   return "NVPTXISD::Suld1DArrayI8Clamp";
00715   case NVPTXISD::Suld1DArrayI16Clamp:  return "NVPTXISD::Suld1DArrayI16Clamp";
00716   case NVPTXISD::Suld1DArrayI32Clamp:  return "NVPTXISD::Suld1DArrayI32Clamp";
00717   case NVPTXISD::Suld1DArrayI64Clamp:  return "NVPTXISD::Suld1DArrayI64Clamp";
00718   case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
00719   case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
00720   case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
00721   case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
00722   case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
00723   case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
00724   case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
00725 
00726   case NVPTXISD::Suld2DI8Clamp:          return "NVPTXISD::Suld2DI8Clamp";
00727   case NVPTXISD::Suld2DI16Clamp:         return "NVPTXISD::Suld2DI16Clamp";
00728   case NVPTXISD::Suld2DI32Clamp:         return "NVPTXISD::Suld2DI32Clamp";
00729   case NVPTXISD::Suld2DI64Clamp:         return "NVPTXISD::Suld2DI64Clamp";
00730   case NVPTXISD::Suld2DV2I8Clamp:        return "NVPTXISD::Suld2DV2I8Clamp";
00731   case NVPTXISD::Suld2DV2I16Clamp:       return "NVPTXISD::Suld2DV2I16Clamp";
00732   case NVPTXISD::Suld2DV2I32Clamp:       return "NVPTXISD::Suld2DV2I32Clamp";
00733   case NVPTXISD::Suld2DV2I64Clamp:       return "NVPTXISD::Suld2DV2I64Clamp";
00734   case NVPTXISD::Suld2DV4I8Clamp:        return "NVPTXISD::Suld2DV4I8Clamp";
00735   case NVPTXISD::Suld2DV4I16Clamp:       return "NVPTXISD::Suld2DV4I16Clamp";
00736   case NVPTXISD::Suld2DV4I32Clamp:       return "NVPTXISD::Suld2DV4I32Clamp";
00737 
00738   case NVPTXISD::Suld2DArrayI8Clamp:   return "NVPTXISD::Suld2DArrayI8Clamp";
00739   case NVPTXISD::Suld2DArrayI16Clamp:  return "NVPTXISD::Suld2DArrayI16Clamp";
00740   case NVPTXISD::Suld2DArrayI32Clamp:  return "NVPTXISD::Suld2DArrayI32Clamp";
00741   case NVPTXISD::Suld2DArrayI64Clamp:  return "NVPTXISD::Suld2DArrayI64Clamp";
00742   case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
00743   case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
00744   case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
00745   case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
00746   case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
00747   case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
00748   case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
00749 
00750   case NVPTXISD::Suld3DI8Clamp:          return "NVPTXISD::Suld3DI8Clamp";
00751   case NVPTXISD::Suld3DI16Clamp:         return "NVPTXISD::Suld3DI16Clamp";
00752   case NVPTXISD::Suld3DI32Clamp:         return "NVPTXISD::Suld3DI32Clamp";
00753   case NVPTXISD::Suld3DI64Clamp:         return "NVPTXISD::Suld3DI64Clamp";
00754   case NVPTXISD::Suld3DV2I8Clamp:        return "NVPTXISD::Suld3DV2I8Clamp";
00755   case NVPTXISD::Suld3DV2I16Clamp:       return "NVPTXISD::Suld3DV2I16Clamp";
00756   case NVPTXISD::Suld3DV2I32Clamp:       return "NVPTXISD::Suld3DV2I32Clamp";
00757   case NVPTXISD::Suld3DV2I64Clamp:       return "NVPTXISD::Suld3DV2I64Clamp";
00758   case NVPTXISD::Suld3DV4I8Clamp:        return "NVPTXISD::Suld3DV4I8Clamp";
00759   case NVPTXISD::Suld3DV4I16Clamp:       return "NVPTXISD::Suld3DV4I16Clamp";
00760   case NVPTXISD::Suld3DV4I32Clamp:       return "NVPTXISD::Suld3DV4I32Clamp";
00761 
00762   case NVPTXISD::Suld1DI8Trap:          return "NVPTXISD::Suld1DI8Trap";
00763   case NVPTXISD::Suld1DI16Trap:         return "NVPTXISD::Suld1DI16Trap";
00764   case NVPTXISD::Suld1DI32Trap:         return "NVPTXISD::Suld1DI32Trap";
00765   case NVPTXISD::Suld1DI64Trap:         return "NVPTXISD::Suld1DI64Trap";
00766   case NVPTXISD::Suld1DV2I8Trap:        return "NVPTXISD::Suld1DV2I8Trap";
00767   case NVPTXISD::Suld1DV2I16Trap:       return "NVPTXISD::Suld1DV2I16Trap";
00768   case NVPTXISD::Suld1DV2I32Trap:       return "NVPTXISD::Suld1DV2I32Trap";
00769   case NVPTXISD::Suld1DV2I64Trap:       return "NVPTXISD::Suld1DV2I64Trap";
00770   case NVPTXISD::Suld1DV4I8Trap:        return "NVPTXISD::Suld1DV4I8Trap";
00771   case NVPTXISD::Suld1DV4I16Trap:       return "NVPTXISD::Suld1DV4I16Trap";
00772   case NVPTXISD::Suld1DV4I32Trap:       return "NVPTXISD::Suld1DV4I32Trap";
00773 
00774   case NVPTXISD::Suld1DArrayI8Trap:     return "NVPTXISD::Suld1DArrayI8Trap";
00775   case NVPTXISD::Suld1DArrayI16Trap:    return "NVPTXISD::Suld1DArrayI16Trap";
00776   case NVPTXISD::Suld1DArrayI32Trap:    return "NVPTXISD::Suld1DArrayI32Trap";
00777   case NVPTXISD::Suld1DArrayI64Trap:    return "NVPTXISD::Suld1DArrayI64Trap";
00778   case NVPTXISD::Suld1DArrayV2I8Trap:   return "NVPTXISD::Suld1DArrayV2I8Trap";
00779   case NVPTXISD::Suld1DArrayV2I16Trap:  return "NVPTXISD::Suld1DArrayV2I16Trap";
00780   case NVPTXISD::Suld1DArrayV2I32Trap:  return "NVPTXISD::Suld1DArrayV2I32Trap";
00781   case NVPTXISD::Suld1DArrayV2I64Trap:  return "NVPTXISD::Suld1DArrayV2I64Trap";
00782   case NVPTXISD::Suld1DArrayV4I8Trap:   return "NVPTXISD::Suld1DArrayV4I8Trap";
00783   case NVPTXISD::Suld1DArrayV4I16Trap:  return "NVPTXISD::Suld1DArrayV4I16Trap";
00784   case NVPTXISD::Suld1DArrayV4I32Trap:  return "NVPTXISD::Suld1DArrayV4I32Trap";
00785 
00786   case NVPTXISD::Suld2DI8Trap:          return "NVPTXISD::Suld2DI8Trap";
00787   case NVPTXISD::Suld2DI16Trap:         return "NVPTXISD::Suld2DI16Trap";
00788   case NVPTXISD::Suld2DI32Trap:         return "NVPTXISD::Suld2DI32Trap";
00789   case NVPTXISD::Suld2DI64Trap:         return "NVPTXISD::Suld2DI64Trap";
00790   case NVPTXISD::Suld2DV2I8Trap:        return "NVPTXISD::Suld2DV2I8Trap";
00791   case NVPTXISD::Suld2DV2I16Trap:       return "NVPTXISD::Suld2DV2I16Trap";
00792   case NVPTXISD::Suld2DV2I32Trap:       return "NVPTXISD::Suld2DV2I32Trap";
00793   case NVPTXISD::Suld2DV2I64Trap:       return "NVPTXISD::Suld2DV2I64Trap";
00794   case NVPTXISD::Suld2DV4I8Trap:        return "NVPTXISD::Suld2DV4I8Trap";
00795   case NVPTXISD::Suld2DV4I16Trap:       return "NVPTXISD::Suld2DV4I16Trap";
00796   case NVPTXISD::Suld2DV4I32Trap:       return "NVPTXISD::Suld2DV4I32Trap";
00797 
00798   case NVPTXISD::Suld2DArrayI8Trap:     return "NVPTXISD::Suld2DArrayI8Trap";
00799   case NVPTXISD::Suld2DArrayI16Trap:    return "NVPTXISD::Suld2DArrayI16Trap";
00800   case NVPTXISD::Suld2DArrayI32Trap:    return "NVPTXISD::Suld2DArrayI32Trap";
00801   case NVPTXISD::Suld2DArrayI64Trap:    return "NVPTXISD::Suld2DArrayI64Trap";
00802   case NVPTXISD::Suld2DArrayV2I8Trap:   return "NVPTXISD::Suld2DArrayV2I8Trap";
00803   case NVPTXISD::Suld2DArrayV2I16Trap:  return "NVPTXISD::Suld2DArrayV2I16Trap";
00804   case NVPTXISD::Suld2DArrayV2I32Trap:  return "NVPTXISD::Suld2DArrayV2I32Trap";
00805   case NVPTXISD::Suld2DArrayV2I64Trap:  return "NVPTXISD::Suld2DArrayV2I64Trap";
00806   case NVPTXISD::Suld2DArrayV4I8Trap:   return "NVPTXISD::Suld2DArrayV4I8Trap";
00807   case NVPTXISD::Suld2DArrayV4I16Trap:  return "NVPTXISD::Suld2DArrayV4I16Trap";
00808   case NVPTXISD::Suld2DArrayV4I32Trap:  return "NVPTXISD::Suld2DArrayV4I32Trap";
00809 
00810   case NVPTXISD::Suld3DI8Trap:          return "NVPTXISD::Suld3DI8Trap";
00811   case NVPTXISD::Suld3DI16Trap:         return "NVPTXISD::Suld3DI16Trap";
00812   case NVPTXISD::Suld3DI32Trap:         return "NVPTXISD::Suld3DI32Trap";
00813   case NVPTXISD::Suld3DI64Trap:         return "NVPTXISD::Suld3DI64Trap";
00814   case NVPTXISD::Suld3DV2I8Trap:        return "NVPTXISD::Suld3DV2I8Trap";
00815   case NVPTXISD::Suld3DV2I16Trap:       return "NVPTXISD::Suld3DV2I16Trap";
00816   case NVPTXISD::Suld3DV2I32Trap:       return "NVPTXISD::Suld3DV2I32Trap";
00817   case NVPTXISD::Suld3DV2I64Trap:       return "NVPTXISD::Suld3DV2I64Trap";
00818   case NVPTXISD::Suld3DV4I8Trap:        return "NVPTXISD::Suld3DV4I8Trap";
00819   case NVPTXISD::Suld3DV4I16Trap:       return "NVPTXISD::Suld3DV4I16Trap";
00820   case NVPTXISD::Suld3DV4I32Trap:       return "NVPTXISD::Suld3DV4I32Trap";
00821 
00822   case NVPTXISD::Suld1DI8Zero:          return "NVPTXISD::Suld1DI8Zero";
00823   case NVPTXISD::Suld1DI16Zero:         return "NVPTXISD::Suld1DI16Zero";
00824   case NVPTXISD::Suld1DI32Zero:         return "NVPTXISD::Suld1DI32Zero";
00825   case NVPTXISD::Suld1DI64Zero:         return "NVPTXISD::Suld1DI64Zero";
00826   case NVPTXISD::Suld1DV2I8Zero:        return "NVPTXISD::Suld1DV2I8Zero";
00827   case NVPTXISD::Suld1DV2I16Zero:       return "NVPTXISD::Suld1DV2I16Zero";
00828   case NVPTXISD::Suld1DV2I32Zero:       return "NVPTXISD::Suld1DV2I32Zero";
00829   case NVPTXISD::Suld1DV2I64Zero:       return "NVPTXISD::Suld1DV2I64Zero";
00830   case NVPTXISD::Suld1DV4I8Zero:        return "NVPTXISD::Suld1DV4I8Zero";
00831   case NVPTXISD::Suld1DV4I16Zero:       return "NVPTXISD::Suld1DV4I16Zero";
00832   case NVPTXISD::Suld1DV4I32Zero:       return "NVPTXISD::Suld1DV4I32Zero";
00833 
00834   case NVPTXISD::Suld1DArrayI8Zero:     return "NVPTXISD::Suld1DArrayI8Zero";
00835   case NVPTXISD::Suld1DArrayI16Zero:    return "NVPTXISD::Suld1DArrayI16Zero";
00836   case NVPTXISD::Suld1DArrayI32Zero:    return "NVPTXISD::Suld1DArrayI32Zero";
00837   case NVPTXISD::Suld1DArrayI64Zero:    return "NVPTXISD::Suld1DArrayI64Zero";
00838   case NVPTXISD::Suld1DArrayV2I8Zero:   return "NVPTXISD::Suld1DArrayV2I8Zero";
00839   case NVPTXISD::Suld1DArrayV2I16Zero:  return "NVPTXISD::Suld1DArrayV2I16Zero";
00840   case NVPTXISD::Suld1DArrayV2I32Zero:  return "NVPTXISD::Suld1DArrayV2I32Zero";
00841   case NVPTXISD::Suld1DArrayV2I64Zero:  return "NVPTXISD::Suld1DArrayV2I64Zero";
00842   case NVPTXISD::Suld1DArrayV4I8Zero:   return "NVPTXISD::Suld1DArrayV4I8Zero";
00843   case NVPTXISD::Suld1DArrayV4I16Zero:  return "NVPTXISD::Suld1DArrayV4I16Zero";
00844   case NVPTXISD::Suld1DArrayV4I32Zero:  return "NVPTXISD::Suld1DArrayV4I32Zero";
00845 
00846   case NVPTXISD::Suld2DI8Zero:          return "NVPTXISD::Suld2DI8Zero";
00847   case NVPTXISD::Suld2DI16Zero:         return "NVPTXISD::Suld2DI16Zero";
00848   case NVPTXISD::Suld2DI32Zero:         return "NVPTXISD::Suld2DI32Zero";
00849   case NVPTXISD::Suld2DI64Zero:         return "NVPTXISD::Suld2DI64Zero";
00850   case NVPTXISD::Suld2DV2I8Zero:        return "NVPTXISD::Suld2DV2I8Zero";
00851   case NVPTXISD::Suld2DV2I16Zero:       return "NVPTXISD::Suld2DV2I16Zero";
00852   case NVPTXISD::Suld2DV2I32Zero:       return "NVPTXISD::Suld2DV2I32Zero";
00853   case NVPTXISD::Suld2DV2I64Zero:       return "NVPTXISD::Suld2DV2I64Zero";
00854   case NVPTXISD::Suld2DV4I8Zero:        return "NVPTXISD::Suld2DV4I8Zero";
00855   case NVPTXISD::Suld2DV4I16Zero:       return "NVPTXISD::Suld2DV4I16Zero";
00856   case NVPTXISD::Suld2DV4I32Zero:       return "NVPTXISD::Suld2DV4I32Zero";
00857 
00858   case NVPTXISD::Suld2DArrayI8Zero:     return "NVPTXISD::Suld2DArrayI8Zero";
00859   case NVPTXISD::Suld2DArrayI16Zero:    return "NVPTXISD::Suld2DArrayI16Zero";
00860   case NVPTXISD::Suld2DArrayI32Zero:    return "NVPTXISD::Suld2DArrayI32Zero";
00861   case NVPTXISD::Suld2DArrayI64Zero:    return "NVPTXISD::Suld2DArrayI64Zero";
00862   case NVPTXISD::Suld2DArrayV2I8Zero:   return "NVPTXISD::Suld2DArrayV2I8Zero";
00863   case NVPTXISD::Suld2DArrayV2I16Zero:  return "NVPTXISD::Suld2DArrayV2I16Zero";
00864   case NVPTXISD::Suld2DArrayV2I32Zero:  return "NVPTXISD::Suld2DArrayV2I32Zero";
00865   case NVPTXISD::Suld2DArrayV2I64Zero:  return "NVPTXISD::Suld2DArrayV2I64Zero";
00866   case NVPTXISD::Suld2DArrayV4I8Zero:   return "NVPTXISD::Suld2DArrayV4I8Zero";
00867   case NVPTXISD::Suld2DArrayV4I16Zero:  return "NVPTXISD::Suld2DArrayV4I16Zero";
00868   case NVPTXISD::Suld2DArrayV4I32Zero:  return "NVPTXISD::Suld2DArrayV4I32Zero";
00869 
00870   case NVPTXISD::Suld3DI8Zero:          return "NVPTXISD::Suld3DI8Zero";
00871   case NVPTXISD::Suld3DI16Zero:         return "NVPTXISD::Suld3DI16Zero";
00872   case NVPTXISD::Suld3DI32Zero:         return "NVPTXISD::Suld3DI32Zero";
00873   case NVPTXISD::Suld3DI64Zero:         return "NVPTXISD::Suld3DI64Zero";
00874   case NVPTXISD::Suld3DV2I8Zero:        return "NVPTXISD::Suld3DV2I8Zero";
00875   case NVPTXISD::Suld3DV2I16Zero:       return "NVPTXISD::Suld3DV2I16Zero";
00876   case NVPTXISD::Suld3DV2I32Zero:       return "NVPTXISD::Suld3DV2I32Zero";
00877   case NVPTXISD::Suld3DV2I64Zero:       return "NVPTXISD::Suld3DV2I64Zero";
00878   case NVPTXISD::Suld3DV4I8Zero:        return "NVPTXISD::Suld3DV4I8Zero";
00879   case NVPTXISD::Suld3DV4I16Zero:       return "NVPTXISD::Suld3DV4I16Zero";
00880   case NVPTXISD::Suld3DV4I32Zero:       return "NVPTXISD::Suld3DV4I32Zero";
00881   }
00882   return nullptr;
00883 }
00884 
00885 TargetLoweringBase::LegalizeTypeAction
00886 NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
00887   if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
00888     return TypeSplitVector;
00889 
00890   return TargetLoweringBase::getPreferredVectorAction(VT);
00891 }
00892 
00893 SDValue
00894 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
00895   SDLoc dl(Op);
00896   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
00897   auto PtrVT = getPointerTy(DAG.getDataLayout());
00898   Op = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
00899   return DAG.getNode(NVPTXISD::Wrapper, dl, PtrVT, Op);
00900 }
00901 
00902 std::string NVPTXTargetLowering::getPrototype(
00903     const DataLayout &DL, Type *retTy, const ArgListTy &Args,
00904     const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment,
00905     const ImmutableCallSite *CS) const {
00906   auto PtrVT = getPointerTy(DL);
00907 
00908   bool isABI = (STI.getSmVersion() >= 20);
00909   assert(isABI && "Non-ABI compilation is not supported");
00910   if (!isABI)
00911     return "";
00912 
00913   std::stringstream O;
00914   O << "prototype_" << uniqueCallSite << " : .callprototype ";
00915 
00916   if (retTy->getTypeID() == Type::VoidTyID) {
00917     O << "()";
00918   } else {
00919     O << "(";
00920     if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
00921       unsigned size = 0;
00922       if (auto *ITy = dyn_cast<IntegerType>(retTy)) {
00923         size = ITy->getBitWidth();
00924         if (size < 32)
00925           size = 32;
00926       } else {
00927         assert(retTy->isFloatingPointTy() &&
00928                "Floating point type expected here");
00929         size = retTy->getPrimitiveSizeInBits();
00930       }
00931 
00932       O << ".param .b" << size << " _";
00933     } else if (isa<PointerType>(retTy)) {
00934       O << ".param .b" << PtrVT.getSizeInBits() << " _";
00935     } else if ((retTy->getTypeID() == Type::StructTyID) ||
00936                isa<VectorType>(retTy)) {
00937       auto &DL = CS->getCalledFunction()->getParent()->getDataLayout();
00938       O << ".param .align " << retAlignment << " .b8 _["
00939         << DL.getTypeAllocSize(retTy) << "]";
00940     } else {
00941       llvm_unreachable("Unknown return type");
00942     }
00943     O << ") ";
00944   }
00945   O << "_ (";
00946 
00947   bool first = true;
00948 
00949   unsigned OIdx = 0;
00950   for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
00951     Type *Ty = Args[i].Ty;
00952     if (!first) {
00953       O << ", ";
00954     }
00955     first = false;
00956 
00957     if (!Outs[OIdx].Flags.isByVal()) {
00958       if (Ty->isAggregateType() || Ty->isVectorTy()) {
00959         unsigned align = 0;
00960         const CallInst *CallI = cast<CallInst>(CS->getInstruction());
00961         // +1 because index 0 is reserved for return type alignment
00962         if (!llvm::getAlign(*CallI, i + 1, align))
00963           align = DL.getABITypeAlignment(Ty);
00964         unsigned sz = DL.getTypeAllocSize(Ty);
00965         O << ".param .align " << align << " .b8 ";
00966         O << "_";
00967         O << "[" << sz << "]";
00968         // update the index for Outs
00969         SmallVector<EVT, 16> vtparts;
00970         ComputeValueVTs(*this, DL, Ty, vtparts);
00971         if (unsigned len = vtparts.size())
00972           OIdx += len - 1;
00973         continue;
00974       }
00975        // i8 types in IR will be i16 types in SDAG
00976       assert((getValueType(DL, Ty) == Outs[OIdx].VT ||
00977               (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
00978              "type mismatch between callee prototype and arguments");
00979       // scalar type
00980       unsigned sz = 0;
00981       if (isa<IntegerType>(Ty)) {
00982         sz = cast<IntegerType>(Ty)->getBitWidth();
00983         if (sz < 32)
00984           sz = 32;
00985       } else if (isa<PointerType>(Ty))
00986         sz = PtrVT.getSizeInBits();
00987       else
00988         sz = Ty->getPrimitiveSizeInBits();
00989       O << ".param .b" << sz << " ";
00990       O << "_";
00991       continue;
00992     }
00993     auto *PTy = dyn_cast<PointerType>(Ty);
00994     assert(PTy && "Param with byval attribute should be a pointer type");
00995     Type *ETy = PTy->getElementType();
00996 
00997     unsigned align = Outs[OIdx].Flags.getByValAlign();
00998     unsigned sz = DL.getTypeAllocSize(ETy);
00999     O << ".param .align " << align << " .b8 ";
01000     O << "_";
01001     O << "[" << sz << "]";
01002   }
01003   O << ");";
01004   return O.str();
01005 }
01006 
01007 unsigned
01008 NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
01009                                           const ImmutableCallSite *CS,
01010                                           Type *Ty,
01011                                           unsigned Idx) const {
01012   unsigned Align = 0;
01013   const Value *DirectCallee = CS->getCalledFunction();
01014 
01015   if (!DirectCallee) {
01016     // We don't have a direct function symbol, but that may be because of
01017     // constant cast instructions in the call.
01018     const Instruction *CalleeI = CS->getInstruction();
01019     assert(CalleeI && "Call target is not a function or derived value?");
01020 
01021     // With bitcast'd call targets, the instruction will be the call
01022     if (isa<CallInst>(CalleeI)) {
01023       // Check if we have call alignment metadata
01024       if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
01025         return Align;
01026 
01027       const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
01028       // Ignore any bitcast instructions
01029       while(isa<ConstantExpr>(CalleeV)) {
01030         const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
01031         if (!CE->isCast())
01032           break;
01033         // Look through the bitcast
01034         CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
01035       }
01036 
01037       // We have now looked past all of the bitcasts.  Do we finally have a
01038       // Function?
01039       if (isa<Function>(CalleeV))
01040         DirectCallee = CalleeV;
01041     }
01042   }
01043 
01044   // Check for function alignment information if we found that the
01045   // ultimate target is a Function
01046   if (DirectCallee)
01047     if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
01048       return Align;
01049 
01050   // Call is indirect or alignment information is not available, fall back to
01051   // the ABI type alignment
01052   auto &DL = CS->getCaller()->getParent()->getDataLayout();
01053   return DL.getABITypeAlignment(Ty);
01054 }
01055 
01056 SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
01057                                        SmallVectorImpl<SDValue> &InVals) const {
01058   SelectionDAG &DAG = CLI.DAG;
01059   SDLoc dl = CLI.DL;
01060   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
01061   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
01062   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
01063   SDValue Chain = CLI.Chain;
01064   SDValue Callee = CLI.Callee;
01065   bool &isTailCall = CLI.IsTailCall;
01066   ArgListTy &Args = CLI.getArgs();
01067   Type *retTy = CLI.RetTy;
01068   ImmutableCallSite *CS = CLI.CS;
01069 
01070   bool isABI = (STI.getSmVersion() >= 20);
01071   assert(isABI && "Non-ABI compilation is not supported");
01072   if (!isABI)
01073     return Chain;
01074   MachineFunction &MF = DAG.getMachineFunction();
01075   const Function *F = MF.getFunction();
01076   auto &DL = MF.getDataLayout();
01077 
01078   SDValue tempChain = Chain;
01079   Chain = DAG.getCALLSEQ_START(Chain,
01080                                DAG.getIntPtrConstant(uniqueCallSite, dl, true),
01081                                dl);
01082   SDValue InFlag = Chain.getValue(1);
01083 
01084   unsigned paramCount = 0;
01085   // Args.size() and Outs.size() need not match.
01086   // Outs.size() will be larger
01087   //   * if there is an aggregate argument with multiple fields (each field
01088   //     showing up separately in Outs)
01089   //   * if there is a vector argument with more than typical vector-length
01090   //     elements (generally if more than 4) where each vector element is
01091   //     individually present in Outs.
01092   // So a different index should be used for indexing into Outs/OutVals.
01093   // See similar issue in LowerFormalArguments.
01094   unsigned OIdx = 0;
01095   // Declare the .params or .reg need to pass values
01096   // to the function
01097   for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
01098     EVT VT = Outs[OIdx].VT;
01099     Type *Ty = Args[i].Ty;
01100 
01101     if (!Outs[OIdx].Flags.isByVal()) {
01102       if (Ty->isAggregateType()) {
01103         // aggregate
01104         SmallVector<EVT, 16> vtparts;
01105         SmallVector<uint64_t, 16> Offsets;
01106         ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts, &Offsets,
01107                            0);
01108 
01109         unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
01110         // declare .param .align <align> .b8 .param<n>[<size>];
01111         unsigned sz = DL.getTypeAllocSize(Ty);
01112         SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01113         SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, dl,
01114                                                              MVT::i32),
01115                                       DAG.getConstant(paramCount, dl, MVT::i32),
01116                                       DAG.getConstant(sz, dl, MVT::i32),
01117                                       InFlag };
01118         Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
01119                             DeclareParamOps);
01120         InFlag = Chain.getValue(1);
01121         for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
01122           EVT elemtype = vtparts[j];
01123           unsigned ArgAlign = GreatestCommonDivisor64(align, Offsets[j]);
01124           if (elemtype.isInteger() && (sz < 8))
01125             sz = 8;
01126           SDValue StVal = OutVals[OIdx];
01127           if (elemtype.getSizeInBits() < 16) {
01128             StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
01129           }
01130           SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01131           SDValue CopyParamOps[] = { Chain,
01132                                      DAG.getConstant(paramCount, dl, MVT::i32),
01133                                      DAG.getConstant(Offsets[j], dl, MVT::i32),
01134                                      StVal, InFlag };
01135           Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
01136                                           CopyParamVTs, CopyParamOps,
01137                                           elemtype, MachinePointerInfo(),
01138                                           ArgAlign);
01139           InFlag = Chain.getValue(1);
01140           ++OIdx;
01141         }
01142         if (vtparts.size() > 0)
01143           --OIdx;
01144         ++paramCount;
01145         continue;
01146       }
01147       if (Ty->isVectorTy()) {
01148         EVT ObjectVT = getValueType(DL, Ty);
01149         unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
01150         // declare .param .align <align> .b8 .param<n>[<size>];
01151         unsigned sz = DL.getTypeAllocSize(Ty);
01152         SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01153         SDValue DeclareParamOps[] = { Chain,
01154                                       DAG.getConstant(align, dl, MVT::i32),
01155                                       DAG.getConstant(paramCount, dl, MVT::i32),
01156                                       DAG.getConstant(sz, dl, MVT::i32),
01157                                       InFlag };
01158         Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
01159                             DeclareParamOps);
01160         InFlag = Chain.getValue(1);
01161         unsigned NumElts = ObjectVT.getVectorNumElements();
01162         EVT EltVT = ObjectVT.getVectorElementType();
01163         EVT MemVT = EltVT;
01164         bool NeedExtend = false;
01165         if (EltVT.getSizeInBits() < 16) {
01166           NeedExtend = true;
01167           EltVT = MVT::i16;
01168         }
01169 
01170         // V1 store
01171         if (NumElts == 1) {
01172           SDValue Elt = OutVals[OIdx++];
01173           if (NeedExtend)
01174             Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
01175 
01176           SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01177           SDValue CopyParamOps[] = { Chain,
01178                                      DAG.getConstant(paramCount, dl, MVT::i32),
01179                                      DAG.getConstant(0, dl, MVT::i32), Elt,
01180                                      InFlag };
01181           Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
01182                                           CopyParamVTs, CopyParamOps,
01183                                           MemVT, MachinePointerInfo());
01184           InFlag = Chain.getValue(1);
01185         } else if (NumElts == 2) {
01186           SDValue Elt0 = OutVals[OIdx++];
01187           SDValue Elt1 = OutVals[OIdx++];
01188           if (NeedExtend) {
01189             Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
01190             Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
01191           }
01192 
01193           SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01194           SDValue CopyParamOps[] = { Chain,
01195                                      DAG.getConstant(paramCount, dl, MVT::i32),
01196                                      DAG.getConstant(0, dl, MVT::i32), Elt0,
01197                                      Elt1, InFlag };
01198           Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
01199                                           CopyParamVTs, CopyParamOps,
01200                                           MemVT, MachinePointerInfo());
01201           InFlag = Chain.getValue(1);
01202         } else {
01203           unsigned curOffset = 0;
01204           // V4 stores
01205           // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
01206           // the
01207           // vector will be expanded to a power of 2 elements, so we know we can
01208           // always round up to the next multiple of 4 when creating the vector
01209           // stores.
01210           // e.g.  4 elem => 1 st.v4
01211           //       6 elem => 2 st.v4
01212           //       8 elem => 2 st.v4
01213           //      11 elem => 3 st.v4
01214           unsigned VecSize = 4;
01215           if (EltVT.getSizeInBits() == 64)
01216             VecSize = 2;
01217 
01218           // This is potentially only part of a vector, so assume all elements
01219           // are packed together.
01220           unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
01221 
01222           for (unsigned i = 0; i < NumElts; i += VecSize) {
01223             // Get values
01224             SDValue StoreVal;
01225             SmallVector<SDValue, 8> Ops;
01226             Ops.push_back(Chain);
01227             Ops.push_back(DAG.getConstant(paramCount, dl, MVT::i32));
01228             Ops.push_back(DAG.getConstant(curOffset, dl, MVT::i32));
01229 
01230             unsigned Opc = NVPTXISD::StoreParamV2;
01231 
01232             StoreVal = OutVals[OIdx++];
01233             if (NeedExtend)
01234               StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
01235             Ops.push_back(StoreVal);
01236 
01237             if (i + 1 < NumElts) {
01238               StoreVal = OutVals[OIdx++];
01239               if (NeedExtend)
01240                 StoreVal =
01241                     DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
01242             } else {
01243               StoreVal = DAG.getUNDEF(EltVT);
01244             }
01245             Ops.push_back(StoreVal);
01246 
01247             if (VecSize == 4) {
01248               Opc = NVPTXISD::StoreParamV4;
01249               if (i + 2 < NumElts) {
01250                 StoreVal = OutVals[OIdx++];
01251                 if (NeedExtend)
01252                   StoreVal =
01253                       DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
01254               } else {
01255                 StoreVal = DAG.getUNDEF(EltVT);
01256               }
01257               Ops.push_back(StoreVal);
01258 
01259               if (i + 3 < NumElts) {
01260                 StoreVal = OutVals[OIdx++];
01261                 if (NeedExtend)
01262                   StoreVal =
01263                       DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
01264               } else {
01265                 StoreVal = DAG.getUNDEF(EltVT);
01266               }
01267               Ops.push_back(StoreVal);
01268             }
01269 
01270             Ops.push_back(InFlag);
01271 
01272             SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01273             Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
01274                                             MemVT, MachinePointerInfo());
01275             InFlag = Chain.getValue(1);
01276             curOffset += PerStoreOffset;
01277           }
01278         }
01279         ++paramCount;
01280         --OIdx;
01281         continue;
01282       }
01283       // Plain scalar
01284       // for ABI,    declare .param .b<size> .param<n>;
01285       unsigned sz = VT.getSizeInBits();
01286       bool needExtend = false;
01287       if (VT.isInteger()) {
01288         if (sz < 16)
01289           needExtend = true;
01290         if (sz < 32)
01291           sz = 32;
01292       }
01293       SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01294       SDValue DeclareParamOps[] = { Chain,
01295                                     DAG.getConstant(paramCount, dl, MVT::i32),
01296                                     DAG.getConstant(sz, dl, MVT::i32),
01297                                     DAG.getConstant(0, dl, MVT::i32), InFlag };
01298       Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
01299                           DeclareParamOps);
01300       InFlag = Chain.getValue(1);
01301       SDValue OutV = OutVals[OIdx];
01302       if (needExtend) {
01303         // zext/sext i1 to i16
01304         unsigned opc = ISD::ZERO_EXTEND;
01305         if (Outs[OIdx].Flags.isSExt())
01306           opc = ISD::SIGN_EXTEND;
01307         OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
01308       }
01309       SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01310       SDValue CopyParamOps[] = { Chain,
01311                                  DAG.getConstant(paramCount, dl, MVT::i32),
01312                                  DAG.getConstant(0, dl, MVT::i32), OutV,
01313                                  InFlag };
01314 
01315       unsigned opcode = NVPTXISD::StoreParam;
01316       if (Outs[OIdx].Flags.isZExt())
01317         opcode = NVPTXISD::StoreParamU32;
01318       else if (Outs[OIdx].Flags.isSExt())
01319         opcode = NVPTXISD::StoreParamS32;
01320       Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
01321                                       VT, MachinePointerInfo());
01322 
01323       InFlag = Chain.getValue(1);
01324       ++paramCount;
01325       continue;
01326     }
01327     // struct or vector
01328     SmallVector<EVT, 16> vtparts;
01329     SmallVector<uint64_t, 16> Offsets;
01330     auto *PTy = dyn_cast<PointerType>(Args[i].Ty);
01331     assert(PTy && "Type of a byval parameter should be pointer");
01332     ComputePTXValueVTs(*this, DAG.getDataLayout(), PTy->getElementType(),
01333                        vtparts, &Offsets, 0);
01334 
01335     // declare .param .align <align> .b8 .param<n>[<size>];
01336     unsigned sz = Outs[OIdx].Flags.getByValSize();
01337     SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01338     unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
01339     // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
01340     // so we don't need to worry about natural alignment or not.
01341     // See TargetLowering::LowerCallTo().
01342     SDValue DeclareParamOps[] = {
01343       Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), dl, MVT::i32),
01344       DAG.getConstant(paramCount, dl, MVT::i32),
01345       DAG.getConstant(sz, dl, MVT::i32), InFlag
01346     };
01347     Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
01348                         DeclareParamOps);
01349     InFlag = Chain.getValue(1);
01350     for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
01351       EVT elemtype = vtparts[j];
01352       int curOffset = Offsets[j];
01353       unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
01354       auto PtrVT = getPointerTy(DAG.getDataLayout());
01355       SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx],
01356                                     DAG.getConstant(curOffset, dl, PtrVT));
01357       SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
01358                                    MachinePointerInfo(), false, false, false,
01359                                    PartAlign);
01360       if (elemtype.getSizeInBits() < 16) {
01361         theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
01362       }
01363       SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01364       SDValue CopyParamOps[] = { Chain,
01365                                  DAG.getConstant(paramCount, dl, MVT::i32),
01366                                  DAG.getConstant(curOffset, dl, MVT::i32),
01367                                  theVal, InFlag };
01368       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
01369                                       CopyParamOps, elemtype,
01370                                       MachinePointerInfo());
01371 
01372       InFlag = Chain.getValue(1);
01373     }
01374     ++paramCount;
01375   }
01376 
01377   GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
01378   unsigned retAlignment = 0;
01379 
01380   // Handle Result
01381   if (Ins.size() > 0) {
01382     SmallVector<EVT, 16> resvtparts;
01383     ComputeValueVTs(*this, DL, retTy, resvtparts);
01384 
01385     // Declare
01386     //  .param .align 16 .b8 retval0[<size-in-bytes>], or
01387     //  .param .b<size-in-bits> retval0
01388     unsigned resultsz = DL.getTypeAllocSizeInBits(retTy);
01389     // Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
01390     // these three types to match the logic in
01391     // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
01392     // Plus, this behavior is consistent with nvcc's.
01393     if (retTy->isFloatingPointTy() || retTy->isIntegerTy() ||
01394         retTy->isPointerTy()) {
01395       // Scalar needs to be at least 32bit wide
01396       if (resultsz < 32)
01397         resultsz = 32;
01398       SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01399       SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
01400                                   DAG.getConstant(resultsz, dl, MVT::i32),
01401                                   DAG.getConstant(0, dl, MVT::i32), InFlag };
01402       Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
01403                           DeclareRetOps);
01404       InFlag = Chain.getValue(1);
01405     } else {
01406       retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
01407       SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01408       SDValue DeclareRetOps[] = { Chain,
01409                                   DAG.getConstant(retAlignment, dl, MVT::i32),
01410                                   DAG.getConstant(resultsz / 8, dl, MVT::i32),
01411                                   DAG.getConstant(0, dl, MVT::i32), InFlag };
01412       Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
01413                           DeclareRetOps);
01414       InFlag = Chain.getValue(1);
01415     }
01416   }
01417 
01418   if (!Func) {
01419     // This is indirect function call case : PTX requires a prototype of the
01420     // form
01421     // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
01422     // to be emitted, and the label has to used as the last arg of call
01423     // instruction.
01424     // The prototype is embedded in a string and put as the operand for a
01425     // CallPrototype SDNode which will print out to the value of the string.
01426     SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01427     std::string Proto =
01428         getPrototype(DAG.getDataLayout(), retTy, Args, Outs, retAlignment, CS);
01429     const char *ProtoStr =
01430       nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
01431     SDValue ProtoOps[] = {
01432       Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
01433     };
01434     Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
01435     InFlag = Chain.getValue(1);
01436   }
01437   // Op to just print "call"
01438   SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01439   SDValue PrintCallOps[] = {
01440     Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InFlag
01441   };
01442   Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
01443                       dl, PrintCallVTs, PrintCallOps);
01444   InFlag = Chain.getValue(1);
01445 
01446   // Ops to print out the function name
01447   SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01448   SDValue CallVoidOps[] = { Chain, Callee, InFlag };
01449   Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
01450   InFlag = Chain.getValue(1);
01451 
01452   // Ops to print out the param list
01453   SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01454   SDValue CallArgBeginOps[] = { Chain, InFlag };
01455   Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
01456                       CallArgBeginOps);
01457   InFlag = Chain.getValue(1);
01458 
01459   for (unsigned i = 0, e = paramCount; i != e; ++i) {
01460     unsigned opcode;
01461     if (i == (e - 1))
01462       opcode = NVPTXISD::LastCallArg;
01463     else
01464       opcode = NVPTXISD::CallArg;
01465     SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01466     SDValue CallArgOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
01467                              DAG.getConstant(i, dl, MVT::i32), InFlag };
01468     Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
01469     InFlag = Chain.getValue(1);
01470   }
01471   SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01472   SDValue CallArgEndOps[] = { Chain,
01473                               DAG.getConstant(Func ? 1 : 0, dl, MVT::i32),
01474                               InFlag };
01475   Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
01476   InFlag = Chain.getValue(1);
01477 
01478   if (!Func) {
01479     SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01480     SDValue PrototypeOps[] = { Chain,
01481                                DAG.getConstant(uniqueCallSite, dl, MVT::i32),
01482                                InFlag };
01483     Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
01484     InFlag = Chain.getValue(1);
01485   }
01486 
01487   // Generate loads from param memory/moves from registers for result
01488   if (Ins.size() > 0) {
01489     if (retTy && retTy->isVectorTy()) {
01490       EVT ObjectVT = getValueType(DL, retTy);
01491       unsigned NumElts = ObjectVT.getVectorNumElements();
01492       EVT EltVT = ObjectVT.getVectorElementType();
01493       assert(STI.getTargetLowering()->getNumRegisters(F->getContext(),
01494                                                       ObjectVT) == NumElts &&
01495              "Vector was not scalarized");
01496       unsigned sz = EltVT.getSizeInBits();
01497       bool needTruncate = sz < 8;
01498 
01499       if (NumElts == 1) {
01500         // Just a simple load
01501         SmallVector<EVT, 4> LoadRetVTs;
01502         if (EltVT == MVT::i1 || EltVT == MVT::i8) {
01503           // If loading i1/i8 result, generate
01504           //   load.b8 i16
01505           //   if i1
01506           //   trunc i16 to i1
01507           LoadRetVTs.push_back(MVT::i16);
01508         } else
01509           LoadRetVTs.push_back(EltVT);
01510         LoadRetVTs.push_back(MVT::Other);
01511         LoadRetVTs.push_back(MVT::Glue);
01512         SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
01513                                 DAG.getConstant(0, dl, MVT::i32), InFlag};
01514         SDValue retval = DAG.getMemIntrinsicNode(
01515             NVPTXISD::LoadParam, dl,
01516             DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
01517         Chain = retval.getValue(1);
01518         InFlag = retval.getValue(2);
01519         SDValue Ret0 = retval;
01520         if (needTruncate)
01521           Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
01522         InVals.push_back(Ret0);
01523       } else if (NumElts == 2) {
01524         // LoadV2
01525         SmallVector<EVT, 4> LoadRetVTs;
01526         if (EltVT == MVT::i1 || EltVT == MVT::i8) {
01527           // If loading i1/i8 result, generate
01528           //   load.b8 i16
01529           //   if i1
01530           //   trunc i16 to i1
01531           LoadRetVTs.push_back(MVT::i16);
01532           LoadRetVTs.push_back(MVT::i16);
01533         } else {
01534           LoadRetVTs.push_back(EltVT);
01535           LoadRetVTs.push_back(EltVT);
01536         }
01537         LoadRetVTs.push_back(MVT::Other);
01538         LoadRetVTs.push_back(MVT::Glue);
01539         SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
01540                                 DAG.getConstant(0, dl, MVT::i32), InFlag};
01541         SDValue retval = DAG.getMemIntrinsicNode(
01542             NVPTXISD::LoadParamV2, dl,
01543             DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
01544         Chain = retval.getValue(2);
01545         InFlag = retval.getValue(3);
01546         SDValue Ret0 = retval.getValue(0);
01547         SDValue Ret1 = retval.getValue(1);
01548         if (needTruncate) {
01549           Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
01550           InVals.push_back(Ret0);
01551           Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
01552           InVals.push_back(Ret1);
01553         } else {
01554           InVals.push_back(Ret0);
01555           InVals.push_back(Ret1);
01556         }
01557       } else {
01558         // Split into N LoadV4
01559         unsigned Ofst = 0;
01560         unsigned VecSize = 4;
01561         unsigned Opc = NVPTXISD::LoadParamV4;
01562         if (EltVT.getSizeInBits() == 64) {
01563           VecSize = 2;
01564           Opc = NVPTXISD::LoadParamV2;
01565         }
01566         EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
01567         for (unsigned i = 0; i < NumElts; i += VecSize) {
01568           SmallVector<EVT, 8> LoadRetVTs;
01569           if (EltVT == MVT::i1 || EltVT == MVT::i8) {
01570             // If loading i1/i8 result, generate
01571             //   load.b8 i16
01572             //   if i1
01573             //   trunc i16 to i1
01574             for (unsigned j = 0; j < VecSize; ++j)
01575               LoadRetVTs.push_back(MVT::i16);
01576           } else {
01577             for (unsigned j = 0; j < VecSize; ++j)
01578               LoadRetVTs.push_back(EltVT);
01579           }
01580           LoadRetVTs.push_back(MVT::Other);
01581           LoadRetVTs.push_back(MVT::Glue);
01582           SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
01583                                   DAG.getConstant(Ofst, dl, MVT::i32), InFlag};
01584           SDValue retval = DAG.getMemIntrinsicNode(
01585               Opc, dl, DAG.getVTList(LoadRetVTs),
01586               LoadRetOps, EltVT, MachinePointerInfo());
01587           if (VecSize == 2) {
01588             Chain = retval.getValue(2);
01589             InFlag = retval.getValue(3);
01590           } else {
01591             Chain = retval.getValue(4);
01592             InFlag = retval.getValue(5);
01593           }
01594 
01595           for (unsigned j = 0; j < VecSize; ++j) {
01596             if (i + j >= NumElts)
01597               break;
01598             SDValue Elt = retval.getValue(j);
01599             if (needTruncate)
01600               Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
01601             InVals.push_back(Elt);
01602           }
01603           Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
01604         }
01605       }
01606     } else {
01607       SmallVector<EVT, 16> VTs;
01608       SmallVector<uint64_t, 16> Offsets;
01609       ComputePTXValueVTs(*this, DAG.getDataLayout(), retTy, VTs, &Offsets, 0);
01610       assert(VTs.size() == Ins.size() && "Bad value decomposition");
01611       unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0);
01612       for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
01613         unsigned sz = VTs[i].getSizeInBits();
01614         unsigned AlignI = GreatestCommonDivisor64(RetAlign, Offsets[i]);
01615         bool needTruncate = sz < 8;
01616         if (VTs[i].isInteger() && (sz < 8))
01617           sz = 8;
01618 
01619         SmallVector<EVT, 4> LoadRetVTs;
01620         EVT TheLoadType = VTs[i];
01621         if (retTy->isIntegerTy() && DL.getTypeAllocSizeInBits(retTy) < 32) {
01622           // This is for integer types only, and specifically not for
01623           // aggregates.
01624           LoadRetVTs.push_back(MVT::i32);
01625           TheLoadType = MVT::i32;
01626         } else if (sz < 16) {
01627           // If loading i1/i8 result, generate
01628           //   load i8 (-> i16)
01629           //   trunc i16 to i1/i8
01630           LoadRetVTs.push_back(MVT::i16);
01631         } else
01632           LoadRetVTs.push_back(Ins[i].VT);
01633         LoadRetVTs.push_back(MVT::Other);
01634         LoadRetVTs.push_back(MVT::Glue);
01635 
01636         SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
01637                                 DAG.getConstant(Offsets[i], dl, MVT::i32),
01638                                 InFlag};
01639         SDValue retval = DAG.getMemIntrinsicNode(
01640             NVPTXISD::LoadParam, dl,
01641             DAG.getVTList(LoadRetVTs), LoadRetOps,
01642             TheLoadType, MachinePointerInfo(), AlignI);
01643         Chain = retval.getValue(1);
01644         InFlag = retval.getValue(2);
01645         SDValue Ret0 = retval.getValue(0);
01646         if (needTruncate)
01647           Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
01648         InVals.push_back(Ret0);
01649       }
01650     }
01651   }
01652 
01653   Chain = DAG.getCALLSEQ_END(Chain,
01654                              DAG.getIntPtrConstant(uniqueCallSite, dl, true),
01655                              DAG.getIntPtrConstant(uniqueCallSite + 1, dl,
01656                                                    true),
01657                              InFlag, dl);
01658   uniqueCallSite++;
01659 
01660   // set isTailCall to false for now, until we figure out how to express
01661   // tail call optimization in PTX
01662   isTailCall = false;
01663   return Chain;
01664 }
01665 
01666 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
01667 // (see LegalizeDAG.cpp). This is slow and uses local memory.
01668 // We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
01669 SDValue
01670 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
01671   SDNode *Node = Op.getNode();
01672   SDLoc dl(Node);
01673   SmallVector<SDValue, 8> Ops;
01674   unsigned NumOperands = Node->getNumOperands();
01675   for (unsigned i = 0; i < NumOperands; ++i) {
01676     SDValue SubOp = Node->getOperand(i);
01677     EVT VVT = SubOp.getNode()->getValueType(0);
01678     EVT EltVT = VVT.getVectorElementType();
01679     unsigned NumSubElem = VVT.getVectorNumElements();
01680     for (unsigned j = 0; j < NumSubElem; ++j) {
01681       Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
01682                                 DAG.getIntPtrConstant(j, dl)));
01683     }
01684   }
01685   return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
01686 }
01687 
01688 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
01689 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
01690 ///    amount, or
01691 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
01692 ///    amount.
01693 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
01694                                                   SelectionDAG &DAG) const {
01695   assert(Op.getNumOperands() == 3 && "Not a double-shift!");
01696   assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
01697 
01698   EVT VT = Op.getValueType();
01699   unsigned VTBits = VT.getSizeInBits();
01700   SDLoc dl(Op);
01701   SDValue ShOpLo = Op.getOperand(0);
01702   SDValue ShOpHi = Op.getOperand(1);
01703   SDValue ShAmt  = Op.getOperand(2);
01704   unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
01705 
01706   if (VTBits == 32 && STI.getSmVersion() >= 35) {
01707 
01708     // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
01709     // {dHi, dLo} = {aHi, aLo} >> Amt
01710     //   dHi = aHi >> Amt
01711     //   dLo = shf.r.clamp aLo, aHi, Amt
01712 
01713     SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
01714     SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
01715                              ShAmt);
01716 
01717     SDValue Ops[2] = { Lo, Hi };
01718     return DAG.getMergeValues(Ops, dl);
01719   }
01720   else {
01721 
01722     // {dHi, dLo} = {aHi, aLo} >> Amt
01723     // - if (Amt>=size) then
01724     //      dLo = aHi >> (Amt-size)
01725     //      dHi = aHi >> Amt (this is either all 0 or all 1)
01726     //   else
01727     //      dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
01728     //      dHi = aHi >> Amt
01729 
01730     SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
01731                                    DAG.getConstant(VTBits, dl, MVT::i32),
01732                                    ShAmt);
01733     SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
01734     SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
01735                                      DAG.getConstant(VTBits, dl, MVT::i32));
01736     SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
01737     SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
01738     SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
01739 
01740     SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
01741                                DAG.getConstant(VTBits, dl, MVT::i32),
01742                                ISD::SETGE);
01743     SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
01744     SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
01745 
01746     SDValue Ops[2] = { Lo, Hi };
01747     return DAG.getMergeValues(Ops, dl);
01748   }
01749 }
01750 
01751 /// LowerShiftLeftParts - Lower SHL_PARTS, which
01752 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
01753 ///    amount, or
01754 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
01755 ///    amount.
01756 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
01757                                                  SelectionDAG &DAG) const {
01758   assert(Op.getNumOperands() == 3 && "Not a double-shift!");
01759   assert(Op.getOpcode() == ISD::SHL_PARTS);
01760 
01761   EVT VT = Op.getValueType();
01762   unsigned VTBits = VT.getSizeInBits();
01763   SDLoc dl(Op);
01764   SDValue ShOpLo = Op.getOperand(0);
01765   SDValue ShOpHi = Op.getOperand(1);
01766   SDValue ShAmt  = Op.getOperand(2);
01767 
01768   if (VTBits == 32 && STI.getSmVersion() >= 35) {
01769 
01770     // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
01771     // {dHi, dLo} = {aHi, aLo} << Amt
01772     //   dHi = shf.l.clamp aLo, aHi, Amt
01773     //   dLo = aLo << Amt
01774 
01775     SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
01776                              ShAmt);
01777     SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
01778 
01779     SDValue Ops[2] = { Lo, Hi };
01780     return DAG.getMergeValues(Ops, dl);
01781   }
01782   else {
01783 
01784     // {dHi, dLo} = {aHi, aLo} << Amt
01785     // - if (Amt>=size) then
01786     //      dLo = aLo << Amt (all 0)
01787     //      dLo = aLo << (Amt-size)
01788     //   else
01789     //      dLo = aLo << Amt
01790     //      dHi = (aHi << Amt) | (aLo >> (size-Amt))
01791 
01792     SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
01793                                    DAG.getConstant(VTBits, dl, MVT::i32),
01794                                    ShAmt);
01795     SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
01796     SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
01797                                      DAG.getConstant(VTBits, dl, MVT::i32));
01798     SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
01799     SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
01800     SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
01801 
01802     SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
01803                                DAG.getConstant(VTBits, dl, MVT::i32),
01804                                ISD::SETGE);
01805     SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
01806     SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
01807 
01808     SDValue Ops[2] = { Lo, Hi };
01809     return DAG.getMergeValues(Ops, dl);
01810   }
01811 }
01812 
01813 SDValue
01814 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
01815   switch (Op.getOpcode()) {
01816   case ISD::RETURNADDR:
01817     return SDValue();
01818   case ISD::FRAMEADDR:
01819     return SDValue();
01820   case ISD::GlobalAddress:
01821     return LowerGlobalAddress(Op, DAG);
01822   case ISD::INTRINSIC_W_CHAIN:
01823     return Op;
01824   case ISD::BUILD_VECTOR:
01825   case ISD::EXTRACT_SUBVECTOR:
01826     return Op;
01827   case ISD::CONCAT_VECTORS:
01828     return LowerCONCAT_VECTORS(Op, DAG);
01829   case ISD::STORE:
01830     return LowerSTORE(Op, DAG);
01831   case ISD::LOAD:
01832     return LowerLOAD(Op, DAG);
01833   case ISD::SHL_PARTS:
01834     return LowerShiftLeftParts(Op, DAG);
01835   case ISD::SRA_PARTS:
01836   case ISD::SRL_PARTS:
01837     return LowerShiftRightParts(Op, DAG);
01838   case ISD::SELECT:
01839     return LowerSelect(Op, DAG);
01840   default:
01841     llvm_unreachable("Custom lowering not defined for operation");
01842   }
01843 }
01844 
01845 SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
01846   SDValue Op0 = Op->getOperand(0);
01847   SDValue Op1 = Op->getOperand(1);
01848   SDValue Op2 = Op->getOperand(2);
01849   SDLoc DL(Op.getNode());
01850 
01851   assert(Op.getValueType() == MVT::i1 && "Custom lowering enabled only for i1");
01852 
01853   Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
01854   Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
01855   SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
01856   SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select);
01857 
01858   return Trunc;
01859 }
01860 
01861 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
01862   if (Op.getValueType() == MVT::i1)
01863     return LowerLOADi1(Op, DAG);
01864   else
01865     return SDValue();
01866 }
01867 
01868 // v = ld i1* addr
01869 //   =>
01870 // v1 = ld i8* addr (-> i16)
01871 // v = trunc i16 to i1
01872 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
01873   SDNode *Node = Op.getNode();
01874   LoadSDNode *LD = cast<LoadSDNode>(Node);
01875   SDLoc dl(Node);
01876   assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
01877   assert(Node->getValueType(0) == MVT::i1 &&
01878          "Custom lowering for i1 load only");
01879   SDValue newLD =
01880       DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
01881                   LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
01882                   LD->isInvariant(), LD->getAlignment());
01883   SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
01884   // The legalizer (the caller) is expecting two values from the legalized
01885   // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
01886   // in LegalizeDAG.cpp which also uses MergeValues.
01887   SDValue Ops[] = { result, LD->getChain() };
01888   return DAG.getMergeValues(Ops, dl);
01889 }
01890 
01891 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
01892   EVT ValVT = Op.getOperand(1).getValueType();
01893   if (ValVT == MVT::i1)
01894     return LowerSTOREi1(Op, DAG);
01895   else if (ValVT.isVector())
01896     return LowerSTOREVector(Op, DAG);
01897   else
01898     return SDValue();
01899 }
01900 
01901 SDValue
01902 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
01903   SDNode *N = Op.getNode();
01904   SDValue Val = N->getOperand(1);
01905   SDLoc DL(N);
01906   EVT ValVT = Val.getValueType();
01907 
01908   if (ValVT.isVector()) {
01909     // We only handle "native" vector sizes for now, e.g. <4 x double> is not
01910     // legal.  We can (and should) split that into 2 stores of <2 x double> here
01911     // but I'm leaving that as a TODO for now.
01912     if (!ValVT.isSimple())
01913       return SDValue();
01914     switch (ValVT.getSimpleVT().SimpleTy) {
01915     default:
01916       return SDValue();
01917     case MVT::v2i8:
01918     case MVT::v2i16:
01919     case MVT::v2i32:
01920     case MVT::v2i64:
01921     case MVT::v2f32:
01922     case MVT::v2f64:
01923     case MVT::v4i8:
01924     case MVT::v4i16:
01925     case MVT::v4i32:
01926     case MVT::v4f32:
01927       // This is a "native" vector type
01928       break;
01929     }
01930 
01931     MemSDNode *MemSD = cast<MemSDNode>(N);
01932     const DataLayout &TD = DAG.getDataLayout();
01933 
01934     unsigned Align = MemSD->getAlignment();
01935     unsigned PrefAlign =
01936         TD.getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
01937     if (Align < PrefAlign) {
01938       // This store is not sufficiently aligned, so bail out and let this vector
01939       // store be scalarized.  Note that we may still be able to emit smaller
01940       // vector stores.  For example, if we are storing a <4 x float> with an
01941       // alignment of 8, this check will fail but the legalizer will try again
01942       // with 2 x <2 x float>, which will succeed with an alignment of 8.
01943       return SDValue();
01944     }
01945 
01946     unsigned Opcode = 0;
01947     EVT EltVT = ValVT.getVectorElementType();
01948     unsigned NumElts = ValVT.getVectorNumElements();
01949 
01950     // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
01951     // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
01952     // stored type to i16 and propagate the "real" type as the memory type.
01953     bool NeedExt = false;
01954     if (EltVT.getSizeInBits() < 16)
01955       NeedExt = true;
01956 
01957     switch (NumElts) {
01958     default:
01959       return SDValue();
01960     case 2:
01961       Opcode = NVPTXISD::StoreV2;
01962       break;
01963     case 4: {
01964       Opcode = NVPTXISD::StoreV4;
01965       break;
01966     }
01967     }
01968 
01969     SmallVector<SDValue, 8> Ops;
01970 
01971     // First is the chain
01972     Ops.push_back(N->getOperand(0));
01973 
01974     // Then the split values
01975     for (unsigned i = 0; i < NumElts; ++i) {
01976       SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
01977                                    DAG.getIntPtrConstant(i, DL));
01978       if (NeedExt)
01979         ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
01980       Ops.push_back(ExtVal);
01981     }
01982 
01983     // Then any remaining arguments
01984     Ops.append(N->op_begin() + 2, N->op_end());
01985 
01986     SDValue NewSt = DAG.getMemIntrinsicNode(
01987         Opcode, DL, DAG.getVTList(MVT::Other), Ops,
01988         MemSD->getMemoryVT(), MemSD->getMemOperand());
01989 
01990     //return DCI.CombineTo(N, NewSt, true);
01991     return NewSt;
01992   }
01993 
01994   return SDValue();
01995 }
01996 
01997 // st i1 v, addr
01998 //    =>
01999 // v1 = zxt v to i16
02000 // st.u8 i16, addr
02001 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
02002   SDNode *Node = Op.getNode();
02003   SDLoc dl(Node);
02004   StoreSDNode *ST = cast<StoreSDNode>(Node);
02005   SDValue Tmp1 = ST->getChain();
02006   SDValue Tmp2 = ST->getBasePtr();
02007   SDValue Tmp3 = ST->getValue();
02008   assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
02009   unsigned Alignment = ST->getAlignment();
02010   bool isVolatile = ST->isVolatile();
02011   bool isNonTemporal = ST->isNonTemporal();
02012   Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
02013   SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
02014                                      ST->getPointerInfo(), MVT::i8, isNonTemporal,
02015                                      isVolatile, Alignment);
02016   return Result;
02017 }
02018 
02019 SDValue
02020 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
02021   std::string ParamSym;
02022   raw_string_ostream ParamStr(ParamSym);
02023 
02024   ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
02025   ParamStr.flush();
02026 
02027   std::string *SavedStr =
02028     nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
02029   return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
02030 }
02031 
02032 // Check to see if the kernel argument is image*_t or sampler_t
02033 
02034 bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
02035   static const char *const specialTypes[] = { "struct._image2d_t",
02036                                               "struct._image3d_t",
02037                                               "struct._sampler_t" };
02038 
02039   Type *Ty = arg->getType();
02040   auto *PTy = dyn_cast<PointerType>(Ty);
02041 
02042   if (!PTy)
02043     return false;
02044 
02045   if (!context)
02046     return false;
02047 
02048   auto *STy = dyn_cast<StructType>(PTy->getElementType());
02049   const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
02050 
02051   return std::find(std::begin(specialTypes), std::end(specialTypes),
02052                    TypeName) != std::end(specialTypes);
02053 }
02054 
02055 SDValue NVPTXTargetLowering::LowerFormalArguments(
02056     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
02057     const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
02058     SmallVectorImpl<SDValue> &InVals) const {
02059   MachineFunction &MF = DAG.getMachineFunction();
02060   const DataLayout &DL = DAG.getDataLayout();
02061   auto PtrVT = getPointerTy(DAG.getDataLayout());
02062 
02063   const Function *F = MF.getFunction();
02064   const AttributeSet &PAL = F->getAttributes();
02065   const TargetLowering *TLI = STI.getTargetLowering();
02066 
02067   SDValue Root = DAG.getRoot();
02068   std::vector<SDValue> OutChains;
02069 
02070   bool isKernel = llvm::isKernelFunction(*F);
02071   bool isABI = (STI.getSmVersion() >= 20);
02072   assert(isABI && "Non-ABI compilation is not supported");
02073   if (!isABI)
02074     return Chain;
02075 
02076   std::vector<Type *> argTypes;
02077   std::vector<const Argument *> theArgs;
02078   for (const Argument &I : F->args()) {
02079     theArgs.push_back(&I);
02080     argTypes.push_back(I.getType());
02081   }
02082   // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
02083   // Ins.size() will be larger
02084   //   * if there is an aggregate argument with multiple fields (each field
02085   //     showing up separately in Ins)
02086   //   * if there is a vector argument with more than typical vector-length
02087   //     elements (generally if more than 4) where each vector element is
02088   //     individually present in Ins.
02089   // So a different index should be used for indexing into Ins.
02090   // See similar issue in LowerCall.
02091   unsigned InsIdx = 0;
02092 
02093   int idx = 0;
02094   for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
02095     Type *Ty = argTypes[i];
02096 
02097     // If the kernel argument is image*_t or sampler_t, convert it to
02098     // a i32 constant holding the parameter position. This can later
02099     // matched in the AsmPrinter to output the correct mangled name.
02100     if (isImageOrSamplerVal(
02101             theArgs[i],
02102             (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
02103                                      : nullptr))) {
02104       assert(isKernel && "Only kernels can have image/sampler params");
02105       InVals.push_back(DAG.getConstant(i + 1, dl, MVT::i32));
02106       continue;
02107     }
02108 
02109     if (theArgs[i]->use_empty()) {
02110       // argument is dead
02111       if (Ty->isAggregateType()) {
02112         SmallVector<EVT, 16> vtparts;
02113 
02114         ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts);
02115         assert(vtparts.size() > 0 && "empty aggregate type not expected");
02116         for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
02117              ++parti) {
02118           InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
02119           ++InsIdx;
02120         }
02121         if (vtparts.size() > 0)
02122           --InsIdx;
02123         continue;
02124       }
02125       if (Ty->isVectorTy()) {
02126         EVT ObjectVT = getValueType(DL, Ty);
02127         unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
02128         for (unsigned parti = 0; parti < NumRegs; ++parti) {
02129           InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
02130           ++InsIdx;
02131         }
02132         if (NumRegs > 0)
02133           --InsIdx;
02134         continue;
02135       }
02136       InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
02137       continue;
02138     }
02139 
02140     // In the following cases, assign a node order of "idx+1"
02141     // to newly created nodes. The SDNodes for params have to
02142     // appear in the same order as their order of appearance
02143     // in the original function. "idx+1" holds that order.
02144     if (!PAL.hasAttribute(i + 1, Attribute::ByVal)) {
02145       if (Ty->isAggregateType()) {
02146         SmallVector<EVT, 16> vtparts;
02147         SmallVector<uint64_t, 16> offsets;
02148 
02149         // NOTE: Here, we lose the ability to issue vector loads for vectors
02150         // that are a part of a struct.  This should be investigated in the
02151         // future.
02152         ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts, &offsets,
02153                            0);
02154         assert(vtparts.size() > 0 && "empty aggregate type not expected");
02155         bool aggregateIsPacked = false;
02156         if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
02157           aggregateIsPacked = STy->isPacked();
02158 
02159         SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
02160         for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
02161              ++parti) {
02162           EVT partVT = vtparts[parti];
02163           Value *srcValue = Constant::getNullValue(
02164               PointerType::get(partVT.getTypeForEVT(F->getContext()),
02165                                llvm::ADDRESS_SPACE_PARAM));
02166           SDValue srcAddr =
02167               DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
02168                           DAG.getConstant(offsets[parti], dl, PtrVT));
02169           unsigned partAlign = aggregateIsPacked
02170                                    ? 1
02171                                    : DL.getABITypeAlignment(
02172                                          partVT.getTypeForEVT(F->getContext()));
02173           SDValue p;
02174           if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
02175             ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? 
02176                                      ISD::SEXTLOAD : ISD::ZEXTLOAD;
02177             p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
02178                                MachinePointerInfo(srcValue), partVT, false,
02179                                false, false, partAlign);
02180           } else {
02181             p = DAG.getLoad(partVT, dl, Root, srcAddr,
02182                             MachinePointerInfo(srcValue), false, false, false,
02183                             partAlign);
02184           }
02185           if (p.getNode())
02186             p.getNode()->setIROrder(idx + 1);
02187           InVals.push_back(p);
02188           ++InsIdx;
02189         }
02190         if (vtparts.size() > 0)
02191           --InsIdx;
02192         continue;
02193       }
02194       if (Ty->isVectorTy()) {
02195         EVT ObjectVT = getValueType(DL, Ty);
02196         SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
02197         unsigned NumElts = ObjectVT.getVectorNumElements();
02198         assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
02199                "Vector was not scalarized");
02200         EVT EltVT = ObjectVT.getVectorElementType();
02201 
02202         // V1 load
02203         // f32 = load ...
02204         if (NumElts == 1) {
02205           // We only have one element, so just directly load it
02206           Value *SrcValue = Constant::getNullValue(PointerType::get(
02207               EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
02208           SDValue P = DAG.getLoad(
02209               EltVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, false,
02210               true,
02211               DL.getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
02212           if (P.getNode())
02213             P.getNode()->setIROrder(idx + 1);
02214 
02215           if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
02216             P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
02217           InVals.push_back(P);
02218           ++InsIdx;
02219         } else if (NumElts == 2) {
02220           // V2 load
02221           // f32,f32 = load ...
02222           EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
02223           Value *SrcValue = Constant::getNullValue(PointerType::get(
02224               VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
02225           SDValue P = DAG.getLoad(
02226               VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, false,
02227               true,
02228               DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
02229           if (P.getNode())
02230             P.getNode()->setIROrder(idx + 1);
02231 
02232           SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
02233                                      DAG.getIntPtrConstant(0, dl));
02234           SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
02235                                      DAG.getIntPtrConstant(1, dl));
02236 
02237           if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
02238             Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
02239             Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
02240           }
02241 
02242           InVals.push_back(Elt0);
02243           InVals.push_back(Elt1);
02244           InsIdx += 2;
02245         } else {
02246           // V4 loads
02247           // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
02248           // the
02249           // vector will be expanded to a power of 2 elements, so we know we can
02250           // always round up to the next multiple of 4 when creating the vector
02251           // loads.
02252           // e.g.  4 elem => 1 ld.v4
02253           //       6 elem => 2 ld.v4
02254           //       8 elem => 2 ld.v4
02255           //      11 elem => 3 ld.v4
02256           unsigned VecSize = 4;
02257           if (EltVT.getSizeInBits() == 64) {
02258             VecSize = 2;
02259           }
02260           EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
02261           unsigned Ofst = 0;
02262           for (unsigned i = 0; i < NumElts; i += VecSize) {
02263             Value *SrcValue = Constant::getNullValue(
02264                 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
02265                                  llvm::ADDRESS_SPACE_PARAM));
02266             SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
02267                                           DAG.getConstant(Ofst, dl, PtrVT));
02268             SDValue P = DAG.getLoad(
02269                 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
02270                 false, true,
02271                 DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
02272             if (P.getNode())
02273               P.getNode()->setIROrder(idx + 1);
02274 
02275             for (unsigned j = 0; j < VecSize; ++j) {
02276               if (i + j >= NumElts)
02277                 break;
02278               SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
02279                                         DAG.getIntPtrConstant(j, dl));
02280               if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
02281                 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
02282               InVals.push_back(Elt);
02283             }
02284             Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
02285           }
02286           InsIdx += NumElts;
02287         }
02288 
02289         if (NumElts > 0)
02290           --InsIdx;
02291         continue;
02292       }
02293       // A plain scalar.
02294       EVT ObjectVT = getValueType(DL, Ty);
02295       // If ABI, load from the param symbol
02296       SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
02297       Value *srcValue = Constant::getNullValue(PointerType::get(
02298           ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
02299       SDValue p;
02300        if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
02301         ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? 
02302                                        ISD::SEXTLOAD : ISD::ZEXTLOAD;
02303         p = DAG.getExtLoad(
02304             ExtOp, dl, Ins[InsIdx].VT, Root, Arg, MachinePointerInfo(srcValue),
02305             ObjectVT, false, false, false,
02306             DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
02307       } else {
02308         p = DAG.getLoad(
02309             Ins[InsIdx].VT, dl, Root, Arg, MachinePointerInfo(srcValue), false,
02310             false, false,
02311             DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
02312       }
02313       if (p.getNode())
02314         p.getNode()->setIROrder(idx + 1);
02315       InVals.push_back(p);
02316       continue;
02317     }
02318 
02319     // Param has ByVal attribute
02320     // Return MoveParam(param symbol).
02321     // Ideally, the param symbol can be returned directly,
02322     // but when SDNode builder decides to use it in a CopyToReg(),
02323     // machine instruction fails because TargetExternalSymbol
02324     // (not lowered) is target dependent, and CopyToReg assumes
02325     // the source is lowered.
02326     EVT ObjectVT = getValueType(DL, Ty);
02327     assert(ObjectVT == Ins[InsIdx].VT &&
02328            "Ins type did not match function type");
02329     SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
02330     SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
02331     if (p.getNode())
02332       p.getNode()->setIROrder(idx + 1);
02333     if (isKernel)
02334       InVals.push_back(p);
02335     else {
02336       SDValue p2 = DAG.getNode(
02337           ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
02338           DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, dl, MVT::i32), p);
02339       InVals.push_back(p2);
02340     }
02341   }
02342 
02343   // Clang will check explicit VarArg and issue error if any. However, Clang
02344   // will let code with
02345   // implicit var arg like f() pass. See bug 617733.
02346   // We treat this case as if the arg list is empty.
02347   // if (F.isVarArg()) {
02348   // assert(0 && "VarArg not supported yet!");
02349   //}
02350 
02351   if (!OutChains.empty())
02352     DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
02353 
02354   return Chain;
02355 }
02356 
02357 
02358 SDValue
02359 NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
02360                                  bool isVarArg,
02361                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
02362                                  const SmallVectorImpl<SDValue> &OutVals,
02363                                  SDLoc dl, SelectionDAG &DAG) const {
02364   MachineFunction &MF = DAG.getMachineFunction();
02365   const Function *F = MF.getFunction();
02366   Type *RetTy = F->getReturnType();
02367   const DataLayout &TD = DAG.getDataLayout();
02368 
02369   bool isABI = (STI.getSmVersion() >= 20);
02370   assert(isABI && "Non-ABI compilation is not supported");
02371   if (!isABI)
02372     return Chain;
02373 
02374   if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
02375     // If we have a vector type, the OutVals array will be the scalarized
02376     // components and we have combine them into 1 or more vector stores.
02377     unsigned NumElts = VTy->getNumElements();
02378     assert(NumElts == Outs.size() && "Bad scalarization of return value");
02379 
02380     // const_cast can be removed in later LLVM versions
02381     EVT EltVT = getValueType(TD, RetTy).getVectorElementType();
02382     bool NeedExtend = false;
02383     if (EltVT.getSizeInBits() < 16)
02384       NeedExtend = true;
02385 
02386     // V1 store
02387     if (NumElts == 1) {
02388       SDValue StoreVal = OutVals[0];
02389       // We only have one element, so just directly store it
02390       if (NeedExtend)
02391         StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
02392       SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal };
02393       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
02394                                       DAG.getVTList(MVT::Other), Ops,
02395                                       EltVT, MachinePointerInfo());
02396 
02397     } else if (NumElts == 2) {
02398       // V2 store
02399       SDValue StoreVal0 = OutVals[0];
02400       SDValue StoreVal1 = OutVals[1];
02401 
02402       if (NeedExtend) {
02403         StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
02404         StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
02405       }
02406 
02407       SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal0,
02408                         StoreVal1 };
02409       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
02410                                       DAG.getVTList(MVT::Other), Ops,
02411                                       EltVT, MachinePointerInfo());
02412     } else {
02413       // V4 stores
02414       // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
02415       // vector will be expanded to a power of 2 elements, so we know we can
02416       // always round up to the next multiple of 4 when creating the vector
02417       // stores.
02418       // e.g.  4 elem => 1 st.v4
02419       //       6 elem => 2 st.v4
02420       //       8 elem => 2 st.v4
02421       //      11 elem => 3 st.v4
02422 
02423       unsigned VecSize = 4;
02424       if (OutVals[0].getValueType().getSizeInBits() == 64)
02425         VecSize = 2;
02426 
02427       unsigned Offset = 0;
02428 
02429       EVT VecVT =
02430           EVT::getVectorVT(F->getContext(), EltVT, VecSize);
02431       unsigned PerStoreOffset =
02432           TD.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
02433 
02434       for (unsigned i = 0; i < NumElts; i += VecSize) {
02435         // Get values
02436         SDValue StoreVal;
02437         SmallVector<SDValue, 8> Ops;
02438         Ops.push_back(Chain);
02439         Ops.push_back(DAG.getConstant(Offset, dl, MVT::i32));
02440         unsigned Opc = NVPTXISD::StoreRetvalV2;
02441         EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
02442 
02443         StoreVal = OutVals[i];
02444         if (NeedExtend)
02445           StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
02446         Ops.push_back(StoreVal);
02447 
02448         if (i + 1 < NumElts) {
02449           StoreVal = OutVals[i + 1];
02450           if (NeedExtend)
02451             StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
02452         } else {
02453           StoreVal = DAG.getUNDEF(ExtendedVT);
02454         }
02455         Ops.push_back(StoreVal);
02456 
02457         if (VecSize == 4) {
02458           Opc = NVPTXISD::StoreRetvalV4;
02459           if (i + 2 < NumElts) {
02460             StoreVal = OutVals[i + 2];
02461             if (NeedExtend)
02462               StoreVal =
02463                   DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
02464           } else {
02465             StoreVal = DAG.getUNDEF(ExtendedVT);
02466           }
02467           Ops.push_back(StoreVal);
02468 
02469           if (i + 3 < NumElts) {
02470             StoreVal = OutVals[i + 3];
02471             if (NeedExtend)
02472               StoreVal =
02473                   DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
02474           } else {
02475             StoreVal = DAG.getUNDEF(ExtendedVT);
02476           }
02477           Ops.push_back(StoreVal);
02478         }
02479 
02480         // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
02481         Chain =
02482             DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
02483                                     EltVT, MachinePointerInfo());
02484         Offset += PerStoreOffset;
02485       }
02486     }
02487   } else {
02488     SmallVector<EVT, 16> ValVTs;
02489     SmallVector<uint64_t, 16> Offsets;
02490     ComputePTXValueVTs(*this, DAG.getDataLayout(), RetTy, ValVTs, &Offsets, 0);
02491     assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
02492 
02493     for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
02494       SDValue theVal = OutVals[i];
02495       EVT TheValType = theVal.getValueType();
02496       unsigned numElems = 1;
02497       if (TheValType.isVector())
02498         numElems = TheValType.getVectorNumElements();
02499       for (unsigned j = 0, je = numElems; j != je; ++j) {
02500         SDValue TmpVal = theVal;
02501         if (TheValType.isVector())
02502           TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
02503                                TheValType.getVectorElementType(), TmpVal,
02504                                DAG.getIntPtrConstant(j, dl));
02505         EVT TheStoreType = ValVTs[i];
02506         if (RetTy->isIntegerTy() && TD.getTypeAllocSizeInBits(RetTy) < 32) {
02507           // The following zero-extension is for integer types only, and
02508           // specifically not for aggregates.
02509           TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
02510           TheStoreType = MVT::i32;
02511         }
02512         else if (TmpVal.getValueType().getSizeInBits() < 16)
02513           TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
02514 
02515         SDValue Ops[] = {
02516           Chain,
02517           DAG.getConstant(Offsets[i], dl, MVT::i32),
02518           TmpVal };
02519         Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
02520                                         DAG.getVTList(MVT::Other), Ops,
02521                                         TheStoreType,
02522                                         MachinePointerInfo());
02523       }
02524     }
02525   }
02526 
02527   return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
02528 }
02529 
02530 
02531 void NVPTXTargetLowering::LowerAsmOperandForConstraint(
02532     SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
02533     SelectionDAG &DAG) const {
02534   if (Constraint.length() > 1)
02535     return;
02536   else
02537     TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
02538 }
02539 
02540 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
02541   switch (Intrinsic) {
02542   default:
02543     return 0;
02544 
02545   case Intrinsic::nvvm_tex_1d_v4f32_s32:
02546     return NVPTXISD::Tex1DFloatS32;
02547   case Intrinsic::nvvm_tex_1d_v4f32_f32:
02548     return NVPTXISD::Tex1DFloatFloat;
02549   case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
02550     return NVPTXISD::Tex1DFloatFloatLevel;
02551   case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
02552     return NVPTXISD::Tex1DFloatFloatGrad;
02553   case Intrinsic::nvvm_tex_1d_v4s32_s32:
02554     return NVPTXISD::Tex1DS32S32;
02555   case Intrinsic::nvvm_tex_1d_v4s32_f32:
02556     return NVPTXISD::Tex1DS32Float;
02557   case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
02558     return NVPTXISD::Tex1DS32FloatLevel;
02559   case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
02560     return NVPTXISD::Tex1DS32FloatGrad;
02561   case Intrinsic::nvvm_tex_1d_v4u32_s32:
02562     return NVPTXISD::Tex1DU32S32;
02563   case Intrinsic::nvvm_tex_1d_v4u32_f32:
02564     return NVPTXISD::Tex1DU32Float;
02565   case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
02566     return NVPTXISD::Tex1DU32FloatLevel;
02567   case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
02568     return NVPTXISD::Tex1DU32FloatGrad;
02569 
02570   case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
02571     return NVPTXISD::Tex1DArrayFloatS32;
02572   case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
02573     return NVPTXISD::Tex1DArrayFloatFloat;
02574   case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
02575     return NVPTXISD::Tex1DArrayFloatFloatLevel;
02576   case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
02577     return NVPTXISD::Tex1DArrayFloatFloatGrad;
02578   case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
02579     return NVPTXISD::Tex1DArrayS32S32;
02580   case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
02581     return NVPTXISD::Tex1DArrayS32Float;
02582   case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
02583     return NVPTXISD::Tex1DArrayS32FloatLevel;
02584   case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
02585     return NVPTXISD::Tex1DArrayS32FloatGrad;
02586   case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
02587     return NVPTXISD::Tex1DArrayU32S32;
02588   case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
02589     return NVPTXISD::Tex1DArrayU32Float;
02590   case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
02591     return NVPTXISD::Tex1DArrayU32FloatLevel;
02592   case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
02593     return NVPTXISD::Tex1DArrayU32FloatGrad;
02594 
02595   case Intrinsic::nvvm_tex_2d_v4f32_s32:
02596     return NVPTXISD::Tex2DFloatS32;
02597   case Intrinsic::nvvm_tex_2d_v4f32_f32:
02598     return NVPTXISD::Tex2DFloatFloat;
02599   case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
02600     return NVPTXISD::Tex2DFloatFloatLevel;
02601   case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
02602     return NVPTXISD::Tex2DFloatFloatGrad;
02603   case Intrinsic::nvvm_tex_2d_v4s32_s32:
02604     return NVPTXISD::Tex2DS32S32;
02605   case Intrinsic::nvvm_tex_2d_v4s32_f32:
02606     return NVPTXISD::Tex2DS32Float;
02607   case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
02608     return NVPTXISD::Tex2DS32FloatLevel;
02609   case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
02610     return NVPTXISD::Tex2DS32FloatGrad;
02611   case Intrinsic::nvvm_tex_2d_v4u32_s32:
02612     return NVPTXISD::Tex2DU32S32;
02613   case Intrinsic::nvvm_tex_2d_v4u32_f32:
02614     return NVPTXISD::Tex2DU32Float;
02615   case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
02616     return NVPTXISD::Tex2DU32FloatLevel;
02617   case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
02618     return NVPTXISD::Tex2DU32FloatGrad;
02619 
02620   case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
02621     return NVPTXISD::Tex2DArrayFloatS32;
02622   case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
02623     return NVPTXISD::Tex2DArrayFloatFloat;
02624   case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
02625     return NVPTXISD::Tex2DArrayFloatFloatLevel;
02626   case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
02627     return NVPTXISD::Tex2DArrayFloatFloatGrad;
02628   case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
02629     return NVPTXISD::Tex2DArrayS32S32;
02630   case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
02631     return NVPTXISD::Tex2DArrayS32Float;
02632   case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
02633     return NVPTXISD::Tex2DArrayS32FloatLevel;
02634   case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
02635     return NVPTXISD::Tex2DArrayS32FloatGrad;
02636   case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
02637     return NVPTXISD::Tex2DArrayU32S32;
02638   case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
02639     return NVPTXISD::Tex2DArrayU32Float;
02640   case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
02641     return NVPTXISD::Tex2DArrayU32FloatLevel;
02642   case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
02643     return NVPTXISD::Tex2DArrayU32FloatGrad;
02644 
02645   case Intrinsic::nvvm_tex_3d_v4f32_s32:
02646     return NVPTXISD::Tex3DFloatS32;
02647   case Intrinsic::nvvm_tex_3d_v4f32_f32:
02648     return NVPTXISD::Tex3DFloatFloat;
02649   case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
02650     return NVPTXISD::Tex3DFloatFloatLevel;
02651   case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
02652     return NVPTXISD::Tex3DFloatFloatGrad;
02653   case Intrinsic::nvvm_tex_3d_v4s32_s32:
02654     return NVPTXISD::Tex3DS32S32;
02655   case Intrinsic::nvvm_tex_3d_v4s32_f32:
02656     return NVPTXISD::Tex3DS32Float;
02657   case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
02658     return NVPTXISD::Tex3DS32FloatLevel;
02659   case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
02660     return NVPTXISD::Tex3DS32FloatGrad;
02661   case Intrinsic::nvvm_tex_3d_v4u32_s32:
02662     return NVPTXISD::Tex3DU32S32;
02663   case Intrinsic::nvvm_tex_3d_v4u32_f32:
02664     return NVPTXISD::Tex3DU32Float;
02665   case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
02666     return NVPTXISD::Tex3DU32FloatLevel;
02667   case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
02668     return NVPTXISD::Tex3DU32FloatGrad;
02669 
02670   case Intrinsic::nvvm_tex_cube_v4f32_f32:
02671     return NVPTXISD::TexCubeFloatFloat;
02672   case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
02673     return NVPTXISD::TexCubeFloatFloatLevel;
02674   case Intrinsic::nvvm_tex_cube_v4s32_f32:
02675     return NVPTXISD::TexCubeS32Float;
02676   case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
02677     return NVPTXISD::TexCubeS32FloatLevel;
02678   case Intrinsic::nvvm_tex_cube_v4u32_f32:
02679     return NVPTXISD::TexCubeU32Float;
02680   case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
02681     return NVPTXISD::TexCubeU32FloatLevel;
02682 
02683   case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
02684     return NVPTXISD::TexCubeArrayFloatFloat;
02685   case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
02686     return NVPTXISD::TexCubeArrayFloatFloatLevel;
02687   case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
02688     return NVPTXISD::TexCubeArrayS32Float;
02689   case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
02690     return NVPTXISD::TexCubeArrayS32FloatLevel;
02691   case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
02692     return NVPTXISD::TexCubeArrayU32Float;
02693   case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
02694     return NVPTXISD::TexCubeArrayU32FloatLevel;
02695 
02696   case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
02697     return NVPTXISD::Tld4R2DFloatFloat;
02698   case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
02699     return NVPTXISD::Tld4G2DFloatFloat;
02700   case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
02701     return NVPTXISD::Tld4B2DFloatFloat;
02702   case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
02703     return NVPTXISD::Tld4A2DFloatFloat;
02704   case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
02705     return NVPTXISD::Tld4R2DS64Float;
02706   case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
02707     return NVPTXISD::Tld4G2DS64Float;
02708   case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
02709     return NVPTXISD::Tld4B2DS64Float;
02710   case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
02711     return NVPTXISD::Tld4A2DS64Float;
02712   case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
02713     return NVPTXISD::Tld4R2DU64Float;
02714   case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
02715     return NVPTXISD::Tld4G2DU64Float;
02716   case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
02717     return NVPTXISD::Tld4B2DU64Float;
02718   case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
02719     return NVPTXISD::Tld4A2DU64Float;
02720 
02721   case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
02722     return NVPTXISD::TexUnified1DFloatS32;
02723   case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
02724     return NVPTXISD::TexUnified1DFloatFloat;
02725   case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
02726     return NVPTXISD::TexUnified1DFloatFloatLevel;
02727   case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
02728     return NVPTXISD::TexUnified1DFloatFloatGrad;
02729   case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
02730     return NVPTXISD::TexUnified1DS32S32;
02731   case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
02732     return NVPTXISD::TexUnified1DS32Float;
02733   case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
02734     return NVPTXISD::TexUnified1DS32FloatLevel;
02735   case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
02736     return NVPTXISD::TexUnified1DS32FloatGrad;
02737   case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
02738     return NVPTXISD::TexUnified1DU32S32;
02739   case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
02740     return NVPTXISD::TexUnified1DU32Float;
02741   case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
02742     return NVPTXISD::TexUnified1DU32FloatLevel;
02743   case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
02744     return NVPTXISD::TexUnified1DU32FloatGrad;
02745 
02746   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
02747     return NVPTXISD::TexUnified1DArrayFloatS32;
02748   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
02749     return NVPTXISD::TexUnified1DArrayFloatFloat;
02750   case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
02751     return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
02752   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
02753     return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
02754   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
02755     return NVPTXISD::TexUnified1DArrayS32S32;
02756   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
02757     return NVPTXISD::TexUnified1DArrayS32Float;
02758   case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
02759     return NVPTXISD::TexUnified1DArrayS32FloatLevel;
02760   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
02761     return NVPTXISD::TexUnified1DArrayS32FloatGrad;
02762   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
02763     return NVPTXISD::TexUnified1DArrayU32S32;
02764   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
02765     return NVPTXISD::TexUnified1DArrayU32Float;
02766   case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
02767     return NVPTXISD::TexUnified1DArrayU32FloatLevel;
02768   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
02769     return NVPTXISD::TexUnified1DArrayU32FloatGrad;
02770 
02771   case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
02772     return NVPTXISD::TexUnified2DFloatS32;
02773   case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
02774     return NVPTXISD::TexUnified2DFloatFloat;
02775   case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
02776     return NVPTXISD::TexUnified2DFloatFloatLevel;
02777   case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
02778     return NVPTXISD::TexUnified2DFloatFloatGrad;
02779   case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
02780     return NVPTXISD::TexUnified2DS32S32;
02781   case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
02782     return NVPTXISD::TexUnified2DS32Float;
02783   case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
02784     return NVPTXISD::TexUnified2DS32FloatLevel;
02785   case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
02786     return NVPTXISD::TexUnified2DS32FloatGrad;
02787   case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
02788     return NVPTXISD::TexUnified2DU32S32;
02789   case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
02790     return NVPTXISD::TexUnified2DU32Float;
02791   case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
02792     return NVPTXISD::TexUnified2DU32FloatLevel;
02793   case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
02794     return NVPTXISD::TexUnified2DU32FloatGrad;
02795 
02796   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
02797     return NVPTXISD::TexUnified2DArrayFloatS32;
02798   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
02799     return NVPTXISD::TexUnified2DArrayFloatFloat;
02800   case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
02801     return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
02802   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
02803     return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
02804   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
02805     return NVPTXISD::TexUnified2DArrayS32S32;
02806   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
02807     return NVPTXISD::TexUnified2DArrayS32Float;
02808   case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
02809     return NVPTXISD::TexUnified2DArrayS32FloatLevel;
02810   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
02811     return NVPTXISD::TexUnified2DArrayS32FloatGrad;
02812   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
02813     return NVPTXISD::TexUnified2DArrayU32S32;
02814   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
02815     return NVPTXISD::TexUnified2DArrayU32Float;
02816   case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
02817     return NVPTXISD::TexUnified2DArrayU32FloatLevel;
02818   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
02819     return NVPTXISD::TexUnified2DArrayU32FloatGrad;
02820 
02821   case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
02822     return NVPTXISD::TexUnified3DFloatS32;
02823   case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
02824     return NVPTXISD::TexUnified3DFloatFloat;
02825   case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
02826     return NVPTXISD::TexUnified3DFloatFloatLevel;
02827   case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
02828     return NVPTXISD::TexUnified3DFloatFloatGrad;
02829   case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
02830     return NVPTXISD::TexUnified3DS32S32;
02831   case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
02832     return NVPTXISD::TexUnified3DS32Float;
02833   case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
02834     return NVPTXISD::TexUnified3DS32FloatLevel;
02835   case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
02836     return NVPTXISD::TexUnified3DS32FloatGrad;
02837   case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
02838     return NVPTXISD::TexUnified3DU32S32;
02839   case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
02840     return NVPTXISD::TexUnified3DU32Float;
02841   case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
02842     return NVPTXISD::TexUnified3DU32FloatLevel;
02843   case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
02844     return NVPTXISD::TexUnified3DU32FloatGrad;
02845 
02846   case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
02847     return NVPTXISD::TexUnifiedCubeFloatFloat;
02848   case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
02849     return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
02850   case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
02851     return NVPTXISD::TexUnifiedCubeS32Float;
02852   case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
02853     return NVPTXISD::TexUnifiedCubeS32FloatLevel;
02854   case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
02855     return NVPTXISD::TexUnifiedCubeU32Float;
02856   case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
02857     return NVPTXISD::TexUnifiedCubeU32FloatLevel;
02858 
02859   case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
02860     return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
02861   case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
02862     return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
02863   case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
02864     return NVPTXISD::TexUnifiedCubeArrayS32Float;
02865   case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
02866     return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
02867   case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
02868     return NVPTXISD::TexUnifiedCubeArrayU32Float;
02869   case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
02870     return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
02871 
02872   case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
02873     return NVPTXISD::Tld4UnifiedR2DFloatFloat;
02874   case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
02875     return NVPTXISD::Tld4UnifiedG2DFloatFloat;
02876   case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
02877     return NVPTXISD::Tld4UnifiedB2DFloatFloat;
02878   case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
02879     return NVPTXISD::Tld4UnifiedA2DFloatFloat;
02880   case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
02881     return NVPTXISD::Tld4UnifiedR2DS64Float;
02882   case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
02883     return NVPTXISD::Tld4UnifiedG2DS64Float;
02884   case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
02885     return NVPTXISD::Tld4UnifiedB2DS64Float;
02886   case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
02887     return NVPTXISD::Tld4UnifiedA2DS64Float;
02888   case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
02889     return NVPTXISD::Tld4UnifiedR2DU64Float;
02890   case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
02891     return NVPTXISD::Tld4UnifiedG2DU64Float;
02892   case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
02893     return NVPTXISD::Tld4UnifiedB2DU64Float;
02894   case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
02895     return NVPTXISD::Tld4UnifiedA2DU64Float;
02896   }
02897 }
02898 
02899 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
02900   switch (Intrinsic) {
02901   default:
02902     return 0;
02903   case Intrinsic::nvvm_suld_1d_i8_clamp:
02904     return NVPTXISD::Suld1DI8Clamp;
02905   case Intrinsic::nvvm_suld_1d_i16_clamp:
02906     return NVPTXISD::Suld1DI16Clamp;
02907   case Intrinsic::nvvm_suld_1d_i32_clamp:
02908     return NVPTXISD::Suld1DI32Clamp;
02909   case Intrinsic::nvvm_suld_1d_i64_clamp:
02910     return NVPTXISD::Suld1DI64Clamp;
02911   case Intrinsic::nvvm_suld_1d_v2i8_clamp:
02912     return NVPTXISD::Suld1DV2I8Clamp;
02913   case Intrinsic::nvvm_suld_1d_v2i16_clamp:
02914     return NVPTXISD::Suld1DV2I16Clamp;
02915   case Intrinsic::nvvm_suld_1d_v2i32_clamp:
02916     return NVPTXISD::Suld1DV2I32Clamp;
02917   case Intrinsic::nvvm_suld_1d_v2i64_clamp:
02918     return NVPTXISD::Suld1DV2I64Clamp;
02919   case Intrinsic::nvvm_suld_1d_v4i8_clamp:
02920     return NVPTXISD::Suld1DV4I8Clamp;
02921   case Intrinsic::nvvm_suld_1d_v4i16_clamp:
02922     return NVPTXISD::Suld1DV4I16Clamp;
02923   case Intrinsic::nvvm_suld_1d_v4i32_clamp:
02924     return NVPTXISD::Suld1DV4I32Clamp;
02925   case Intrinsic::nvvm_suld_1d_array_i8_clamp:
02926     return NVPTXISD::Suld1DArrayI8Clamp;
02927   case Intrinsic::nvvm_suld_1d_array_i16_clamp:
02928     return NVPTXISD::Suld1DArrayI16Clamp;
02929   case Intrinsic::nvvm_suld_1d_array_i32_clamp:
02930     return NVPTXISD::Suld1DArrayI32Clamp;
02931   case Intrinsic::nvvm_suld_1d_array_i64_clamp:
02932     return NVPTXISD::Suld1DArrayI64Clamp;
02933   case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
02934     return NVPTXISD::Suld1DArrayV2I8Clamp;
02935   case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
02936     return NVPTXISD::Suld1DArrayV2I16Clamp;
02937   case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
02938     return NVPTXISD::Suld1DArrayV2I32Clamp;
02939   case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
02940     return NVPTXISD::Suld1DArrayV2I64Clamp;
02941   case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
02942     return NVPTXISD::Suld1DArrayV4I8Clamp;
02943   case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
02944     return NVPTXISD::Suld1DArrayV4I16Clamp;
02945   case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
02946     return NVPTXISD::Suld1DArrayV4I32Clamp;
02947   case Intrinsic::nvvm_suld_2d_i8_clamp:
02948     return NVPTXISD::Suld2DI8Clamp;
02949   case Intrinsic::nvvm_suld_2d_i16_clamp:
02950     return NVPTXISD::Suld2DI16Clamp;
02951   case Intrinsic::nvvm_suld_2d_i32_clamp:
02952     return NVPTXISD::Suld2DI32Clamp;
02953   case Intrinsic::nvvm_suld_2d_i64_clamp:
02954     return NVPTXISD::Suld2DI64Clamp;
02955   case Intrinsic::nvvm_suld_2d_v2i8_clamp:
02956     return NVPTXISD::Suld2DV2I8Clamp;
02957   case Intrinsic::nvvm_suld_2d_v2i16_clamp:
02958     return NVPTXISD::Suld2DV2I16Clamp;
02959   case Intrinsic::nvvm_suld_2d_v2i32_clamp:
02960     return NVPTXISD::Suld2DV2I32Clamp;
02961   case Intrinsic::nvvm_suld_2d_v2i64_clamp:
02962     return NVPTXISD::Suld2DV2I64Clamp;
02963   case Intrinsic::nvvm_suld_2d_v4i8_clamp:
02964     return NVPTXISD::Suld2DV4I8Clamp;
02965   case Intrinsic::nvvm_suld_2d_v4i16_clamp:
02966     return NVPTXISD::Suld2DV4I16Clamp;
02967   case Intrinsic::nvvm_suld_2d_v4i32_clamp:
02968     return NVPTXISD::Suld2DV4I32Clamp;
02969   case Intrinsic::nvvm_suld_2d_array_i8_clamp:
02970     return NVPTXISD::Suld2DArrayI8Clamp;
02971   case Intrinsic::nvvm_suld_2d_array_i16_clamp:
02972     return NVPTXISD::Suld2DArrayI16Clamp;
02973   case Intrinsic::nvvm_suld_2d_array_i32_clamp:
02974     return NVPTXISD::Suld2DArrayI32Clamp;
02975   case Intrinsic::nvvm_suld_2d_array_i64_clamp:
02976     return NVPTXISD::Suld2DArrayI64Clamp;
02977   case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
02978     return NVPTXISD::Suld2DArrayV2I8Clamp;
02979   case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
02980     return NVPTXISD::Suld2DArrayV2I16Clamp;
02981   case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
02982     return NVPTXISD::Suld2DArrayV2I32Clamp;
02983   case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
02984     return NVPTXISD::Suld2DArrayV2I64Clamp;
02985   case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
02986     return NVPTXISD::Suld2DArrayV4I8Clamp;
02987   case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
02988     return NVPTXISD::Suld2DArrayV4I16Clamp;
02989   case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
02990     return NVPTXISD::Suld2DArrayV4I32Clamp;
02991   case Intrinsic::nvvm_suld_3d_i8_clamp:
02992     return NVPTXISD::Suld3DI8Clamp;
02993   case Intrinsic::nvvm_suld_3d_i16_clamp:
02994     return NVPTXISD::Suld3DI16Clamp;
02995   case Intrinsic::nvvm_suld_3d_i32_clamp:
02996     return NVPTXISD::Suld3DI32Clamp;
02997   case Intrinsic::nvvm_suld_3d_i64_clamp:
02998     return NVPTXISD::Suld3DI64Clamp;
02999   case Intrinsic::nvvm_suld_3d_v2i8_clamp:
03000     return NVPTXISD::Suld3DV2I8Clamp;
03001   case Intrinsic::nvvm_suld_3d_v2i16_clamp:
03002     return NVPTXISD::Suld3DV2I16Clamp;
03003   case Intrinsic::nvvm_suld_3d_v2i32_clamp:
03004     return NVPTXISD::Suld3DV2I32Clamp;
03005   case Intrinsic::nvvm_suld_3d_v2i64_clamp:
03006     return NVPTXISD::Suld3DV2I64Clamp;
03007   case Intrinsic::nvvm_suld_3d_v4i8_clamp:
03008     return NVPTXISD::Suld3DV4I8Clamp;
03009   case Intrinsic::nvvm_suld_3d_v4i16_clamp:
03010     return NVPTXISD::Suld3DV4I16Clamp;
03011   case Intrinsic::nvvm_suld_3d_v4i32_clamp:
03012     return NVPTXISD::Suld3DV4I32Clamp;
03013   case Intrinsic::nvvm_suld_1d_i8_trap:
03014     return NVPTXISD::Suld1DI8Trap;
03015   case Intrinsic::nvvm_suld_1d_i16_trap:
03016     return NVPTXISD::Suld1DI16Trap;
03017   case Intrinsic::nvvm_suld_1d_i32_trap:
03018     return NVPTXISD::Suld1DI32Trap;
03019   case Intrinsic::nvvm_suld_1d_i64_trap:
03020     return NVPTXISD::Suld1DI64Trap;
03021   case Intrinsic::nvvm_suld_1d_v2i8_trap:
03022     return NVPTXISD::Suld1DV2I8Trap;
03023   case Intrinsic::nvvm_suld_1d_v2i16_trap:
03024     return NVPTXISD::Suld1DV2I16Trap;
03025   case Intrinsic::nvvm_suld_1d_v2i32_trap:
03026     return NVPTXISD::Suld1DV2I32Trap;
03027   case Intrinsic::nvvm_suld_1d_v2i64_trap:
03028     return NVPTXISD::Suld1DV2I64Trap;
03029   case Intrinsic::nvvm_suld_1d_v4i8_trap:
03030     return NVPTXISD::Suld1DV4I8Trap;
03031   case Intrinsic::nvvm_suld_1d_v4i16_trap:
03032     return NVPTXISD::Suld1DV4I16Trap;
03033   case Intrinsic::nvvm_suld_1d_v4i32_trap:
03034     return NVPTXISD::Suld1DV4I32Trap;
03035   case Intrinsic::nvvm_suld_1d_array_i8_trap:
03036     return NVPTXISD::Suld1DArrayI8Trap;
03037   case Intrinsic::nvvm_suld_1d_array_i16_trap:
03038     return NVPTXISD::Suld1DArrayI16Trap;
03039   case Intrinsic::nvvm_suld_1d_array_i32_trap:
03040     return NVPTXISD::Suld1DArrayI32Trap;
03041   case Intrinsic::nvvm_suld_1d_array_i64_trap:
03042     return NVPTXISD::Suld1DArrayI64Trap;
03043   case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
03044     return NVPTXISD::Suld1DArrayV2I8Trap;
03045   case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
03046     return NVPTXISD::Suld1DArrayV2I16Trap;
03047   case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
03048     return NVPTXISD::Suld1DArrayV2I32Trap;
03049   case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
03050     return NVPTXISD::Suld1DArrayV2I64Trap;
03051   case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
03052     return NVPTXISD::Suld1DArrayV4I8Trap;
03053   case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
03054     return NVPTXISD::Suld1DArrayV4I16Trap;
03055   case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
03056     return NVPTXISD::Suld1DArrayV4I32Trap;
03057   case Intrinsic::nvvm_suld_2d_i8_trap:
03058     return NVPTXISD::Suld2DI8Trap;
03059   case Intrinsic::nvvm_suld_2d_i16_trap:
03060     return NVPTXISD::Suld2DI16Trap;
03061   case Intrinsic::nvvm_suld_2d_i32_trap:
03062     return NVPTXISD::Suld2DI32Trap;
03063   case Intrinsic::nvvm_suld_2d_i64_trap:
03064     return NVPTXISD::Suld2DI64Trap;
03065   case Intrinsic::nvvm_suld_2d_v2i8_trap:
03066     return NVPTXISD::Suld2DV2I8Trap;
03067   case Intrinsic::nvvm_suld_2d_v2i16_trap:
03068     return NVPTXISD::Suld2DV2I16Trap;
03069   case Intrinsic::nvvm_suld_2d_v2i32_trap:
03070     return NVPTXISD::Suld2DV2I32Trap;
03071   case Intrinsic::nvvm_suld_2d_v2i64_trap:
03072     return NVPTXISD::Suld2DV2I64Trap;
03073   case Intrinsic::nvvm_suld_2d_v4i8_trap:
03074     return NVPTXISD::Suld2DV4I8Trap;
03075   case Intrinsic::nvvm_suld_2d_v4i16_trap:
03076     return NVPTXISD::Suld2DV4I16Trap;
03077   case Intrinsic::nvvm_suld_2d_v4i32_trap:
03078     return NVPTXISD::Suld2DV4I32Trap;
03079   case Intrinsic::nvvm_suld_2d_array_i8_trap:
03080     return NVPTXISD::Suld2DArrayI8Trap;
03081   case Intrinsic::nvvm_suld_2d_array_i16_trap:
03082     return NVPTXISD::Suld2DArrayI16Trap;
03083   case Intrinsic::nvvm_suld_2d_array_i32_trap:
03084     return NVPTXISD::Suld2DArrayI32Trap;
03085   case Intrinsic::nvvm_suld_2d_array_i64_trap:
03086     return NVPTXISD::Suld2DArrayI64Trap;
03087   case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
03088     return NVPTXISD::Suld2DArrayV2I8Trap;
03089   case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
03090     return NVPTXISD::Suld2DArrayV2I16Trap;
03091   case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
03092     return NVPTXISD::Suld2DArrayV2I32Trap;
03093   case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
03094     return NVPTXISD::Suld2DArrayV2I64Trap;
03095   case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
03096     return NVPTXISD::Suld2DArrayV4I8Trap;
03097   case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
03098     return NVPTXISD::Suld2DArrayV4I16Trap;
03099   case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
03100     return NVPTXISD::Suld2DArrayV4I32Trap;
03101   case Intrinsic::nvvm_suld_3d_i8_trap:
03102     return NVPTXISD::Suld3DI8Trap;
03103   case Intrinsic::nvvm_suld_3d_i16_trap:
03104     return NVPTXISD::Suld3DI16Trap;
03105   case Intrinsic::nvvm_suld_3d_i32_trap:
03106     return NVPTXISD::Suld3DI32Trap;
03107   case Intrinsic::nvvm_suld_3d_i64_trap:
03108     return NVPTXISD::Suld3DI64Trap;
03109   case Intrinsic::nvvm_suld_3d_v2i8_trap:
03110     return NVPTXISD::Suld3DV2I8Trap;
03111   case Intrinsic::nvvm_suld_3d_v2i16_trap:
03112     return NVPTXISD::Suld3DV2I16Trap;
03113   case Intrinsic::nvvm_suld_3d_v2i32_trap:
03114     return NVPTXISD::Suld3DV2I32Trap;
03115   case Intrinsic::nvvm_suld_3d_v2i64_trap:
03116     return NVPTXISD::Suld3DV2I64Trap;
03117   case Intrinsic::nvvm_suld_3d_v4i8_trap:
03118     return NVPTXISD::Suld3DV4I8Trap;
03119   case Intrinsic::nvvm_suld_3d_v4i16_trap:
03120     return NVPTXISD::Suld3DV4I16Trap;
03121   case Intrinsic::nvvm_suld_3d_v4i32_trap:
03122     return NVPTXISD::Suld3DV4I32Trap;
03123   case Intrinsic::nvvm_suld_1d_i8_zero:
03124     return NVPTXISD::Suld1DI8Zero;
03125   case Intrinsic::nvvm_suld_1d_i16_zero:
03126     return NVPTXISD::Suld1DI16Zero;
03127   case Intrinsic::nvvm_suld_1d_i32_zero:
03128     return NVPTXISD::Suld1DI32Zero;
03129   case Intrinsic::nvvm_suld_1d_i64_zero:
03130     return NVPTXISD::Suld1DI64Zero;
03131   case Intrinsic::nvvm_suld_1d_v2i8_zero:
03132     return NVPTXISD::Suld1DV2I8Zero;
03133   case Intrinsic::nvvm_suld_1d_v2i16_zero:
03134     return NVPTXISD::Suld1DV2I16Zero;
03135   case Intrinsic::nvvm_suld_1d_v2i32_zero:
03136     return NVPTXISD::Suld1DV2I32Zero;
03137   case Intrinsic::nvvm_suld_1d_v2i64_zero:
03138     return NVPTXISD::Suld1DV2I64Zero;
03139   case Intrinsic::nvvm_suld_1d_v4i8_zero:
03140     return NVPTXISD::Suld1DV4I8Zero;
03141   case Intrinsic::nvvm_suld_1d_v4i16_zero:
03142     return NVPTXISD::Suld1DV4I16Zero;
03143   case Intrinsic::nvvm_suld_1d_v4i32_zero:
03144     return NVPTXISD::Suld1DV4I32Zero;
03145   case Intrinsic::nvvm_suld_1d_array_i8_zero:
03146     return NVPTXISD::Suld1DArrayI8Zero;
03147   case Intrinsic::nvvm_suld_1d_array_i16_zero:
03148     return NVPTXISD::Suld1DArrayI16Zero;
03149   case Intrinsic::nvvm_suld_1d_array_i32_zero:
03150     return NVPTXISD::Suld1DArrayI32Zero;
03151   case Intrinsic::nvvm_suld_1d_array_i64_zero:
03152     return NVPTXISD::Suld1DArrayI64Zero;
03153   case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
03154     return NVPTXISD::Suld1DArrayV2I8Zero;
03155   case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
03156     return NVPTXISD::Suld1DArrayV2I16Zero;
03157   case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
03158     return NVPTXISD::Suld1DArrayV2I32Zero;
03159   case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
03160     return NVPTXISD::Suld1DArrayV2I64Zero;
03161   case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
03162     return NVPTXISD::Suld1DArrayV4I8Zero;
03163   case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
03164     return NVPTXISD::Suld1DArrayV4I16Zero;
03165   case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
03166     return NVPTXISD::Suld1DArrayV4I32Zero;
03167   case Intrinsic::nvvm_suld_2d_i8_zero:
03168     return NVPTXISD::Suld2DI8Zero;
03169   case Intrinsic::nvvm_suld_2d_i16_zero:
03170     return NVPTXISD::Suld2DI16Zero;
03171   case Intrinsic::nvvm_suld_2d_i32_zero:
03172     return NVPTXISD::Suld2DI32Zero;
03173   case Intrinsic::nvvm_suld_2d_i64_zero:
03174     return NVPTXISD::Suld2DI64Zero;
03175   case Intrinsic::nvvm_suld_2d_v2i8_zero:
03176     return NVPTXISD::Suld2DV2I8Zero;
03177   case Intrinsic::nvvm_suld_2d_v2i16_zero:
03178     return NVPTXISD::Suld2DV2I16Zero;
03179   case Intrinsic::nvvm_suld_2d_v2i32_zero:
03180     return NVPTXISD::Suld2DV2I32Zero;
03181   case Intrinsic::nvvm_suld_2d_v2i64_zero:
03182     return NVPTXISD::Suld2DV2I64Zero;
03183   case Intrinsic::nvvm_suld_2d_v4i8_zero:
03184     return NVPTXISD::Suld2DV4I8Zero;
03185   case Intrinsic::nvvm_suld_2d_v4i16_zero:
03186     return NVPTXISD::Suld2DV4I16Zero;
03187   case Intrinsic::nvvm_suld_2d_v4i32_zero:
03188     return NVPTXISD::Suld2DV4I32Zero;
03189   case Intrinsic::nvvm_suld_2d_array_i8_zero:
03190     return NVPTXISD::Suld2DArrayI8Zero;
03191   case Intrinsic::nvvm_suld_2d_array_i16_zero:
03192     return NVPTXISD::Suld2DArrayI16Zero;
03193   case Intrinsic::nvvm_suld_2d_array_i32_zero:
03194     return NVPTXISD::Suld2DArrayI32Zero;
03195   case Intrinsic::nvvm_suld_2d_array_i64_zero:
03196     return NVPTXISD::Suld2DArrayI64Zero;
03197   case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
03198     return NVPTXISD::Suld2DArrayV2I8Zero;
03199   case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
03200     return NVPTXISD::Suld2DArrayV2I16Zero;
03201   case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
03202     return NVPTXISD::Suld2DArrayV2I32Zero;
03203   case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
03204     return NVPTXISD::Suld2DArrayV2I64Zero;
03205   case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
03206     return NVPTXISD::Suld2DArrayV4I8Zero;
03207   case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
03208     return NVPTXISD::Suld2DArrayV4I16Zero;
03209   case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
03210     return NVPTXISD::Suld2DArrayV4I32Zero;
03211   case Intrinsic::nvvm_suld_3d_i8_zero:
03212     return NVPTXISD::Suld3DI8Zero;
03213   case Intrinsic::nvvm_suld_3d_i16_zero:
03214     return NVPTXISD::Suld3DI16Zero;
03215   case Intrinsic::nvvm_suld_3d_i32_zero:
03216     return NVPTXISD::Suld3DI32Zero;
03217   case Intrinsic::nvvm_suld_3d_i64_zero:
03218     return NVPTXISD::Suld3DI64Zero;
03219   case Intrinsic::nvvm_suld_3d_v2i8_zero:
03220     return NVPTXISD::Suld3DV2I8Zero;
03221   case Intrinsic::nvvm_suld_3d_v2i16_zero:
03222     return NVPTXISD::Suld3DV2I16Zero;
03223   case Intrinsic::nvvm_suld_3d_v2i32_zero:
03224     return NVPTXISD::Suld3DV2I32Zero;
03225   case Intrinsic::nvvm_suld_3d_v2i64_zero:
03226     return NVPTXISD::Suld3DV2I64Zero;
03227   case Intrinsic::nvvm_suld_3d_v4i8_zero:
03228     return NVPTXISD::Suld3DV4I8Zero;
03229   case Intrinsic::nvvm_suld_3d_v4i16_zero:
03230     return NVPTXISD::Suld3DV4I16Zero;
03231   case Intrinsic::nvvm_suld_3d_v4i32_zero:
03232     return NVPTXISD::Suld3DV4I32Zero;
03233   }
03234 }
03235 
03236 // llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
03237 // TgtMemIntrinsic
03238 // because we need the information that is only available in the "Value" type
03239 // of destination
03240 // pointer. In particular, the address space information.
03241 bool NVPTXTargetLowering::getTgtMemIntrinsic(
03242     IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
03243   switch (Intrinsic) {
03244   default:
03245     return false;
03246 
03247   case Intrinsic::nvvm_atomic_load_add_f32:
03248     Info.opc = ISD::INTRINSIC_W_CHAIN;
03249     Info.memVT = MVT::f32;
03250     Info.ptrVal = I.getArgOperand(0);
03251     Info.offset = 0;
03252     Info.vol = 0;
03253     Info.readMem = true;
03254     Info.writeMem = true;
03255     Info.align = 0;
03256     return true;
03257 
03258   case Intrinsic::nvvm_atomic_load_inc_32:
03259   case Intrinsic::nvvm_atomic_load_dec_32:
03260     Info.opc = ISD::INTRINSIC_W_CHAIN;
03261     Info.memVT = MVT::i32;
03262     Info.ptrVal = I.getArgOperand(0);
03263     Info.offset = 0;
03264     Info.vol = 0;
03265     Info.readMem = true;
03266     Info.writeMem = true;
03267     Info.align = 0;
03268     return true;
03269 
03270   case Intrinsic::nvvm_ldu_global_i:
03271   case Intrinsic::nvvm_ldu_global_f:
03272   case Intrinsic::nvvm_ldu_global_p: {
03273     auto &DL = I.getModule()->getDataLayout();
03274     Info.opc = ISD::INTRINSIC_W_CHAIN;
03275     if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
03276       Info.memVT = getValueType(DL, I.getType());
03277     else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
03278       Info.memVT = getPointerTy(DL);
03279     else
03280       Info.memVT = getValueType(DL, I.getType());
03281     Info.ptrVal = I.getArgOperand(0);
03282     Info.offset = 0;
03283     Info.vol = 0;
03284     Info.readMem = true;
03285     Info.writeMem = false;
03286     Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
03287 
03288     return true;
03289   }
03290   case Intrinsic::nvvm_ldg_global_i:
03291   case Intrinsic::nvvm_ldg_global_f:
03292   case Intrinsic::nvvm_ldg_global_p: {
03293     auto &DL = I.getModule()->getDataLayout();
03294 
03295     Info.opc = ISD::INTRINSIC_W_CHAIN;
03296     if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
03297       Info.memVT = getValueType(DL, I.getType());
03298     else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
03299       Info.memVT = getPointerTy(DL);
03300     else
03301       Info.memVT = getValueType(DL, I.getType());
03302     Info.ptrVal = I.getArgOperand(0);
03303     Info.offset = 0;
03304     Info.vol = 0;
03305     Info.readMem = true;
03306     Info.writeMem = false;
03307     Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
03308 
03309     return true;
03310   }
03311 
03312   case Intrinsic::nvvm_tex_1d_v4f32_s32:
03313   case Intrinsic::nvvm_tex_1d_v4f32_f32:
03314   case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
03315   case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
03316   case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
03317   case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
03318   case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
03319   case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
03320   case Intrinsic::nvvm_tex_2d_v4f32_s32:
03321   case Intrinsic::nvvm_tex_2d_v4f32_f32:
03322   case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
03323   case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
03324   case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
03325   case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
03326   case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
03327   case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
03328   case Intrinsic::nvvm_tex_3d_v4f32_s32:
03329   case Intrinsic::nvvm_tex_3d_v4f32_f32:
03330   case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
03331   case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
03332   case Intrinsic::nvvm_tex_cube_v4f32_f32:
03333   case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
03334   case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
03335   case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
03336   case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
03337   case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
03338   case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
03339   case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
03340   case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
03341   case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
03342   case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
03343   case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
03344   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
03345   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
03346   case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
03347   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
03348   case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
03349   case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
03350   case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
03351   case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
03352   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
03353   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
03354   case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
03355   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
03356   case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
03357   case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
03358   case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
03359   case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
03360   case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
03361   case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
03362   case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
03363   case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
03364   case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
03365   case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
03366   case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
03367   case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32: {
03368     Info.opc = getOpcForTextureInstr(Intrinsic);
03369     Info.memVT = MVT::v4f32;
03370     Info.ptrVal = nullptr;
03371     Info.offset = 0;
03372     Info.vol = 0;
03373     Info.readMem = true;
03374     Info.writeMem = false;
03375     Info.align = 16;
03376     return true;
03377   }
03378   case Intrinsic::nvvm_tex_1d_v4s32_s32:
03379   case Intrinsic::nvvm_tex_1d_v4s32_f32:
03380   case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
03381   case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
03382   case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
03383   case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
03384   case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
03385   case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
03386   case Intrinsic::nvvm_tex_2d_v4s32_s32:
03387   case Intrinsic::nvvm_tex_2d_v4s32_f32:
03388   case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
03389   case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
03390   case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
03391   case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
03392   case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
03393   case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
03394   case Intrinsic::nvvm_tex_3d_v4s32_s32:
03395   case Intrinsic::nvvm_tex_3d_v4s32_f32:
03396   case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
03397   case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
03398   case Intrinsic::nvvm_tex_cube_v4s32_f32:
03399   case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
03400   case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
03401   case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
03402   case Intrinsic::nvvm_tex_cube_v4u32_f32:
03403   case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
03404   case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
03405   case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
03406   case Intrinsic::nvvm_tex_1d_v4u32_s32:
03407   case Intrinsic::nvvm_tex_1d_v4u32_f32:
03408   case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
03409   case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
03410   case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
03411   case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
03412   case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
03413   case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
03414   case Intrinsic::nvvm_tex_2d_v4u32_s32:
03415   case Intrinsic::nvvm_tex_2d_v4u32_f32:
03416   case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
03417   case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
03418   case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
03419   case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
03420   case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
03421   case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
03422   case Intrinsic::nvvm_tex_3d_v4u32_s32:
03423   case Intrinsic::nvvm_tex_3d_v4u32_f32:
03424   case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
03425   case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
03426   case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
03427   case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
03428   case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
03429   case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
03430   case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
03431   case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
03432   case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
03433   case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
03434   case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
03435   case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
03436   case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
03437   case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
03438   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
03439   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
03440   case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
03441   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
03442   case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
03443   case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
03444   case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
03445   case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
03446   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
03447   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
03448   case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
03449   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
03450   case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
03451   case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
03452   case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
03453   case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
03454   case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
03455   case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
03456   case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
03457   case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
03458   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
03459   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
03460   case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
03461   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
03462   case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
03463   case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
03464   case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
03465   case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
03466   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
03467   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
03468   case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
03469   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
03470   case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
03471   case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
03472   case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
03473   case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
03474   case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
03475   case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
03476   case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
03477   case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
03478   case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
03479   case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
03480   case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
03481   case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
03482   case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
03483   case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
03484   case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
03485   case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
03486   case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
03487   case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
03488   case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
03489   case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32: {
03490     Info.opc = getOpcForTextureInstr(Intrinsic);
03491     Info.memVT = MVT::v4i32;
03492     Info.ptrVal = nullptr;
03493     Info.offset = 0;
03494     Info.vol = 0;
03495     Info.readMem = true;
03496     Info.writeMem = false;
03497     Info.align = 16;
03498     return true;
03499   }
03500   case Intrinsic::nvvm_suld_1d_i8_clamp:
03501   case Intrinsic::nvvm_suld_1d_v2i8_clamp:
03502   case Intrinsic::nvvm_suld_1d_v4i8_clamp:
03503   case Intrinsic::nvvm_suld_1d_array_i8_clamp:
03504   case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
03505   case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
03506   case Intrinsic::nvvm_suld_2d_i8_clamp:
03507   case Intrinsic::nvvm_suld_2d_v2i8_clamp:
03508   case Intrinsic::nvvm_suld_2d_v4i8_clamp:
03509   case Intrinsic::nvvm_suld_2d_array_i8_clamp:
03510   case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
03511   case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
03512   case Intrinsic::nvvm_suld_3d_i8_clamp:
03513   case Intrinsic::nvvm_suld_3d_v2i8_clamp:
03514   case Intrinsic::nvvm_suld_3d_v4i8_clamp:
03515   case Intrinsic::nvvm_suld_1d_i8_trap:
03516   case Intrinsic::nvvm_suld_1d_v2i8_trap:
03517   case Intrinsic::nvvm_suld_1d_v4i8_trap:
03518   case Intrinsic::nvvm_suld_1d_array_i8_trap:
03519   case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
03520   case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
03521   case Intrinsic::nvvm_suld_2d_i8_trap:
03522   case Intrinsic::nvvm_suld_2d_v2i8_trap:
03523   case Intrinsic::nvvm_suld_2d_v4i8_trap:
03524   case Intrinsic::nvvm_suld_2d_array_i8_trap:
03525   case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
03526   case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
03527   case Intrinsic::nvvm_suld_3d_i8_trap:
03528   case Intrinsic::nvvm_suld_3d_v2i8_trap:
03529   case Intrinsic::nvvm_suld_3d_v4i8_trap:
03530   case Intrinsic::nvvm_suld_1d_i8_zero:
03531   case Intrinsic::nvvm_suld_1d_v2i8_zero:
03532   case Intrinsic::nvvm_suld_1d_v4i8_zero:
03533   case Intrinsic::nvvm_suld_1d_array_i8_zero:
03534   case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
03535   case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
03536   case Intrinsic::nvvm_suld_2d_i8_zero:
03537   case Intrinsic::nvvm_suld_2d_v2i8_zero:
03538   case Intrinsic::nvvm_suld_2d_v4i8_zero:
03539   case Intrinsic::nvvm_suld_2d_array_i8_zero:
03540   case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
03541   case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
03542   case Intrinsic::nvvm_suld_3d_i8_zero:
03543   case Intrinsic::nvvm_suld_3d_v2i8_zero:
03544   case Intrinsic::nvvm_suld_3d_v4i8_zero: {
03545     Info.opc = getOpcForSurfaceInstr(Intrinsic);
03546     Info.memVT = MVT::i8;
03547     Info.ptrVal = nullptr;
03548     Info.offset = 0;
03549     Info.vol = 0;
03550     Info.readMem = true;
03551     Info.writeMem = false;
03552     Info.align = 16;
03553     return true;
03554   }
03555   case Intrinsic::nvvm_suld_1d_i16_clamp:
03556   case Intrinsic::nvvm_suld_1d_v2i16_clamp:
03557   case Intrinsic::nvvm_suld_1d_v4i16_clamp:
03558   case Intrinsic::nvvm_suld_1d_array_i16_clamp:
03559   case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
03560   case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
03561   case Intrinsic::nvvm_suld_2d_i16_clamp:
03562   case Intrinsic::nvvm_suld_2d_v2i16_clamp:
03563   case Intrinsic::nvvm_suld_2d_v4i16_clamp:
03564   case Intrinsic::nvvm_suld_2d_array_i16_clamp:
03565   case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
03566   case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
03567   case Intrinsic::nvvm_suld_3d_i16_clamp:
03568   case Intrinsic::nvvm_suld_3d_v2i16_clamp:
03569   case Intrinsic::nvvm_suld_3d_v4i16_clamp:
03570   case Intrinsic::nvvm_suld_1d_i16_trap:
03571   case Intrinsic::nvvm_suld_1d_v2i16_trap:
03572   case Intrinsic::nvvm_suld_1d_v4i16_trap:
03573   case Intrinsic::nvvm_suld_1d_array_i16_trap:
03574   case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
03575   case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
03576   case Intrinsic::nvvm_suld_2d_i16_trap:
03577   case Intrinsic::nvvm_suld_2d_v2i16_trap:
03578   case Intrinsic::nvvm_suld_2d_v4i16_trap:
03579   case Intrinsic::nvvm_suld_2d_array_i16_trap:
03580   case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
03581   case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
03582   case Intrinsic::nvvm_suld_3d_i16_trap:
03583   case Intrinsic::nvvm_suld_3d_v2i16_trap:
03584   case Intrinsic::nvvm_suld_3d_v4i16_trap:
03585   case Intrinsic::nvvm_suld_1d_i16_zero:
03586   case Intrinsic::nvvm_suld_1d_v2i16_zero:
03587   case Intrinsic::nvvm_suld_1d_v4i16_zero:
03588   case Intrinsic::nvvm_suld_1d_array_i16_zero:
03589   case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
03590   case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
03591   case Intrinsic::nvvm_suld_2d_i16_zero:
03592   case Intrinsic::nvvm_suld_2d_v2i16_zero:
03593   case Intrinsic::nvvm_suld_2d_v4i16_zero:
03594   case Intrinsic::nvvm_suld_2d_array_i16_zero:
03595   case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
03596   case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
03597   case Intrinsic::nvvm_suld_3d_i16_zero:
03598   case Intrinsic::nvvm_suld_3d_v2i16_zero:
03599   case Intrinsic::nvvm_suld_3d_v4i16_zero: {
03600     Info.opc = getOpcForSurfaceInstr(Intrinsic);
03601     Info.memVT = MVT::i16;
03602     Info.ptrVal = nullptr;
03603     Info.offset = 0;
03604     Info.vol = 0;
03605     Info.readMem = true;
03606     Info.writeMem = false;
03607     Info.align = 16;
03608     return true;
03609   }
03610   case Intrinsic::nvvm_suld_1d_i32_clamp:
03611   case Intrinsic::nvvm_suld_1d_v2i32_clamp:
03612   case Intrinsic::nvvm_suld_1d_v4i32_clamp:
03613   case Intrinsic::nvvm_suld_1d_array_i32_clamp:
03614   case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
03615   case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
03616   case Intrinsic::nvvm_suld_2d_i32_clamp:
03617   case Intrinsic::nvvm_suld_2d_v2i32_clamp:
03618   case Intrinsic::nvvm_suld_2d_v4i32_clamp:
03619   case Intrinsic::nvvm_suld_2d_array_i32_clamp:
03620   case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
03621   case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
03622   case Intrinsic::nvvm_suld_3d_i32_clamp:
03623   case Intrinsic::nvvm_suld_3d_v2i32_clamp:
03624   case Intrinsic::nvvm_suld_3d_v4i32_clamp:
03625   case Intrinsic::nvvm_suld_1d_i32_trap:
03626   case Intrinsic::nvvm_suld_1d_v2i32_trap:
03627   case Intrinsic::nvvm_suld_1d_v4i32_trap:
03628   case Intrinsic::nvvm_suld_1d_array_i32_trap:
03629   case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
03630   case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
03631   case Intrinsic::nvvm_suld_2d_i32_trap:
03632   case Intrinsic::nvvm_suld_2d_v2i32_trap:
03633   case Intrinsic::nvvm_suld_2d_v4i32_trap:
03634   case Intrinsic::nvvm_suld_2d_array_i32_trap:
03635   case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
03636   case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
03637   case Intrinsic::nvvm_suld_3d_i32_trap:
03638   case Intrinsic::nvvm_suld_3d_v2i32_trap:
03639   case Intrinsic::nvvm_suld_3d_v4i32_trap:
03640   case Intrinsic::nvvm_suld_1d_i32_zero:
03641   case Intrinsic::nvvm_suld_1d_v2i32_zero:
03642   case Intrinsic::nvvm_suld_1d_v4i32_zero:
03643   case Intrinsic::nvvm_suld_1d_array_i32_zero:
03644   case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
03645   case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
03646   case Intrinsic::nvvm_suld_2d_i32_zero:
03647   case Intrinsic::nvvm_suld_2d_v2i32_zero:
03648   case Intrinsic::nvvm_suld_2d_v4i32_zero:
03649   case Intrinsic::nvvm_suld_2d_array_i32_zero:
03650   case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
03651   case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
03652   case Intrinsic::nvvm_suld_3d_i32_zero:
03653   case Intrinsic::nvvm_suld_3d_v2i32_zero:
03654   case Intrinsic::nvvm_suld_3d_v4i32_zero: {
03655     Info.opc = getOpcForSurfaceInstr(Intrinsic);
03656     Info.memVT = MVT::i32;
03657     Info.ptrVal = nullptr;
03658     Info.offset = 0;
03659     Info.vol = 0;
03660     Info.readMem = true;
03661     Info.writeMem = false;
03662     Info.align = 16;
03663     return true;
03664   }
03665   case Intrinsic::nvvm_suld_1d_i64_clamp:
03666   case Intrinsic::nvvm_suld_1d_v2i64_clamp:
03667   case Intrinsic::nvvm_suld_1d_array_i64_clamp:
03668   case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
03669   case Intrinsic::nvvm_suld_2d_i64_clamp:
03670   case Intrinsic::nvvm_suld_2d_v2i64_clamp:
03671   case Intrinsic::nvvm_suld_2d_array_i64_clamp:
03672   case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
03673   case Intrinsic::nvvm_suld_3d_i64_clamp:
03674   case Intrinsic::nvvm_suld_3d_v2i64_clamp:
03675   case Intrinsic::nvvm_suld_1d_i64_trap:
03676   case Intrinsic::nvvm_suld_1d_v2i64_trap:
03677   case Intrinsic::nvvm_suld_1d_array_i64_trap:
03678   case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
03679   case Intrinsic::nvvm_suld_2d_i64_trap:
03680   case Intrinsic::nvvm_suld_2d_v2i64_trap:
03681   case Intrinsic::nvvm_suld_2d_array_i64_trap:
03682   case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
03683   case Intrinsic::nvvm_suld_3d_i64_trap:
03684   case Intrinsic::nvvm_suld_3d_v2i64_trap:
03685   case Intrinsic::nvvm_suld_1d_i64_zero:
03686   case Intrinsic::nvvm_suld_1d_v2i64_zero:
03687   case Intrinsic::nvvm_suld_1d_array_i64_zero:
03688   case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
03689   case Intrinsic::nvvm_suld_2d_i64_zero:
03690   case Intrinsic::nvvm_suld_2d_v2i64_zero:
03691   case Intrinsic::nvvm_suld_2d_array_i64_zero:
03692   case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
03693   case Intrinsic::nvvm_suld_3d_i64_zero:
03694   case Intrinsic::nvvm_suld_3d_v2i64_zero: {
03695     Info.opc = getOpcForSurfaceInstr(Intrinsic);
03696     Info.memVT = MVT::i64;
03697     Info.ptrVal = nullptr;
03698     Info.offset = 0;
03699     Info.vol = 0;
03700     Info.readMem = true;
03701     Info.writeMem = false;
03702     Info.align = 16;
03703     return true;
03704   }
03705   }
03706   return false;
03707 }
03708 
03709 /// isLegalAddressingMode - Return true if the addressing mode represented
03710 /// by AM is legal for this target, for a load/store of the specified type.
03711 /// Used to guide target specific optimizations, like loop strength reduction
03712 /// (LoopStrengthReduce.cpp) and memory optimization for address mode
03713 /// (CodeGenPrepare.cpp)
03714 bool NVPTXTargetLowering::isLegalAddressingMode(const DataLayout &DL,
03715                                                 const AddrMode &AM, Type *Ty,
03716                                                 unsigned AS) const {
03717 
03718   // AddrMode - This represents an addressing mode of:
03719   //    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
03720   //
03721   // The legal address modes are
03722   // - [avar]
03723   // - [areg]
03724   // - [areg+immoff]
03725   // - [immAddr]
03726 
03727   if (AM.BaseGV) {
03728     return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale;
03729   }
03730 
03731   switch (AM.Scale) {
03732   case 0: // "r", "r+i" or "i" is allowed
03733     break;
03734   case 1:
03735     if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
03736       return false;
03737     // Otherwise we have r+i.
03738     break;
03739   default:
03740     // No scale > 1 is allowed
03741     return false;
03742   }
03743   return true;
03744 }
03745 
03746 //===----------------------------------------------------------------------===//
03747 //                         NVPTX Inline Assembly Support
03748 //===----------------------------------------------------------------------===//
03749 
03750 /// getConstraintType - Given a constraint letter, return the type of
03751 /// constraint it is for this target.
03752 NVPTXTargetLowering::ConstraintType
03753 NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {
03754   if (Constraint.size() == 1) {
03755     switch (Constraint[0]) {
03756     default:
03757       break;
03758     case 'b':
03759     case 'r':
03760     case 'h':
03761     case 'c':
03762     case 'l':
03763     case 'f':
03764     case 'd':
03765     case '0':
03766     case 'N':
03767       return C_RegisterClass;
03768     }
03769   }
03770   return TargetLowering::getConstraintType(Constraint);
03771 }
03772 
03773 std::pair<unsigned, const TargetRegisterClass *>
03774 NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
03775                                                   StringRef Constraint,
03776                                                   MVT VT) const {
03777   if (Constraint.size() == 1) {
03778     switch (Constraint[0]) {
03779     case 'b':
03780       return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
03781     case 'c':
03782       return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
03783     case 'h':
03784       return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
03785     case 'r':
03786       return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
03787     case 'l':
03788     case 'N':
03789       return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
03790     case 'f':
03791       return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
03792     case 'd':
03793       return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
03794     }
03795   }
03796   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
03797 }
03798 
03799 //===----------------------------------------------------------------------===//
03800 //                         NVPTX DAG Combining
03801 //===----------------------------------------------------------------------===//
03802 
03803 bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
03804                                    CodeGenOpt::Level OptLevel) const {
03805   const Function *F = MF.getFunction();
03806   const TargetOptions &TO = MF.getTarget().Options;
03807 
03808   // Always honor command-line argument
03809   if (FMAContractLevelOpt.getNumOccurrences() > 0) {
03810     return FMAContractLevelOpt > 0;
03811   } else if (OptLevel == 0) {
03812     // Do not contract if we're not optimizing the code
03813     return false;
03814   } else if (TO.AllowFPOpFusion == FPOpFusion::Fast || TO.UnsafeFPMath) {
03815     // Honor TargetOptions flags that explicitly say fusion is okay
03816     return true;
03817   } else if (F->hasFnAttribute("unsafe-fp-math")) {
03818     // Check for unsafe-fp-math=true coming from Clang
03819     Attribute Attr = F->getFnAttribute("unsafe-fp-math");
03820     StringRef Val = Attr.getValueAsString();
03821     if (Val == "true")
03822       return true;
03823   }
03824 
03825   // We did not have a clear indication that fusion is allowed, so assume not
03826   return false;
03827 }
03828 
03829 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
03830 /// operands N0 and N1.  This is a helper for PerformADDCombine that is
03831 /// called with the default operands, and if that fails, with commuted
03832 /// operands.
03833 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
03834                                            TargetLowering::DAGCombinerInfo &DCI,
03835                                              const NVPTXSubtarget &Subtarget,
03836                                              CodeGenOpt::Level OptLevel) {
03837   SelectionDAG  &DAG = DCI.DAG;
03838   // Skip non-integer, non-scalar case
03839   EVT VT=N0.getValueType();
03840   if (VT.isVector())
03841     return SDValue();
03842 
03843   // fold (add (mul a, b), c) -> (mad a, b, c)
03844   //
03845   if (N0.getOpcode() == ISD::MUL) {
03846     assert (VT.isInteger());
03847     // For integer:
03848     // Since integer multiply-add costs the same as integer multiply
03849     // but is more costly than integer add, do the fusion only when
03850     // the mul is only used in the add.
03851     if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
03852         !N0.getNode()->hasOneUse())
03853       return SDValue();
03854 
03855     // Do the folding
03856     return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
03857                        N0.getOperand(0), N0.getOperand(1), N1);
03858   }
03859   else if (N0.getOpcode() == ISD::FMUL) {
03860     if (VT == MVT::f32 || VT == MVT::f64) {
03861       const auto *TLI = static_cast<const NVPTXTargetLowering *>(
03862           &DAG.getTargetLoweringInfo());
03863       if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
03864         return SDValue();
03865 
03866       // For floating point:
03867       // Do the fusion only when the mul has less than 5 uses and all
03868       // are add.
03869       // The heuristic is that if a use is not an add, then that use
03870       // cannot be fused into fma, therefore mul is still needed anyway.
03871       // If there are more than 4 uses, even if they are all add, fusing
03872       // them will increase register pressue.
03873       //
03874       int numUses = 0;
03875       int nonAddCount = 0;
03876       for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
03877            UE = N0.getNode()->use_end();
03878            UI != UE; ++UI) {
03879         numUses++;
03880         SDNode *User = *UI;
03881         if (User->getOpcode() != ISD::FADD)
03882           ++nonAddCount;
03883       }
03884       if (numUses >= 5)
03885         return SDValue();
03886       if (nonAddCount) {
03887         int orderNo = N->getIROrder();
03888         int orderNo2 = N0.getNode()->getIROrder();
03889         // simple heuristics here for considering potential register
03890         // pressure, the logics here is that the differnce are used
03891         // to measure the distance between def and use, the longer distance
03892         // more likely cause register pressure.
03893         if (orderNo - orderNo2 < 500)
03894           return SDValue();
03895 
03896         // Now, check if at least one of the FMUL's operands is live beyond the node N,
03897         // which guarantees that the FMA will not increase register pressure at node N.
03898         bool opIsLive = false;
03899         const SDNode *left = N0.getOperand(0).getNode();
03900         const SDNode *right = N0.getOperand(1).getNode();
03901 
03902         if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
03903           opIsLive = true;
03904 
03905         if (!opIsLive)
03906           for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
03907             SDNode *User = *UI;
03908             int orderNo3 = User->getIROrder();
03909             if (orderNo3 > orderNo) {
03910               opIsLive = true;
03911               break;
03912             }
03913           }
03914 
03915         if (!opIsLive)
03916           for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
03917             SDNode *User = *UI;
03918             int orderNo3 = User->getIROrder();
03919             if (orderNo3 > orderNo) {
03920               opIsLive = true;
03921               break;
03922             }
03923           }
03924 
03925         if (!opIsLive)
03926           return SDValue();
03927       }
03928 
03929       return DAG.getNode(ISD::FMA, SDLoc(N), VT,
03930                          N0.getOperand(0), N0.getOperand(1), N1);
03931     }
03932   }
03933 
03934   return SDValue();
03935 }
03936 
03937 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
03938 ///
03939 static SDValue PerformADDCombine(SDNode *N,
03940                                  TargetLowering::DAGCombinerInfo &DCI,
03941                                  const NVPTXSubtarget &Subtarget,
03942                                  CodeGenOpt::Level OptLevel) {
03943   SDValue N0 = N->getOperand(0);
03944   SDValue N1 = N->getOperand(1);
03945 
03946   // First try with the default operand order.
03947   SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
03948                                                  OptLevel);
03949   if (Result.getNode())
03950     return Result;
03951 
03952   // If that didn't work, try again with the operands commuted.
03953   return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
03954 }
03955 
03956 static SDValue PerformANDCombine(SDNode *N,
03957                                  TargetLowering::DAGCombinerInfo &DCI) {
03958   // The type legalizer turns a vector load of i8 values into a zextload to i16
03959   // registers, optionally ANY_EXTENDs it (if target type is integer),
03960   // and ANDs off the high 8 bits. Since we turn this load into a
03961   // target-specific DAG node, the DAG combiner fails to eliminate these AND
03962   // nodes. Do that here.
03963   SDValue Val = N->getOperand(0);
03964   SDValue Mask = N->getOperand(1);
03965 
03966   if (isa<ConstantSDNode>(Val)) {
03967     std::swap(Val, Mask);
03968   }
03969 
03970   SDValue AExt;
03971   // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
03972   if (Val.getOpcode() == ISD::ANY_EXTEND) {
03973     AExt = Val;
03974     Val = Val->getOperand(0);
03975   }
03976 
03977   if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
03978     Val = Val->getOperand(0);
03979   }
03980 
03981   if (Val->getOpcode() == NVPTXISD::LoadV2 ||
03982       Val->getOpcode() == NVPTXISD::LoadV4) {
03983     ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
03984     if (!MaskCnst) {
03985       // Not an AND with a constant
03986       return SDValue();
03987     }
03988 
03989     uint64_t MaskVal = MaskCnst->getZExtValue();
03990     if (MaskVal != 0xff) {
03991       // Not an AND that chops off top 8 bits
03992       return SDValue();
03993     }
03994 
03995     MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
03996     if (!Mem) {
03997       // Not a MemSDNode?!?
03998       return SDValue();
03999     }
04000 
04001     EVT MemVT = Mem->getMemoryVT();
04002     if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
04003       // We only handle the i8 case
04004       return SDValue();
04005     }
04006 
04007     unsigned ExtType =
04008       cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
04009         getZExtValue();
04010     if (ExtType == ISD::SEXTLOAD) {
04011       // If for some reason the load is a sextload, the and is needed to zero
04012       // out the high 8 bits
04013       return SDValue();
04014     }
04015 
04016     bool AddTo = false;
04017     if (AExt.getNode() != 0) {
04018       // Re-insert the ext as a zext.
04019       Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
04020                             AExt.getValueType(), Val);
04021       AddTo = true;
04022     }
04023 
04024     // If we get here, the AND is unnecessary.  Just replace it with the load
04025     DCI.CombineTo(N, Val, AddTo);
04026   }
04027 
04028   return SDValue();
04029 }
04030 
04031 static SDValue PerformSELECTCombine(SDNode *N,
04032                                     TargetLowering::DAGCombinerInfo &DCI) {
04033   // Currently this detects patterns for integer min and max and
04034   // lowers them to PTX-specific intrinsics that enable hardware
04035   // support.
04036 
04037   const SDValue Cond = N->getOperand(0);
04038   if (Cond.getOpcode() != ISD::SETCC) return SDValue();
04039 
04040   const SDValue LHS = Cond.getOperand(0);
04041   const SDValue RHS = Cond.getOperand(1);
04042   const SDValue True = N->getOperand(1);
04043   const SDValue False = N->getOperand(2);
04044   if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
04045     return SDValue();
04046 
04047   const EVT VT = N->getValueType(0);
04048   if (VT != MVT::i32 && VT != MVT::i64) return SDValue();
04049 
04050   const ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
04051   SDValue Larger;  // The larger of LHS and RHS when condition is true.
04052   switch (CC) {
04053     case ISD::SETULT:
04054     case ISD::SETULE:
04055     case ISD::SETLT:
04056     case ISD::SETLE:
04057       Larger = RHS;
04058       break;
04059 
04060     case ISD::SETGT:
04061     case ISD::SETGE:
04062     case ISD::SETUGT:
04063     case ISD::SETUGE:
04064       Larger = LHS;
04065       break;
04066 
04067     default:
04068       return SDValue();
04069   }
04070   const bool IsMax = (Larger == True);
04071   const bool IsSigned = ISD::isSignedIntSetCC(CC);
04072 
04073   unsigned IntrinsicId;
04074   if (VT == MVT::i32) {
04075     if (IsSigned)
04076       IntrinsicId = IsMax ? Intrinsic::nvvm_max_i : Intrinsic::nvvm_min_i;
04077     else
04078       IntrinsicId = IsMax ? Intrinsic::nvvm_max_ui : Intrinsic::nvvm_min_ui;
04079   } else {
04080     assert(VT == MVT::i64);
04081     if (IsSigned)
04082       IntrinsicId = IsMax ? Intrinsic::nvvm_max_ll : Intrinsic::nvvm_min_ll;
04083     else
04084       IntrinsicId = IsMax ? Intrinsic::nvvm_max_ull : Intrinsic::nvvm_min_ull;
04085   }
04086 
04087   SDLoc DL(N);
04088   return DCI.DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
04089                          DCI.DAG.getConstant(IntrinsicId, DL, VT), LHS, RHS);
04090 }
04091 
04092 enum OperandSignedness {
04093   Signed = 0,
04094   Unsigned,
04095   Unknown
04096 };
04097 
04098 /// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
04099 /// that can be demoted to \p OptSize bits without loss of information. The
04100 /// signedness of the operand, if determinable, is placed in \p S.
04101 static bool IsMulWideOperandDemotable(SDValue Op,
04102                                       unsigned OptSize,
04103                                       OperandSignedness &S) {
04104   S = Unknown;
04105 
04106   if (Op.getOpcode() == ISD::SIGN_EXTEND ||
04107       Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
04108     EVT OrigVT = Op.getOperand(0).getValueType();
04109     if (OrigVT.getSizeInBits() <= OptSize) {
04110       S = Signed;
04111       return true;
04112     }
04113   } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
04114     EVT OrigVT = Op.getOperand(0).getValueType();
04115     if (OrigVT.getSizeInBits() <= OptSize) {
04116       S = Unsigned;
04117       return true;
04118     }
04119   }
04120 
04121   return false;
04122 }
04123 
04124 /// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
04125 /// be demoted to \p OptSize bits without loss of information. If the operands
04126 /// contain a constant, it should appear as the RHS operand. The signedness of
04127 /// the operands is placed in \p IsSigned.
04128 static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
04129                                         unsigned OptSize,
04130                                         bool &IsSigned) {
04131 
04132   OperandSignedness LHSSign;
04133 
04134   // The LHS operand must be a demotable op
04135   if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
04136     return false;
04137 
04138   // We should have been able to determine the signedness from the LHS
04139   if (LHSSign == Unknown)
04140     return false;
04141 
04142   IsSigned = (LHSSign == Signed);
04143 
04144   // The RHS can be a demotable op or a constant
04145   if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
04146     APInt Val = CI->getAPIntValue();
04147     if (LHSSign == Unsigned) {
04148       return Val.isIntN(OptSize);
04149     } else {
04150       return Val.isSignedIntN(OptSize);
04151     }
04152   } else {
04153     OperandSignedness RHSSign;
04154     if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
04155       return false;
04156 
04157     return LHSSign == RHSSign;
04158   }
04159 }
04160 
04161 /// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
04162 /// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
04163 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
04164 /// amount.
04165 static SDValue TryMULWIDECombine(SDNode *N,
04166                                  TargetLowering::DAGCombinerInfo &DCI) {
04167   EVT MulType = N->getValueType(0);
04168   if (MulType != MVT::i32 && MulType != MVT::i64) {
04169     return SDValue();
04170   }
04171 
04172   SDLoc DL(N);
04173   unsigned OptSize = MulType.getSizeInBits() >> 1;
04174   SDValue LHS = N->getOperand(0);
04175   SDValue RHS = N->getOperand(1);
04176 
04177   // Canonicalize the multiply so the constant (if any) is on the right
04178   if (N->getOpcode() == ISD::MUL) {
04179     if (isa<ConstantSDNode>(LHS)) {
04180       std::swap(LHS, RHS);
04181     }
04182   }
04183 
04184   // If we have a SHL, determine the actual multiply amount
04185   if (N->getOpcode() == ISD::SHL) {
04186     ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
04187     if (!ShlRHS) {
04188       return SDValue();
04189     }
04190 
04191     APInt ShiftAmt = ShlRHS->getAPIntValue();
04192     unsigned BitWidth = MulType.getSizeInBits();
04193     if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
04194       APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
04195       RHS = DCI.DAG.getConstant(MulVal, DL, MulType);
04196     } else {
04197       return SDValue();
04198     }
04199   }
04200 
04201   bool Signed;
04202   // Verify that our operands are demotable
04203   if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
04204     return SDValue();
04205   }
04206 
04207   EVT DemotedVT;
04208   if (MulType == MVT::i32) {
04209     DemotedVT = MVT::i16;
04210   } else {
04211     DemotedVT = MVT::i32;
04212   }
04213 
04214   // Truncate the operands to the correct size. Note that these are just for
04215   // type consistency and will (likely) be eliminated in later phases.
04216   SDValue TruncLHS =
04217     DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS);
04218   SDValue TruncRHS =
04219     DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS);
04220 
04221   unsigned Opc;
04222   if (Signed) {
04223     Opc = NVPTXISD::MUL_WIDE_SIGNED;
04224   } else {
04225     Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
04226   }
04227 
04228   return DCI.DAG.getNode(Opc, DL, MulType, TruncLHS, TruncRHS);
04229 }
04230 
04231 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
04232 static SDValue PerformMULCombine(SDNode *N,
04233                                  TargetLowering::DAGCombinerInfo &DCI,
04234                                  CodeGenOpt::Level OptLevel) {
04235   if (OptLevel > 0) {
04236     // Try mul.wide combining at OptLevel > 0
04237     SDValue Ret = TryMULWIDECombine(N, DCI);
04238     if (Ret.getNode())
04239       return Ret;
04240   }
04241 
04242   return SDValue();
04243 }
04244 
04245 /// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
04246 static SDValue PerformSHLCombine(SDNode *N,
04247                                  TargetLowering::DAGCombinerInfo &DCI,
04248                                  CodeGenOpt::Level OptLevel) {
04249   if (OptLevel > 0) {
04250     // Try mul.wide combining at OptLevel > 0
04251     SDValue Ret = TryMULWIDECombine(N, DCI);
04252     if (Ret.getNode())
04253       return Ret;
04254   }
04255 
04256   return SDValue();
04257 }
04258 
04259 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
04260                                                DAGCombinerInfo &DCI) const {
04261   CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
04262   switch (N->getOpcode()) {
04263     default: break;
04264     case ISD::ADD:
04265     case ISD::FADD:
04266       return PerformADDCombine(N, DCI, STI, OptLevel);
04267     case ISD::MUL:
04268       return PerformMULCombine(N, DCI, OptLevel);
04269     case ISD::SHL:
04270       return PerformSHLCombine(N, DCI, OptLevel);
04271     case ISD::AND:
04272       return PerformANDCombine(N, DCI);
04273     case ISD::SELECT:
04274       return PerformSELECTCombine(N, DCI);
04275   }
04276   return SDValue();
04277 }
04278 
04279 /// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
04280 static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
04281                               SmallVectorImpl<SDValue> &Results) {
04282   EVT ResVT = N->getValueType(0);
04283   SDLoc DL(N);
04284 
04285   assert(ResVT.isVector() && "Vector load must have vector type");
04286 
04287   // We only handle "native" vector sizes for now, e.g. <4 x double> is not
04288   // legal.  We can (and should) split that into 2 loads of <2 x double> here
04289   // but I'm leaving that as a TODO for now.
04290   assert(ResVT.isSimple() && "Can only handle simple types");
04291   switch (ResVT.getSimpleVT().SimpleTy) {
04292   default:
04293     return;
04294   case MVT::v2i8:
04295   case MVT::v2i16:
04296   case MVT::v2i32:
04297   case MVT::v2i64:
04298   case MVT::v2f32:
04299   case MVT::v2f64:
04300   case MVT::v4i8:
04301   case MVT::v4i16:
04302   case MVT::v4i32:
04303   case MVT::v4f32:
04304     // This is a "native" vector type
04305     break;
04306   }
04307 
04308   LoadSDNode *LD = cast<LoadSDNode>(N);
04309 
04310   unsigned Align = LD->getAlignment();
04311   auto &TD = DAG.getDataLayout();
04312   unsigned PrefAlign =
04313       TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
04314   if (Align < PrefAlign) {
04315     // This load is not sufficiently aligned, so bail out and let this vector
04316     // load be scalarized.  Note that we may still be able to emit smaller
04317     // vector loads.  For example, if we are loading a <4 x float> with an
04318     // alignment of 8, this check will fail but the legalizer will try again
04319     // with 2 x <2 x float>, which will succeed with an alignment of 8.
04320     return;
04321   }
04322 
04323   EVT EltVT = ResVT.getVectorElementType();
04324   unsigned NumElts = ResVT.getVectorNumElements();
04325 
04326   // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
04327   // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
04328   // loaded type to i16 and propagate the "real" type as the memory type.
04329   bool NeedTrunc = false;
04330   if (EltVT.getSizeInBits() < 16) {
04331     EltVT = MVT::i16;
04332     NeedTrunc = true;
04333   }
04334 
04335   unsigned Opcode = 0;
04336   SDVTList LdResVTs;
04337 
04338   switch (NumElts) {
04339   default:
04340     return;
04341   case 2:
04342     Opcode = NVPTXISD::LoadV2;
04343     LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
04344     break;
04345   case 4: {
04346     Opcode = NVPTXISD::LoadV4;
04347     EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
04348     LdResVTs = DAG.getVTList(ListVTs);
04349     break;
04350   }
04351   }
04352 
04353   // Copy regular operands
04354   SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
04355 
04356   // The select routine does not have access to the LoadSDNode instance, so
04357   // pass along the extension information
04358   OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));
04359 
04360   SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
04361                                           LD->getMemoryVT(),
04362                                           LD->getMemOperand());
04363 
04364   SmallVector<SDValue, 4> ScalarRes;
04365 
04366   for (unsigned i = 0; i < NumElts; ++i) {
04367     SDValue Res = NewLD.getValue(i);
04368     if (NeedTrunc)
04369       Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
04370     ScalarRes.push_back(Res);
04371   }
04372 
04373   SDValue LoadChain = NewLD.getValue(NumElts);
04374 
04375   SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
04376 
04377   Results.push_back(BuildVec);
04378   Results.push_back(LoadChain);
04379 }
04380 
04381 static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
04382                                      SmallVectorImpl<SDValue> &Results) {
04383   SDValue Chain = N->getOperand(0);
04384   SDValue Intrin = N->getOperand(1);
04385   SDLoc DL(N);
04386 
04387   // Get the intrinsic ID
04388   unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
04389   switch (IntrinNo) {
04390   default:
04391     return;
04392   case Intrinsic::nvvm_ldg_global_i:
04393   case Intrinsic::nvvm_ldg_global_f:
04394   case Intrinsic::nvvm_ldg_global_p:
04395   case Intrinsic::nvvm_ldu_global_i:
04396   case Intrinsic::nvvm_ldu_global_f:
04397   case Intrinsic::nvvm_ldu_global_p: {
04398     EVT ResVT = N->getValueType(0);
04399 
04400     if (ResVT.isVector()) {
04401       // Vector LDG/LDU
04402 
04403       unsigned NumElts = ResVT.getVectorNumElements();
04404       EVT EltVT = ResVT.getVectorElementType();
04405 
04406       // Since LDU/LDG are target nodes, we cannot rely on DAG type
04407       // legalization.
04408       // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
04409       // loaded type to i16 and propagate the "real" type as the memory type.
04410       bool NeedTrunc = false;
04411       if (EltVT.getSizeInBits() < 16) {
04412         EltVT = MVT::i16;
04413         NeedTrunc = true;
04414       }
04415 
04416       unsigned Opcode = 0;
04417       SDVTList LdResVTs;
04418 
04419       switch (NumElts) {
04420       default:
04421         return;
04422       case 2:
04423         switch (IntrinNo) {
04424         default:
04425           return;
04426         case Intrinsic::nvvm_ldg_global_i:
04427         case Intrinsic::nvvm_ldg_global_f:
04428         case Intrinsic::nvvm_ldg_global_p:
04429           Opcode = NVPTXISD::LDGV2;
04430           break;
04431         case Intrinsic::nvvm_ldu_global_i:
04432         case Intrinsic::nvvm_ldu_global_f:
04433         case Intrinsic::nvvm_ldu_global_p:
04434           Opcode = NVPTXISD::LDUV2;
04435           break;
04436         }
04437         LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
04438         break;
04439       case 4: {
04440         switch (IntrinNo) {
04441         default:
04442           return;
04443         case Intrinsic::nvvm_ldg_global_i:
04444         case Intrinsic::nvvm_ldg_global_f:
04445         case Intrinsic::nvvm_ldg_global_p:
04446           Opcode = NVPTXISD::LDGV4;
04447           break;
04448         case Intrinsic::nvvm_ldu_global_i:
04449         case Intrinsic::nvvm_ldu_global_f:
04450         case Intrinsic::nvvm_ldu_global_p:
04451           Opcode = NVPTXISD::LDUV4;
04452           break;
04453         }
04454         EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
04455         LdResVTs = DAG.getVTList(ListVTs);
04456         break;
04457       }
04458       }
04459 
04460       SmallVector<SDValue, 8> OtherOps;
04461 
04462       // Copy regular operands
04463 
04464       OtherOps.push_back(Chain); // Chain
04465                                  // Skip operand 1 (intrinsic ID)
04466       // Others
04467       OtherOps.append(N->op_begin() + 2, N->op_end());
04468 
04469       MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
04470 
04471       SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
04472                                               MemSD->getMemoryVT(),
04473                                               MemSD->getMemOperand());
04474 
04475       SmallVector<SDValue, 4> ScalarRes;
04476 
04477       for (unsigned i = 0; i < NumElts; ++i) {
04478         SDValue Res = NewLD.getValue(i);
04479         if (NeedTrunc)
04480           Res =
04481               DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
04482         ScalarRes.push_back(Res);
04483       }
04484 
04485       SDValue LoadChain = NewLD.getValue(NumElts);
04486 
04487       SDValue BuildVec =
04488           DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
04489 
04490       Results.push_back(BuildVec);
04491       Results.push_back(LoadChain);
04492     } else {
04493       // i8 LDG/LDU
04494       assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
04495              "Custom handling of non-i8 ldu/ldg?");
04496 
04497       // Just copy all operands as-is
04498       SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
04499 
04500       // Force output to i16
04501       SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
04502 
04503       MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
04504 
04505       // We make sure the memory type is i8, which will be used during isel
04506       // to select the proper instruction.
04507       SDValue NewLD =
04508           DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
04509                                   MVT::i8, MemSD->getMemOperand());
04510 
04511       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
04512                                     NewLD.getValue(0)));
04513       Results.push_back(NewLD.getValue(1));
04514     }
04515   }
04516   }
04517 }
04518 
04519 void NVPTXTargetLowering::ReplaceNodeResults(
04520     SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
04521   switch (N->getOpcode()) {
04522   default:
04523     report_fatal_error("Unhandled custom legalization");
04524   case ISD::LOAD:
04525     ReplaceLoadVector(N, DAG, Results);
04526     return;
04527   case ISD::INTRINSIC_W_CHAIN:
04528     ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
04529     return;
04530   }
04531 }
04532 
04533 // Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
04534 void NVPTXSection::anchor() {}
04535 
04536 NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
04537   delete static_cast<NVPTXSection *>(TextSection);
04538   delete static_cast<NVPTXSection *>(DataSection);
04539   delete static_cast<NVPTXSection *>(BSSSection);
04540   delete static_cast<NVPTXSection *>(ReadOnlySection);
04541 
04542   delete static_cast<NVPTXSection *>(StaticCtorSection);
04543   delete static_cast<NVPTXSection *>(StaticDtorSection);
04544   delete static_cast<NVPTXSection *>(LSDASection);
04545   delete static_cast<NVPTXSection *>(EHFrameSection);
04546   delete static_cast<NVPTXSection *>(DwarfAbbrevSection);
04547   delete static_cast<NVPTXSection *>(DwarfInfoSection);
04548   delete static_cast<NVPTXSection *>(DwarfLineSection);
04549   delete static_cast<NVPTXSection *>(DwarfFrameSection);
04550   delete static_cast<NVPTXSection *>(DwarfPubTypesSection);
04551   delete static_cast<const NVPTXSection *>(DwarfDebugInlineSection);
04552   delete static_cast<NVPTXSection *>(DwarfStrSection);
04553   delete static_cast<NVPTXSection *>(DwarfLocSection);
04554   delete static_cast<NVPTXSection *>(DwarfARangesSection);
04555   delete static_cast<NVPTXSection *>(DwarfRangesSection);
04556   delete static_cast<NVPTXSection *>(DwarfMacinfoSection);
04557 }
04558 
04559 MCSection *
04560 NVPTXTargetObjectFile::SelectSectionForGlobal(const GlobalValue *GV,
04561                                               SectionKind Kind, Mangler &Mang,
04562                                               const TargetMachine &TM) const {
04563   return getDataSection();
04564 }