LLVM API Documentation

NVPTXISelLowering.cpp
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00001 //
00002 //                     The LLVM Compiler Infrastructure
00003 //
00004 // This file is distributed under the University of Illinois Open Source
00005 // License. See LICENSE.TXT for details.
00006 //
00007 //===----------------------------------------------------------------------===//
00008 //
00009 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
00010 // selection DAG.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "NVPTXISelLowering.h"
00015 #include "NVPTX.h"
00016 #include "NVPTXTargetMachine.h"
00017 #include "NVPTXTargetObjectFile.h"
00018 #include "NVPTXUtilities.h"
00019 #include "llvm/CodeGen/Analysis.h"
00020 #include "llvm/CodeGen/MachineFrameInfo.h"
00021 #include "llvm/CodeGen/MachineFunction.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineRegisterInfo.h"
00024 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
00025 #include "llvm/IR/CallSite.h"
00026 #include "llvm/IR/DerivedTypes.h"
00027 #include "llvm/IR/Function.h"
00028 #include "llvm/IR/GlobalValue.h"
00029 #include "llvm/IR/IntrinsicInst.h"
00030 #include "llvm/IR/Intrinsics.h"
00031 #include "llvm/IR/Module.h"
00032 #include "llvm/MC/MCSectionELF.h"
00033 #include "llvm/Support/CommandLine.h"
00034 #include "llvm/Support/Debug.h"
00035 #include "llvm/Support/ErrorHandling.h"
00036 #include "llvm/Support/MathExtras.h"
00037 #include "llvm/Support/raw_ostream.h"
00038 #include <sstream>
00039 
00040 #undef DEBUG_TYPE
00041 #define DEBUG_TYPE "nvptx-lower"
00042 
00043 using namespace llvm;
00044 
00045 static unsigned int uniqueCallSite = 0;
00046 
00047 static cl::opt<bool> sched4reg(
00048     "nvptx-sched4reg",
00049     cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
00050 
00051 static cl::opt<unsigned>
00052 FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
00053                     cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
00054                              " 1: do it  2: do it aggressively"),
00055                     cl::init(2));
00056 
00057 static bool IsPTXVectorType(MVT VT) {
00058   switch (VT.SimpleTy) {
00059   default:
00060     return false;
00061   case MVT::v2i1:
00062   case MVT::v4i1:
00063   case MVT::v2i8:
00064   case MVT::v4i8:
00065   case MVT::v2i16:
00066   case MVT::v4i16:
00067   case MVT::v2i32:
00068   case MVT::v4i32:
00069   case MVT::v2i64:
00070   case MVT::v2f32:
00071   case MVT::v4f32:
00072   case MVT::v2f64:
00073     return true;
00074   }
00075 }
00076 
00077 /// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
00078 /// EVTs that compose it.  Unlike ComputeValueVTs, this will break apart vectors
00079 /// into their primitive components.
00080 /// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
00081 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
00082 /// LowerCall, and LowerReturn.
00083 static void ComputePTXValueVTs(const TargetLowering &TLI, Type *Ty,
00084                                SmallVectorImpl<EVT> &ValueVTs,
00085                                SmallVectorImpl<uint64_t> *Offsets = nullptr,
00086                                uint64_t StartingOffset = 0) {
00087   SmallVector<EVT, 16> TempVTs;
00088   SmallVector<uint64_t, 16> TempOffsets;
00089 
00090   ComputeValueVTs(TLI, Ty, TempVTs, &TempOffsets, StartingOffset);
00091   for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
00092     EVT VT = TempVTs[i];
00093     uint64_t Off = TempOffsets[i];
00094     if (VT.isVector())
00095       for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
00096         ValueVTs.push_back(VT.getVectorElementType());
00097         if (Offsets)
00098           Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
00099       }
00100     else {
00101       ValueVTs.push_back(VT);
00102       if (Offsets)
00103         Offsets->push_back(Off);
00104     }
00105   }
00106 }
00107 
00108 // NVPTXTargetLowering Constructor.
00109 NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM)
00110     : TargetLowering(TM, new NVPTXTargetObjectFile()), nvTM(&TM),
00111       nvptxSubtarget(TM.getSubtarget<NVPTXSubtarget>()) {
00112 
00113   // always lower memset, memcpy, and memmove intrinsics to load/store
00114   // instructions, rather
00115   // then generating calls to memset, mempcy or memmove.
00116   MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
00117   MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
00118   MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
00119 
00120   setBooleanContents(ZeroOrNegativeOneBooleanContent);
00121   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
00122 
00123   // Jump is Expensive. Don't create extra control flow for 'and', 'or'
00124   // condition branches.
00125   setJumpIsExpensive(true);
00126 
00127   // By default, use the Source scheduling
00128   if (sched4reg)
00129     setSchedulingPreference(Sched::RegPressure);
00130   else
00131     setSchedulingPreference(Sched::Source);
00132 
00133   addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
00134   addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
00135   addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
00136   addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
00137   addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
00138   addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
00139 
00140   // Operations not directly supported by NVPTX.
00141   setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
00142   setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
00143   setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
00144   setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
00145   setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
00146   setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
00147   setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
00148   setOperationAction(ISD::BR_CC, MVT::f32, Expand);
00149   setOperationAction(ISD::BR_CC, MVT::f64, Expand);
00150   setOperationAction(ISD::BR_CC, MVT::i1, Expand);
00151   setOperationAction(ISD::BR_CC, MVT::i8, Expand);
00152   setOperationAction(ISD::BR_CC, MVT::i16, Expand);
00153   setOperationAction(ISD::BR_CC, MVT::i32, Expand);
00154   setOperationAction(ISD::BR_CC, MVT::i64, Expand);
00155   // Some SIGN_EXTEND_INREG can be done using cvt instruction.
00156   // For others we will expand to a SHL/SRA pair.
00157   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
00158   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
00159   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
00160   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
00161   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
00162 
00163   setOperationAction(ISD::SHL_PARTS, MVT::i32  , Custom);
00164   setOperationAction(ISD::SRA_PARTS, MVT::i32  , Custom);
00165   setOperationAction(ISD::SRL_PARTS, MVT::i32  , Custom);
00166   setOperationAction(ISD::SHL_PARTS, MVT::i64  , Custom);
00167   setOperationAction(ISD::SRA_PARTS, MVT::i64  , Custom);
00168   setOperationAction(ISD::SRL_PARTS, MVT::i64  , Custom);
00169 
00170   if (nvptxSubtarget.hasROT64()) {
00171     setOperationAction(ISD::ROTL, MVT::i64, Legal);
00172     setOperationAction(ISD::ROTR, MVT::i64, Legal);
00173   } else {
00174     setOperationAction(ISD::ROTL, MVT::i64, Expand);
00175     setOperationAction(ISD::ROTR, MVT::i64, Expand);
00176   }
00177   if (nvptxSubtarget.hasROT32()) {
00178     setOperationAction(ISD::ROTL, MVT::i32, Legal);
00179     setOperationAction(ISD::ROTR, MVT::i32, Legal);
00180   } else {
00181     setOperationAction(ISD::ROTL, MVT::i32, Expand);
00182     setOperationAction(ISD::ROTR, MVT::i32, Expand);
00183   }
00184 
00185   setOperationAction(ISD::ROTL, MVT::i16, Expand);
00186   setOperationAction(ISD::ROTR, MVT::i16, Expand);
00187   setOperationAction(ISD::ROTL, MVT::i8, Expand);
00188   setOperationAction(ISD::ROTR, MVT::i8, Expand);
00189   setOperationAction(ISD::BSWAP, MVT::i16, Expand);
00190   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
00191   setOperationAction(ISD::BSWAP, MVT::i64, Expand);
00192 
00193   // Indirect branch is not supported.
00194   // This also disables Jump Table creation.
00195   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
00196   setOperationAction(ISD::BRIND, MVT::Other, Expand);
00197 
00198   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
00199   setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
00200 
00201   // We want to legalize constant related memmove and memcopy
00202   // intrinsics.
00203   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
00204 
00205   // Turn FP extload into load/fextend
00206   setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
00207   setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
00208   // Turn FP truncstore into trunc + store.
00209   setTruncStoreAction(MVT::f32, MVT::f16, Expand);
00210   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
00211   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
00212 
00213   // PTX does not support load / store predicate registers
00214   setOperationAction(ISD::LOAD, MVT::i1, Custom);
00215   setOperationAction(ISD::STORE, MVT::i1, Custom);
00216 
00217   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
00218   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
00219   setTruncStoreAction(MVT::i64, MVT::i1, Expand);
00220   setTruncStoreAction(MVT::i32, MVT::i1, Expand);
00221   setTruncStoreAction(MVT::i16, MVT::i1, Expand);
00222   setTruncStoreAction(MVT::i8, MVT::i1, Expand);
00223 
00224   // This is legal in NVPTX
00225   setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
00226   setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
00227 
00228   // TRAP can be lowered to PTX trap
00229   setOperationAction(ISD::TRAP, MVT::Other, Legal);
00230 
00231   setOperationAction(ISD::ADDC, MVT::i64, Expand);
00232   setOperationAction(ISD::ADDE, MVT::i64, Expand);
00233 
00234   // Register custom handling for vector loads/stores
00235   for (int i = MVT::FIRST_VECTOR_VALUETYPE; i <= MVT::LAST_VECTOR_VALUETYPE;
00236        ++i) {
00237     MVT VT = (MVT::SimpleValueType) i;
00238     if (IsPTXVectorType(VT)) {
00239       setOperationAction(ISD::LOAD, VT, Custom);
00240       setOperationAction(ISD::STORE, VT, Custom);
00241       setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
00242     }
00243   }
00244 
00245   // Custom handling for i8 intrinsics
00246   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
00247 
00248   setOperationAction(ISD::CTLZ, MVT::i16, Legal);
00249   setOperationAction(ISD::CTLZ, MVT::i32, Legal);
00250   setOperationAction(ISD::CTLZ, MVT::i64, Legal);
00251   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
00252   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
00253   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
00254   setOperationAction(ISD::CTTZ, MVT::i16, Expand);
00255   setOperationAction(ISD::CTTZ, MVT::i32, Expand);
00256   setOperationAction(ISD::CTTZ, MVT::i64, Expand);
00257   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
00258   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
00259   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
00260   setOperationAction(ISD::CTPOP, MVT::i16, Legal);
00261   setOperationAction(ISD::CTPOP, MVT::i32, Legal);
00262   setOperationAction(ISD::CTPOP, MVT::i64, Legal);
00263 
00264   // We have some custom DAG combine patterns for these nodes
00265   setTargetDAGCombine(ISD::ADD);
00266   setTargetDAGCombine(ISD::AND);
00267   setTargetDAGCombine(ISD::FADD);
00268   setTargetDAGCombine(ISD::MUL);
00269   setTargetDAGCombine(ISD::SHL);
00270 
00271   // Now deduce the information based on the above mentioned
00272   // actions
00273   computeRegisterProperties();
00274 }
00275 
00276 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
00277   switch (Opcode) {
00278   default:
00279     return nullptr;
00280   case NVPTXISD::CALL:
00281     return "NVPTXISD::CALL";
00282   case NVPTXISD::RET_FLAG:
00283     return "NVPTXISD::RET_FLAG";
00284   case NVPTXISD::Wrapper:
00285     return "NVPTXISD::Wrapper";
00286   case NVPTXISD::DeclareParam:
00287     return "NVPTXISD::DeclareParam";
00288   case NVPTXISD::DeclareScalarParam:
00289     return "NVPTXISD::DeclareScalarParam";
00290   case NVPTXISD::DeclareRet:
00291     return "NVPTXISD::DeclareRet";
00292   case NVPTXISD::DeclareRetParam:
00293     return "NVPTXISD::DeclareRetParam";
00294   case NVPTXISD::PrintCall:
00295     return "NVPTXISD::PrintCall";
00296   case NVPTXISD::LoadParam:
00297     return "NVPTXISD::LoadParam";
00298   case NVPTXISD::LoadParamV2:
00299     return "NVPTXISD::LoadParamV2";
00300   case NVPTXISD::LoadParamV4:
00301     return "NVPTXISD::LoadParamV4";
00302   case NVPTXISD::StoreParam:
00303     return "NVPTXISD::StoreParam";
00304   case NVPTXISD::StoreParamV2:
00305     return "NVPTXISD::StoreParamV2";
00306   case NVPTXISD::StoreParamV4:
00307     return "NVPTXISD::StoreParamV4";
00308   case NVPTXISD::StoreParamS32:
00309     return "NVPTXISD::StoreParamS32";
00310   case NVPTXISD::StoreParamU32:
00311     return "NVPTXISD::StoreParamU32";
00312   case NVPTXISD::CallArgBegin:
00313     return "NVPTXISD::CallArgBegin";
00314   case NVPTXISD::CallArg:
00315     return "NVPTXISD::CallArg";
00316   case NVPTXISD::LastCallArg:
00317     return "NVPTXISD::LastCallArg";
00318   case NVPTXISD::CallArgEnd:
00319     return "NVPTXISD::CallArgEnd";
00320   case NVPTXISD::CallVoid:
00321     return "NVPTXISD::CallVoid";
00322   case NVPTXISD::CallVal:
00323     return "NVPTXISD::CallVal";
00324   case NVPTXISD::CallSymbol:
00325     return "NVPTXISD::CallSymbol";
00326   case NVPTXISD::Prototype:
00327     return "NVPTXISD::Prototype";
00328   case NVPTXISD::MoveParam:
00329     return "NVPTXISD::MoveParam";
00330   case NVPTXISD::StoreRetval:
00331     return "NVPTXISD::StoreRetval";
00332   case NVPTXISD::StoreRetvalV2:
00333     return "NVPTXISD::StoreRetvalV2";
00334   case NVPTXISD::StoreRetvalV4:
00335     return "NVPTXISD::StoreRetvalV4";
00336   case NVPTXISD::PseudoUseParam:
00337     return "NVPTXISD::PseudoUseParam";
00338   case NVPTXISD::RETURN:
00339     return "NVPTXISD::RETURN";
00340   case NVPTXISD::CallSeqBegin:
00341     return "NVPTXISD::CallSeqBegin";
00342   case NVPTXISD::CallSeqEnd:
00343     return "NVPTXISD::CallSeqEnd";
00344   case NVPTXISD::CallPrototype:
00345     return "NVPTXISD::CallPrototype";
00346   case NVPTXISD::LoadV2:
00347     return "NVPTXISD::LoadV2";
00348   case NVPTXISD::LoadV4:
00349     return "NVPTXISD::LoadV4";
00350   case NVPTXISD::LDGV2:
00351     return "NVPTXISD::LDGV2";
00352   case NVPTXISD::LDGV4:
00353     return "NVPTXISD::LDGV4";
00354   case NVPTXISD::LDUV2:
00355     return "NVPTXISD::LDUV2";
00356   case NVPTXISD::LDUV4:
00357     return "NVPTXISD::LDUV4";
00358   case NVPTXISD::StoreV2:
00359     return "NVPTXISD::StoreV2";
00360   case NVPTXISD::StoreV4:
00361     return "NVPTXISD::StoreV4";
00362   case NVPTXISD::FUN_SHFL_CLAMP:
00363     return "NVPTXISD::FUN_SHFL_CLAMP";
00364   case NVPTXISD::FUN_SHFR_CLAMP:
00365     return "NVPTXISD::FUN_SHFR_CLAMP";
00366   case NVPTXISD::IMAD:
00367     return "NVPTXISD::IMAD";
00368   case NVPTXISD::MUL_WIDE_SIGNED:
00369     return "NVPTXISD::MUL_WIDE_SIGNED";
00370   case NVPTXISD::MUL_WIDE_UNSIGNED:
00371     return "NVPTXISD::MUL_WIDE_UNSIGNED";
00372   case NVPTXISD::Tex1DFloatS32:        return "NVPTXISD::Tex1DFloatS32";
00373   case NVPTXISD::Tex1DFloatFloat:      return "NVPTXISD::Tex1DFloatFloat";
00374   case NVPTXISD::Tex1DFloatFloatLevel:
00375     return "NVPTXISD::Tex1DFloatFloatLevel";
00376   case NVPTXISD::Tex1DFloatFloatGrad:
00377     return "NVPTXISD::Tex1DFloatFloatGrad";
00378   case NVPTXISD::Tex1DS32S32:          return "NVPTXISD::Tex1DS32S32";
00379   case NVPTXISD::Tex1DS32Float:        return "NVPTXISD::Tex1DS32Float";
00380   case NVPTXISD::Tex1DS32FloatLevel:
00381     return "NVPTXISD::Tex1DS32FloatLevel";
00382   case NVPTXISD::Tex1DS32FloatGrad:
00383     return "NVPTXISD::Tex1DS32FloatGrad";
00384   case NVPTXISD::Tex1DU32S32:          return "NVPTXISD::Tex1DU32S32";
00385   case NVPTXISD::Tex1DU32Float:        return "NVPTXISD::Tex1DU32Float";
00386   case NVPTXISD::Tex1DU32FloatLevel:
00387     return "NVPTXISD::Tex1DU32FloatLevel";
00388   case NVPTXISD::Tex1DU32FloatGrad:
00389     return "NVPTXISD::Tex1DU32FloatGrad";
00390   case NVPTXISD::Tex1DArrayFloatS32:   return "NVPTXISD::Tex1DArrayFloatS32";
00391   case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
00392   case NVPTXISD::Tex1DArrayFloatFloatLevel:
00393     return "NVPTXISD::Tex1DArrayFloatFloatLevel";
00394   case NVPTXISD::Tex1DArrayFloatFloatGrad:
00395     return "NVPTXISD::Tex1DArrayFloatFloatGrad";
00396   case NVPTXISD::Tex1DArrayS32S32:     return "NVPTXISD::Tex1DArrayS32S32";
00397   case NVPTXISD::Tex1DArrayS32Float:   return "NVPTXISD::Tex1DArrayS32Float";
00398   case NVPTXISD::Tex1DArrayS32FloatLevel:
00399     return "NVPTXISD::Tex1DArrayS32FloatLevel";
00400   case NVPTXISD::Tex1DArrayS32FloatGrad:
00401     return "NVPTXISD::Tex1DArrayS32FloatGrad";
00402   case NVPTXISD::Tex1DArrayU32S32:     return "NVPTXISD::Tex1DArrayU32S32";
00403   case NVPTXISD::Tex1DArrayU32Float:   return "NVPTXISD::Tex1DArrayU32Float";
00404   case NVPTXISD::Tex1DArrayU32FloatLevel:
00405     return "NVPTXISD::Tex1DArrayU32FloatLevel";
00406   case NVPTXISD::Tex1DArrayU32FloatGrad:
00407     return "NVPTXISD::Tex1DArrayU32FloatGrad";
00408   case NVPTXISD::Tex2DFloatS32:        return "NVPTXISD::Tex2DFloatS32";
00409   case NVPTXISD::Tex2DFloatFloat:      return "NVPTXISD::Tex2DFloatFloat";
00410   case NVPTXISD::Tex2DFloatFloatLevel:
00411     return "NVPTXISD::Tex2DFloatFloatLevel";
00412   case NVPTXISD::Tex2DFloatFloatGrad:
00413     return "NVPTXISD::Tex2DFloatFloatGrad";
00414   case NVPTXISD::Tex2DS32S32:          return "NVPTXISD::Tex2DS32S32";
00415   case NVPTXISD::Tex2DS32Float:        return "NVPTXISD::Tex2DS32Float";
00416   case NVPTXISD::Tex2DS32FloatLevel:
00417     return "NVPTXISD::Tex2DS32FloatLevel";
00418   case NVPTXISD::Tex2DS32FloatGrad:
00419     return "NVPTXISD::Tex2DS32FloatGrad";
00420   case NVPTXISD::Tex2DU32S32:          return "NVPTXISD::Tex2DU32S32";
00421   case NVPTXISD::Tex2DU32Float:        return "NVPTXISD::Tex2DU32Float";
00422   case NVPTXISD::Tex2DU32FloatLevel:
00423     return "NVPTXISD::Tex2DU32FloatLevel";
00424   case NVPTXISD::Tex2DU32FloatGrad:
00425     return "NVPTXISD::Tex2DU32FloatGrad";
00426   case NVPTXISD::Tex2DArrayFloatS32:   return "NVPTXISD::Tex2DArrayFloatS32";
00427   case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
00428   case NVPTXISD::Tex2DArrayFloatFloatLevel:
00429     return "NVPTXISD::Tex2DArrayFloatFloatLevel";
00430   case NVPTXISD::Tex2DArrayFloatFloatGrad:
00431     return "NVPTXISD::Tex2DArrayFloatFloatGrad";
00432   case NVPTXISD::Tex2DArrayS32S32:     return "NVPTXISD::Tex2DArrayS32S32";
00433   case NVPTXISD::Tex2DArrayS32Float:   return "NVPTXISD::Tex2DArrayS32Float";
00434   case NVPTXISD::Tex2DArrayS32FloatLevel:
00435     return "NVPTXISD::Tex2DArrayS32FloatLevel";
00436   case NVPTXISD::Tex2DArrayS32FloatGrad:
00437     return "NVPTXISD::Tex2DArrayS32FloatGrad";
00438   case NVPTXISD::Tex2DArrayU32S32:     return "NVPTXISD::Tex2DArrayU32S32";
00439   case NVPTXISD::Tex2DArrayU32Float:   return "NVPTXISD::Tex2DArrayU32Float";
00440   case NVPTXISD::Tex2DArrayU32FloatLevel:
00441     return "NVPTXISD::Tex2DArrayU32FloatLevel";
00442   case NVPTXISD::Tex2DArrayU32FloatGrad:
00443     return "NVPTXISD::Tex2DArrayU32FloatGrad";
00444   case NVPTXISD::Tex3DFloatS32:        return "NVPTXISD::Tex3DFloatS32";
00445   case NVPTXISD::Tex3DFloatFloat:      return "NVPTXISD::Tex3DFloatFloat";
00446   case NVPTXISD::Tex3DFloatFloatLevel:
00447     return "NVPTXISD::Tex3DFloatFloatLevel";
00448   case NVPTXISD::Tex3DFloatFloatGrad:
00449     return "NVPTXISD::Tex3DFloatFloatGrad";
00450   case NVPTXISD::Tex3DS32S32:          return "NVPTXISD::Tex3DS32S32";
00451   case NVPTXISD::Tex3DS32Float:        return "NVPTXISD::Tex3DS32Float";
00452   case NVPTXISD::Tex3DS32FloatLevel:
00453     return "NVPTXISD::Tex3DS32FloatLevel";
00454   case NVPTXISD::Tex3DS32FloatGrad:
00455     return "NVPTXISD::Tex3DS32FloatGrad";
00456   case NVPTXISD::Tex3DU32S32:          return "NVPTXISD::Tex3DU32S32";
00457   case NVPTXISD::Tex3DU32Float:        return "NVPTXISD::Tex3DU32Float";
00458   case NVPTXISD::Tex3DU32FloatLevel:
00459     return "NVPTXISD::Tex3DU32FloatLevel";
00460   case NVPTXISD::Tex3DU32FloatGrad:
00461     return "NVPTXISD::Tex3DU32FloatGrad";
00462   case NVPTXISD::TexCubeFloatFloat:      return "NVPTXISD::TexCubeFloatFloat";
00463   case NVPTXISD::TexCubeFloatFloatLevel:
00464     return "NVPTXISD::TexCubeFloatFloatLevel";
00465   case NVPTXISD::TexCubeS32Float:        return "NVPTXISD::TexCubeS32Float";
00466   case NVPTXISD::TexCubeS32FloatLevel:
00467     return "NVPTXISD::TexCubeS32FloatLevel";
00468   case NVPTXISD::TexCubeU32Float:        return "NVPTXISD::TexCubeU32Float";
00469   case NVPTXISD::TexCubeU32FloatLevel:
00470     return "NVPTXISD::TexCubeU32FloatLevel";
00471   case NVPTXISD::TexCubeArrayFloatFloat:
00472     return "NVPTXISD::TexCubeArrayFloatFloat";
00473   case NVPTXISD::TexCubeArrayFloatFloatLevel:
00474     return "NVPTXISD::TexCubeArrayFloatFloatLevel";
00475   case NVPTXISD::TexCubeArrayS32Float:
00476     return "NVPTXISD::TexCubeArrayS32Float";
00477   case NVPTXISD::TexCubeArrayS32FloatLevel:
00478     return "NVPTXISD::TexCubeArrayS32FloatLevel";
00479   case NVPTXISD::TexCubeArrayU32Float:
00480     return "NVPTXISD::TexCubeArrayU32Float";
00481   case NVPTXISD::TexCubeArrayU32FloatLevel:
00482     return "NVPTXISD::TexCubeArrayU32FloatLevel";
00483   case NVPTXISD::Tld4R2DFloatFloat:
00484     return "NVPTXISD::Tld4R2DFloatFloat";
00485   case NVPTXISD::Tld4G2DFloatFloat:
00486     return "NVPTXISD::Tld4G2DFloatFloat";
00487   case NVPTXISD::Tld4B2DFloatFloat:
00488     return "NVPTXISD::Tld4B2DFloatFloat";
00489   case NVPTXISD::Tld4A2DFloatFloat:
00490     return "NVPTXISD::Tld4A2DFloatFloat";
00491   case NVPTXISD::Tld4R2DS64Float:
00492     return "NVPTXISD::Tld4R2DS64Float";
00493   case NVPTXISD::Tld4G2DS64Float:
00494     return "NVPTXISD::Tld4G2DS64Float";
00495   case NVPTXISD::Tld4B2DS64Float:
00496     return "NVPTXISD::Tld4B2DS64Float";
00497   case NVPTXISD::Tld4A2DS64Float:
00498     return "NVPTXISD::Tld4A2DS64Float";
00499   case NVPTXISD::Tld4R2DU64Float:
00500     return "NVPTXISD::Tld4R2DU64Float";
00501   case NVPTXISD::Tld4G2DU64Float:
00502     return "NVPTXISD::Tld4G2DU64Float";
00503   case NVPTXISD::Tld4B2DU64Float:
00504     return "NVPTXISD::Tld4B2DU64Float";
00505   case NVPTXISD::Tld4A2DU64Float:
00506     return "NVPTXISD::Tld4A2DU64Float";
00507 
00508   case NVPTXISD::TexUnified1DFloatS32:
00509     return "NVPTXISD::TexUnified1DFloatS32";
00510   case NVPTXISD::TexUnified1DFloatFloat:
00511     return "NVPTXISD::TexUnified1DFloatFloat";
00512   case NVPTXISD::TexUnified1DFloatFloatLevel:
00513     return "NVPTXISD::TexUnified1DFloatFloatLevel";
00514   case NVPTXISD::TexUnified1DFloatFloatGrad:
00515     return "NVPTXISD::TexUnified1DFloatFloatGrad";
00516   case NVPTXISD::TexUnified1DS32S32:
00517     return "NVPTXISD::TexUnified1DS32S32";
00518   case NVPTXISD::TexUnified1DS32Float:
00519     return "NVPTXISD::TexUnified1DS32Float";
00520   case NVPTXISD::TexUnified1DS32FloatLevel:
00521     return "NVPTXISD::TexUnified1DS32FloatLevel";
00522   case NVPTXISD::TexUnified1DS32FloatGrad:
00523     return "NVPTXISD::TexUnified1DS32FloatGrad";
00524   case NVPTXISD::TexUnified1DU32S32:
00525     return "NVPTXISD::TexUnified1DU32S32";
00526   case NVPTXISD::TexUnified1DU32Float:
00527     return "NVPTXISD::TexUnified1DU32Float";
00528   case NVPTXISD::TexUnified1DU32FloatLevel:
00529     return "NVPTXISD::TexUnified1DU32FloatLevel";
00530   case NVPTXISD::TexUnified1DU32FloatGrad:
00531     return "NVPTXISD::TexUnified1DU32FloatGrad";
00532   case NVPTXISD::TexUnified1DArrayFloatS32:
00533     return "NVPTXISD::TexUnified1DArrayFloatS32";
00534   case NVPTXISD::TexUnified1DArrayFloatFloat:
00535     return "NVPTXISD::TexUnified1DArrayFloatFloat";
00536   case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
00537     return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
00538   case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
00539     return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
00540   case NVPTXISD::TexUnified1DArrayS32S32:
00541     return "NVPTXISD::TexUnified1DArrayS32S32";
00542   case NVPTXISD::TexUnified1DArrayS32Float:
00543     return "NVPTXISD::TexUnified1DArrayS32Float";
00544   case NVPTXISD::TexUnified1DArrayS32FloatLevel:
00545     return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
00546   case NVPTXISD::TexUnified1DArrayS32FloatGrad:
00547     return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
00548   case NVPTXISD::TexUnified1DArrayU32S32:
00549     return "NVPTXISD::TexUnified1DArrayU32S32";
00550   case NVPTXISD::TexUnified1DArrayU32Float:
00551     return "NVPTXISD::TexUnified1DArrayU32Float";
00552   case NVPTXISD::TexUnified1DArrayU32FloatLevel:
00553     return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
00554   case NVPTXISD::TexUnified1DArrayU32FloatGrad:
00555     return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
00556   case NVPTXISD::TexUnified2DFloatS32:
00557     return "NVPTXISD::TexUnified2DFloatS32";
00558   case NVPTXISD::TexUnified2DFloatFloat:
00559     return "NVPTXISD::TexUnified2DFloatFloat";
00560   case NVPTXISD::TexUnified2DFloatFloatLevel:
00561     return "NVPTXISD::TexUnified2DFloatFloatLevel";
00562   case NVPTXISD::TexUnified2DFloatFloatGrad:
00563     return "NVPTXISD::TexUnified2DFloatFloatGrad";
00564   case NVPTXISD::TexUnified2DS32S32:
00565     return "NVPTXISD::TexUnified2DS32S32";
00566   case NVPTXISD::TexUnified2DS32Float:
00567     return "NVPTXISD::TexUnified2DS32Float";
00568   case NVPTXISD::TexUnified2DS32FloatLevel:
00569     return "NVPTXISD::TexUnified2DS32FloatLevel";
00570   case NVPTXISD::TexUnified2DS32FloatGrad:
00571     return "NVPTXISD::TexUnified2DS32FloatGrad";
00572   case NVPTXISD::TexUnified2DU32S32:
00573     return "NVPTXISD::TexUnified2DU32S32";
00574   case NVPTXISD::TexUnified2DU32Float:
00575     return "NVPTXISD::TexUnified2DU32Float";
00576   case NVPTXISD::TexUnified2DU32FloatLevel:
00577     return "NVPTXISD::TexUnified2DU32FloatLevel";
00578   case NVPTXISD::TexUnified2DU32FloatGrad:
00579     return "NVPTXISD::TexUnified2DU32FloatGrad";
00580   case NVPTXISD::TexUnified2DArrayFloatS32:
00581     return "NVPTXISD::TexUnified2DArrayFloatS32";
00582   case NVPTXISD::TexUnified2DArrayFloatFloat:
00583     return "NVPTXISD::TexUnified2DArrayFloatFloat";
00584   case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
00585     return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
00586   case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
00587     return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
00588   case NVPTXISD::TexUnified2DArrayS32S32:
00589     return "NVPTXISD::TexUnified2DArrayS32S32";
00590   case NVPTXISD::TexUnified2DArrayS32Float:
00591     return "NVPTXISD::TexUnified2DArrayS32Float";
00592   case NVPTXISD::TexUnified2DArrayS32FloatLevel:
00593     return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
00594   case NVPTXISD::TexUnified2DArrayS32FloatGrad:
00595     return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
00596   case NVPTXISD::TexUnified2DArrayU32S32:
00597     return "NVPTXISD::TexUnified2DArrayU32S32";
00598   case NVPTXISD::TexUnified2DArrayU32Float:
00599     return "NVPTXISD::TexUnified2DArrayU32Float";
00600   case NVPTXISD::TexUnified2DArrayU32FloatLevel:
00601     return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
00602   case NVPTXISD::TexUnified2DArrayU32FloatGrad:
00603     return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
00604   case NVPTXISD::TexUnified3DFloatS32:
00605     return "NVPTXISD::TexUnified3DFloatS32";
00606   case NVPTXISD::TexUnified3DFloatFloat:
00607     return "NVPTXISD::TexUnified3DFloatFloat";
00608   case NVPTXISD::TexUnified3DFloatFloatLevel:
00609     return "NVPTXISD::TexUnified3DFloatFloatLevel";
00610   case NVPTXISD::TexUnified3DFloatFloatGrad:
00611     return "NVPTXISD::TexUnified3DFloatFloatGrad";
00612   case NVPTXISD::TexUnified3DS32S32:
00613     return "NVPTXISD::TexUnified3DS32S32";
00614   case NVPTXISD::TexUnified3DS32Float:
00615     return "NVPTXISD::TexUnified3DS32Float";
00616   case NVPTXISD::TexUnified3DS32FloatLevel:
00617     return "NVPTXISD::TexUnified3DS32FloatLevel";
00618   case NVPTXISD::TexUnified3DS32FloatGrad:
00619     return "NVPTXISD::TexUnified3DS32FloatGrad";
00620   case NVPTXISD::TexUnified3DU32S32:
00621     return "NVPTXISD::TexUnified3DU32S32";
00622   case NVPTXISD::TexUnified3DU32Float:
00623     return "NVPTXISD::TexUnified3DU32Float";
00624   case NVPTXISD::TexUnified3DU32FloatLevel:
00625     return "NVPTXISD::TexUnified3DU32FloatLevel";
00626   case NVPTXISD::TexUnified3DU32FloatGrad:
00627     return "NVPTXISD::TexUnified3DU32FloatGrad";
00628   case NVPTXISD::TexUnifiedCubeFloatFloat:
00629     return "NVPTXISD::TexUnifiedCubeFloatFloat";
00630   case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
00631     return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
00632   case NVPTXISD::TexUnifiedCubeS32Float:
00633     return "NVPTXISD::TexUnifiedCubeS32Float";
00634   case NVPTXISD::TexUnifiedCubeS32FloatLevel:
00635     return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
00636   case NVPTXISD::TexUnifiedCubeU32Float:
00637     return "NVPTXISD::TexUnifiedCubeU32Float";
00638   case NVPTXISD::TexUnifiedCubeU32FloatLevel:
00639     return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
00640   case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
00641     return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
00642   case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
00643     return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
00644   case NVPTXISD::TexUnifiedCubeArrayS32Float:
00645     return "NVPTXISD::TexUnifiedCubeArrayS32Float";
00646   case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
00647     return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
00648   case NVPTXISD::TexUnifiedCubeArrayU32Float:
00649     return "NVPTXISD::TexUnifiedCubeArrayU32Float";
00650   case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
00651     return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
00652   case NVPTXISD::Tld4UnifiedR2DFloatFloat:
00653     return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
00654   case NVPTXISD::Tld4UnifiedG2DFloatFloat:
00655     return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
00656   case NVPTXISD::Tld4UnifiedB2DFloatFloat:
00657     return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
00658   case NVPTXISD::Tld4UnifiedA2DFloatFloat:
00659     return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
00660   case NVPTXISD::Tld4UnifiedR2DS64Float:
00661     return "NVPTXISD::Tld4UnifiedR2DS64Float";
00662   case NVPTXISD::Tld4UnifiedG2DS64Float:
00663     return "NVPTXISD::Tld4UnifiedG2DS64Float";
00664   case NVPTXISD::Tld4UnifiedB2DS64Float:
00665     return "NVPTXISD::Tld4UnifiedB2DS64Float";
00666   case NVPTXISD::Tld4UnifiedA2DS64Float:
00667     return "NVPTXISD::Tld4UnifiedA2DS64Float";
00668   case NVPTXISD::Tld4UnifiedR2DU64Float:
00669     return "NVPTXISD::Tld4UnifiedR2DU64Float";
00670   case NVPTXISD::Tld4UnifiedG2DU64Float:
00671     return "NVPTXISD::Tld4UnifiedG2DU64Float";
00672   case NVPTXISD::Tld4UnifiedB2DU64Float:
00673     return "NVPTXISD::Tld4UnifiedB2DU64Float";
00674   case NVPTXISD::Tld4UnifiedA2DU64Float:
00675     return "NVPTXISD::Tld4UnifiedA2DU64Float";
00676 
00677   case NVPTXISD::Suld1DI8Clamp:          return "NVPTXISD::Suld1DI8Clamp";
00678   case NVPTXISD::Suld1DI16Clamp:         return "NVPTXISD::Suld1DI16Clamp";
00679   case NVPTXISD::Suld1DI32Clamp:         return "NVPTXISD::Suld1DI32Clamp";
00680   case NVPTXISD::Suld1DI64Clamp:         return "NVPTXISD::Suld1DI64Clamp";
00681   case NVPTXISD::Suld1DV2I8Clamp:        return "NVPTXISD::Suld1DV2I8Clamp";
00682   case NVPTXISD::Suld1DV2I16Clamp:       return "NVPTXISD::Suld1DV2I16Clamp";
00683   case NVPTXISD::Suld1DV2I32Clamp:       return "NVPTXISD::Suld1DV2I32Clamp";
00684   case NVPTXISD::Suld1DV2I64Clamp:       return "NVPTXISD::Suld1DV2I64Clamp";
00685   case NVPTXISD::Suld1DV4I8Clamp:        return "NVPTXISD::Suld1DV4I8Clamp";
00686   case NVPTXISD::Suld1DV4I16Clamp:       return "NVPTXISD::Suld1DV4I16Clamp";
00687   case NVPTXISD::Suld1DV4I32Clamp:       return "NVPTXISD::Suld1DV4I32Clamp";
00688 
00689   case NVPTXISD::Suld1DArrayI8Clamp:   return "NVPTXISD::Suld1DArrayI8Clamp";
00690   case NVPTXISD::Suld1DArrayI16Clamp:  return "NVPTXISD::Suld1DArrayI16Clamp";
00691   case NVPTXISD::Suld1DArrayI32Clamp:  return "NVPTXISD::Suld1DArrayI32Clamp";
00692   case NVPTXISD::Suld1DArrayI64Clamp:  return "NVPTXISD::Suld1DArrayI64Clamp";
00693   case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
00694   case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
00695   case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
00696   case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
00697   case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
00698   case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
00699   case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
00700 
00701   case NVPTXISD::Suld2DI8Clamp:          return "NVPTXISD::Suld2DI8Clamp";
00702   case NVPTXISD::Suld2DI16Clamp:         return "NVPTXISD::Suld2DI16Clamp";
00703   case NVPTXISD::Suld2DI32Clamp:         return "NVPTXISD::Suld2DI32Clamp";
00704   case NVPTXISD::Suld2DI64Clamp:         return "NVPTXISD::Suld2DI64Clamp";
00705   case NVPTXISD::Suld2DV2I8Clamp:        return "NVPTXISD::Suld2DV2I8Clamp";
00706   case NVPTXISD::Suld2DV2I16Clamp:       return "NVPTXISD::Suld2DV2I16Clamp";
00707   case NVPTXISD::Suld2DV2I32Clamp:       return "NVPTXISD::Suld2DV2I32Clamp";
00708   case NVPTXISD::Suld2DV2I64Clamp:       return "NVPTXISD::Suld2DV2I64Clamp";
00709   case NVPTXISD::Suld2DV4I8Clamp:        return "NVPTXISD::Suld2DV4I8Clamp";
00710   case NVPTXISD::Suld2DV4I16Clamp:       return "NVPTXISD::Suld2DV4I16Clamp";
00711   case NVPTXISD::Suld2DV4I32Clamp:       return "NVPTXISD::Suld2DV4I32Clamp";
00712 
00713   case NVPTXISD::Suld2DArrayI8Clamp:   return "NVPTXISD::Suld2DArrayI8Clamp";
00714   case NVPTXISD::Suld2DArrayI16Clamp:  return "NVPTXISD::Suld2DArrayI16Clamp";
00715   case NVPTXISD::Suld2DArrayI32Clamp:  return "NVPTXISD::Suld2DArrayI32Clamp";
00716   case NVPTXISD::Suld2DArrayI64Clamp:  return "NVPTXISD::Suld2DArrayI64Clamp";
00717   case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
00718   case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
00719   case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
00720   case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
00721   case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
00722   case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
00723   case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
00724 
00725   case NVPTXISD::Suld3DI8Clamp:          return "NVPTXISD::Suld3DI8Clamp";
00726   case NVPTXISD::Suld3DI16Clamp:         return "NVPTXISD::Suld3DI16Clamp";
00727   case NVPTXISD::Suld3DI32Clamp:         return "NVPTXISD::Suld3DI32Clamp";
00728   case NVPTXISD::Suld3DI64Clamp:         return "NVPTXISD::Suld3DI64Clamp";
00729   case NVPTXISD::Suld3DV2I8Clamp:        return "NVPTXISD::Suld3DV2I8Clamp";
00730   case NVPTXISD::Suld3DV2I16Clamp:       return "NVPTXISD::Suld3DV2I16Clamp";
00731   case NVPTXISD::Suld3DV2I32Clamp:       return "NVPTXISD::Suld3DV2I32Clamp";
00732   case NVPTXISD::Suld3DV2I64Clamp:       return "NVPTXISD::Suld3DV2I64Clamp";
00733   case NVPTXISD::Suld3DV4I8Clamp:        return "NVPTXISD::Suld3DV4I8Clamp";
00734   case NVPTXISD::Suld3DV4I16Clamp:       return "NVPTXISD::Suld3DV4I16Clamp";
00735   case NVPTXISD::Suld3DV4I32Clamp:       return "NVPTXISD::Suld3DV4I32Clamp";
00736 
00737   case NVPTXISD::Suld1DI8Trap:          return "NVPTXISD::Suld1DI8Trap";
00738   case NVPTXISD::Suld1DI16Trap:         return "NVPTXISD::Suld1DI16Trap";
00739   case NVPTXISD::Suld1DI32Trap:         return "NVPTXISD::Suld1DI32Trap";
00740   case NVPTXISD::Suld1DI64Trap:         return "NVPTXISD::Suld1DI64Trap";
00741   case NVPTXISD::Suld1DV2I8Trap:        return "NVPTXISD::Suld1DV2I8Trap";
00742   case NVPTXISD::Suld1DV2I16Trap:       return "NVPTXISD::Suld1DV2I16Trap";
00743   case NVPTXISD::Suld1DV2I32Trap:       return "NVPTXISD::Suld1DV2I32Trap";
00744   case NVPTXISD::Suld1DV2I64Trap:       return "NVPTXISD::Suld1DV2I64Trap";
00745   case NVPTXISD::Suld1DV4I8Trap:        return "NVPTXISD::Suld1DV4I8Trap";
00746   case NVPTXISD::Suld1DV4I16Trap:       return "NVPTXISD::Suld1DV4I16Trap";
00747   case NVPTXISD::Suld1DV4I32Trap:       return "NVPTXISD::Suld1DV4I32Trap";
00748 
00749   case NVPTXISD::Suld1DArrayI8Trap:     return "NVPTXISD::Suld1DArrayI8Trap";
00750   case NVPTXISD::Suld1DArrayI16Trap:    return "NVPTXISD::Suld1DArrayI16Trap";
00751   case NVPTXISD::Suld1DArrayI32Trap:    return "NVPTXISD::Suld1DArrayI32Trap";
00752   case NVPTXISD::Suld1DArrayI64Trap:    return "NVPTXISD::Suld1DArrayI64Trap";
00753   case NVPTXISD::Suld1DArrayV2I8Trap:   return "NVPTXISD::Suld1DArrayV2I8Trap";
00754   case NVPTXISD::Suld1DArrayV2I16Trap:  return "NVPTXISD::Suld1DArrayV2I16Trap";
00755   case NVPTXISD::Suld1DArrayV2I32Trap:  return "NVPTXISD::Suld1DArrayV2I32Trap";
00756   case NVPTXISD::Suld1DArrayV2I64Trap:  return "NVPTXISD::Suld1DArrayV2I64Trap";
00757   case NVPTXISD::Suld1DArrayV4I8Trap:   return "NVPTXISD::Suld1DArrayV4I8Trap";
00758   case NVPTXISD::Suld1DArrayV4I16Trap:  return "NVPTXISD::Suld1DArrayV4I16Trap";
00759   case NVPTXISD::Suld1DArrayV4I32Trap:  return "NVPTXISD::Suld1DArrayV4I32Trap";
00760 
00761   case NVPTXISD::Suld2DI8Trap:          return "NVPTXISD::Suld2DI8Trap";
00762   case NVPTXISD::Suld2DI16Trap:         return "NVPTXISD::Suld2DI16Trap";
00763   case NVPTXISD::Suld2DI32Trap:         return "NVPTXISD::Suld2DI32Trap";
00764   case NVPTXISD::Suld2DI64Trap:         return "NVPTXISD::Suld2DI64Trap";
00765   case NVPTXISD::Suld2DV2I8Trap:        return "NVPTXISD::Suld2DV2I8Trap";
00766   case NVPTXISD::Suld2DV2I16Trap:       return "NVPTXISD::Suld2DV2I16Trap";
00767   case NVPTXISD::Suld2DV2I32Trap:       return "NVPTXISD::Suld2DV2I32Trap";
00768   case NVPTXISD::Suld2DV2I64Trap:       return "NVPTXISD::Suld2DV2I64Trap";
00769   case NVPTXISD::Suld2DV4I8Trap:        return "NVPTXISD::Suld2DV4I8Trap";
00770   case NVPTXISD::Suld2DV4I16Trap:       return "NVPTXISD::Suld2DV4I16Trap";
00771   case NVPTXISD::Suld2DV4I32Trap:       return "NVPTXISD::Suld2DV4I32Trap";
00772 
00773   case NVPTXISD::Suld2DArrayI8Trap:     return "NVPTXISD::Suld2DArrayI8Trap";
00774   case NVPTXISD::Suld2DArrayI16Trap:    return "NVPTXISD::Suld2DArrayI16Trap";
00775   case NVPTXISD::Suld2DArrayI32Trap:    return "NVPTXISD::Suld2DArrayI32Trap";
00776   case NVPTXISD::Suld2DArrayI64Trap:    return "NVPTXISD::Suld2DArrayI64Trap";
00777   case NVPTXISD::Suld2DArrayV2I8Trap:   return "NVPTXISD::Suld2DArrayV2I8Trap";
00778   case NVPTXISD::Suld2DArrayV2I16Trap:  return "NVPTXISD::Suld2DArrayV2I16Trap";
00779   case NVPTXISD::Suld2DArrayV2I32Trap:  return "NVPTXISD::Suld2DArrayV2I32Trap";
00780   case NVPTXISD::Suld2DArrayV2I64Trap:  return "NVPTXISD::Suld2DArrayV2I64Trap";
00781   case NVPTXISD::Suld2DArrayV4I8Trap:   return "NVPTXISD::Suld2DArrayV4I8Trap";
00782   case NVPTXISD::Suld2DArrayV4I16Trap:  return "NVPTXISD::Suld2DArrayV4I16Trap";
00783   case NVPTXISD::Suld2DArrayV4I32Trap:  return "NVPTXISD::Suld2DArrayV4I32Trap";
00784 
00785   case NVPTXISD::Suld3DI8Trap:          return "NVPTXISD::Suld3DI8Trap";
00786   case NVPTXISD::Suld3DI16Trap:         return "NVPTXISD::Suld3DI16Trap";
00787   case NVPTXISD::Suld3DI32Trap:         return "NVPTXISD::Suld3DI32Trap";
00788   case NVPTXISD::Suld3DI64Trap:         return "NVPTXISD::Suld3DI64Trap";
00789   case NVPTXISD::Suld3DV2I8Trap:        return "NVPTXISD::Suld3DV2I8Trap";
00790   case NVPTXISD::Suld3DV2I16Trap:       return "NVPTXISD::Suld3DV2I16Trap";
00791   case NVPTXISD::Suld3DV2I32Trap:       return "NVPTXISD::Suld3DV2I32Trap";
00792   case NVPTXISD::Suld3DV2I64Trap:       return "NVPTXISD::Suld3DV2I64Trap";
00793   case NVPTXISD::Suld3DV4I8Trap:        return "NVPTXISD::Suld3DV4I8Trap";
00794   case NVPTXISD::Suld3DV4I16Trap:       return "NVPTXISD::Suld3DV4I16Trap";
00795   case NVPTXISD::Suld3DV4I32Trap:       return "NVPTXISD::Suld3DV4I32Trap";
00796 
00797   case NVPTXISD::Suld1DI8Zero:          return "NVPTXISD::Suld1DI8Zero";
00798   case NVPTXISD::Suld1DI16Zero:         return "NVPTXISD::Suld1DI16Zero";
00799   case NVPTXISD::Suld1DI32Zero:         return "NVPTXISD::Suld1DI32Zero";
00800   case NVPTXISD::Suld1DI64Zero:         return "NVPTXISD::Suld1DI64Zero";
00801   case NVPTXISD::Suld1DV2I8Zero:        return "NVPTXISD::Suld1DV2I8Zero";
00802   case NVPTXISD::Suld1DV2I16Zero:       return "NVPTXISD::Suld1DV2I16Zero";
00803   case NVPTXISD::Suld1DV2I32Zero:       return "NVPTXISD::Suld1DV2I32Zero";
00804   case NVPTXISD::Suld1DV2I64Zero:       return "NVPTXISD::Suld1DV2I64Zero";
00805   case NVPTXISD::Suld1DV4I8Zero:        return "NVPTXISD::Suld1DV4I8Zero";
00806   case NVPTXISD::Suld1DV4I16Zero:       return "NVPTXISD::Suld1DV4I16Zero";
00807   case NVPTXISD::Suld1DV4I32Zero:       return "NVPTXISD::Suld1DV4I32Zero";
00808 
00809   case NVPTXISD::Suld1DArrayI8Zero:     return "NVPTXISD::Suld1DArrayI8Zero";
00810   case NVPTXISD::Suld1DArrayI16Zero:    return "NVPTXISD::Suld1DArrayI16Zero";
00811   case NVPTXISD::Suld1DArrayI32Zero:    return "NVPTXISD::Suld1DArrayI32Zero";
00812   case NVPTXISD::Suld1DArrayI64Zero:    return "NVPTXISD::Suld1DArrayI64Zero";
00813   case NVPTXISD::Suld1DArrayV2I8Zero:   return "NVPTXISD::Suld1DArrayV2I8Zero";
00814   case NVPTXISD::Suld1DArrayV2I16Zero:  return "NVPTXISD::Suld1DArrayV2I16Zero";
00815   case NVPTXISD::Suld1DArrayV2I32Zero:  return "NVPTXISD::Suld1DArrayV2I32Zero";
00816   case NVPTXISD::Suld1DArrayV2I64Zero:  return "NVPTXISD::Suld1DArrayV2I64Zero";
00817   case NVPTXISD::Suld1DArrayV4I8Zero:   return "NVPTXISD::Suld1DArrayV4I8Zero";
00818   case NVPTXISD::Suld1DArrayV4I16Zero:  return "NVPTXISD::Suld1DArrayV4I16Zero";
00819   case NVPTXISD::Suld1DArrayV4I32Zero:  return "NVPTXISD::Suld1DArrayV4I32Zero";
00820 
00821   case NVPTXISD::Suld2DI8Zero:          return "NVPTXISD::Suld2DI8Zero";
00822   case NVPTXISD::Suld2DI16Zero:         return "NVPTXISD::Suld2DI16Zero";
00823   case NVPTXISD::Suld2DI32Zero:         return "NVPTXISD::Suld2DI32Zero";
00824   case NVPTXISD::Suld2DI64Zero:         return "NVPTXISD::Suld2DI64Zero";
00825   case NVPTXISD::Suld2DV2I8Zero:        return "NVPTXISD::Suld2DV2I8Zero";
00826   case NVPTXISD::Suld2DV2I16Zero:       return "NVPTXISD::Suld2DV2I16Zero";
00827   case NVPTXISD::Suld2DV2I32Zero:       return "NVPTXISD::Suld2DV2I32Zero";
00828   case NVPTXISD::Suld2DV2I64Zero:       return "NVPTXISD::Suld2DV2I64Zero";
00829   case NVPTXISD::Suld2DV4I8Zero:        return "NVPTXISD::Suld2DV4I8Zero";
00830   case NVPTXISD::Suld2DV4I16Zero:       return "NVPTXISD::Suld2DV4I16Zero";
00831   case NVPTXISD::Suld2DV4I32Zero:       return "NVPTXISD::Suld2DV4I32Zero";
00832 
00833   case NVPTXISD::Suld2DArrayI8Zero:     return "NVPTXISD::Suld2DArrayI8Zero";
00834   case NVPTXISD::Suld2DArrayI16Zero:    return "NVPTXISD::Suld2DArrayI16Zero";
00835   case NVPTXISD::Suld2DArrayI32Zero:    return "NVPTXISD::Suld2DArrayI32Zero";
00836   case NVPTXISD::Suld2DArrayI64Zero:    return "NVPTXISD::Suld2DArrayI64Zero";
00837   case NVPTXISD::Suld2DArrayV2I8Zero:   return "NVPTXISD::Suld2DArrayV2I8Zero";
00838   case NVPTXISD::Suld2DArrayV2I16Zero:  return "NVPTXISD::Suld2DArrayV2I16Zero";
00839   case NVPTXISD::Suld2DArrayV2I32Zero:  return "NVPTXISD::Suld2DArrayV2I32Zero";
00840   case NVPTXISD::Suld2DArrayV2I64Zero:  return "NVPTXISD::Suld2DArrayV2I64Zero";
00841   case NVPTXISD::Suld2DArrayV4I8Zero:   return "NVPTXISD::Suld2DArrayV4I8Zero";
00842   case NVPTXISD::Suld2DArrayV4I16Zero:  return "NVPTXISD::Suld2DArrayV4I16Zero";
00843   case NVPTXISD::Suld2DArrayV4I32Zero:  return "NVPTXISD::Suld2DArrayV4I32Zero";
00844 
00845   case NVPTXISD::Suld3DI8Zero:          return "NVPTXISD::Suld3DI8Zero";
00846   case NVPTXISD::Suld3DI16Zero:         return "NVPTXISD::Suld3DI16Zero";
00847   case NVPTXISD::Suld3DI32Zero:         return "NVPTXISD::Suld3DI32Zero";
00848   case NVPTXISD::Suld3DI64Zero:         return "NVPTXISD::Suld3DI64Zero";
00849   case NVPTXISD::Suld3DV2I8Zero:        return "NVPTXISD::Suld3DV2I8Zero";
00850   case NVPTXISD::Suld3DV2I16Zero:       return "NVPTXISD::Suld3DV2I16Zero";
00851   case NVPTXISD::Suld3DV2I32Zero:       return "NVPTXISD::Suld3DV2I32Zero";
00852   case NVPTXISD::Suld3DV2I64Zero:       return "NVPTXISD::Suld3DV2I64Zero";
00853   case NVPTXISD::Suld3DV4I8Zero:        return "NVPTXISD::Suld3DV4I8Zero";
00854   case NVPTXISD::Suld3DV4I16Zero:       return "NVPTXISD::Suld3DV4I16Zero";
00855   case NVPTXISD::Suld3DV4I32Zero:       return "NVPTXISD::Suld3DV4I32Zero";
00856   }
00857 }
00858 
00859 TargetLoweringBase::LegalizeTypeAction
00860 NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
00861   if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
00862     return TypeSplitVector;
00863 
00864   return TargetLoweringBase::getPreferredVectorAction(VT);
00865 }
00866 
00867 SDValue
00868 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
00869   SDLoc dl(Op);
00870   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
00871   Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
00872   return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
00873 }
00874 
00875 std::string
00876 NVPTXTargetLowering::getPrototype(Type *retTy, const ArgListTy &Args,
00877                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
00878                                   unsigned retAlignment,
00879                                   const ImmutableCallSite *CS) const {
00880 
00881   bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
00882   assert(isABI && "Non-ABI compilation is not supported");
00883   if (!isABI)
00884     return "";
00885 
00886   std::stringstream O;
00887   O << "prototype_" << uniqueCallSite << " : .callprototype ";
00888 
00889   if (retTy->getTypeID() == Type::VoidTyID) {
00890     O << "()";
00891   } else {
00892     O << "(";
00893     if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
00894       unsigned size = 0;
00895       if (const IntegerType *ITy = dyn_cast<IntegerType>(retTy)) {
00896         size = ITy->getBitWidth();
00897         if (size < 32)
00898           size = 32;
00899       } else {
00900         assert(retTy->isFloatingPointTy() &&
00901                "Floating point type expected here");
00902         size = retTy->getPrimitiveSizeInBits();
00903       }
00904 
00905       O << ".param .b" << size << " _";
00906     } else if (isa<PointerType>(retTy)) {
00907       O << ".param .b" << getPointerTy().getSizeInBits() << " _";
00908     } else {
00909       if((retTy->getTypeID() == Type::StructTyID) ||
00910          isa<VectorType>(retTy)) {
00911         O << ".param .align "
00912           << retAlignment
00913           << " .b8 _["
00914           << getDataLayout()->getTypeAllocSize(retTy) << "]";
00915       } else {
00916         assert(false && "Unknown return type");
00917       }
00918     }
00919     O << ") ";
00920   }
00921   O << "_ (";
00922 
00923   bool first = true;
00924   MVT thePointerTy = getPointerTy();
00925 
00926   unsigned OIdx = 0;
00927   for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
00928     Type *Ty = Args[i].Ty;
00929     if (!first) {
00930       O << ", ";
00931     }
00932     first = false;
00933 
00934     if (Outs[OIdx].Flags.isByVal() == false) {
00935       if (Ty->isAggregateType() || Ty->isVectorTy()) {
00936         unsigned align = 0;
00937         const CallInst *CallI = cast<CallInst>(CS->getInstruction());
00938         const DataLayout *TD = getDataLayout();
00939         // +1 because index 0 is reserved for return type alignment
00940         if (!llvm::getAlign(*CallI, i + 1, align))
00941           align = TD->getABITypeAlignment(Ty);
00942         unsigned sz = TD->getTypeAllocSize(Ty);
00943         O << ".param .align " << align << " .b8 ";
00944         O << "_";
00945         O << "[" << sz << "]";
00946         // update the index for Outs
00947         SmallVector<EVT, 16> vtparts;
00948         ComputeValueVTs(*this, Ty, vtparts);
00949         if (unsigned len = vtparts.size())
00950           OIdx += len - 1;
00951         continue;
00952       }
00953        // i8 types in IR will be i16 types in SDAG
00954       assert((getValueType(Ty) == Outs[OIdx].VT ||
00955              (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
00956              "type mismatch between callee prototype and arguments");
00957       // scalar type
00958       unsigned sz = 0;
00959       if (isa<IntegerType>(Ty)) {
00960         sz = cast<IntegerType>(Ty)->getBitWidth();
00961         if (sz < 32)
00962           sz = 32;
00963       } else if (isa<PointerType>(Ty))
00964         sz = thePointerTy.getSizeInBits();
00965       else
00966         sz = Ty->getPrimitiveSizeInBits();
00967       O << ".param .b" << sz << " ";
00968       O << "_";
00969       continue;
00970     }
00971     const PointerType *PTy = dyn_cast<PointerType>(Ty);
00972     assert(PTy && "Param with byval attribute should be a pointer type");
00973     Type *ETy = PTy->getElementType();
00974 
00975     unsigned align = Outs[OIdx].Flags.getByValAlign();
00976     unsigned sz = getDataLayout()->getTypeAllocSize(ETy);
00977     O << ".param .align " << align << " .b8 ";
00978     O << "_";
00979     O << "[" << sz << "]";
00980   }
00981   O << ");";
00982   return O.str();
00983 }
00984 
00985 unsigned
00986 NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
00987                                           const ImmutableCallSite *CS,
00988                                           Type *Ty,
00989                                           unsigned Idx) const {
00990   const DataLayout *TD = getDataLayout();
00991   unsigned Align = 0;
00992   const Value *DirectCallee = CS->getCalledFunction();
00993 
00994   if (!DirectCallee) {
00995     // We don't have a direct function symbol, but that may be because of
00996     // constant cast instructions in the call.
00997     const Instruction *CalleeI = CS->getInstruction();
00998     assert(CalleeI && "Call target is not a function or derived value?");
00999 
01000     // With bitcast'd call targets, the instruction will be the call
01001     if (isa<CallInst>(CalleeI)) {
01002       // Check if we have call alignment metadata
01003       if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
01004         return Align;
01005 
01006       const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
01007       // Ignore any bitcast instructions
01008       while(isa<ConstantExpr>(CalleeV)) {
01009         const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
01010         if (!CE->isCast())
01011           break;
01012         // Look through the bitcast
01013         CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
01014       }
01015 
01016       // We have now looked past all of the bitcasts.  Do we finally have a
01017       // Function?
01018       if (isa<Function>(CalleeV))
01019         DirectCallee = CalleeV;
01020     }
01021   }
01022 
01023   // Check for function alignment information if we found that the
01024   // ultimate target is a Function
01025   if (DirectCallee)
01026     if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
01027       return Align;
01028 
01029   // Call is indirect or alignment information is not available, fall back to
01030   // the ABI type alignment
01031   return TD->getABITypeAlignment(Ty);
01032 }
01033 
01034 SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
01035                                        SmallVectorImpl<SDValue> &InVals) const {
01036   SelectionDAG &DAG = CLI.DAG;
01037   SDLoc dl = CLI.DL;
01038   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
01039   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
01040   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
01041   SDValue Chain = CLI.Chain;
01042   SDValue Callee = CLI.Callee;
01043   bool &isTailCall = CLI.IsTailCall;
01044   ArgListTy &Args = CLI.getArgs();
01045   Type *retTy = CLI.RetTy;
01046   ImmutableCallSite *CS = CLI.CS;
01047 
01048   bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
01049   assert(isABI && "Non-ABI compilation is not supported");
01050   if (!isABI)
01051     return Chain;
01052   const DataLayout *TD = getDataLayout();
01053   MachineFunction &MF = DAG.getMachineFunction();
01054   const Function *F = MF.getFunction();
01055 
01056   SDValue tempChain = Chain;
01057   Chain =
01058       DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
01059                            dl);
01060   SDValue InFlag = Chain.getValue(1);
01061 
01062   unsigned paramCount = 0;
01063   // Args.size() and Outs.size() need not match.
01064   // Outs.size() will be larger
01065   //   * if there is an aggregate argument with multiple fields (each field
01066   //     showing up separately in Outs)
01067   //   * if there is a vector argument with more than typical vector-length
01068   //     elements (generally if more than 4) where each vector element is
01069   //     individually present in Outs.
01070   // So a different index should be used for indexing into Outs/OutVals.
01071   // See similar issue in LowerFormalArguments.
01072   unsigned OIdx = 0;
01073   // Declare the .params or .reg need to pass values
01074   // to the function
01075   for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
01076     EVT VT = Outs[OIdx].VT;
01077     Type *Ty = Args[i].Ty;
01078 
01079     if (Outs[OIdx].Flags.isByVal() == false) {
01080       if (Ty->isAggregateType()) {
01081         // aggregate
01082         SmallVector<EVT, 16> vtparts;
01083         SmallVector<uint64_t, 16> Offsets;
01084         ComputePTXValueVTs(*this, Ty, vtparts, &Offsets, 0);
01085 
01086         unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
01087         // declare .param .align <align> .b8 .param<n>[<size>];
01088         unsigned sz = TD->getTypeAllocSize(Ty);
01089         SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01090         SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
01091                                       DAG.getConstant(paramCount, MVT::i32),
01092                                       DAG.getConstant(sz, MVT::i32), InFlag };
01093         Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
01094                             DeclareParamOps);
01095         InFlag = Chain.getValue(1);
01096         for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
01097           EVT elemtype = vtparts[j];
01098           unsigned ArgAlign = GreatestCommonDivisor64(align, Offsets[j]);
01099           if (elemtype.isInteger() && (sz < 8))
01100             sz = 8;
01101           SDValue StVal = OutVals[OIdx];
01102           if (elemtype.getSizeInBits() < 16) {
01103             StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
01104           }
01105           SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01106           SDValue CopyParamOps[] = { Chain,
01107                                      DAG.getConstant(paramCount, MVT::i32),
01108                                      DAG.getConstant(Offsets[j], MVT::i32),
01109                                      StVal, InFlag };
01110           Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
01111                                           CopyParamVTs, CopyParamOps,
01112                                           elemtype, MachinePointerInfo(),
01113                                           ArgAlign);
01114           InFlag = Chain.getValue(1);
01115           ++OIdx;
01116         }
01117         if (vtparts.size() > 0)
01118           --OIdx;
01119         ++paramCount;
01120         continue;
01121       }
01122       if (Ty->isVectorTy()) {
01123         EVT ObjectVT = getValueType(Ty);
01124         unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
01125         // declare .param .align <align> .b8 .param<n>[<size>];
01126         unsigned sz = TD->getTypeAllocSize(Ty);
01127         SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01128         SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, MVT::i32),
01129                                       DAG.getConstant(paramCount, MVT::i32),
01130                                       DAG.getConstant(sz, MVT::i32), InFlag };
01131         Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
01132                             DeclareParamOps);
01133         InFlag = Chain.getValue(1);
01134         unsigned NumElts = ObjectVT.getVectorNumElements();
01135         EVT EltVT = ObjectVT.getVectorElementType();
01136         EVT MemVT = EltVT;
01137         bool NeedExtend = false;
01138         if (EltVT.getSizeInBits() < 16) {
01139           NeedExtend = true;
01140           EltVT = MVT::i16;
01141         }
01142 
01143         // V1 store
01144         if (NumElts == 1) {
01145           SDValue Elt = OutVals[OIdx++];
01146           if (NeedExtend)
01147             Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
01148 
01149           SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01150           SDValue CopyParamOps[] = { Chain,
01151                                      DAG.getConstant(paramCount, MVT::i32),
01152                                      DAG.getConstant(0, MVT::i32), Elt,
01153                                      InFlag };
01154           Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
01155                                           CopyParamVTs, CopyParamOps,
01156                                           MemVT, MachinePointerInfo());
01157           InFlag = Chain.getValue(1);
01158         } else if (NumElts == 2) {
01159           SDValue Elt0 = OutVals[OIdx++];
01160           SDValue Elt1 = OutVals[OIdx++];
01161           if (NeedExtend) {
01162             Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
01163             Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
01164           }
01165 
01166           SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01167           SDValue CopyParamOps[] = { Chain,
01168                                      DAG.getConstant(paramCount, MVT::i32),
01169                                      DAG.getConstant(0, MVT::i32), Elt0, Elt1,
01170                                      InFlag };
01171           Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
01172                                           CopyParamVTs, CopyParamOps,
01173                                           MemVT, MachinePointerInfo());
01174           InFlag = Chain.getValue(1);
01175         } else {
01176           unsigned curOffset = 0;
01177           // V4 stores
01178           // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
01179           // the
01180           // vector will be expanded to a power of 2 elements, so we know we can
01181           // always round up to the next multiple of 4 when creating the vector
01182           // stores.
01183           // e.g.  4 elem => 1 st.v4
01184           //       6 elem => 2 st.v4
01185           //       8 elem => 2 st.v4
01186           //      11 elem => 3 st.v4
01187           unsigned VecSize = 4;
01188           if (EltVT.getSizeInBits() == 64)
01189             VecSize = 2;
01190 
01191           // This is potentially only part of a vector, so assume all elements
01192           // are packed together.
01193           unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
01194 
01195           for (unsigned i = 0; i < NumElts; i += VecSize) {
01196             // Get values
01197             SDValue StoreVal;
01198             SmallVector<SDValue, 8> Ops;
01199             Ops.push_back(Chain);
01200             Ops.push_back(DAG.getConstant(paramCount, MVT::i32));
01201             Ops.push_back(DAG.getConstant(curOffset, MVT::i32));
01202 
01203             unsigned Opc = NVPTXISD::StoreParamV2;
01204 
01205             StoreVal = OutVals[OIdx++];
01206             if (NeedExtend)
01207               StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
01208             Ops.push_back(StoreVal);
01209 
01210             if (i + 1 < NumElts) {
01211               StoreVal = OutVals[OIdx++];
01212               if (NeedExtend)
01213                 StoreVal =
01214                     DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
01215             } else {
01216               StoreVal = DAG.getUNDEF(EltVT);
01217             }
01218             Ops.push_back(StoreVal);
01219 
01220             if (VecSize == 4) {
01221               Opc = NVPTXISD::StoreParamV4;
01222               if (i + 2 < NumElts) {
01223                 StoreVal = OutVals[OIdx++];
01224                 if (NeedExtend)
01225                   StoreVal =
01226                       DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
01227               } else {
01228                 StoreVal = DAG.getUNDEF(EltVT);
01229               }
01230               Ops.push_back(StoreVal);
01231 
01232               if (i + 3 < NumElts) {
01233                 StoreVal = OutVals[OIdx++];
01234                 if (NeedExtend)
01235                   StoreVal =
01236                       DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
01237               } else {
01238                 StoreVal = DAG.getUNDEF(EltVT);
01239               }
01240               Ops.push_back(StoreVal);
01241             }
01242 
01243             Ops.push_back(InFlag);
01244 
01245             SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01246             Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
01247                                             MemVT, MachinePointerInfo());
01248             InFlag = Chain.getValue(1);
01249             curOffset += PerStoreOffset;
01250           }
01251         }
01252         ++paramCount;
01253         --OIdx;
01254         continue;
01255       }
01256       // Plain scalar
01257       // for ABI,    declare .param .b<size> .param<n>;
01258       unsigned sz = VT.getSizeInBits();
01259       bool needExtend = false;
01260       if (VT.isInteger()) {
01261         if (sz < 16)
01262           needExtend = true;
01263         if (sz < 32)
01264           sz = 32;
01265       }
01266       SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01267       SDValue DeclareParamOps[] = { Chain,
01268                                     DAG.getConstant(paramCount, MVT::i32),
01269                                     DAG.getConstant(sz, MVT::i32),
01270                                     DAG.getConstant(0, MVT::i32), InFlag };
01271       Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
01272                           DeclareParamOps);
01273       InFlag = Chain.getValue(1);
01274       SDValue OutV = OutVals[OIdx];
01275       if (needExtend) {
01276         // zext/sext i1 to i16
01277         unsigned opc = ISD::ZERO_EXTEND;
01278         if (Outs[OIdx].Flags.isSExt())
01279           opc = ISD::SIGN_EXTEND;
01280         OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
01281       }
01282       SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01283       SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
01284                                  DAG.getConstant(0, MVT::i32), OutV, InFlag };
01285 
01286       unsigned opcode = NVPTXISD::StoreParam;
01287       if (Outs[OIdx].Flags.isZExt())
01288         opcode = NVPTXISD::StoreParamU32;
01289       else if (Outs[OIdx].Flags.isSExt())
01290         opcode = NVPTXISD::StoreParamS32;
01291       Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
01292                                       VT, MachinePointerInfo());
01293 
01294       InFlag = Chain.getValue(1);
01295       ++paramCount;
01296       continue;
01297     }
01298     // struct or vector
01299     SmallVector<EVT, 16> vtparts;
01300     SmallVector<uint64_t, 16> Offsets;
01301     const PointerType *PTy = dyn_cast<PointerType>(Args[i].Ty);
01302     assert(PTy && "Type of a byval parameter should be pointer");
01303     ComputePTXValueVTs(*this, PTy->getElementType(), vtparts, &Offsets, 0);
01304 
01305     // declare .param .align <align> .b8 .param<n>[<size>];
01306     unsigned sz = Outs[OIdx].Flags.getByValSize();
01307     SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01308     unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
01309     // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
01310     // so we don't need to worry about natural alignment or not.
01311     // See TargetLowering::LowerCallTo().
01312     SDValue DeclareParamOps[] = {
01313       Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), MVT::i32),
01314       DAG.getConstant(paramCount, MVT::i32), DAG.getConstant(sz, MVT::i32),
01315       InFlag
01316     };
01317     Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
01318                         DeclareParamOps);
01319     InFlag = Chain.getValue(1);
01320     for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
01321       EVT elemtype = vtparts[j];
01322       int curOffset = Offsets[j];
01323       unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
01324       SDValue srcAddr =
01325           DAG.getNode(ISD::ADD, dl, getPointerTy(), OutVals[OIdx],
01326                       DAG.getConstant(curOffset, getPointerTy()));
01327       SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
01328                                    MachinePointerInfo(), false, false, false,
01329                                    PartAlign);
01330       if (elemtype.getSizeInBits() < 16) {
01331         theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
01332       }
01333       SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01334       SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
01335                                  DAG.getConstant(curOffset, MVT::i32), theVal,
01336                                  InFlag };
01337       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
01338                                       CopyParamOps, elemtype,
01339                                       MachinePointerInfo());
01340 
01341       InFlag = Chain.getValue(1);
01342     }
01343     ++paramCount;
01344   }
01345 
01346   GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
01347   unsigned retAlignment = 0;
01348 
01349   // Handle Result
01350   if (Ins.size() > 0) {
01351     SmallVector<EVT, 16> resvtparts;
01352     ComputeValueVTs(*this, retTy, resvtparts);
01353 
01354     // Declare
01355     //  .param .align 16 .b8 retval0[<size-in-bytes>], or
01356     //  .param .b<size-in-bits> retval0
01357     unsigned resultsz = TD->getTypeAllocSizeInBits(retTy);
01358     // Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
01359     // these three types to match the logic in
01360     // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
01361     // Plus, this behavior is consistent with nvcc's.
01362     if (retTy->isFloatingPointTy() || retTy->isIntegerTy() ||
01363         retTy->isPointerTy()) {
01364       // Scalar needs to be at least 32bit wide
01365       if (resultsz < 32)
01366         resultsz = 32;
01367       SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01368       SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, MVT::i32),
01369                                   DAG.getConstant(resultsz, MVT::i32),
01370                                   DAG.getConstant(0, MVT::i32), InFlag };
01371       Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
01372                           DeclareRetOps);
01373       InFlag = Chain.getValue(1);
01374     } else {
01375       retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
01376       SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01377       SDValue DeclareRetOps[] = { Chain,
01378                                   DAG.getConstant(retAlignment, MVT::i32),
01379                                   DAG.getConstant(resultsz / 8, MVT::i32),
01380                                   DAG.getConstant(0, MVT::i32), InFlag };
01381       Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
01382                           DeclareRetOps);
01383       InFlag = Chain.getValue(1);
01384     }
01385   }
01386 
01387   if (!Func) {
01388     // This is indirect function call case : PTX requires a prototype of the
01389     // form
01390     // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
01391     // to be emitted, and the label has to used as the last arg of call
01392     // instruction.
01393     // The prototype is embedded in a string and put as the operand for a
01394     // CallPrototype SDNode which will print out to the value of the string.
01395     SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01396     std::string Proto = getPrototype(retTy, Args, Outs, retAlignment, CS);
01397     const char *ProtoStr =
01398       nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
01399     SDValue ProtoOps[] = {
01400       Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
01401     };
01402     Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
01403     InFlag = Chain.getValue(1);
01404   }
01405   // Op to just print "call"
01406   SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01407   SDValue PrintCallOps[] = {
01408     Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, MVT::i32), InFlag
01409   };
01410   Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
01411                       dl, PrintCallVTs, PrintCallOps);
01412   InFlag = Chain.getValue(1);
01413 
01414   // Ops to print out the function name
01415   SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01416   SDValue CallVoidOps[] = { Chain, Callee, InFlag };
01417   Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
01418   InFlag = Chain.getValue(1);
01419 
01420   // Ops to print out the param list
01421   SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01422   SDValue CallArgBeginOps[] = { Chain, InFlag };
01423   Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
01424                       CallArgBeginOps);
01425   InFlag = Chain.getValue(1);
01426 
01427   for (unsigned i = 0, e = paramCount; i != e; ++i) {
01428     unsigned opcode;
01429     if (i == (e - 1))
01430       opcode = NVPTXISD::LastCallArg;
01431     else
01432       opcode = NVPTXISD::CallArg;
01433     SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01434     SDValue CallArgOps[] = { Chain, DAG.getConstant(1, MVT::i32),
01435                              DAG.getConstant(i, MVT::i32), InFlag };
01436     Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
01437     InFlag = Chain.getValue(1);
01438   }
01439   SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01440   SDValue CallArgEndOps[] = { Chain, DAG.getConstant(Func ? 1 : 0, MVT::i32),
01441                               InFlag };
01442   Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
01443   InFlag = Chain.getValue(1);
01444 
01445   if (!Func) {
01446     SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
01447     SDValue PrototypeOps[] = { Chain, DAG.getConstant(uniqueCallSite, MVT::i32),
01448                                InFlag };
01449     Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
01450     InFlag = Chain.getValue(1);
01451   }
01452 
01453   // Generate loads from param memory/moves from registers for result
01454   if (Ins.size() > 0) {
01455     if (retTy && retTy->isVectorTy()) {
01456       EVT ObjectVT = getValueType(retTy);
01457       unsigned NumElts = ObjectVT.getVectorNumElements();
01458       EVT EltVT = ObjectVT.getVectorElementType();
01459       assert(nvTM->getSubtargetImpl()->getTargetLowering()->getNumRegisters(
01460                  F->getContext(), ObjectVT) == NumElts &&
01461              "Vector was not scalarized");
01462       unsigned sz = EltVT.getSizeInBits();
01463       bool needTruncate = sz < 8 ? true : false;
01464 
01465       if (NumElts == 1) {
01466         // Just a simple load
01467         SmallVector<EVT, 4> LoadRetVTs;
01468         if (EltVT == MVT::i1 || EltVT == MVT::i8) {
01469           // If loading i1/i8 result, generate
01470           //   load.b8 i16
01471           //   if i1
01472           //   trunc i16 to i1
01473           LoadRetVTs.push_back(MVT::i16);
01474         } else
01475           LoadRetVTs.push_back(EltVT);
01476         LoadRetVTs.push_back(MVT::Other);
01477         LoadRetVTs.push_back(MVT::Glue);
01478         SmallVector<SDValue, 4> LoadRetOps;
01479         LoadRetOps.push_back(Chain);
01480         LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
01481         LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
01482         LoadRetOps.push_back(InFlag);
01483         SDValue retval = DAG.getMemIntrinsicNode(
01484             NVPTXISD::LoadParam, dl,
01485             DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
01486         Chain = retval.getValue(1);
01487         InFlag = retval.getValue(2);
01488         SDValue Ret0 = retval;
01489         if (needTruncate)
01490           Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
01491         InVals.push_back(Ret0);
01492       } else if (NumElts == 2) {
01493         // LoadV2
01494         SmallVector<EVT, 4> LoadRetVTs;
01495         if (EltVT == MVT::i1 || EltVT == MVT::i8) {
01496           // If loading i1/i8 result, generate
01497           //   load.b8 i16
01498           //   if i1
01499           //   trunc i16 to i1
01500           LoadRetVTs.push_back(MVT::i16);
01501           LoadRetVTs.push_back(MVT::i16);
01502         } else {
01503           LoadRetVTs.push_back(EltVT);
01504           LoadRetVTs.push_back(EltVT);
01505         }
01506         LoadRetVTs.push_back(MVT::Other);
01507         LoadRetVTs.push_back(MVT::Glue);
01508         SmallVector<SDValue, 4> LoadRetOps;
01509         LoadRetOps.push_back(Chain);
01510         LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
01511         LoadRetOps.push_back(DAG.getConstant(0, MVT::i32));
01512         LoadRetOps.push_back(InFlag);
01513         SDValue retval = DAG.getMemIntrinsicNode(
01514             NVPTXISD::LoadParamV2, dl,
01515             DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
01516         Chain = retval.getValue(2);
01517         InFlag = retval.getValue(3);
01518         SDValue Ret0 = retval.getValue(0);
01519         SDValue Ret1 = retval.getValue(1);
01520         if (needTruncate) {
01521           Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
01522           InVals.push_back(Ret0);
01523           Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
01524           InVals.push_back(Ret1);
01525         } else {
01526           InVals.push_back(Ret0);
01527           InVals.push_back(Ret1);
01528         }
01529       } else {
01530         // Split into N LoadV4
01531         unsigned Ofst = 0;
01532         unsigned VecSize = 4;
01533         unsigned Opc = NVPTXISD::LoadParamV4;
01534         if (EltVT.getSizeInBits() == 64) {
01535           VecSize = 2;
01536           Opc = NVPTXISD::LoadParamV2;
01537         }
01538         EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
01539         for (unsigned i = 0; i < NumElts; i += VecSize) {
01540           SmallVector<EVT, 8> LoadRetVTs;
01541           if (EltVT == MVT::i1 || EltVT == MVT::i8) {
01542             // If loading i1/i8 result, generate
01543             //   load.b8 i16
01544             //   if i1
01545             //   trunc i16 to i1
01546             for (unsigned j = 0; j < VecSize; ++j)
01547               LoadRetVTs.push_back(MVT::i16);
01548           } else {
01549             for (unsigned j = 0; j < VecSize; ++j)
01550               LoadRetVTs.push_back(EltVT);
01551           }
01552           LoadRetVTs.push_back(MVT::Other);
01553           LoadRetVTs.push_back(MVT::Glue);
01554           SmallVector<SDValue, 4> LoadRetOps;
01555           LoadRetOps.push_back(Chain);
01556           LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
01557           LoadRetOps.push_back(DAG.getConstant(Ofst, MVT::i32));
01558           LoadRetOps.push_back(InFlag);
01559           SDValue retval = DAG.getMemIntrinsicNode(
01560               Opc, dl, DAG.getVTList(LoadRetVTs),
01561               LoadRetOps, EltVT, MachinePointerInfo());
01562           if (VecSize == 2) {
01563             Chain = retval.getValue(2);
01564             InFlag = retval.getValue(3);
01565           } else {
01566             Chain = retval.getValue(4);
01567             InFlag = retval.getValue(5);
01568           }
01569 
01570           for (unsigned j = 0; j < VecSize; ++j) {
01571             if (i + j >= NumElts)
01572               break;
01573             SDValue Elt = retval.getValue(j);
01574             if (needTruncate)
01575               Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
01576             InVals.push_back(Elt);
01577           }
01578           Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
01579         }
01580       }
01581     } else {
01582       SmallVector<EVT, 16> VTs;
01583       SmallVector<uint64_t, 16> Offsets;
01584       ComputePTXValueVTs(*this, retTy, VTs, &Offsets, 0);
01585       assert(VTs.size() == Ins.size() && "Bad value decomposition");
01586       unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0);
01587       for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
01588         unsigned sz = VTs[i].getSizeInBits();
01589         unsigned AlignI = GreatestCommonDivisor64(RetAlign, Offsets[i]);
01590         bool needTruncate = sz < 8 ? true : false;
01591         if (VTs[i].isInteger() && (sz < 8))
01592           sz = 8;
01593 
01594         SmallVector<EVT, 4> LoadRetVTs;
01595         EVT TheLoadType = VTs[i];
01596         if (retTy->isIntegerTy() &&
01597             TD->getTypeAllocSizeInBits(retTy) < 32) {
01598           // This is for integer types only, and specifically not for
01599           // aggregates.
01600           LoadRetVTs.push_back(MVT::i32);
01601           TheLoadType = MVT::i32;
01602         } else if (sz < 16) {
01603           // If loading i1/i8 result, generate
01604           //   load i8 (-> i16)
01605           //   trunc i16 to i1/i8
01606           LoadRetVTs.push_back(MVT::i16);
01607         } else
01608           LoadRetVTs.push_back(Ins[i].VT);
01609         LoadRetVTs.push_back(MVT::Other);
01610         LoadRetVTs.push_back(MVT::Glue);
01611 
01612         SmallVector<SDValue, 4> LoadRetOps;
01613         LoadRetOps.push_back(Chain);
01614         LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
01615         LoadRetOps.push_back(DAG.getConstant(Offsets[i], MVT::i32));
01616         LoadRetOps.push_back(InFlag);
01617         SDValue retval = DAG.getMemIntrinsicNode(
01618             NVPTXISD::LoadParam, dl,
01619             DAG.getVTList(LoadRetVTs), LoadRetOps,
01620             TheLoadType, MachinePointerInfo(), AlignI);
01621         Chain = retval.getValue(1);
01622         InFlag = retval.getValue(2);
01623         SDValue Ret0 = retval.getValue(0);
01624         if (needTruncate)
01625           Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
01626         InVals.push_back(Ret0);
01627       }
01628     }
01629   }
01630 
01631   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(uniqueCallSite, true),
01632                              DAG.getIntPtrConstant(uniqueCallSite + 1, true),
01633                              InFlag, dl);
01634   uniqueCallSite++;
01635 
01636   // set isTailCall to false for now, until we figure out how to express
01637   // tail call optimization in PTX
01638   isTailCall = false;
01639   return Chain;
01640 }
01641 
01642 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
01643 // (see LegalizeDAG.cpp). This is slow and uses local memory.
01644 // We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
01645 SDValue
01646 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
01647   SDNode *Node = Op.getNode();
01648   SDLoc dl(Node);
01649   SmallVector<SDValue, 8> Ops;
01650   unsigned NumOperands = Node->getNumOperands();
01651   for (unsigned i = 0; i < NumOperands; ++i) {
01652     SDValue SubOp = Node->getOperand(i);
01653     EVT VVT = SubOp.getNode()->getValueType(0);
01654     EVT EltVT = VVT.getVectorElementType();
01655     unsigned NumSubElem = VVT.getVectorNumElements();
01656     for (unsigned j = 0; j < NumSubElem; ++j) {
01657       Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
01658                                 DAG.getIntPtrConstant(j)));
01659     }
01660   }
01661   return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
01662 }
01663 
01664 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
01665 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
01666 ///    amount, or
01667 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
01668 ///    amount.
01669 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
01670                                                   SelectionDAG &DAG) const {
01671   assert(Op.getNumOperands() == 3 && "Not a double-shift!");
01672   assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
01673 
01674   EVT VT = Op.getValueType();
01675   unsigned VTBits = VT.getSizeInBits();
01676   SDLoc dl(Op);
01677   SDValue ShOpLo = Op.getOperand(0);
01678   SDValue ShOpHi = Op.getOperand(1);
01679   SDValue ShAmt  = Op.getOperand(2);
01680   unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
01681 
01682   if (VTBits == 32 && nvptxSubtarget.getSmVersion() >= 35) {
01683 
01684     // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
01685     // {dHi, dLo} = {aHi, aLo} >> Amt
01686     //   dHi = aHi >> Amt
01687     //   dLo = shf.r.clamp aLo, aHi, Amt
01688 
01689     SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
01690     SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
01691                              ShAmt);
01692 
01693     SDValue Ops[2] = { Lo, Hi };
01694     return DAG.getMergeValues(Ops, dl);
01695   }
01696   else {
01697 
01698     // {dHi, dLo} = {aHi, aLo} >> Amt
01699     // - if (Amt>=size) then
01700     //      dLo = aHi >> (Amt-size)
01701     //      dHi = aHi >> Amt (this is either all 0 or all 1)
01702     //   else
01703     //      dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
01704     //      dHi = aHi >> Amt
01705 
01706     SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
01707                                    DAG.getConstant(VTBits, MVT::i32), ShAmt);
01708     SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
01709     SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
01710                                      DAG.getConstant(VTBits, MVT::i32));
01711     SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
01712     SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
01713     SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
01714 
01715     SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
01716                                DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
01717     SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
01718     SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
01719 
01720     SDValue Ops[2] = { Lo, Hi };
01721     return DAG.getMergeValues(Ops, dl);
01722   }
01723 }
01724 
01725 /// LowerShiftLeftParts - Lower SHL_PARTS, which
01726 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
01727 ///    amount, or
01728 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
01729 ///    amount.
01730 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
01731                                                  SelectionDAG &DAG) const {
01732   assert(Op.getNumOperands() == 3 && "Not a double-shift!");
01733   assert(Op.getOpcode() == ISD::SHL_PARTS);
01734 
01735   EVT VT = Op.getValueType();
01736   unsigned VTBits = VT.getSizeInBits();
01737   SDLoc dl(Op);
01738   SDValue ShOpLo = Op.getOperand(0);
01739   SDValue ShOpHi = Op.getOperand(1);
01740   SDValue ShAmt  = Op.getOperand(2);
01741 
01742   if (VTBits == 32 && nvptxSubtarget.getSmVersion() >= 35) {
01743 
01744     // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
01745     // {dHi, dLo} = {aHi, aLo} << Amt
01746     //   dHi = shf.l.clamp aLo, aHi, Amt
01747     //   dLo = aLo << Amt
01748 
01749     SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
01750                              ShAmt);
01751     SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
01752 
01753     SDValue Ops[2] = { Lo, Hi };
01754     return DAG.getMergeValues(Ops, dl);
01755   }
01756   else {
01757 
01758     // {dHi, dLo} = {aHi, aLo} << Amt
01759     // - if (Amt>=size) then
01760     //      dLo = aLo << Amt (all 0)
01761     //      dLo = aLo << (Amt-size)
01762     //   else
01763     //      dLo = aLo << Amt
01764     //      dHi = (aHi << Amt) | (aLo >> (size-Amt))
01765 
01766     SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
01767                                    DAG.getConstant(VTBits, MVT::i32), ShAmt);
01768     SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
01769     SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
01770                                      DAG.getConstant(VTBits, MVT::i32));
01771     SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
01772     SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
01773     SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
01774 
01775     SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
01776                                DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
01777     SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
01778     SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
01779 
01780     SDValue Ops[2] = { Lo, Hi };
01781     return DAG.getMergeValues(Ops, dl);
01782   }
01783 }
01784 
01785 SDValue
01786 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
01787   switch (Op.getOpcode()) {
01788   case ISD::RETURNADDR:
01789     return SDValue();
01790   case ISD::FRAMEADDR:
01791     return SDValue();
01792   case ISD::GlobalAddress:
01793     return LowerGlobalAddress(Op, DAG);
01794   case ISD::INTRINSIC_W_CHAIN:
01795     return Op;
01796   case ISD::BUILD_VECTOR:
01797   case ISD::EXTRACT_SUBVECTOR:
01798     return Op;
01799   case ISD::CONCAT_VECTORS:
01800     return LowerCONCAT_VECTORS(Op, DAG);
01801   case ISD::STORE:
01802     return LowerSTORE(Op, DAG);
01803   case ISD::LOAD:
01804     return LowerLOAD(Op, DAG);
01805   case ISD::SHL_PARTS:
01806     return LowerShiftLeftParts(Op, DAG);
01807   case ISD::SRA_PARTS:
01808   case ISD::SRL_PARTS:
01809     return LowerShiftRightParts(Op, DAG);
01810   default:
01811     llvm_unreachable("Custom lowering not defined for operation");
01812   }
01813 }
01814 
01815 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
01816   if (Op.getValueType() == MVT::i1)
01817     return LowerLOADi1(Op, DAG);
01818   else
01819     return SDValue();
01820 }
01821 
01822 // v = ld i1* addr
01823 //   =>
01824 // v1 = ld i8* addr (-> i16)
01825 // v = trunc i16 to i1
01826 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
01827   SDNode *Node = Op.getNode();
01828   LoadSDNode *LD = cast<LoadSDNode>(Node);
01829   SDLoc dl(Node);
01830   assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
01831   assert(Node->getValueType(0) == MVT::i1 &&
01832          "Custom lowering for i1 load only");
01833   SDValue newLD =
01834       DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
01835                   LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
01836                   LD->isInvariant(), LD->getAlignment());
01837   SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
01838   // The legalizer (the caller) is expecting two values from the legalized
01839   // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
01840   // in LegalizeDAG.cpp which also uses MergeValues.
01841   SDValue Ops[] = { result, LD->getChain() };
01842   return DAG.getMergeValues(Ops, dl);
01843 }
01844 
01845 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
01846   EVT ValVT = Op.getOperand(1).getValueType();
01847   if (ValVT == MVT::i1)
01848     return LowerSTOREi1(Op, DAG);
01849   else if (ValVT.isVector())
01850     return LowerSTOREVector(Op, DAG);
01851   else
01852     return SDValue();
01853 }
01854 
01855 SDValue
01856 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
01857   SDNode *N = Op.getNode();
01858   SDValue Val = N->getOperand(1);
01859   SDLoc DL(N);
01860   EVT ValVT = Val.getValueType();
01861 
01862   if (ValVT.isVector()) {
01863     // We only handle "native" vector sizes for now, e.g. <4 x double> is not
01864     // legal.  We can (and should) split that into 2 stores of <2 x double> here
01865     // but I'm leaving that as a TODO for now.
01866     if (!ValVT.isSimple())
01867       return SDValue();
01868     switch (ValVT.getSimpleVT().SimpleTy) {
01869     default:
01870       return SDValue();
01871     case MVT::v2i8:
01872     case MVT::v2i16:
01873     case MVT::v2i32:
01874     case MVT::v2i64:
01875     case MVT::v2f32:
01876     case MVT::v2f64:
01877     case MVT::v4i8:
01878     case MVT::v4i16:
01879     case MVT::v4i32:
01880     case MVT::v4f32:
01881       // This is a "native" vector type
01882       break;
01883     }
01884 
01885     MemSDNode *MemSD = cast<MemSDNode>(N);
01886     const DataLayout *TD = getDataLayout();
01887 
01888     unsigned Align = MemSD->getAlignment();
01889     unsigned PrefAlign =
01890       TD->getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
01891     if (Align < PrefAlign) {
01892       // This store is not sufficiently aligned, so bail out and let this vector
01893       // store be scalarized.  Note that we may still be able to emit smaller
01894       // vector stores.  For example, if we are storing a <4 x float> with an
01895       // alignment of 8, this check will fail but the legalizer will try again
01896       // with 2 x <2 x float>, which will succeed with an alignment of 8.
01897       return SDValue();
01898     }
01899 
01900     unsigned Opcode = 0;
01901     EVT EltVT = ValVT.getVectorElementType();
01902     unsigned NumElts = ValVT.getVectorNumElements();
01903 
01904     // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
01905     // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
01906     // stored type to i16 and propagate the "real" type as the memory type.
01907     bool NeedExt = false;
01908     if (EltVT.getSizeInBits() < 16)
01909       NeedExt = true;
01910 
01911     switch (NumElts) {
01912     default:
01913       return SDValue();
01914     case 2:
01915       Opcode = NVPTXISD::StoreV2;
01916       break;
01917     case 4: {
01918       Opcode = NVPTXISD::StoreV4;
01919       break;
01920     }
01921     }
01922 
01923     SmallVector<SDValue, 8> Ops;
01924 
01925     // First is the chain
01926     Ops.push_back(N->getOperand(0));
01927 
01928     // Then the split values
01929     for (unsigned i = 0; i < NumElts; ++i) {
01930       SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
01931                                    DAG.getIntPtrConstant(i));
01932       if (NeedExt)
01933         ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
01934       Ops.push_back(ExtVal);
01935     }
01936 
01937     // Then any remaining arguments
01938     for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
01939       Ops.push_back(N->getOperand(i));
01940     }
01941 
01942     SDValue NewSt = DAG.getMemIntrinsicNode(
01943         Opcode, DL, DAG.getVTList(MVT::Other), Ops,
01944         MemSD->getMemoryVT(), MemSD->getMemOperand());
01945 
01946     //return DCI.CombineTo(N, NewSt, true);
01947     return NewSt;
01948   }
01949 
01950   return SDValue();
01951 }
01952 
01953 // st i1 v, addr
01954 //    =>
01955 // v1 = zxt v to i16
01956 // st.u8 i16, addr
01957 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
01958   SDNode *Node = Op.getNode();
01959   SDLoc dl(Node);
01960   StoreSDNode *ST = cast<StoreSDNode>(Node);
01961   SDValue Tmp1 = ST->getChain();
01962   SDValue Tmp2 = ST->getBasePtr();
01963   SDValue Tmp3 = ST->getValue();
01964   assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
01965   unsigned Alignment = ST->getAlignment();
01966   bool isVolatile = ST->isVolatile();
01967   bool isNonTemporal = ST->isNonTemporal();
01968   Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
01969   SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
01970                                      ST->getPointerInfo(), MVT::i8, isNonTemporal,
01971                                      isVolatile, Alignment);
01972   return Result;
01973 }
01974 
01975 SDValue NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname,
01976                                         int idx, EVT v) const {
01977   std::string *name = nvTM->getManagedStrPool()->getManagedString(inname);
01978   std::stringstream suffix;
01979   suffix << idx;
01980   *name += suffix.str();
01981   return DAG.getTargetExternalSymbol(name->c_str(), v);
01982 }
01983 
01984 SDValue
01985 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
01986   std::string ParamSym;
01987   raw_string_ostream ParamStr(ParamSym);
01988 
01989   ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
01990   ParamStr.flush();
01991 
01992   std::string *SavedStr =
01993     nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
01994   return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
01995 }
01996 
01997 SDValue NVPTXTargetLowering::getParamHelpSymbol(SelectionDAG &DAG, int idx) {
01998   return getExtSymb(DAG, ".HLPPARAM", idx);
01999 }
02000 
02001 // Check to see if the kernel argument is image*_t or sampler_t
02002 
02003 bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
02004   static const char *const specialTypes[] = { "struct._image2d_t",
02005                                               "struct._image3d_t",
02006                                               "struct._sampler_t" };
02007 
02008   const Type *Ty = arg->getType();
02009   const PointerType *PTy = dyn_cast<PointerType>(Ty);
02010 
02011   if (!PTy)
02012     return false;
02013 
02014   if (!context)
02015     return false;
02016 
02017   const StructType *STy = dyn_cast<StructType>(PTy->getElementType());
02018   const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
02019 
02020   for (int i = 0, e = array_lengthof(specialTypes); i != e; ++i)
02021     if (TypeName == specialTypes[i])
02022       return true;
02023 
02024   return false;
02025 }
02026 
02027 SDValue NVPTXTargetLowering::LowerFormalArguments(
02028     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
02029     const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
02030     SmallVectorImpl<SDValue> &InVals) const {
02031   MachineFunction &MF = DAG.getMachineFunction();
02032   const DataLayout *TD = getDataLayout();
02033 
02034   const Function *F = MF.getFunction();
02035   const AttributeSet &PAL = F->getAttributes();
02036   const TargetLowering *TLI = DAG.getSubtarget().getTargetLowering();
02037 
02038   SDValue Root = DAG.getRoot();
02039   std::vector<SDValue> OutChains;
02040 
02041   bool isKernel = llvm::isKernelFunction(*F);
02042   bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
02043   assert(isABI && "Non-ABI compilation is not supported");
02044   if (!isABI)
02045     return Chain;
02046 
02047   std::vector<Type *> argTypes;
02048   std::vector<const Argument *> theArgs;
02049   for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
02050        I != E; ++I) {
02051     theArgs.push_back(I);
02052     argTypes.push_back(I->getType());
02053   }
02054   // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
02055   // Ins.size() will be larger
02056   //   * if there is an aggregate argument with multiple fields (each field
02057   //     showing up separately in Ins)
02058   //   * if there is a vector argument with more than typical vector-length
02059   //     elements (generally if more than 4) where each vector element is
02060   //     individually present in Ins.
02061   // So a different index should be used for indexing into Ins.
02062   // See similar issue in LowerCall.
02063   unsigned InsIdx = 0;
02064 
02065   int idx = 0;
02066   for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
02067     Type *Ty = argTypes[i];
02068 
02069     // If the kernel argument is image*_t or sampler_t, convert it to
02070     // a i32 constant holding the parameter position. This can later
02071     // matched in the AsmPrinter to output the correct mangled name.
02072     if (isImageOrSamplerVal(
02073             theArgs[i],
02074             (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
02075                                      : nullptr))) {
02076       assert(isKernel && "Only kernels can have image/sampler params");
02077       InVals.push_back(DAG.getConstant(i + 1, MVT::i32));
02078       continue;
02079     }
02080 
02081     if (theArgs[i]->use_empty()) {
02082       // argument is dead
02083       if (Ty->isAggregateType()) {
02084         SmallVector<EVT, 16> vtparts;
02085 
02086         ComputePTXValueVTs(*this, Ty, vtparts);
02087         assert(vtparts.size() > 0 && "empty aggregate type not expected");
02088         for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
02089              ++parti) {
02090           InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
02091           ++InsIdx;
02092         }
02093         if (vtparts.size() > 0)
02094           --InsIdx;
02095         continue;
02096       }
02097       if (Ty->isVectorTy()) {
02098         EVT ObjectVT = getValueType(Ty);
02099         unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
02100         for (unsigned parti = 0; parti < NumRegs; ++parti) {
02101           InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
02102           ++InsIdx;
02103         }
02104         if (NumRegs > 0)
02105           --InsIdx;
02106         continue;
02107       }
02108       InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
02109       continue;
02110     }
02111 
02112     // In the following cases, assign a node order of "idx+1"
02113     // to newly created nodes. The SDNodes for params have to
02114     // appear in the same order as their order of appearance
02115     // in the original function. "idx+1" holds that order.
02116     if (PAL.hasAttribute(i + 1, Attribute::ByVal) == false) {
02117       if (Ty->isAggregateType()) {
02118         SmallVector<EVT, 16> vtparts;
02119         SmallVector<uint64_t, 16> offsets;
02120 
02121         // NOTE: Here, we lose the ability to issue vector loads for vectors
02122         // that are a part of a struct.  This should be investigated in the
02123         // future.
02124         ComputePTXValueVTs(*this, Ty, vtparts, &offsets, 0);
02125         assert(vtparts.size() > 0 && "empty aggregate type not expected");
02126         bool aggregateIsPacked = false;
02127         if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
02128           aggregateIsPacked = STy->isPacked();
02129 
02130         SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
02131         for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
02132              ++parti) {
02133           EVT partVT = vtparts[parti];
02134           Value *srcValue = Constant::getNullValue(
02135               PointerType::get(partVT.getTypeForEVT(F->getContext()),
02136                                llvm::ADDRESS_SPACE_PARAM));
02137           SDValue srcAddr =
02138               DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
02139                           DAG.getConstant(offsets[parti], getPointerTy()));
02140           unsigned partAlign =
02141               aggregateIsPacked ? 1
02142                                 : TD->getABITypeAlignment(
02143                                       partVT.getTypeForEVT(F->getContext()));
02144           SDValue p;
02145           if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
02146             ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? 
02147                                      ISD::SEXTLOAD : ISD::ZEXTLOAD;
02148             p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
02149                                MachinePointerInfo(srcValue), partVT, false,
02150                                false, false, partAlign);
02151           } else {
02152             p = DAG.getLoad(partVT, dl, Root, srcAddr,
02153                             MachinePointerInfo(srcValue), false, false, false,
02154                             partAlign);
02155           }
02156           if (p.getNode())
02157             p.getNode()->setIROrder(idx + 1);
02158           InVals.push_back(p);
02159           ++InsIdx;
02160         }
02161         if (vtparts.size() > 0)
02162           --InsIdx;
02163         continue;
02164       }
02165       if (Ty->isVectorTy()) {
02166         EVT ObjectVT = getValueType(Ty);
02167         SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
02168         unsigned NumElts = ObjectVT.getVectorNumElements();
02169         assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
02170                "Vector was not scalarized");
02171         EVT EltVT = ObjectVT.getVectorElementType();
02172 
02173         // V1 load
02174         // f32 = load ...
02175         if (NumElts == 1) {
02176           // We only have one element, so just directly load it
02177           Value *SrcValue = Constant::getNullValue(PointerType::get(
02178               EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
02179           SDValue P = DAG.getLoad(
02180               EltVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false,
02181               false, true,
02182               TD->getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
02183           if (P.getNode())
02184             P.getNode()->setIROrder(idx + 1);
02185 
02186           if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
02187             P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
02188           InVals.push_back(P);
02189           ++InsIdx;
02190         } else if (NumElts == 2) {
02191           // V2 load
02192           // f32,f32 = load ...
02193           EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
02194           Value *SrcValue = Constant::getNullValue(PointerType::get(
02195               VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
02196           SDValue P = DAG.getLoad(
02197               VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false,
02198               false, true,
02199               TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
02200           if (P.getNode())
02201             P.getNode()->setIROrder(idx + 1);
02202 
02203           SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
02204                                      DAG.getIntPtrConstant(0));
02205           SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
02206                                      DAG.getIntPtrConstant(1));
02207 
02208           if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
02209             Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
02210             Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
02211           }
02212 
02213           InVals.push_back(Elt0);
02214           InVals.push_back(Elt1);
02215           InsIdx += 2;
02216         } else {
02217           // V4 loads
02218           // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
02219           // the
02220           // vector will be expanded to a power of 2 elements, so we know we can
02221           // always round up to the next multiple of 4 when creating the vector
02222           // loads.
02223           // e.g.  4 elem => 1 ld.v4
02224           //       6 elem => 2 ld.v4
02225           //       8 elem => 2 ld.v4
02226           //      11 elem => 3 ld.v4
02227           unsigned VecSize = 4;
02228           if (EltVT.getSizeInBits() == 64) {
02229             VecSize = 2;
02230           }
02231           EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
02232           unsigned Ofst = 0;
02233           for (unsigned i = 0; i < NumElts; i += VecSize) {
02234             Value *SrcValue = Constant::getNullValue(
02235                 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
02236                                  llvm::ADDRESS_SPACE_PARAM));
02237             SDValue SrcAddr =
02238                 DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
02239                             DAG.getConstant(Ofst, getPointerTy()));
02240             SDValue P = DAG.getLoad(
02241                 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
02242                 false, true,
02243                 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
02244             if (P.getNode())
02245               P.getNode()->setIROrder(idx + 1);
02246 
02247             for (unsigned j = 0; j < VecSize; ++j) {
02248               if (i + j >= NumElts)
02249                 break;
02250               SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
02251                                         DAG.getIntPtrConstant(j));
02252               if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
02253                 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
02254               InVals.push_back(Elt);
02255             }
02256             Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
02257           }
02258           InsIdx += NumElts;
02259         }
02260 
02261         if (NumElts > 0)
02262           --InsIdx;
02263         continue;
02264       }
02265       // A plain scalar.
02266       EVT ObjectVT = getValueType(Ty);
02267       // If ABI, load from the param symbol
02268       SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
02269       Value *srcValue = Constant::getNullValue(PointerType::get(
02270           ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
02271       SDValue p;
02272        if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
02273         ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? 
02274                                        ISD::SEXTLOAD : ISD::ZEXTLOAD;
02275         p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg,
02276                            MachinePointerInfo(srcValue), ObjectVT, false, false,
02277                            false,
02278         TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
02279       } else {
02280         p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg,
02281                         MachinePointerInfo(srcValue), false, false, false,
02282         TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
02283       }
02284       if (p.getNode())
02285         p.getNode()->setIROrder(idx + 1);
02286       InVals.push_back(p);
02287       continue;
02288     }
02289 
02290     // Param has ByVal attribute
02291     // Return MoveParam(param symbol).
02292     // Ideally, the param symbol can be returned directly,
02293     // but when SDNode builder decides to use it in a CopyToReg(),
02294     // machine instruction fails because TargetExternalSymbol
02295     // (not lowered) is target dependent, and CopyToReg assumes
02296     // the source is lowered.
02297     EVT ObjectVT = getValueType(Ty);
02298     assert(ObjectVT == Ins[InsIdx].VT &&
02299            "Ins type did not match function type");
02300     SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
02301     SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
02302     if (p.getNode())
02303       p.getNode()->setIROrder(idx + 1);
02304     if (isKernel)
02305       InVals.push_back(p);
02306     else {
02307       SDValue p2 = DAG.getNode(
02308           ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
02309           DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, MVT::i32), p);
02310       InVals.push_back(p2);
02311     }
02312   }
02313 
02314   // Clang will check explicit VarArg and issue error if any. However, Clang
02315   // will let code with
02316   // implicit var arg like f() pass. See bug 617733.
02317   // We treat this case as if the arg list is empty.
02318   // if (F.isVarArg()) {
02319   // assert(0 && "VarArg not supported yet!");
02320   //}
02321 
02322   if (!OutChains.empty())
02323     DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
02324 
02325   return Chain;
02326 }
02327 
02328 
02329 SDValue
02330 NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
02331                                  bool isVarArg,
02332                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
02333                                  const SmallVectorImpl<SDValue> &OutVals,
02334                                  SDLoc dl, SelectionDAG &DAG) const {
02335   MachineFunction &MF = DAG.getMachineFunction();
02336   const Function *F = MF.getFunction();
02337   Type *RetTy = F->getReturnType();
02338   const DataLayout *TD = getDataLayout();
02339 
02340   bool isABI = (nvptxSubtarget.getSmVersion() >= 20);
02341   assert(isABI && "Non-ABI compilation is not supported");
02342   if (!isABI)
02343     return Chain;
02344 
02345   if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
02346     // If we have a vector type, the OutVals array will be the scalarized
02347     // components and we have combine them into 1 or more vector stores.
02348     unsigned NumElts = VTy->getNumElements();
02349     assert(NumElts == Outs.size() && "Bad scalarization of return value");
02350 
02351     // const_cast can be removed in later LLVM versions
02352     EVT EltVT = getValueType(RetTy).getVectorElementType();
02353     bool NeedExtend = false;
02354     if (EltVT.getSizeInBits() < 16)
02355       NeedExtend = true;
02356 
02357     // V1 store
02358     if (NumElts == 1) {
02359       SDValue StoreVal = OutVals[0];
02360       // We only have one element, so just directly store it
02361       if (NeedExtend)
02362         StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
02363       SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal };
02364       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
02365                                       DAG.getVTList(MVT::Other), Ops,
02366                                       EltVT, MachinePointerInfo());
02367 
02368     } else if (NumElts == 2) {
02369       // V2 store
02370       SDValue StoreVal0 = OutVals[0];
02371       SDValue StoreVal1 = OutVals[1];
02372 
02373       if (NeedExtend) {
02374         StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
02375         StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
02376       }
02377 
02378       SDValue Ops[] = { Chain, DAG.getConstant(0, MVT::i32), StoreVal0,
02379                         StoreVal1 };
02380       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
02381                                       DAG.getVTList(MVT::Other), Ops,
02382                                       EltVT, MachinePointerInfo());
02383     } else {
02384       // V4 stores
02385       // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
02386       // vector will be expanded to a power of 2 elements, so we know we can
02387       // always round up to the next multiple of 4 when creating the vector
02388       // stores.
02389       // e.g.  4 elem => 1 st.v4
02390       //       6 elem => 2 st.v4
02391       //       8 elem => 2 st.v4
02392       //      11 elem => 3 st.v4
02393 
02394       unsigned VecSize = 4;
02395       if (OutVals[0].getValueType().getSizeInBits() == 64)
02396         VecSize = 2;
02397 
02398       unsigned Offset = 0;
02399 
02400       EVT VecVT =
02401           EVT::getVectorVT(F->getContext(), EltVT, VecSize);
02402       unsigned PerStoreOffset =
02403           TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
02404 
02405       for (unsigned i = 0; i < NumElts; i += VecSize) {
02406         // Get values
02407         SDValue StoreVal;
02408         SmallVector<SDValue, 8> Ops;
02409         Ops.push_back(Chain);
02410         Ops.push_back(DAG.getConstant(Offset, MVT::i32));
02411         unsigned Opc = NVPTXISD::StoreRetvalV2;
02412         EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
02413 
02414         StoreVal = OutVals[i];
02415         if (NeedExtend)
02416           StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
02417         Ops.push_back(StoreVal);
02418 
02419         if (i + 1 < NumElts) {
02420           StoreVal = OutVals[i + 1];
02421           if (NeedExtend)
02422             StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
02423         } else {
02424           StoreVal = DAG.getUNDEF(ExtendedVT);
02425         }
02426         Ops.push_back(StoreVal);
02427 
02428         if (VecSize == 4) {
02429           Opc = NVPTXISD::StoreRetvalV4;
02430           if (i + 2 < NumElts) {
02431             StoreVal = OutVals[i + 2];
02432             if (NeedExtend)
02433               StoreVal =
02434                   DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
02435           } else {
02436             StoreVal = DAG.getUNDEF(ExtendedVT);
02437           }
02438           Ops.push_back(StoreVal);
02439 
02440           if (i + 3 < NumElts) {
02441             StoreVal = OutVals[i + 3];
02442             if (NeedExtend)
02443               StoreVal =
02444                   DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
02445           } else {
02446             StoreVal = DAG.getUNDEF(ExtendedVT);
02447           }
02448           Ops.push_back(StoreVal);
02449         }
02450 
02451         // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
02452         Chain =
02453             DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
02454                                     EltVT, MachinePointerInfo());
02455         Offset += PerStoreOffset;
02456       }
02457     }
02458   } else {
02459     SmallVector<EVT, 16> ValVTs;
02460     SmallVector<uint64_t, 16> Offsets;
02461     ComputePTXValueVTs(*this, RetTy, ValVTs, &Offsets, 0);
02462     assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
02463 
02464     for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
02465       SDValue theVal = OutVals[i];
02466       EVT TheValType = theVal.getValueType();
02467       unsigned numElems = 1;
02468       if (TheValType.isVector())
02469         numElems = TheValType.getVectorNumElements();
02470       for (unsigned j = 0, je = numElems; j != je; ++j) {
02471         SDValue TmpVal = theVal;
02472         if (TheValType.isVector())
02473           TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
02474                                TheValType.getVectorElementType(), TmpVal,
02475                                DAG.getIntPtrConstant(j));
02476         EVT TheStoreType = ValVTs[i];
02477         if (RetTy->isIntegerTy() &&
02478             TD->getTypeAllocSizeInBits(RetTy) < 32) {
02479           // The following zero-extension is for integer types only, and
02480           // specifically not for aggregates.
02481           TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
02482           TheStoreType = MVT::i32;
02483         }
02484         else if (TmpVal.getValueType().getSizeInBits() < 16)
02485           TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
02486 
02487         SDValue Ops[] = {
02488           Chain,
02489           DAG.getConstant(Offsets[i], MVT::i32),
02490           TmpVal };
02491         Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
02492                                         DAG.getVTList(MVT::Other), Ops,
02493                                         TheStoreType,
02494                                         MachinePointerInfo());
02495       }
02496     }
02497   }
02498 
02499   return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
02500 }
02501 
02502 
02503 void NVPTXTargetLowering::LowerAsmOperandForConstraint(
02504     SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
02505     SelectionDAG &DAG) const {
02506   if (Constraint.length() > 1)
02507     return;
02508   else
02509     TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
02510 }
02511 
02512 // NVPTX suuport vector of legal types of any length in Intrinsics because the
02513 // NVPTX specific type legalizer
02514 // will legalize them to the PTX supported length.
02515 bool NVPTXTargetLowering::isTypeSupportedInIntrinsic(MVT VT) const {
02516   if (isTypeLegal(VT))
02517     return true;
02518   if (VT.isVector()) {
02519     MVT eVT = VT.getVectorElementType();
02520     if (isTypeLegal(eVT))
02521       return true;
02522   }
02523   return false;
02524 }
02525 
02526 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
02527   switch (Intrinsic) {
02528   default:
02529     return 0;
02530 
02531   case Intrinsic::nvvm_tex_1d_v4f32_s32:
02532     return NVPTXISD::Tex1DFloatS32;
02533   case Intrinsic::nvvm_tex_1d_v4f32_f32:
02534     return NVPTXISD::Tex1DFloatFloat;
02535   case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
02536     return NVPTXISD::Tex1DFloatFloatLevel;
02537   case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
02538     return NVPTXISD::Tex1DFloatFloatGrad;
02539   case Intrinsic::nvvm_tex_1d_v4s32_s32:
02540     return NVPTXISD::Tex1DS32S32;
02541   case Intrinsic::nvvm_tex_1d_v4s32_f32:
02542     return NVPTXISD::Tex1DS32Float;
02543   case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
02544     return NVPTXISD::Tex1DS32FloatLevel;
02545   case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
02546     return NVPTXISD::Tex1DS32FloatGrad;
02547   case Intrinsic::nvvm_tex_1d_v4u32_s32:
02548     return NVPTXISD::Tex1DU32S32;
02549   case Intrinsic::nvvm_tex_1d_v4u32_f32:
02550     return NVPTXISD::Tex1DU32Float;
02551   case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
02552     return NVPTXISD::Tex1DU32FloatLevel;
02553   case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
02554     return NVPTXISD::Tex1DU32FloatGrad;
02555 
02556   case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
02557     return NVPTXISD::Tex1DArrayFloatS32;
02558   case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
02559     return NVPTXISD::Tex1DArrayFloatFloat;
02560   case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
02561     return NVPTXISD::Tex1DArrayFloatFloatLevel;
02562   case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
02563     return NVPTXISD::Tex1DArrayFloatFloatGrad;
02564   case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
02565     return NVPTXISD::Tex1DArrayS32S32;
02566   case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
02567     return NVPTXISD::Tex1DArrayS32Float;
02568   case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
02569     return NVPTXISD::Tex1DArrayS32FloatLevel;
02570   case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
02571     return NVPTXISD::Tex1DArrayS32FloatGrad;
02572   case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
02573     return NVPTXISD::Tex1DArrayU32S32;
02574   case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
02575     return NVPTXISD::Tex1DArrayU32Float;
02576   case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
02577     return NVPTXISD::Tex1DArrayU32FloatLevel;
02578   case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
02579     return NVPTXISD::Tex1DArrayU32FloatGrad;
02580 
02581   case Intrinsic::nvvm_tex_2d_v4f32_s32:
02582     return NVPTXISD::Tex2DFloatS32;
02583   case Intrinsic::nvvm_tex_2d_v4f32_f32:
02584     return NVPTXISD::Tex2DFloatFloat;
02585   case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
02586     return NVPTXISD::Tex2DFloatFloatLevel;
02587   case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
02588     return NVPTXISD::Tex2DFloatFloatGrad;
02589   case Intrinsic::nvvm_tex_2d_v4s32_s32:
02590     return NVPTXISD::Tex2DS32S32;
02591   case Intrinsic::nvvm_tex_2d_v4s32_f32:
02592     return NVPTXISD::Tex2DS32Float;
02593   case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
02594     return NVPTXISD::Tex2DS32FloatLevel;
02595   case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
02596     return NVPTXISD::Tex2DS32FloatGrad;
02597   case Intrinsic::nvvm_tex_2d_v4u32_s32:
02598     return NVPTXISD::Tex2DU32S32;
02599   case Intrinsic::nvvm_tex_2d_v4u32_f32:
02600     return NVPTXISD::Tex2DU32Float;
02601   case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
02602     return NVPTXISD::Tex2DU32FloatLevel;
02603   case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
02604     return NVPTXISD::Tex2DU32FloatGrad;
02605 
02606   case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
02607     return NVPTXISD::Tex2DArrayFloatS32;
02608   case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
02609     return NVPTXISD::Tex2DArrayFloatFloat;
02610   case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
02611     return NVPTXISD::Tex2DArrayFloatFloatLevel;
02612   case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
02613     return NVPTXISD::Tex2DArrayFloatFloatGrad;
02614   case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
02615     return NVPTXISD::Tex2DArrayS32S32;
02616   case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
02617     return NVPTXISD::Tex2DArrayS32Float;
02618   case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
02619     return NVPTXISD::Tex2DArrayS32FloatLevel;
02620   case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
02621     return NVPTXISD::Tex2DArrayS32FloatGrad;
02622   case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
02623     return NVPTXISD::Tex2DArrayU32S32;
02624   case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
02625     return NVPTXISD::Tex2DArrayU32Float;
02626   case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
02627     return NVPTXISD::Tex2DArrayU32FloatLevel;
02628   case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
02629     return NVPTXISD::Tex2DArrayU32FloatGrad;
02630 
02631   case Intrinsic::nvvm_tex_3d_v4f32_s32:
02632     return NVPTXISD::Tex3DFloatS32;
02633   case Intrinsic::nvvm_tex_3d_v4f32_f32:
02634     return NVPTXISD::Tex3DFloatFloat;
02635   case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
02636     return NVPTXISD::Tex3DFloatFloatLevel;
02637   case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
02638     return NVPTXISD::Tex3DFloatFloatGrad;
02639   case Intrinsic::nvvm_tex_3d_v4s32_s32:
02640     return NVPTXISD::Tex3DS32S32;
02641   case Intrinsic::nvvm_tex_3d_v4s32_f32:
02642     return NVPTXISD::Tex3DS32Float;
02643   case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
02644     return NVPTXISD::Tex3DS32FloatLevel;
02645   case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
02646     return NVPTXISD::Tex3DS32FloatGrad;
02647   case Intrinsic::nvvm_tex_3d_v4u32_s32:
02648     return NVPTXISD::Tex3DU32S32;
02649   case Intrinsic::nvvm_tex_3d_v4u32_f32:
02650     return NVPTXISD::Tex3DU32Float;
02651   case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
02652     return NVPTXISD::Tex3DU32FloatLevel;
02653   case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
02654     return NVPTXISD::Tex3DU32FloatGrad;
02655 
02656   case Intrinsic::nvvm_tex_cube_v4f32_f32:
02657     return NVPTXISD::TexCubeFloatFloat;
02658   case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
02659     return NVPTXISD::TexCubeFloatFloatLevel;
02660   case Intrinsic::nvvm_tex_cube_v4s32_f32:
02661     return NVPTXISD::TexCubeS32Float;
02662   case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
02663     return NVPTXISD::TexCubeS32FloatLevel;
02664   case Intrinsic::nvvm_tex_cube_v4u32_f32:
02665     return NVPTXISD::TexCubeU32Float;
02666   case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
02667     return NVPTXISD::TexCubeU32FloatLevel;
02668 
02669   case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
02670     return NVPTXISD::TexCubeArrayFloatFloat;
02671   case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
02672     return NVPTXISD::TexCubeArrayFloatFloatLevel;
02673   case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
02674     return NVPTXISD::TexCubeArrayS32Float;
02675   case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
02676     return NVPTXISD::TexCubeArrayS32FloatLevel;
02677   case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
02678     return NVPTXISD::TexCubeArrayU32Float;
02679   case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
02680     return NVPTXISD::TexCubeArrayU32FloatLevel;
02681 
02682   case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
02683     return NVPTXISD::Tld4R2DFloatFloat;
02684   case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
02685     return NVPTXISD::Tld4G2DFloatFloat;
02686   case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
02687     return NVPTXISD::Tld4B2DFloatFloat;
02688   case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
02689     return NVPTXISD::Tld4A2DFloatFloat;
02690   case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
02691     return NVPTXISD::Tld4R2DS64Float;
02692   case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
02693     return NVPTXISD::Tld4G2DS64Float;
02694   case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
02695     return NVPTXISD::Tld4B2DS64Float;
02696   case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
02697     return NVPTXISD::Tld4A2DS64Float;
02698   case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
02699     return NVPTXISD::Tld4R2DU64Float;
02700   case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
02701     return NVPTXISD::Tld4G2DU64Float;
02702   case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
02703     return NVPTXISD::Tld4B2DU64Float;
02704   case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
02705     return NVPTXISD::Tld4A2DU64Float;
02706 
02707   case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
02708     return NVPTXISD::TexUnified1DFloatS32;
02709   case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
02710     return NVPTXISD::TexUnified1DFloatFloat;
02711   case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
02712     return NVPTXISD::TexUnified1DFloatFloatLevel;
02713   case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
02714     return NVPTXISD::TexUnified1DFloatFloatGrad;
02715   case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
02716     return NVPTXISD::TexUnified1DS32S32;
02717   case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
02718     return NVPTXISD::TexUnified1DS32Float;
02719   case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
02720     return NVPTXISD::TexUnified1DS32FloatLevel;
02721   case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
02722     return NVPTXISD::TexUnified1DS32FloatGrad;
02723   case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
02724     return NVPTXISD::TexUnified1DU32S32;
02725   case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
02726     return NVPTXISD::TexUnified1DU32Float;
02727   case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
02728     return NVPTXISD::TexUnified1DU32FloatLevel;
02729   case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
02730     return NVPTXISD::TexUnified1DU32FloatGrad;
02731 
02732   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
02733     return NVPTXISD::TexUnified1DArrayFloatS32;
02734   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
02735     return NVPTXISD::TexUnified1DArrayFloatFloat;
02736   case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
02737     return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
02738   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
02739     return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
02740   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
02741     return NVPTXISD::TexUnified1DArrayS32S32;
02742   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
02743     return NVPTXISD::TexUnified1DArrayS32Float;
02744   case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
02745     return NVPTXISD::TexUnified1DArrayS32FloatLevel;
02746   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
02747     return NVPTXISD::TexUnified1DArrayS32FloatGrad;
02748   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
02749     return NVPTXISD::TexUnified1DArrayU32S32;
02750   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
02751     return NVPTXISD::TexUnified1DArrayU32Float;
02752   case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
02753     return NVPTXISD::TexUnified1DArrayU32FloatLevel;
02754   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
02755     return NVPTXISD::TexUnified1DArrayU32FloatGrad;
02756 
02757   case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
02758     return NVPTXISD::TexUnified2DFloatS32;
02759   case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
02760     return NVPTXISD::TexUnified2DFloatFloat;
02761   case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
02762     return NVPTXISD::TexUnified2DFloatFloatLevel;
02763   case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
02764     return NVPTXISD::TexUnified2DFloatFloatGrad;
02765   case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
02766     return NVPTXISD::TexUnified2DS32S32;
02767   case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
02768     return NVPTXISD::TexUnified2DS32Float;
02769   case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
02770     return NVPTXISD::TexUnified2DS32FloatLevel;
02771   case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
02772     return NVPTXISD::TexUnified2DS32FloatGrad;
02773   case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
02774     return NVPTXISD::TexUnified2DU32S32;
02775   case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
02776     return NVPTXISD::TexUnified2DU32Float;
02777   case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
02778     return NVPTXISD::TexUnified2DU32FloatLevel;
02779   case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
02780     return NVPTXISD::TexUnified2DU32FloatGrad;
02781 
02782   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
02783     return NVPTXISD::TexUnified2DArrayFloatS32;
02784   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
02785     return NVPTXISD::TexUnified2DArrayFloatFloat;
02786   case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
02787     return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
02788   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
02789     return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
02790   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
02791     return NVPTXISD::TexUnified2DArrayS32S32;
02792   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
02793     return NVPTXISD::TexUnified2DArrayS32Float;
02794   case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
02795     return NVPTXISD::TexUnified2DArrayS32FloatLevel;
02796   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
02797     return NVPTXISD::TexUnified2DArrayS32FloatGrad;
02798   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
02799     return NVPTXISD::TexUnified2DArrayU32S32;
02800   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
02801     return NVPTXISD::TexUnified2DArrayU32Float;
02802   case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
02803     return NVPTXISD::TexUnified2DArrayU32FloatLevel;
02804   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
02805     return NVPTXISD::TexUnified2DArrayU32FloatGrad;
02806 
02807   case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
02808     return NVPTXISD::TexUnified3DFloatS32;
02809   case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
02810     return NVPTXISD::TexUnified3DFloatFloat;
02811   case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
02812     return NVPTXISD::TexUnified3DFloatFloatLevel;
02813   case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
02814     return NVPTXISD::TexUnified3DFloatFloatGrad;
02815   case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
02816     return NVPTXISD::TexUnified3DS32S32;
02817   case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
02818     return NVPTXISD::TexUnified3DS32Float;
02819   case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
02820     return NVPTXISD::TexUnified3DS32FloatLevel;
02821   case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
02822     return NVPTXISD::TexUnified3DS32FloatGrad;
02823   case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
02824     return NVPTXISD::TexUnified3DU32S32;
02825   case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
02826     return NVPTXISD::TexUnified3DU32Float;
02827   case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
02828     return NVPTXISD::TexUnified3DU32FloatLevel;
02829   case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
02830     return NVPTXISD::TexUnified3DU32FloatGrad;
02831 
02832   case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
02833     return NVPTXISD::TexUnifiedCubeFloatFloat;
02834   case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
02835     return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
02836   case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
02837     return NVPTXISD::TexUnifiedCubeS32Float;
02838   case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
02839     return NVPTXISD::TexUnifiedCubeS32FloatLevel;
02840   case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
02841     return NVPTXISD::TexUnifiedCubeU32Float;
02842   case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
02843     return NVPTXISD::TexUnifiedCubeU32FloatLevel;
02844 
02845   case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
02846     return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
02847   case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
02848     return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
02849   case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
02850     return NVPTXISD::TexUnifiedCubeArrayS32Float;
02851   case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
02852     return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
02853   case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
02854     return NVPTXISD::TexUnifiedCubeArrayU32Float;
02855   case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
02856     return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
02857 
02858   case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
02859     return NVPTXISD::Tld4UnifiedR2DFloatFloat;
02860   case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
02861     return NVPTXISD::Tld4UnifiedG2DFloatFloat;
02862   case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
02863     return NVPTXISD::Tld4UnifiedB2DFloatFloat;
02864   case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
02865     return NVPTXISD::Tld4UnifiedA2DFloatFloat;
02866   case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
02867     return NVPTXISD::Tld4UnifiedR2DS64Float;
02868   case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
02869     return NVPTXISD::Tld4UnifiedG2DS64Float;
02870   case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
02871     return NVPTXISD::Tld4UnifiedB2DS64Float;
02872   case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
02873     return NVPTXISD::Tld4UnifiedA2DS64Float;
02874   case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
02875     return NVPTXISD::Tld4UnifiedR2DU64Float;
02876   case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
02877     return NVPTXISD::Tld4UnifiedG2DU64Float;
02878   case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
02879     return NVPTXISD::Tld4UnifiedB2DU64Float;
02880   case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
02881     return NVPTXISD::Tld4UnifiedA2DU64Float;
02882   }
02883 }
02884 
02885 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
02886   switch (Intrinsic) {
02887   default:
02888     return 0;
02889   case Intrinsic::nvvm_suld_1d_i8_clamp:
02890     return NVPTXISD::Suld1DI8Clamp;
02891   case Intrinsic::nvvm_suld_1d_i16_clamp:
02892     return NVPTXISD::Suld1DI16Clamp;
02893   case Intrinsic::nvvm_suld_1d_i32_clamp:
02894     return NVPTXISD::Suld1DI32Clamp;
02895   case Intrinsic::nvvm_suld_1d_i64_clamp:
02896     return NVPTXISD::Suld1DI64Clamp;
02897   case Intrinsic::nvvm_suld_1d_v2i8_clamp:
02898     return NVPTXISD::Suld1DV2I8Clamp;
02899   case Intrinsic::nvvm_suld_1d_v2i16_clamp:
02900     return NVPTXISD::Suld1DV2I16Clamp;
02901   case Intrinsic::nvvm_suld_1d_v2i32_clamp:
02902     return NVPTXISD::Suld1DV2I32Clamp;
02903   case Intrinsic::nvvm_suld_1d_v2i64_clamp:
02904     return NVPTXISD::Suld1DV2I64Clamp;
02905   case Intrinsic::nvvm_suld_1d_v4i8_clamp:
02906     return NVPTXISD::Suld1DV4I8Clamp;
02907   case Intrinsic::nvvm_suld_1d_v4i16_clamp:
02908     return NVPTXISD::Suld1DV4I16Clamp;
02909   case Intrinsic::nvvm_suld_1d_v4i32_clamp:
02910     return NVPTXISD::Suld1DV4I32Clamp;
02911   case Intrinsic::nvvm_suld_1d_array_i8_clamp:
02912     return NVPTXISD::Suld1DArrayI8Clamp;
02913   case Intrinsic::nvvm_suld_1d_array_i16_clamp:
02914     return NVPTXISD::Suld1DArrayI16Clamp;
02915   case Intrinsic::nvvm_suld_1d_array_i32_clamp:
02916     return NVPTXISD::Suld1DArrayI32Clamp;
02917   case Intrinsic::nvvm_suld_1d_array_i64_clamp:
02918     return NVPTXISD::Suld1DArrayI64Clamp;
02919   case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
02920     return NVPTXISD::Suld1DArrayV2I8Clamp;
02921   case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
02922     return NVPTXISD::Suld1DArrayV2I16Clamp;
02923   case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
02924     return NVPTXISD::Suld1DArrayV2I32Clamp;
02925   case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
02926     return NVPTXISD::Suld1DArrayV2I64Clamp;
02927   case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
02928     return NVPTXISD::Suld1DArrayV4I8Clamp;
02929   case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
02930     return NVPTXISD::Suld1DArrayV4I16Clamp;
02931   case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
02932     return NVPTXISD::Suld1DArrayV4I32Clamp;
02933   case Intrinsic::nvvm_suld_2d_i8_clamp:
02934     return NVPTXISD::Suld2DI8Clamp;
02935   case Intrinsic::nvvm_suld_2d_i16_clamp:
02936     return NVPTXISD::Suld2DI16Clamp;
02937   case Intrinsic::nvvm_suld_2d_i32_clamp:
02938     return NVPTXISD::Suld2DI32Clamp;
02939   case Intrinsic::nvvm_suld_2d_i64_clamp:
02940     return NVPTXISD::Suld2DI64Clamp;
02941   case Intrinsic::nvvm_suld_2d_v2i8_clamp:
02942     return NVPTXISD::Suld2DV2I8Clamp;
02943   case Intrinsic::nvvm_suld_2d_v2i16_clamp:
02944     return NVPTXISD::Suld2DV2I16Clamp;
02945   case Intrinsic::nvvm_suld_2d_v2i32_clamp:
02946     return NVPTXISD::Suld2DV2I32Clamp;
02947   case Intrinsic::nvvm_suld_2d_v2i64_clamp:
02948     return NVPTXISD::Suld2DV2I64Clamp;
02949   case Intrinsic::nvvm_suld_2d_v4i8_clamp:
02950     return NVPTXISD::Suld2DV4I8Clamp;
02951   case Intrinsic::nvvm_suld_2d_v4i16_clamp:
02952     return NVPTXISD::Suld2DV4I16Clamp;
02953   case Intrinsic::nvvm_suld_2d_v4i32_clamp:
02954     return NVPTXISD::Suld2DV4I32Clamp;
02955   case Intrinsic::nvvm_suld_2d_array_i8_clamp:
02956     return NVPTXISD::Suld2DArrayI8Clamp;
02957   case Intrinsic::nvvm_suld_2d_array_i16_clamp:
02958     return NVPTXISD::Suld2DArrayI16Clamp;
02959   case Intrinsic::nvvm_suld_2d_array_i32_clamp:
02960     return NVPTXISD::Suld2DArrayI32Clamp;
02961   case Intrinsic::nvvm_suld_2d_array_i64_clamp:
02962     return NVPTXISD::Suld2DArrayI64Clamp;
02963   case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
02964     return NVPTXISD::Suld2DArrayV2I8Clamp;
02965   case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
02966     return NVPTXISD::Suld2DArrayV2I16Clamp;
02967   case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
02968     return NVPTXISD::Suld2DArrayV2I32Clamp;
02969   case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
02970     return NVPTXISD::Suld2DArrayV2I64Clamp;
02971   case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
02972     return NVPTXISD::Suld2DArrayV4I8Clamp;
02973   case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
02974     return NVPTXISD::Suld2DArrayV4I16Clamp;
02975   case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
02976     return NVPTXISD::Suld2DArrayV4I32Clamp;
02977   case Intrinsic::nvvm_suld_3d_i8_clamp:
02978     return NVPTXISD::Suld3DI8Clamp;
02979   case Intrinsic::nvvm_suld_3d_i16_clamp:
02980     return NVPTXISD::Suld3DI16Clamp;
02981   case Intrinsic::nvvm_suld_3d_i32_clamp:
02982     return NVPTXISD::Suld3DI32Clamp;
02983   case Intrinsic::nvvm_suld_3d_i64_clamp:
02984     return NVPTXISD::Suld3DI64Clamp;
02985   case Intrinsic::nvvm_suld_3d_v2i8_clamp:
02986     return NVPTXISD::Suld3DV2I8Clamp;
02987   case Intrinsic::nvvm_suld_3d_v2i16_clamp:
02988     return NVPTXISD::Suld3DV2I16Clamp;
02989   case Intrinsic::nvvm_suld_3d_v2i32_clamp:
02990     return NVPTXISD::Suld3DV2I32Clamp;
02991   case Intrinsic::nvvm_suld_3d_v2i64_clamp:
02992     return NVPTXISD::Suld3DV2I64Clamp;
02993   case Intrinsic::nvvm_suld_3d_v4i8_clamp:
02994     return NVPTXISD::Suld3DV4I8Clamp;
02995   case Intrinsic::nvvm_suld_3d_v4i16_clamp:
02996     return NVPTXISD::Suld3DV4I16Clamp;
02997   case Intrinsic::nvvm_suld_3d_v4i32_clamp:
02998     return NVPTXISD::Suld3DV4I32Clamp;
02999   case Intrinsic::nvvm_suld_1d_i8_trap:
03000     return NVPTXISD::Suld1DI8Trap;
03001   case Intrinsic::nvvm_suld_1d_i16_trap:
03002     return NVPTXISD::Suld1DI16Trap;
03003   case Intrinsic::nvvm_suld_1d_i32_trap:
03004     return NVPTXISD::Suld1DI32Trap;
03005   case Intrinsic::nvvm_suld_1d_i64_trap:
03006     return NVPTXISD::Suld1DI64Trap;
03007   case Intrinsic::nvvm_suld_1d_v2i8_trap:
03008     return NVPTXISD::Suld1DV2I8Trap;
03009   case Intrinsic::nvvm_suld_1d_v2i16_trap:
03010     return NVPTXISD::Suld1DV2I16Trap;
03011   case Intrinsic::nvvm_suld_1d_v2i32_trap:
03012     return NVPTXISD::Suld1DV2I32Trap;
03013   case Intrinsic::nvvm_suld_1d_v2i64_trap:
03014     return NVPTXISD::Suld1DV2I64Trap;
03015   case Intrinsic::nvvm_suld_1d_v4i8_trap:
03016     return NVPTXISD::Suld1DV4I8Trap;
03017   case Intrinsic::nvvm_suld_1d_v4i16_trap:
03018     return NVPTXISD::Suld1DV4I16Trap;
03019   case Intrinsic::nvvm_suld_1d_v4i32_trap:
03020     return NVPTXISD::Suld1DV4I32Trap;
03021   case Intrinsic::nvvm_suld_1d_array_i8_trap:
03022     return NVPTXISD::Suld1DArrayI8Trap;
03023   case Intrinsic::nvvm_suld_1d_array_i16_trap:
03024     return NVPTXISD::Suld1DArrayI16Trap;
03025   case Intrinsic::nvvm_suld_1d_array_i32_trap:
03026     return NVPTXISD::Suld1DArrayI32Trap;
03027   case Intrinsic::nvvm_suld_1d_array_i64_trap:
03028     return NVPTXISD::Suld1DArrayI64Trap;
03029   case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
03030     return NVPTXISD::Suld1DArrayV2I8Trap;
03031   case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
03032     return NVPTXISD::Suld1DArrayV2I16Trap;
03033   case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
03034     return NVPTXISD::Suld1DArrayV2I32Trap;
03035   case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
03036     return NVPTXISD::Suld1DArrayV2I64Trap;
03037   case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
03038     return NVPTXISD::Suld1DArrayV4I8Trap;
03039   case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
03040     return NVPTXISD::Suld1DArrayV4I16Trap;
03041   case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
03042     return NVPTXISD::Suld1DArrayV4I32Trap;
03043   case Intrinsic::nvvm_suld_2d_i8_trap:
03044     return NVPTXISD::Suld2DI8Trap;
03045   case Intrinsic::nvvm_suld_2d_i16_trap:
03046     return NVPTXISD::Suld2DI16Trap;
03047   case Intrinsic::nvvm_suld_2d_i32_trap:
03048     return NVPTXISD::Suld2DI32Trap;
03049   case Intrinsic::nvvm_suld_2d_i64_trap:
03050     return NVPTXISD::Suld2DI64Trap;
03051   case Intrinsic::nvvm_suld_2d_v2i8_trap:
03052     return NVPTXISD::Suld2DV2I8Trap;
03053   case Intrinsic::nvvm_suld_2d_v2i16_trap:
03054     return NVPTXISD::Suld2DV2I16Trap;
03055   case Intrinsic::nvvm_suld_2d_v2i32_trap:
03056     return NVPTXISD::Suld2DV2I32Trap;
03057   case Intrinsic::nvvm_suld_2d_v2i64_trap:
03058     return NVPTXISD::Suld2DV2I64Trap;
03059   case Intrinsic::nvvm_suld_2d_v4i8_trap:
03060     return NVPTXISD::Suld2DV4I8Trap;
03061   case Intrinsic::nvvm_suld_2d_v4i16_trap:
03062     return NVPTXISD::Suld2DV4I16Trap;
03063   case Intrinsic::nvvm_suld_2d_v4i32_trap:
03064     return NVPTXISD::Suld2DV4I32Trap;
03065   case Intrinsic::nvvm_suld_2d_array_i8_trap:
03066     return NVPTXISD::Suld2DArrayI8Trap;
03067   case Intrinsic::nvvm_suld_2d_array_i16_trap:
03068     return NVPTXISD::Suld2DArrayI16Trap;
03069   case Intrinsic::nvvm_suld_2d_array_i32_trap:
03070     return NVPTXISD::Suld2DArrayI32Trap;
03071   case Intrinsic::nvvm_suld_2d_array_i64_trap:
03072     return NVPTXISD::Suld2DArrayI64Trap;
03073   case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
03074     return NVPTXISD::Suld2DArrayV2I8Trap;
03075   case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
03076     return NVPTXISD::Suld2DArrayV2I16Trap;
03077   case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
03078     return NVPTXISD::Suld2DArrayV2I32Trap;
03079   case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
03080     return NVPTXISD::Suld2DArrayV2I64Trap;
03081   case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
03082     return NVPTXISD::Suld2DArrayV4I8Trap;
03083   case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
03084     return NVPTXISD::Suld2DArrayV4I16Trap;
03085   case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
03086     return NVPTXISD::Suld2DArrayV4I32Trap;
03087   case Intrinsic::nvvm_suld_3d_i8_trap:
03088     return NVPTXISD::Suld3DI8Trap;
03089   case Intrinsic::nvvm_suld_3d_i16_trap:
03090     return NVPTXISD::Suld3DI16Trap;
03091   case Intrinsic::nvvm_suld_3d_i32_trap:
03092     return NVPTXISD::Suld3DI32Trap;
03093   case Intrinsic::nvvm_suld_3d_i64_trap:
03094     return NVPTXISD::Suld3DI64Trap;
03095   case Intrinsic::nvvm_suld_3d_v2i8_trap:
03096     return NVPTXISD::Suld3DV2I8Trap;
03097   case Intrinsic::nvvm_suld_3d_v2i16_trap:
03098     return NVPTXISD::Suld3DV2I16Trap;
03099   case Intrinsic::nvvm_suld_3d_v2i32_trap:
03100     return NVPTXISD::Suld3DV2I32Trap;
03101   case Intrinsic::nvvm_suld_3d_v2i64_trap:
03102     return NVPTXISD::Suld3DV2I64Trap;
03103   case Intrinsic::nvvm_suld_3d_v4i8_trap:
03104     return NVPTXISD::Suld3DV4I8Trap;
03105   case Intrinsic::nvvm_suld_3d_v4i16_trap:
03106     return NVPTXISD::Suld3DV4I16Trap;
03107   case Intrinsic::nvvm_suld_3d_v4i32_trap:
03108     return NVPTXISD::Suld3DV4I32Trap;
03109   case Intrinsic::nvvm_suld_1d_i8_zero:
03110     return NVPTXISD::Suld1DI8Zero;
03111   case Intrinsic::nvvm_suld_1d_i16_zero:
03112     return NVPTXISD::Suld1DI16Zero;
03113   case Intrinsic::nvvm_suld_1d_i32_zero:
03114     return NVPTXISD::Suld1DI32Zero;
03115   case Intrinsic::nvvm_suld_1d_i64_zero:
03116     return NVPTXISD::Suld1DI64Zero;
03117   case Intrinsic::nvvm_suld_1d_v2i8_zero:
03118     return NVPTXISD::Suld1DV2I8Zero;
03119   case Intrinsic::nvvm_suld_1d_v2i16_zero:
03120     return NVPTXISD::Suld1DV2I16Zero;
03121   case Intrinsic::nvvm_suld_1d_v2i32_zero:
03122     return NVPTXISD::Suld1DV2I32Zero;
03123   case Intrinsic::nvvm_suld_1d_v2i64_zero:
03124     return NVPTXISD::Suld1DV2I64Zero;
03125   case Intrinsic::nvvm_suld_1d_v4i8_zero:
03126     return NVPTXISD::Suld1DV4I8Zero;
03127   case Intrinsic::nvvm_suld_1d_v4i16_zero:
03128     return NVPTXISD::Suld1DV4I16Zero;
03129   case Intrinsic::nvvm_suld_1d_v4i32_zero:
03130     return NVPTXISD::Suld1DV4I32Zero;
03131   case Intrinsic::nvvm_suld_1d_array_i8_zero:
03132     return NVPTXISD::Suld1DArrayI8Zero;
03133   case Intrinsic::nvvm_suld_1d_array_i16_zero:
03134     return NVPTXISD::Suld1DArrayI16Zero;
03135   case Intrinsic::nvvm_suld_1d_array_i32_zero:
03136     return NVPTXISD::Suld1DArrayI32Zero;
03137   case Intrinsic::nvvm_suld_1d_array_i64_zero:
03138     return NVPTXISD::Suld1DArrayI64Zero;
03139   case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
03140     return NVPTXISD::Suld1DArrayV2I8Zero;
03141   case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
03142     return NVPTXISD::Suld1DArrayV2I16Zero;
03143   case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
03144     return NVPTXISD::Suld1DArrayV2I32Zero;
03145   case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
03146     return NVPTXISD::Suld1DArrayV2I64Zero;
03147   case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
03148     return NVPTXISD::Suld1DArrayV4I8Zero;
03149   case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
03150     return NVPTXISD::Suld1DArrayV4I16Zero;
03151   case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
03152     return NVPTXISD::Suld1DArrayV4I32Zero;
03153   case Intrinsic::nvvm_suld_2d_i8_zero:
03154     return NVPTXISD::Suld2DI8Zero;
03155   case Intrinsic::nvvm_suld_2d_i16_zero:
03156     return NVPTXISD::Suld2DI16Zero;
03157   case Intrinsic::nvvm_suld_2d_i32_zero:
03158     return NVPTXISD::Suld2DI32Zero;
03159   case Intrinsic::nvvm_suld_2d_i64_zero:
03160     return NVPTXISD::Suld2DI64Zero;
03161   case Intrinsic::nvvm_suld_2d_v2i8_zero:
03162     return NVPTXISD::Suld2DV2I8Zero;
03163   case Intrinsic::nvvm_suld_2d_v2i16_zero:
03164     return NVPTXISD::Suld2DV2I16Zero;
03165   case Intrinsic::nvvm_suld_2d_v2i32_zero:
03166     return NVPTXISD::Suld2DV2I32Zero;
03167   case Intrinsic::nvvm_suld_2d_v2i64_zero:
03168     return NVPTXISD::Suld2DV2I64Zero;
03169   case Intrinsic::nvvm_suld_2d_v4i8_zero:
03170     return NVPTXISD::Suld2DV4I8Zero;
03171   case Intrinsic::nvvm_suld_2d_v4i16_zero:
03172     return NVPTXISD::Suld2DV4I16Zero;
03173   case Intrinsic::nvvm_suld_2d_v4i32_zero:
03174     return NVPTXISD::Suld2DV4I32Zero;
03175   case Intrinsic::nvvm_suld_2d_array_i8_zero:
03176     return NVPTXISD::Suld2DArrayI8Zero;
03177   case Intrinsic::nvvm_suld_2d_array_i16_zero:
03178     return NVPTXISD::Suld2DArrayI16Zero;
03179   case Intrinsic::nvvm_suld_2d_array_i32_zero:
03180     return NVPTXISD::Suld2DArrayI32Zero;
03181   case Intrinsic::nvvm_suld_2d_array_i64_zero:
03182     return NVPTXISD::Suld2DArrayI64Zero;
03183   case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
03184     return NVPTXISD::Suld2DArrayV2I8Zero;
03185   case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
03186     return NVPTXISD::Suld2DArrayV2I16Zero;
03187   case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
03188     return NVPTXISD::Suld2DArrayV2I32Zero;
03189   case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
03190     return NVPTXISD::Suld2DArrayV2I64Zero;
03191   case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
03192     return NVPTXISD::Suld2DArrayV4I8Zero;
03193   case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
03194     return NVPTXISD::Suld2DArrayV4I16Zero;
03195   case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
03196     return NVPTXISD::Suld2DArrayV4I32Zero;
03197   case Intrinsic::nvvm_suld_3d_i8_zero:
03198     return NVPTXISD::Suld3DI8Zero;
03199   case Intrinsic::nvvm_suld_3d_i16_zero:
03200     return NVPTXISD::Suld3DI16Zero;
03201   case Intrinsic::nvvm_suld_3d_i32_zero:
03202     return NVPTXISD::Suld3DI32Zero;
03203   case Intrinsic::nvvm_suld_3d_i64_zero:
03204     return NVPTXISD::Suld3DI64Zero;
03205   case Intrinsic::nvvm_suld_3d_v2i8_zero:
03206     return NVPTXISD::Suld3DV2I8Zero;
03207   case Intrinsic::nvvm_suld_3d_v2i16_zero:
03208     return NVPTXISD::Suld3DV2I16Zero;
03209   case Intrinsic::nvvm_suld_3d_v2i32_zero:
03210     return NVPTXISD::Suld3DV2I32Zero;
03211   case Intrinsic::nvvm_suld_3d_v2i64_zero:
03212     return NVPTXISD::Suld3DV2I64Zero;
03213   case Intrinsic::nvvm_suld_3d_v4i8_zero:
03214     return NVPTXISD::Suld3DV4I8Zero;
03215   case Intrinsic::nvvm_suld_3d_v4i16_zero:
03216     return NVPTXISD::Suld3DV4I16Zero;
03217   case Intrinsic::nvvm_suld_3d_v4i32_zero:
03218     return NVPTXISD::Suld3DV4I32Zero;
03219   }
03220 }
03221 
03222 // llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
03223 // TgtMemIntrinsic
03224 // because we need the information that is only available in the "Value" type
03225 // of destination
03226 // pointer. In particular, the address space information.
03227 bool NVPTXTargetLowering::getTgtMemIntrinsic(
03228     IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
03229   switch (Intrinsic) {
03230   default:
03231     return false;
03232 
03233   case Intrinsic::nvvm_atomic_load_add_f32:
03234     Info.opc = ISD::INTRINSIC_W_CHAIN;
03235     Info.memVT = MVT::f32;
03236     Info.ptrVal = I.getArgOperand(0);
03237     Info.offset = 0;
03238     Info.vol = 0;
03239     Info.readMem = true;
03240     Info.writeMem = true;
03241     Info.align = 0;
03242     return true;
03243 
03244   case Intrinsic::nvvm_atomic_load_inc_32:
03245   case Intrinsic::nvvm_atomic_load_dec_32:
03246     Info.opc = ISD::INTRINSIC_W_CHAIN;
03247     Info.memVT = MVT::i32;
03248     Info.ptrVal = I.getArgOperand(0);
03249     Info.offset = 0;
03250     Info.vol = 0;
03251     Info.readMem = true;
03252     Info.writeMem = true;
03253     Info.align = 0;
03254     return true;
03255 
03256   case Intrinsic::nvvm_ldu_global_i:
03257   case Intrinsic::nvvm_ldu_global_f:
03258   case Intrinsic::nvvm_ldu_global_p: {
03259 
03260     Info.opc = ISD::INTRINSIC_W_CHAIN;
03261     if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
03262       Info.memVT = getValueType(I.getType());
03263     else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
03264       Info.memVT = getPointerTy();
03265     else
03266       Info.memVT = getValueType(I.getType());
03267     Info.ptrVal = I.getArgOperand(0);
03268     Info.offset = 0;
03269     Info.vol = 0;
03270     Info.readMem = true;
03271     Info.writeMem = false;
03272     Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
03273 
03274     return true;
03275   }
03276   case Intrinsic::nvvm_ldg_global_i:
03277   case Intrinsic::nvvm_ldg_global_f:
03278   case Intrinsic::nvvm_ldg_global_p: {
03279 
03280     Info.opc = ISD::INTRINSIC_W_CHAIN;
03281     if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
03282       Info.memVT = getValueType(I.getType());
03283     else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
03284       Info.memVT = getPointerTy();
03285     else
03286       Info.memVT = getValueType(I.getType());
03287     Info.ptrVal = I.getArgOperand(0);
03288     Info.offset = 0;
03289     Info.vol = 0;
03290     Info.readMem = true;
03291     Info.writeMem = false;
03292     Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
03293 
03294     return true;
03295   }
03296 
03297   case Intrinsic::nvvm_tex_1d_v4f32_s32:
03298   case Intrinsic::nvvm_tex_1d_v4f32_f32:
03299   case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
03300   case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
03301   case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
03302   case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
03303   case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
03304   case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
03305   case Intrinsic::nvvm_tex_2d_v4f32_s32:
03306   case Intrinsic::nvvm_tex_2d_v4f32_f32:
03307   case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
03308   case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
03309   case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
03310   case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
03311   case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
03312   case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
03313   case Intrinsic::nvvm_tex_3d_v4f32_s32:
03314   case Intrinsic::nvvm_tex_3d_v4f32_f32:
03315   case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
03316   case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
03317   case Intrinsic::nvvm_tex_cube_v4f32_f32:
03318   case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
03319   case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
03320   case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
03321   case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
03322   case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
03323   case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
03324   case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
03325   case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
03326   case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
03327   case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
03328   case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
03329   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
03330   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
03331   case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
03332   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
03333   case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
03334   case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
03335   case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
03336   case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
03337   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
03338   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
03339   case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
03340   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
03341   case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
03342   case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
03343   case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
03344   case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
03345   case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
03346   case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
03347   case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
03348   case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
03349   case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
03350   case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
03351   case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
03352   case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32: {
03353     Info.opc = getOpcForTextureInstr(Intrinsic);
03354     Info.memVT = MVT::v4f32;
03355     Info.ptrVal = nullptr;
03356     Info.offset = 0;
03357     Info.vol = 0;
03358     Info.readMem = true;
03359     Info.writeMem = false;
03360     Info.align = 16;
03361     return true;
03362   }
03363   case Intrinsic::nvvm_tex_1d_v4s32_s32:
03364   case Intrinsic::nvvm_tex_1d_v4s32_f32:
03365   case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
03366   case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
03367   case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
03368   case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
03369   case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
03370   case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
03371   case Intrinsic::nvvm_tex_2d_v4s32_s32:
03372   case Intrinsic::nvvm_tex_2d_v4s32_f32:
03373   case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
03374   case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
03375   case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
03376   case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
03377   case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
03378   case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
03379   case Intrinsic::nvvm_tex_3d_v4s32_s32:
03380   case Intrinsic::nvvm_tex_3d_v4s32_f32:
03381   case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
03382   case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
03383   case Intrinsic::nvvm_tex_cube_v4s32_f32:
03384   case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
03385   case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
03386   case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
03387   case Intrinsic::nvvm_tex_cube_v4u32_f32:
03388   case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
03389   case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
03390   case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
03391   case Intrinsic::nvvm_tex_1d_v4u32_s32:
03392   case Intrinsic::nvvm_tex_1d_v4u32_f32:
03393   case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
03394   case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
03395   case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
03396   case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
03397   case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
03398   case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
03399   case Intrinsic::nvvm_tex_2d_v4u32_s32:
03400   case Intrinsic::nvvm_tex_2d_v4u32_f32:
03401   case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
03402   case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
03403   case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
03404   case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
03405   case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
03406   case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
03407   case Intrinsic::nvvm_tex_3d_v4u32_s32:
03408   case Intrinsic::nvvm_tex_3d_v4u32_f32:
03409   case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
03410   case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
03411   case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
03412   case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
03413   case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
03414   case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
03415   case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
03416   case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
03417   case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
03418   case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
03419   case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
03420   case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
03421   case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
03422   case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
03423   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
03424   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
03425   case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
03426   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
03427   case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
03428   case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
03429   case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
03430   case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
03431   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
03432   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
03433   case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
03434   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
03435   case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
03436   case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
03437   case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
03438   case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
03439   case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
03440   case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
03441   case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
03442   case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
03443   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
03444   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
03445   case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
03446   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
03447   case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
03448   case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
03449   case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
03450   case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
03451   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
03452   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
03453   case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
03454   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
03455   case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
03456   case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
03457   case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
03458   case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
03459   case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
03460   case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
03461   case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
03462   case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
03463   case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
03464   case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
03465   case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
03466   case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
03467   case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
03468   case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
03469   case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
03470   case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
03471   case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
03472   case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
03473   case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
03474   case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32: {
03475     Info.opc = getOpcForTextureInstr(Intrinsic);
03476     Info.memVT = MVT::v4i32;
03477     Info.ptrVal = nullptr;
03478     Info.offset = 0;
03479     Info.vol = 0;
03480     Info.readMem = true;
03481     Info.writeMem = false;
03482     Info.align = 16;
03483     return true;
03484   }
03485   case Intrinsic::nvvm_suld_1d_i8_clamp:
03486   case Intrinsic::nvvm_suld_1d_v2i8_clamp:
03487   case Intrinsic::nvvm_suld_1d_v4i8_clamp:
03488   case Intrinsic::nvvm_suld_1d_array_i8_clamp:
03489   case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
03490   case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
03491   case Intrinsic::nvvm_suld_2d_i8_clamp:
03492   case Intrinsic::nvvm_suld_2d_v2i8_clamp:
03493   case Intrinsic::nvvm_suld_2d_v4i8_clamp:
03494   case Intrinsic::nvvm_suld_2d_array_i8_clamp:
03495   case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
03496   case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
03497   case Intrinsic::nvvm_suld_3d_i8_clamp:
03498   case Intrinsic::nvvm_suld_3d_v2i8_clamp:
03499   case Intrinsic::nvvm_suld_3d_v4i8_clamp:
03500   case Intrinsic::nvvm_suld_1d_i8_trap:
03501   case Intrinsic::nvvm_suld_1d_v2i8_trap:
03502   case Intrinsic::nvvm_suld_1d_v4i8_trap:
03503   case Intrinsic::nvvm_suld_1d_array_i8_trap:
03504   case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
03505   case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
03506   case Intrinsic::nvvm_suld_2d_i8_trap:
03507   case Intrinsic::nvvm_suld_2d_v2i8_trap:
03508   case Intrinsic::nvvm_suld_2d_v4i8_trap:
03509   case Intrinsic::nvvm_suld_2d_array_i8_trap:
03510   case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
03511   case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
03512   case Intrinsic::nvvm_suld_3d_i8_trap:
03513   case Intrinsic::nvvm_suld_3d_v2i8_trap:
03514   case Intrinsic::nvvm_suld_3d_v4i8_trap:
03515   case Intrinsic::nvvm_suld_1d_i8_zero:
03516   case Intrinsic::nvvm_suld_1d_v2i8_zero:
03517   case Intrinsic::nvvm_suld_1d_v4i8_zero:
03518   case Intrinsic::nvvm_suld_1d_array_i8_zero:
03519   case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
03520   case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
03521   case Intrinsic::nvvm_suld_2d_i8_zero:
03522   case Intrinsic::nvvm_suld_2d_v2i8_zero:
03523   case Intrinsic::nvvm_suld_2d_v4i8_zero:
03524   case Intrinsic::nvvm_suld_2d_array_i8_zero:
03525   case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
03526   case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
03527   case Intrinsic::nvvm_suld_3d_i8_zero:
03528   case Intrinsic::nvvm_suld_3d_v2i8_zero:
03529   case Intrinsic::nvvm_suld_3d_v4i8_zero: {
03530     Info.opc = getOpcForSurfaceInstr(Intrinsic);
03531     Info.memVT = MVT::i8;
03532     Info.ptrVal = nullptr;
03533     Info.offset = 0;
03534     Info.vol = 0;
03535     Info.readMem = true;
03536     Info.writeMem = false;
03537     Info.align = 16;
03538     return true;
03539   }
03540   case Intrinsic::nvvm_suld_1d_i16_clamp:
03541   case Intrinsic::nvvm_suld_1d_v2i16_clamp:
03542   case Intrinsic::nvvm_suld_1d_v4i16_clamp:
03543   case Intrinsic::nvvm_suld_1d_array_i16_clamp:
03544   case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
03545   case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
03546   case Intrinsic::nvvm_suld_2d_i16_clamp:
03547   case Intrinsic::nvvm_suld_2d_v2i16_clamp:
03548   case Intrinsic::nvvm_suld_2d_v4i16_clamp:
03549   case Intrinsic::nvvm_suld_2d_array_i16_clamp:
03550   case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
03551   case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
03552   case Intrinsic::nvvm_suld_3d_i16_clamp:
03553   case Intrinsic::nvvm_suld_3d_v2i16_clamp:
03554   case Intrinsic::nvvm_suld_3d_v4i16_clamp:
03555   case Intrinsic::nvvm_suld_1d_i16_trap:
03556   case Intrinsic::nvvm_suld_1d_v2i16_trap:
03557   case Intrinsic::nvvm_suld_1d_v4i16_trap:
03558   case Intrinsic::nvvm_suld_1d_array_i16_trap:
03559   case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
03560   case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
03561   case Intrinsic::nvvm_suld_2d_i16_trap:
03562   case Intrinsic::nvvm_suld_2d_v2i16_trap:
03563   case Intrinsic::nvvm_suld_2d_v4i16_trap:
03564   case Intrinsic::nvvm_suld_2d_array_i16_trap:
03565   case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
03566   case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
03567   case Intrinsic::nvvm_suld_3d_i16_trap:
03568   case Intrinsic::nvvm_suld_3d_v2i16_trap:
03569   case Intrinsic::nvvm_suld_3d_v4i16_trap:
03570   case Intrinsic::nvvm_suld_1d_i16_zero:
03571   case Intrinsic::nvvm_suld_1d_v2i16_zero:
03572   case Intrinsic::nvvm_suld_1d_v4i16_zero:
03573   case Intrinsic::nvvm_suld_1d_array_i16_zero:
03574   case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
03575   case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
03576   case Intrinsic::nvvm_suld_2d_i16_zero:
03577   case Intrinsic::nvvm_suld_2d_v2i16_zero:
03578   case Intrinsic::nvvm_suld_2d_v4i16_zero:
03579   case Intrinsic::nvvm_suld_2d_array_i16_zero:
03580   case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
03581   case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
03582   case Intrinsic::nvvm_suld_3d_i16_zero:
03583   case Intrinsic::nvvm_suld_3d_v2i16_zero:
03584   case Intrinsic::nvvm_suld_3d_v4i16_zero: {
03585     Info.opc = getOpcForSurfaceInstr(Intrinsic);
03586     Info.memVT = MVT::i16;
03587     Info.ptrVal = nullptr;
03588     Info.offset = 0;
03589     Info.vol = 0;
03590     Info.readMem = true;
03591     Info.writeMem = false;
03592     Info.align = 16;
03593     return true;
03594   }
03595   case Intrinsic::nvvm_suld_1d_i32_clamp:
03596   case Intrinsic::nvvm_suld_1d_v2i32_clamp:
03597   case Intrinsic::nvvm_suld_1d_v4i32_clamp:
03598   case Intrinsic::nvvm_suld_1d_array_i32_clamp:
03599   case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
03600   case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
03601   case Intrinsic::nvvm_suld_2d_i32_clamp:
03602   case Intrinsic::nvvm_suld_2d_v2i32_clamp:
03603   case Intrinsic::nvvm_suld_2d_v4i32_clamp:
03604   case Intrinsic::nvvm_suld_2d_array_i32_clamp:
03605   case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
03606   case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
03607   case Intrinsic::nvvm_suld_3d_i32_clamp:
03608   case Intrinsic::nvvm_suld_3d_v2i32_clamp:
03609   case Intrinsic::nvvm_suld_3d_v4i32_clamp:
03610   case Intrinsic::nvvm_suld_1d_i32_trap:
03611   case Intrinsic::nvvm_suld_1d_v2i32_trap:
03612   case Intrinsic::nvvm_suld_1d_v4i32_trap:
03613   case Intrinsic::nvvm_suld_1d_array_i32_trap:
03614   case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
03615   case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
03616   case Intrinsic::nvvm_suld_2d_i32_trap:
03617   case Intrinsic::nvvm_suld_2d_v2i32_trap:
03618   case Intrinsic::nvvm_suld_2d_v4i32_trap:
03619   case Intrinsic::nvvm_suld_2d_array_i32_trap:
03620   case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
03621   case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
03622   case Intrinsic::nvvm_suld_3d_i32_trap:
03623   case Intrinsic::nvvm_suld_3d_v2i32_trap:
03624   case Intrinsic::nvvm_suld_3d_v4i32_trap:
03625   case Intrinsic::nvvm_suld_1d_i32_zero:
03626   case Intrinsic::nvvm_suld_1d_v2i32_zero:
03627   case Intrinsic::nvvm_suld_1d_v4i32_zero:
03628   case Intrinsic::nvvm_suld_1d_array_i32_zero:
03629   case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
03630   case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
03631   case Intrinsic::nvvm_suld_2d_i32_zero:
03632   case Intrinsic::nvvm_suld_2d_v2i32_zero:
03633   case Intrinsic::nvvm_suld_2d_v4i32_zero:
03634   case Intrinsic::nvvm_suld_2d_array_i32_zero:
03635   case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
03636   case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
03637   case Intrinsic::nvvm_suld_3d_i32_zero:
03638   case Intrinsic::nvvm_suld_3d_v2i32_zero:
03639   case Intrinsic::nvvm_suld_3d_v4i32_zero: {
03640     Info.opc = getOpcForSurfaceInstr(Intrinsic);
03641     Info.memVT = MVT::i32;
03642     Info.ptrVal = nullptr;
03643     Info.offset = 0;
03644     Info.vol = 0;
03645     Info.readMem = true;
03646     Info.writeMem = false;
03647     Info.align = 16;
03648     return true;
03649   }
03650   case Intrinsic::nvvm_suld_1d_i64_clamp:
03651   case Intrinsic::nvvm_suld_1d_v2i64_clamp:
03652   case Intrinsic::nvvm_suld_1d_array_i64_clamp:
03653   case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
03654   case Intrinsic::nvvm_suld_2d_i64_clamp:
03655   case Intrinsic::nvvm_suld_2d_v2i64_clamp:
03656   case Intrinsic::nvvm_suld_2d_array_i64_clamp:
03657   case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
03658   case Intrinsic::nvvm_suld_3d_i64_clamp:
03659   case Intrinsic::nvvm_suld_3d_v2i64_clamp:
03660   case Intrinsic::nvvm_suld_1d_i64_trap:
03661   case Intrinsic::nvvm_suld_1d_v2i64_trap:
03662   case Intrinsic::nvvm_suld_1d_array_i64_trap:
03663   case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
03664   case Intrinsic::nvvm_suld_2d_i64_trap:
03665   case Intrinsic::nvvm_suld_2d_v2i64_trap:
03666   case Intrinsic::nvvm_suld_2d_array_i64_trap:
03667   case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
03668   case Intrinsic::nvvm_suld_3d_i64_trap:
03669   case Intrinsic::nvvm_suld_3d_v2i64_trap:
03670   case Intrinsic::nvvm_suld_1d_i64_zero:
03671   case Intrinsic::nvvm_suld_1d_v2i64_zero:
03672   case Intrinsic::nvvm_suld_1d_array_i64_zero:
03673   case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
03674   case Intrinsic::nvvm_suld_2d_i64_zero:
03675   case Intrinsic::nvvm_suld_2d_v2i64_zero:
03676   case Intrinsic::nvvm_suld_2d_array_i64_zero:
03677   case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
03678   case Intrinsic::nvvm_suld_3d_i64_zero:
03679   case Intrinsic::nvvm_suld_3d_v2i64_zero: {
03680     Info.opc = getOpcForSurfaceInstr(Intrinsic);
03681     Info.memVT = MVT::i64;
03682     Info.ptrVal = nullptr;
03683     Info.offset = 0;
03684     Info.vol = 0;
03685     Info.readMem = true;
03686     Info.writeMem = false;
03687     Info.align = 16;
03688     return true;
03689   }
03690   }
03691   return false;
03692 }
03693 
03694 /// isLegalAddressingMode - Return true if the addressing mode represented
03695 /// by AM is legal for this target, for a load/store of the specified type.
03696 /// Used to guide target specific optimizations, like loop strength reduction
03697 /// (LoopStrengthReduce.cpp) and memory optimization for address mode
03698 /// (CodeGenPrepare.cpp)
03699 bool NVPTXTargetLowering::isLegalAddressingMode(const AddrMode &AM,
03700                                                 Type *Ty) const {
03701 
03702   // AddrMode - This represents an addressing mode of:
03703   //    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
03704   //
03705   // The legal address modes are
03706   // - [avar]
03707   // - [areg]
03708   // - [areg+immoff]
03709   // - [immAddr]
03710 
03711   if (AM.BaseGV) {
03712     if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
03713       return false;
03714     return true;
03715   }
03716 
03717   switch (AM.Scale) {
03718   case 0: // "r", "r+i" or "i" is allowed
03719     break;
03720   case 1:
03721     if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
03722       return false;
03723     // Otherwise we have r+i.
03724     break;
03725   default:
03726     // No scale > 1 is allowed
03727     return false;
03728   }
03729   return true;
03730 }
03731 
03732 //===----------------------------------------------------------------------===//
03733 //                         NVPTX Inline Assembly Support
03734 //===----------------------------------------------------------------------===//
03735 
03736 /// getConstraintType - Given a constraint letter, return the type of
03737 /// constraint it is for this target.
03738 NVPTXTargetLowering::ConstraintType
03739 NVPTXTargetLowering::getConstraintType(const std::string &Constraint) const {
03740   if (Constraint.size() == 1) {
03741     switch (Constraint[0]) {
03742     default:
03743       break;
03744     case 'b':
03745     case 'r':
03746     case 'h':
03747     case 'c':
03748     case 'l':
03749     case 'f':
03750     case 'd':
03751     case '0':
03752     case 'N':
03753       return C_RegisterClass;
03754     }
03755   }
03756   return TargetLowering::getConstraintType(Constraint);
03757 }
03758 
03759 std::pair<unsigned, const TargetRegisterClass *>
03760 NVPTXTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
03761                                                   MVT VT) const {
03762   if (Constraint.size() == 1) {
03763     switch (Constraint[0]) {
03764     case 'b':
03765       return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
03766     case 'c':
03767       return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
03768     case 'h':
03769       return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
03770     case 'r':
03771       return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
03772     case 'l':
03773     case 'N':
03774       return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
03775     case 'f':
03776       return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
03777     case 'd':
03778       return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
03779     }
03780   }
03781   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
03782 }
03783 
03784 /// getFunctionAlignment - Return the Log2 alignment of this function.
03785 unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
03786   return 4;
03787 }
03788 
03789 //===----------------------------------------------------------------------===//
03790 //                         NVPTX DAG Combining
03791 //===----------------------------------------------------------------------===//
03792 
03793 bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
03794                                    CodeGenOpt::Level OptLevel) const {
03795   const Function *F = MF.getFunction();
03796   const TargetOptions &TO = MF.getTarget().Options;
03797 
03798   // Always honor command-line argument
03799   if (FMAContractLevelOpt.getNumOccurrences() > 0) {
03800     return FMAContractLevelOpt > 0;
03801   } else if (OptLevel == 0) {
03802     // Do not contract if we're not optimizing the code
03803     return false;
03804   } else if (TO.AllowFPOpFusion == FPOpFusion::Fast || TO.UnsafeFPMath) {
03805     // Honor TargetOptions flags that explicitly say fusion is okay
03806     return true;
03807   } else if (F->hasFnAttribute("unsafe-fp-math")) {
03808     // Check for unsafe-fp-math=true coming from Clang
03809     Attribute Attr = F->getFnAttribute("unsafe-fp-math");
03810     StringRef Val = Attr.getValueAsString();
03811     if (Val == "true")
03812       return true;
03813   }
03814 
03815   // We did not have a clear indication that fusion is allowed, so assume not
03816   return false;
03817 }
03818 
03819 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
03820 /// operands N0 and N1.  This is a helper for PerformADDCombine that is
03821 /// called with the default operands, and if that fails, with commuted
03822 /// operands.
03823 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
03824                                            TargetLowering::DAGCombinerInfo &DCI,
03825                                              const NVPTXSubtarget &Subtarget,
03826                                              CodeGenOpt::Level OptLevel) {
03827   SelectionDAG  &DAG = DCI.DAG;
03828   // Skip non-integer, non-scalar case
03829   EVT VT=N0.getValueType();
03830   if (VT.isVector())
03831     return SDValue();
03832 
03833   // fold (add (mul a, b), c) -> (mad a, b, c)
03834   //
03835   if (N0.getOpcode() == ISD::MUL) {
03836     assert (VT.isInteger());
03837     // For integer:
03838     // Since integer multiply-add costs the same as integer multiply
03839     // but is more costly than integer add, do the fusion only when
03840     // the mul is only used in the add.
03841     if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
03842         !N0.getNode()->hasOneUse())
03843       return SDValue();
03844 
03845     // Do the folding
03846     return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
03847                        N0.getOperand(0), N0.getOperand(1), N1);
03848   }
03849   else if (N0.getOpcode() == ISD::FMUL) {
03850     if (VT == MVT::f32 || VT == MVT::f64) {
03851       const auto *TLI = static_cast<const NVPTXTargetLowering *>(
03852           &DAG.getTargetLoweringInfo());
03853       if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
03854         return SDValue();
03855 
03856       // For floating point:
03857       // Do the fusion only when the mul has less than 5 uses and all
03858       // are add.
03859       // The heuristic is that if a use is not an add, then that use
03860       // cannot be fused into fma, therefore mul is still needed anyway.
03861       // If there are more than 4 uses, even if they are all add, fusing
03862       // them will increase register pressue.
03863       //
03864       int numUses = 0;
03865       int nonAddCount = 0;
03866       for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
03867            UE = N0.getNode()->use_end();
03868            UI != UE; ++UI) {
03869         numUses++;
03870         SDNode *User = *UI;
03871         if (User->getOpcode() != ISD::FADD)
03872           ++nonAddCount;
03873       }
03874       if (numUses >= 5)
03875         return SDValue();
03876       if (nonAddCount) {
03877         int orderNo = N->getIROrder();
03878         int orderNo2 = N0.getNode()->getIROrder();
03879         // simple heuristics here for considering potential register
03880         // pressure, the logics here is that the differnce are used
03881         // to measure the distance between def and use, the longer distance
03882         // more likely cause register pressure.
03883         if (orderNo - orderNo2 < 500)
03884           return SDValue();
03885 
03886         // Now, check if at least one of the FMUL's operands is live beyond the node N,
03887         // which guarantees that the FMA will not increase register pressure at node N.
03888         bool opIsLive = false;
03889         const SDNode *left = N0.getOperand(0).getNode();
03890         const SDNode *right = N0.getOperand(1).getNode();
03891 
03892         if (dyn_cast<ConstantSDNode>(left) || dyn_cast<ConstantSDNode>(right))
03893           opIsLive = true;
03894 
03895         if (!opIsLive)
03896           for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
03897             SDNode *User = *UI;
03898             int orderNo3 = User->getIROrder();
03899             if (orderNo3 > orderNo) {
03900               opIsLive = true;
03901               break;
03902             }
03903           }
03904 
03905         if (!opIsLive)
03906           for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
03907             SDNode *User = *UI;
03908             int orderNo3 = User->getIROrder();
03909             if (orderNo3 > orderNo) {
03910               opIsLive = true;
03911               break;
03912             }
03913           }
03914 
03915         if (!opIsLive)
03916           return SDValue();
03917       }
03918 
03919       return DAG.getNode(ISD::FMA, SDLoc(N), VT,
03920                          N0.getOperand(0), N0.getOperand(1), N1);
03921     }
03922   }
03923 
03924   return SDValue();
03925 }
03926 
03927 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
03928 ///
03929 static SDValue PerformADDCombine(SDNode *N,
03930                                  TargetLowering::DAGCombinerInfo &DCI,
03931                                  const NVPTXSubtarget &Subtarget,
03932                                  CodeGenOpt::Level OptLevel) {
03933   SDValue N0 = N->getOperand(0);
03934   SDValue N1 = N->getOperand(1);
03935 
03936   // First try with the default operand order.
03937   SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
03938                                                  OptLevel);
03939   if (Result.getNode())
03940     return Result;
03941 
03942   // If that didn't work, try again with the operands commuted.
03943   return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
03944 }
03945 
03946 static SDValue PerformANDCombine(SDNode *N,
03947                                  TargetLowering::DAGCombinerInfo &DCI) {
03948   // The type legalizer turns a vector load of i8 values into a zextload to i16
03949   // registers, optionally ANY_EXTENDs it (if target type is integer),
03950   // and ANDs off the high 8 bits. Since we turn this load into a
03951   // target-specific DAG node, the DAG combiner fails to eliminate these AND
03952   // nodes. Do that here.
03953   SDValue Val = N->getOperand(0);
03954   SDValue Mask = N->getOperand(1);
03955 
03956   if (isa<ConstantSDNode>(Val)) {
03957     std::swap(Val, Mask);
03958   }
03959 
03960   SDValue AExt;
03961   // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
03962   if (Val.getOpcode() == ISD::ANY_EXTEND) {
03963     AExt = Val;
03964     Val = Val->getOperand(0);
03965   }
03966 
03967   if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
03968     Val = Val->getOperand(0);
03969   }
03970 
03971   if (Val->getOpcode() == NVPTXISD::LoadV2 ||
03972       Val->getOpcode() == NVPTXISD::LoadV4) {
03973     ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
03974     if (!MaskCnst) {
03975       // Not an AND with a constant
03976       return SDValue();
03977     }
03978 
03979     uint64_t MaskVal = MaskCnst->getZExtValue();
03980     if (MaskVal != 0xff) {
03981       // Not an AND that chops off top 8 bits
03982       return SDValue();
03983     }
03984 
03985     MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
03986     if (!Mem) {
03987       // Not a MemSDNode?!?
03988       return SDValue();
03989     }
03990 
03991     EVT MemVT = Mem->getMemoryVT();
03992     if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
03993       // We only handle the i8 case
03994       return SDValue();
03995     }
03996 
03997     unsigned ExtType =
03998       cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
03999         getZExtValue();
04000     if (ExtType == ISD::SEXTLOAD) {
04001       // If for some reason the load is a sextload, the and is needed to zero
04002       // out the high 8 bits
04003       return SDValue();
04004     }
04005 
04006     bool AddTo = false;
04007     if (AExt.getNode() != 0) {
04008       // Re-insert the ext as a zext.
04009       Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
04010                             AExt.getValueType(), Val);
04011       AddTo = true;
04012     }
04013 
04014     // If we get here, the AND is unnecessary.  Just replace it with the load
04015     DCI.CombineTo(N, Val, AddTo);
04016   }
04017 
04018   return SDValue();
04019 }
04020 
04021 enum OperandSignedness {
04022   Signed = 0,
04023   Unsigned,
04024   Unknown
04025 };
04026 
04027 /// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
04028 /// that can be demoted to \p OptSize bits without loss of information. The
04029 /// signedness of the operand, if determinable, is placed in \p S.
04030 static bool IsMulWideOperandDemotable(SDValue Op,
04031                                       unsigned OptSize,
04032                                       OperandSignedness &S) {
04033   S = Unknown;
04034 
04035   if (Op.getOpcode() == ISD::SIGN_EXTEND ||
04036       Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
04037     EVT OrigVT = Op.getOperand(0).getValueType();
04038     if (OrigVT.getSizeInBits() <= OptSize) {
04039       S = Signed;
04040       return true;
04041     }
04042   } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
04043     EVT OrigVT = Op.getOperand(0).getValueType();
04044     if (OrigVT.getSizeInBits() <= OptSize) {
04045       S = Unsigned;
04046       return true;
04047     }
04048   }
04049 
04050   return false;
04051 }
04052 
04053 /// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
04054 /// be demoted to \p OptSize bits without loss of information. If the operands
04055 /// contain a constant, it should appear as the RHS operand. The signedness of
04056 /// the operands is placed in \p IsSigned.
04057 static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
04058                                         unsigned OptSize,
04059                                         bool &IsSigned) {
04060 
04061   OperandSignedness LHSSign;
04062 
04063   // The LHS operand must be a demotable op
04064   if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
04065     return false;
04066 
04067   // We should have been able to determine the signedness from the LHS
04068   if (LHSSign == Unknown)
04069     return false;
04070 
04071   IsSigned = (LHSSign == Signed);
04072 
04073   // The RHS can be a demotable op or a constant
04074   if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
04075     APInt Val = CI->getAPIntValue();
04076     if (LHSSign == Unsigned) {
04077       if (Val.isIntN(OptSize)) {
04078         return true;
04079       }
04080       return false;
04081     } else {
04082       if (Val.isSignedIntN(OptSize)) {
04083         return true;
04084       }
04085       return false;
04086     }
04087   } else {
04088     OperandSignedness RHSSign;
04089     if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
04090       return false;
04091 
04092     if (LHSSign != RHSSign)
04093       return false;
04094 
04095     return true;
04096   }
04097 }
04098 
04099 /// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
04100 /// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
04101 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
04102 /// amount.
04103 static SDValue TryMULWIDECombine(SDNode *N,
04104                                  TargetLowering::DAGCombinerInfo &DCI) {
04105   EVT MulType = N->getValueType(0);
04106   if (MulType != MVT::i32 && MulType != MVT::i64) {
04107     return SDValue();
04108   }
04109 
04110   unsigned OptSize = MulType.getSizeInBits() >> 1;
04111   SDValue LHS = N->getOperand(0);
04112   SDValue RHS = N->getOperand(1);
04113 
04114   // Canonicalize the multiply so the constant (if any) is on the right
04115   if (N->getOpcode() == ISD::MUL) {
04116     if (isa<ConstantSDNode>(LHS)) {
04117       std::swap(LHS, RHS);
04118     }
04119   }
04120 
04121   // If we have a SHL, determine the actual multiply amount
04122   if (N->getOpcode() == ISD::SHL) {
04123     ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
04124     if (!ShlRHS) {
04125       return SDValue();
04126     }
04127 
04128     APInt ShiftAmt = ShlRHS->getAPIntValue();
04129     unsigned BitWidth = MulType.getSizeInBits();
04130     if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
04131       APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
04132       RHS = DCI.DAG.getConstant(MulVal, MulType);
04133     } else {
04134       return SDValue();
04135     }
04136   }
04137 
04138   bool Signed;
04139   // Verify that our operands are demotable
04140   if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
04141     return SDValue();
04142   }
04143 
04144   EVT DemotedVT;
04145   if (MulType == MVT::i32) {
04146     DemotedVT = MVT::i16;
04147   } else {
04148     DemotedVT = MVT::i32;
04149   }
04150 
04151   // Truncate the operands to the correct size. Note that these are just for
04152   // type consistency and will (likely) be eliminated in later phases.
04153   SDValue TruncLHS =
04154     DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, LHS);
04155   SDValue TruncRHS =
04156     DCI.DAG.getNode(ISD::TRUNCATE, SDLoc(N), DemotedVT, RHS);
04157 
04158   unsigned Opc;
04159   if (Signed) {
04160     Opc = NVPTXISD::MUL_WIDE_SIGNED;
04161   } else {
04162     Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
04163   }
04164 
04165   return DCI.DAG.getNode(Opc, SDLoc(N), MulType, TruncLHS, TruncRHS);
04166 }
04167 
04168 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
04169 static SDValue PerformMULCombine(SDNode *N,
04170                                  TargetLowering::DAGCombinerInfo &DCI,
04171                                  CodeGenOpt::Level OptLevel) {
04172   if (OptLevel > 0) {
04173     // Try mul.wide combining at OptLevel > 0
04174     SDValue Ret = TryMULWIDECombine(N, DCI);
04175     if (Ret.getNode())
04176       return Ret;
04177   }
04178 
04179   return SDValue();
04180 }
04181 
04182 /// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
04183 static SDValue PerformSHLCombine(SDNode *N,
04184                                  TargetLowering::DAGCombinerInfo &DCI,
04185                                  CodeGenOpt::Level OptLevel) {
04186   if (OptLevel > 0) {
04187     // Try mul.wide combining at OptLevel > 0
04188     SDValue Ret = TryMULWIDECombine(N, DCI);
04189     if (Ret.getNode())
04190       return Ret;
04191   }
04192 
04193   return SDValue();
04194 }
04195 
04196 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
04197                                                DAGCombinerInfo &DCI) const {
04198   CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
04199   switch (N->getOpcode()) {
04200     default: break;
04201     case ISD::ADD:
04202     case ISD::FADD:
04203       return PerformADDCombine(N, DCI, nvptxSubtarget, OptLevel);
04204     case ISD::MUL:
04205       return PerformMULCombine(N, DCI, OptLevel);
04206     case ISD::SHL:
04207       return PerformSHLCombine(N, DCI, OptLevel);
04208     case ISD::AND:
04209       return PerformANDCombine(N, DCI);
04210   }
04211   return SDValue();
04212 }
04213 
04214 /// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
04215 static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
04216                               const DataLayout *TD,
04217                               SmallVectorImpl<SDValue> &Results) {
04218   EVT ResVT = N->getValueType(0);
04219   SDLoc DL(N);
04220 
04221   assert(ResVT.isVector() && "Vector load must have vector type");
04222 
04223   // We only handle "native" vector sizes for now, e.g. <4 x double> is not
04224   // legal.  We can (and should) split that into 2 loads of <2 x double> here
04225   // but I'm leaving that as a TODO for now.
04226   assert(ResVT.isSimple() && "Can only handle simple types");
04227   switch (ResVT.getSimpleVT().SimpleTy) {
04228   default:
04229     return;
04230   case MVT::v2i8:
04231   case MVT::v2i16:
04232   case MVT::v2i32:
04233   case MVT::v2i64:
04234   case MVT::v2f32:
04235   case MVT::v2f64:
04236   case MVT::v4i8:
04237   case MVT::v4i16:
04238   case MVT::v4i32:
04239   case MVT::v4f32:
04240     // This is a "native" vector type
04241     break;
04242   }
04243 
04244   LoadSDNode *LD = cast<LoadSDNode>(N);
04245 
04246   unsigned Align = LD->getAlignment();
04247   unsigned PrefAlign =
04248     TD->getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
04249   if (Align < PrefAlign) {
04250     // This load is not sufficiently aligned, so bail out and let this vector
04251     // load be scalarized.  Note that we may still be able to emit smaller
04252     // vector loads.  For example, if we are loading a <4 x float> with an
04253     // alignment of 8, this check will fail but the legalizer will try again
04254     // with 2 x <2 x float>, which will succeed with an alignment of 8.
04255     return;
04256   }
04257 
04258   EVT EltVT = ResVT.getVectorElementType();
04259   unsigned NumElts = ResVT.getVectorNumElements();
04260 
04261   // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
04262   // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
04263   // loaded type to i16 and propagate the "real" type as the memory type.
04264   bool NeedTrunc = false;
04265   if (EltVT.getSizeInBits() < 16) {
04266     EltVT = MVT::i16;
04267     NeedTrunc = true;
04268   }
04269 
04270   unsigned Opcode = 0;
04271   SDVTList LdResVTs;
04272 
04273   switch (NumElts) {
04274   default:
04275     return;
04276   case 2:
04277     Opcode = NVPTXISD::LoadV2;
04278     LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
04279     break;
04280   case 4: {
04281     Opcode = NVPTXISD::LoadV4;
04282     EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
04283     LdResVTs = DAG.getVTList(ListVTs);
04284     break;
04285   }
04286   }
04287 
04288   SmallVector<SDValue, 8> OtherOps;
04289 
04290   // Copy regular operands
04291   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
04292     OtherOps.push_back(N->getOperand(i));
04293 
04294   // The select routine does not have access to the LoadSDNode instance, so
04295   // pass along the extension information
04296   OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType()));
04297 
04298   SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
04299                                           LD->getMemoryVT(),
04300                                           LD->getMemOperand());
04301 
04302   SmallVector<SDValue, 4> ScalarRes;
04303 
04304   for (unsigned i = 0; i < NumElts; ++i) {
04305     SDValue Res = NewLD.getValue(i);
04306     if (NeedTrunc)
04307       Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
04308     ScalarRes.push_back(Res);
04309   }
04310 
04311   SDValue LoadChain = NewLD.getValue(NumElts);
04312 
04313   SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
04314 
04315   Results.push_back(BuildVec);
04316   Results.push_back(LoadChain);
04317 }
04318 
04319 static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
04320                                      SmallVectorImpl<SDValue> &Results) {
04321   SDValue Chain = N->getOperand(0);
04322   SDValue Intrin = N->getOperand(1);
04323   SDLoc DL(N);
04324 
04325   // Get the intrinsic ID
04326   unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
04327   switch (IntrinNo) {
04328   default:
04329     return;
04330   case Intrinsic::nvvm_ldg_global_i:
04331   case Intrinsic::nvvm_ldg_global_f:
04332   case Intrinsic::nvvm_ldg_global_p:
04333   case Intrinsic::nvvm_ldu_global_i:
04334   case Intrinsic::nvvm_ldu_global_f:
04335   case Intrinsic::nvvm_ldu_global_p: {
04336     EVT ResVT = N->getValueType(0);
04337 
04338     if (ResVT.isVector()) {
04339       // Vector LDG/LDU
04340 
04341       unsigned NumElts = ResVT.getVectorNumElements();
04342       EVT EltVT = ResVT.getVectorElementType();
04343 
04344       // Since LDU/LDG are target nodes, we cannot rely on DAG type
04345       // legalization.
04346       // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
04347       // loaded type to i16 and propagate the "real" type as the memory type.
04348       bool NeedTrunc = false;
04349       if (EltVT.getSizeInBits() < 16) {
04350         EltVT = MVT::i16;
04351         NeedTrunc = true;
04352       }
04353 
04354       unsigned Opcode = 0;
04355       SDVTList LdResVTs;
04356 
04357       switch (NumElts) {
04358       default:
04359         return;
04360       case 2:
04361         switch (IntrinNo) {
04362         default:
04363           return;
04364         case Intrinsic::nvvm_ldg_global_i:
04365         case Intrinsic::nvvm_ldg_global_f:
04366         case Intrinsic::nvvm_ldg_global_p:
04367           Opcode = NVPTXISD::LDGV2;
04368           break;
04369         case Intrinsic::nvvm_ldu_global_i:
04370         case Intrinsic::nvvm_ldu_global_f:
04371         case Intrinsic::nvvm_ldu_global_p:
04372           Opcode = NVPTXISD::LDUV2;
04373           break;
04374         }
04375         LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
04376         break;
04377       case 4: {
04378         switch (IntrinNo) {
04379         default:
04380           return;
04381         case Intrinsic::nvvm_ldg_global_i:
04382         case Intrinsic::nvvm_ldg_global_f:
04383         case Intrinsic::nvvm_ldg_global_p:
04384           Opcode = NVPTXISD::LDGV4;
04385           break;
04386         case Intrinsic::nvvm_ldu_global_i:
04387         case Intrinsic::nvvm_ldu_global_f:
04388         case Intrinsic::nvvm_ldu_global_p:
04389           Opcode = NVPTXISD::LDUV4;
04390           break;
04391         }
04392         EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
04393         LdResVTs = DAG.getVTList(ListVTs);
04394         break;
04395       }
04396       }
04397 
04398       SmallVector<SDValue, 8> OtherOps;
04399 
04400       // Copy regular operands
04401 
04402       OtherOps.push_back(Chain); // Chain
04403                                  // Skip operand 1 (intrinsic ID)
04404       // Others
04405       for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i)
04406         OtherOps.push_back(N->getOperand(i));
04407 
04408       MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
04409 
04410       SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
04411                                               MemSD->getMemoryVT(),
04412                                               MemSD->getMemOperand());
04413 
04414       SmallVector<SDValue, 4> ScalarRes;
04415 
04416       for (unsigned i = 0; i < NumElts; ++i) {
04417         SDValue Res = NewLD.getValue(i);
04418         if (NeedTrunc)
04419           Res =
04420               DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
04421         ScalarRes.push_back(Res);
04422       }
04423 
04424       SDValue LoadChain = NewLD.getValue(NumElts);
04425 
04426       SDValue BuildVec =
04427           DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
04428 
04429       Results.push_back(BuildVec);
04430       Results.push_back(LoadChain);
04431     } else {
04432       // i8 LDG/LDU
04433       assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
04434              "Custom handling of non-i8 ldu/ldg?");
04435 
04436       // Just copy all operands as-is
04437       SmallVector<SDValue, 4> Ops;
04438       for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
04439         Ops.push_back(N->getOperand(i));
04440 
04441       // Force output to i16
04442       SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
04443 
04444       MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
04445 
04446       // We make sure the memory type is i8, which will be used during isel
04447       // to select the proper instruction.
04448       SDValue NewLD =
04449           DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
04450                                   MVT::i8, MemSD->getMemOperand());
04451 
04452       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
04453                                     NewLD.getValue(0)));
04454       Results.push_back(NewLD.getValue(1));
04455     }
04456   }
04457   }
04458 }
04459 
04460 void NVPTXTargetLowering::ReplaceNodeResults(
04461     SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
04462   switch (N->getOpcode()) {
04463   default:
04464     report_fatal_error("Unhandled custom legalization");
04465   case ISD::LOAD:
04466     ReplaceLoadVector(N, DAG, getDataLayout(), Results);
04467     return;
04468   case ISD::INTRINSIC_W_CHAIN:
04469     ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
04470     return;
04471   }
04472 }
04473 
04474 // Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
04475 void NVPTXSection::anchor() {}
04476 
04477 NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
04478   delete TextSection;
04479   delete DataSection;
04480   delete BSSSection;
04481   delete ReadOnlySection;
04482 
04483   delete StaticCtorSection;
04484   delete StaticDtorSection;
04485   delete LSDASection;
04486   delete EHFrameSection;
04487   delete DwarfAbbrevSection;
04488   delete DwarfInfoSection;
04489   delete DwarfLineSection;
04490   delete DwarfFrameSection;
04491   delete DwarfPubTypesSection;
04492   delete DwarfDebugInlineSection;
04493   delete DwarfStrSection;
04494   delete DwarfLocSection;
04495   delete DwarfARangesSection;
04496   delete DwarfRangesSection;
04497   delete DwarfMacroInfoSection;
04498 }