LLVM API Documentation

MipsISelLowering.cpp
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00001 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines the interfaces that Mips uses to lower LLVM code into a
00011 // selection DAG.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 #define DEBUG_TYPE "mips-lower"
00015 #include "MipsISelLowering.h"
00016 #include "InstPrinter/MipsInstPrinter.h"
00017 #include "MCTargetDesc/MipsBaseInfo.h"
00018 #include "MipsMachineFunction.h"
00019 #include "MipsSubtarget.h"
00020 #include "MipsTargetMachine.h"
00021 #include "MipsTargetObjectFile.h"
00022 #include "llvm/ADT/Statistic.h"
00023 #include "llvm/ADT/StringSwitch.h"
00024 #include "llvm/CodeGen/CallingConvLower.h"
00025 #include "llvm/CodeGen/MachineFrameInfo.h"
00026 #include "llvm/CodeGen/MachineFunction.h"
00027 #include "llvm/CodeGen/MachineInstrBuilder.h"
00028 #include "llvm/CodeGen/MachineRegisterInfo.h"
00029 #include "llvm/CodeGen/SelectionDAGISel.h"
00030 #include "llvm/CodeGen/ValueTypes.h"
00031 #include "llvm/IR/CallingConv.h"
00032 #include "llvm/IR/DerivedTypes.h"
00033 #include "llvm/IR/GlobalVariable.h"
00034 #include "llvm/Support/CommandLine.h"
00035 #include "llvm/Support/Debug.h"
00036 #include "llvm/Support/ErrorHandling.h"
00037 #include "llvm/Support/raw_ostream.h"
00038 #include <cctype>
00039 
00040 using namespace llvm;
00041 
00042 STATISTIC(NumTailCalls, "Number of tail calls");
00043 
00044 static cl::opt<bool>
00045 LargeGOT("mxgot", cl::Hidden,
00046          cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
00047 
00048 static cl::opt<bool>
00049 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
00050                cl::desc("MIPS: Don't trap on integer division by zero."),
00051                cl::init(false));
00052 
00053 cl::opt<bool>
00054 EnableMipsFastISel("mips-fast-isel", cl::Hidden,
00055   cl::desc("Allow mips-fast-isel to be used"),
00056   cl::init(false));
00057 
00058 static const MCPhysReg O32IntRegs[4] = {
00059   Mips::A0, Mips::A1, Mips::A2, Mips::A3
00060 };
00061 
00062 static const MCPhysReg Mips64IntRegs[8] = {
00063   Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
00064   Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
00065 };
00066 
00067 static const MCPhysReg Mips64DPRegs[8] = {
00068   Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
00069   Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
00070 };
00071 
00072 // If I is a shifted mask, set the size (Size) and the first bit of the
00073 // mask (Pos), and return true.
00074 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
00075 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
00076   if (!isShiftedMask_64(I))
00077     return false;
00078 
00079   Size = CountPopulation_64(I);
00080   Pos = countTrailingZeros(I);
00081   return true;
00082 }
00083 
00084 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
00085   MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
00086   return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
00087 }
00088 
00089 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
00090                                           SelectionDAG &DAG,
00091                                           unsigned Flag) const {
00092   return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
00093 }
00094 
00095 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
00096                                           SelectionDAG &DAG,
00097                                           unsigned Flag) const {
00098   return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
00099 }
00100 
00101 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
00102                                           SelectionDAG &DAG,
00103                                           unsigned Flag) const {
00104   return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
00105 }
00106 
00107 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
00108                                           SelectionDAG &DAG,
00109                                           unsigned Flag) const {
00110   return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
00111 }
00112 
00113 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
00114                                           SelectionDAG &DAG,
00115                                           unsigned Flag) const {
00116   return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
00117                                    N->getOffset(), Flag);
00118 }
00119 
00120 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
00121   switch (Opcode) {
00122   case MipsISD::JmpLink:           return "MipsISD::JmpLink";
00123   case MipsISD::TailCall:          return "MipsISD::TailCall";
00124   case MipsISD::Hi:                return "MipsISD::Hi";
00125   case MipsISD::Lo:                return "MipsISD::Lo";
00126   case MipsISD::GPRel:             return "MipsISD::GPRel";
00127   case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
00128   case MipsISD::Ret:               return "MipsISD::Ret";
00129   case MipsISD::EH_RETURN:         return "MipsISD::EH_RETURN";
00130   case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
00131   case MipsISD::FPCmp:             return "MipsISD::FPCmp";
00132   case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
00133   case MipsISD::CMovFP_F:          return "MipsISD::CMovFP_F";
00134   case MipsISD::TruncIntFP:        return "MipsISD::TruncIntFP";
00135   case MipsISD::MFHI:              return "MipsISD::MFHI";
00136   case MipsISD::MFLO:              return "MipsISD::MFLO";
00137   case MipsISD::MTLOHI:            return "MipsISD::MTLOHI";
00138   case MipsISD::Mult:              return "MipsISD::Mult";
00139   case MipsISD::Multu:             return "MipsISD::Multu";
00140   case MipsISD::MAdd:              return "MipsISD::MAdd";
00141   case MipsISD::MAddu:             return "MipsISD::MAddu";
00142   case MipsISD::MSub:              return "MipsISD::MSub";
00143   case MipsISD::MSubu:             return "MipsISD::MSubu";
00144   case MipsISD::DivRem:            return "MipsISD::DivRem";
00145   case MipsISD::DivRemU:           return "MipsISD::DivRemU";
00146   case MipsISD::DivRem16:          return "MipsISD::DivRem16";
00147   case MipsISD::DivRemU16:         return "MipsISD::DivRemU16";
00148   case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64";
00149   case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
00150   case MipsISD::Wrapper:           return "MipsISD::Wrapper";
00151   case MipsISD::Sync:              return "MipsISD::Sync";
00152   case MipsISD::Ext:               return "MipsISD::Ext";
00153   case MipsISD::Ins:               return "MipsISD::Ins";
00154   case MipsISD::LWL:               return "MipsISD::LWL";
00155   case MipsISD::LWR:               return "MipsISD::LWR";
00156   case MipsISD::SWL:               return "MipsISD::SWL";
00157   case MipsISD::SWR:               return "MipsISD::SWR";
00158   case MipsISD::LDL:               return "MipsISD::LDL";
00159   case MipsISD::LDR:               return "MipsISD::LDR";
00160   case MipsISD::SDL:               return "MipsISD::SDL";
00161   case MipsISD::SDR:               return "MipsISD::SDR";
00162   case MipsISD::EXTP:              return "MipsISD::EXTP";
00163   case MipsISD::EXTPDP:            return "MipsISD::EXTPDP";
00164   case MipsISD::EXTR_S_H:          return "MipsISD::EXTR_S_H";
00165   case MipsISD::EXTR_W:            return "MipsISD::EXTR_W";
00166   case MipsISD::EXTR_R_W:          return "MipsISD::EXTR_R_W";
00167   case MipsISD::EXTR_RS_W:         return "MipsISD::EXTR_RS_W";
00168   case MipsISD::SHILO:             return "MipsISD::SHILO";
00169   case MipsISD::MTHLIP:            return "MipsISD::MTHLIP";
00170   case MipsISD::MULT:              return "MipsISD::MULT";
00171   case MipsISD::MULTU:             return "MipsISD::MULTU";
00172   case MipsISD::MADD_DSP:          return "MipsISD::MADD_DSP";
00173   case MipsISD::MADDU_DSP:         return "MipsISD::MADDU_DSP";
00174   case MipsISD::MSUB_DSP:          return "MipsISD::MSUB_DSP";
00175   case MipsISD::MSUBU_DSP:         return "MipsISD::MSUBU_DSP";
00176   case MipsISD::SHLL_DSP:          return "MipsISD::SHLL_DSP";
00177   case MipsISD::SHRA_DSP:          return "MipsISD::SHRA_DSP";
00178   case MipsISD::SHRL_DSP:          return "MipsISD::SHRL_DSP";
00179   case MipsISD::SETCC_DSP:         return "MipsISD::SETCC_DSP";
00180   case MipsISD::SELECT_CC_DSP:     return "MipsISD::SELECT_CC_DSP";
00181   case MipsISD::VALL_ZERO:         return "MipsISD::VALL_ZERO";
00182   case MipsISD::VANY_ZERO:         return "MipsISD::VANY_ZERO";
00183   case MipsISD::VALL_NONZERO:      return "MipsISD::VALL_NONZERO";
00184   case MipsISD::VANY_NONZERO:      return "MipsISD::VANY_NONZERO";
00185   case MipsISD::VCEQ:              return "MipsISD::VCEQ";
00186   case MipsISD::VCLE_S:            return "MipsISD::VCLE_S";
00187   case MipsISD::VCLE_U:            return "MipsISD::VCLE_U";
00188   case MipsISD::VCLT_S:            return "MipsISD::VCLT_S";
00189   case MipsISD::VCLT_U:            return "MipsISD::VCLT_U";
00190   case MipsISD::VSMAX:             return "MipsISD::VSMAX";
00191   case MipsISD::VSMIN:             return "MipsISD::VSMIN";
00192   case MipsISD::VUMAX:             return "MipsISD::VUMAX";
00193   case MipsISD::VUMIN:             return "MipsISD::VUMIN";
00194   case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
00195   case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
00196   case MipsISD::VNOR:              return "MipsISD::VNOR";
00197   case MipsISD::VSHF:              return "MipsISD::VSHF";
00198   case MipsISD::SHF:               return "MipsISD::SHF";
00199   case MipsISD::ILVEV:             return "MipsISD::ILVEV";
00200   case MipsISD::ILVOD:             return "MipsISD::ILVOD";
00201   case MipsISD::ILVL:              return "MipsISD::ILVL";
00202   case MipsISD::ILVR:              return "MipsISD::ILVR";
00203   case MipsISD::PCKEV:             return "MipsISD::PCKEV";
00204   case MipsISD::PCKOD:             return "MipsISD::PCKOD";
00205   case MipsISD::INSVE:             return "MipsISD::INSVE";
00206   default:                         return NULL;
00207   }
00208 }
00209 
00210 MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
00211     : TargetLowering(TM, new MipsTargetObjectFile()),
00212       Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
00213   // Mips does not have i1 type, so use i32 for
00214   // setcc operations results (slt, sgt, ...).
00215   setBooleanContents(ZeroOrOneBooleanContent);
00216   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
00217 
00218   // Load extented operations for i1 types must be promoted
00219   setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
00220   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
00221   setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
00222 
00223   // MIPS doesn't have extending float->double load/store
00224   setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
00225   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
00226 
00227   // Used by legalize types to correctly generate the setcc result.
00228   // Without this, every float setcc comes with a AND/OR with the result,
00229   // we don't want this, since the fpcmp result goes to a flag register,
00230   // which is used implicitly by brcond and select operations.
00231   AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
00232 
00233   // Mips Custom Operations
00234   setOperationAction(ISD::BR_JT,              MVT::Other, Custom);
00235   setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
00236   setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
00237   setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
00238   setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
00239   setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
00240   setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
00241   setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
00242   setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
00243   setOperationAction(ISD::SELECT_CC,          MVT::f32,   Custom);
00244   setOperationAction(ISD::SELECT_CC,          MVT::f64,   Custom);
00245   setOperationAction(ISD::SETCC,              MVT::f32,   Custom);
00246   setOperationAction(ISD::SETCC,              MVT::f64,   Custom);
00247   setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
00248   setOperationAction(ISD::VASTART,            MVT::Other, Custom);
00249   setOperationAction(ISD::FCOPYSIGN,          MVT::f32,   Custom);
00250   setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);
00251   setOperationAction(ISD::FP_TO_SINT,         MVT::i32,   Custom);
00252 
00253   if (isGP64bit()) {
00254     setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);
00255     setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
00256     setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);
00257     setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);
00258     setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);
00259     setOperationAction(ISD::SELECT,             MVT::i64,   Custom);
00260     setOperationAction(ISD::LOAD,               MVT::i64,   Custom);
00261     setOperationAction(ISD::STORE,              MVT::i64,   Custom);
00262     setOperationAction(ISD::FP_TO_SINT,         MVT::i64,   Custom);
00263   }
00264 
00265   if (!isGP64bit()) {
00266     setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);
00267     setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);
00268     setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);
00269   }
00270 
00271   setOperationAction(ISD::ADD,                MVT::i32,   Custom);
00272   if (isGP64bit())
00273     setOperationAction(ISD::ADD,                MVT::i64,   Custom);
00274 
00275   setOperationAction(ISD::SDIV, MVT::i32, Expand);
00276   setOperationAction(ISD::SREM, MVT::i32, Expand);
00277   setOperationAction(ISD::UDIV, MVT::i32, Expand);
00278   setOperationAction(ISD::UREM, MVT::i32, Expand);
00279   setOperationAction(ISD::SDIV, MVT::i64, Expand);
00280   setOperationAction(ISD::SREM, MVT::i64, Expand);
00281   setOperationAction(ISD::UDIV, MVT::i64, Expand);
00282   setOperationAction(ISD::UREM, MVT::i64, Expand);
00283 
00284   // Operations not directly supported by Mips.
00285   setOperationAction(ISD::BR_CC,             MVT::f32,   Expand);
00286   setOperationAction(ISD::BR_CC,             MVT::f64,   Expand);
00287   setOperationAction(ISD::BR_CC,             MVT::i32,   Expand);
00288   setOperationAction(ISD::BR_CC,             MVT::i64,   Expand);
00289   setOperationAction(ISD::SELECT_CC,         MVT::Other, Expand);
00290   setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
00291   setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);
00292   setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
00293   setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);
00294   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
00295   if (Subtarget->hasCnMips()) {
00296     setOperationAction(ISD::CTPOP,           MVT::i32,   Legal);
00297     setOperationAction(ISD::CTPOP,           MVT::i64,   Legal);
00298   } else {
00299     setOperationAction(ISD::CTPOP,           MVT::i32,   Expand);
00300     setOperationAction(ISD::CTPOP,           MVT::i64,   Expand);
00301   }
00302   setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
00303   setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);
00304   setOperationAction(ISD::CTTZ_ZERO_UNDEF,   MVT::i32,   Expand);
00305   setOperationAction(ISD::CTTZ_ZERO_UNDEF,   MVT::i64,   Expand);
00306   setOperationAction(ISD::CTLZ_ZERO_UNDEF,   MVT::i32,   Expand);
00307   setOperationAction(ISD::CTLZ_ZERO_UNDEF,   MVT::i64,   Expand);
00308   setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
00309   setOperationAction(ISD::ROTL,              MVT::i64,   Expand);
00310   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);
00311   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);
00312 
00313   if (!Subtarget->hasMips32r2())
00314     setOperationAction(ISD::ROTR, MVT::i32,   Expand);
00315 
00316   if (!Subtarget->hasMips64r2())
00317     setOperationAction(ISD::ROTR, MVT::i64,   Expand);
00318 
00319   setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
00320   setOperationAction(ISD::FSIN,              MVT::f64,   Expand);
00321   setOperationAction(ISD::FCOS,              MVT::f32,   Expand);
00322   setOperationAction(ISD::FCOS,              MVT::f64,   Expand);
00323   setOperationAction(ISD::FSINCOS,           MVT::f32,   Expand);
00324   setOperationAction(ISD::FSINCOS,           MVT::f64,   Expand);
00325   setOperationAction(ISD::FPOWI,             MVT::f32,   Expand);
00326   setOperationAction(ISD::FPOW,              MVT::f32,   Expand);
00327   setOperationAction(ISD::FPOW,              MVT::f64,   Expand);
00328   setOperationAction(ISD::FLOG,              MVT::f32,   Expand);
00329   setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);
00330   setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);
00331   setOperationAction(ISD::FEXP,              MVT::f32,   Expand);
00332   setOperationAction(ISD::FMA,               MVT::f32,   Expand);
00333   setOperationAction(ISD::FMA,               MVT::f64,   Expand);
00334   setOperationAction(ISD::FREM,              MVT::f32,   Expand);
00335   setOperationAction(ISD::FREM,              MVT::f64,   Expand);
00336 
00337   setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
00338 
00339   setOperationAction(ISD::VAARG,             MVT::Other, Expand);
00340   setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
00341   setOperationAction(ISD::VAEND,             MVT::Other, Expand);
00342 
00343   // Use the default for now
00344   setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
00345   setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
00346 
00347   setOperationAction(ISD::ATOMIC_LOAD,       MVT::i32,    Expand);
00348   setOperationAction(ISD::ATOMIC_LOAD,       MVT::i64,    Expand);
00349   setOperationAction(ISD::ATOMIC_STORE,      MVT::i32,    Expand);
00350   setOperationAction(ISD::ATOMIC_STORE,      MVT::i64,    Expand);
00351 
00352   setInsertFencesForAtomic(true);
00353 
00354   if (!Subtarget->hasSEInReg()) {
00355     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
00356     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
00357   }
00358 
00359   if (!Subtarget->hasBitCount()) {
00360     setOperationAction(ISD::CTLZ, MVT::i32, Expand);
00361     setOperationAction(ISD::CTLZ, MVT::i64, Expand);
00362   }
00363 
00364   if (!Subtarget->hasSwap()) {
00365     setOperationAction(ISD::BSWAP, MVT::i32, Expand);
00366     setOperationAction(ISD::BSWAP, MVT::i64, Expand);
00367   }
00368 
00369   if (isGP64bit()) {
00370     setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
00371     setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
00372     setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
00373     setTruncStoreAction(MVT::i64, MVT::i32, Custom);
00374   }
00375 
00376   setOperationAction(ISD::TRAP, MVT::Other, Legal);
00377 
00378   setTargetDAGCombine(ISD::SDIVREM);
00379   setTargetDAGCombine(ISD::UDIVREM);
00380   setTargetDAGCombine(ISD::SELECT);
00381   setTargetDAGCombine(ISD::AND);
00382   setTargetDAGCombine(ISD::OR);
00383   setTargetDAGCombine(ISD::ADD);
00384 
00385   setMinFunctionAlignment(isGP64bit() ? 3 : 2);
00386 
00387   setStackPointerRegisterToSaveRestore(isN64() ? Mips::SP_64 : Mips::SP);
00388 
00389   setExceptionPointerRegister(isN64() ? Mips::A0_64 : Mips::A0);
00390   setExceptionSelectorRegister(isN64() ? Mips::A1_64 : Mips::A1);
00391 
00392   MaxStoresPerMemcpy = 16;
00393 
00394   isMicroMips = Subtarget->inMicroMipsMode();
00395 }
00396 
00397 const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) {
00398   if (TM.getSubtargetImpl()->inMips16Mode())
00399     return llvm::createMips16TargetLowering(TM);
00400 
00401   return llvm::createMipsSETargetLowering(TM);
00402 }
00403 
00404 // Create a fast isel object.
00405 FastISel *
00406 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
00407                                   const TargetLibraryInfo *libInfo) const {
00408   if (!EnableMipsFastISel)
00409     return TargetLowering::createFastISel(funcInfo, libInfo);
00410   return Mips::createFastISel(funcInfo, libInfo);
00411 }
00412 
00413 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
00414   if (!VT.isVector())
00415     return MVT::i32;
00416   return VT.changeVectorElementTypeToInteger();
00417 }
00418 
00419 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
00420                                     TargetLowering::DAGCombinerInfo &DCI,
00421                                     const MipsSubtarget *Subtarget) {
00422   if (DCI.isBeforeLegalizeOps())
00423     return SDValue();
00424 
00425   EVT Ty = N->getValueType(0);
00426   unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
00427   unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
00428   unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
00429                                                   MipsISD::DivRemU16;
00430   SDLoc DL(N);
00431 
00432   SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
00433                                N->getOperand(0), N->getOperand(1));
00434   SDValue InChain = DAG.getEntryNode();
00435   SDValue InGlue = DivRem;
00436 
00437   // insert MFLO
00438   if (N->hasAnyUseOfValue(0)) {
00439     SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
00440                                             InGlue);
00441     DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
00442     InChain = CopyFromLo.getValue(1);
00443     InGlue = CopyFromLo.getValue(2);
00444   }
00445 
00446   // insert MFHI
00447   if (N->hasAnyUseOfValue(1)) {
00448     SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
00449                                             HI, Ty, InGlue);
00450     DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
00451   }
00452 
00453   return SDValue();
00454 }
00455 
00456 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
00457   switch (CC) {
00458   default: llvm_unreachable("Unknown fp condition code!");
00459   case ISD::SETEQ:
00460   case ISD::SETOEQ: return Mips::FCOND_OEQ;
00461   case ISD::SETUNE: return Mips::FCOND_UNE;
00462   case ISD::SETLT:
00463   case ISD::SETOLT: return Mips::FCOND_OLT;
00464   case ISD::SETGT:
00465   case ISD::SETOGT: return Mips::FCOND_OGT;
00466   case ISD::SETLE:
00467   case ISD::SETOLE: return Mips::FCOND_OLE;
00468   case ISD::SETGE:
00469   case ISD::SETOGE: return Mips::FCOND_OGE;
00470   case ISD::SETULT: return Mips::FCOND_ULT;
00471   case ISD::SETULE: return Mips::FCOND_ULE;
00472   case ISD::SETUGT: return Mips::FCOND_UGT;
00473   case ISD::SETUGE: return Mips::FCOND_UGE;
00474   case ISD::SETUO:  return Mips::FCOND_UN;
00475   case ISD::SETO:   return Mips::FCOND_OR;
00476   case ISD::SETNE:
00477   case ISD::SETONE: return Mips::FCOND_ONE;
00478   case ISD::SETUEQ: return Mips::FCOND_UEQ;
00479   }
00480 }
00481 
00482 
00483 /// This function returns true if the floating point conditional branches and
00484 /// conditional moves which use condition code CC should be inverted.
00485 static bool invertFPCondCodeUser(Mips::CondCode CC) {
00486   if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
00487     return false;
00488 
00489   assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
00490          "Illegal Condition Code");
00491 
00492   return true;
00493 }
00494 
00495 // Creates and returns an FPCmp node from a setcc node.
00496 // Returns Op if setcc is not a floating point comparison.
00497 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
00498   // must be a SETCC node
00499   if (Op.getOpcode() != ISD::SETCC)
00500     return Op;
00501 
00502   SDValue LHS = Op.getOperand(0);
00503 
00504   if (!LHS.getValueType().isFloatingPoint())
00505     return Op;
00506 
00507   SDValue RHS = Op.getOperand(1);
00508   SDLoc DL(Op);
00509 
00510   // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
00511   // node if necessary.
00512   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
00513 
00514   return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
00515                      DAG.getConstant(condCodeToFCC(CC), MVT::i32));
00516 }
00517 
00518 // Creates and returns a CMovFPT/F node.
00519 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
00520                             SDValue False, SDLoc DL) {
00521   ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
00522   bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
00523   SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
00524 
00525   return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
00526                      True.getValueType(), True, FCC0, False, Cond);
00527 }
00528 
00529 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
00530                                     TargetLowering::DAGCombinerInfo &DCI,
00531                                     const MipsSubtarget *Subtarget) {
00532   if (DCI.isBeforeLegalizeOps())
00533     return SDValue();
00534 
00535   SDValue SetCC = N->getOperand(0);
00536 
00537   if ((SetCC.getOpcode() != ISD::SETCC) ||
00538       !SetCC.getOperand(0).getValueType().isInteger())
00539     return SDValue();
00540 
00541   SDValue False = N->getOperand(2);
00542   EVT FalseTy = False.getValueType();
00543 
00544   if (!FalseTy.isInteger())
00545     return SDValue();
00546 
00547   ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
00548 
00549   // If the RHS (False) is 0, we swap the order of the operands
00550   // of ISD::SELECT (obviously also inverting the condition) so that we can
00551   // take advantage of conditional moves using the $0 register.
00552   // Example:
00553   //   return (a != 0) ? x : 0;
00554   //     load $reg, x
00555   //     movz $reg, $0, a
00556   if (!FalseC)
00557     return SDValue();
00558 
00559   const SDLoc DL(N);
00560 
00561   if (!FalseC->getZExtValue()) {
00562     ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
00563     SDValue True = N->getOperand(1);
00564 
00565     SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
00566                          SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
00567 
00568     return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
00569   }
00570 
00571   // If both operands are integer constants there's a possibility that we
00572   // can do some interesting optimizations.
00573   SDValue True = N->getOperand(1);
00574   ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
00575 
00576   if (!TrueC || !True.getValueType().isInteger())
00577     return SDValue();
00578 
00579   // We'll also ignore MVT::i64 operands as this optimizations proves
00580   // to be ineffective because of the required sign extensions as the result
00581   // of a SETCC operator is always MVT::i32 for non-vector types.
00582   if (True.getValueType() == MVT::i64)
00583     return SDValue();
00584 
00585   int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
00586 
00587   // 1)  (a < x) ? y : y-1
00588   //  slti $reg1, a, x
00589   //  addiu $reg2, $reg1, y-1
00590   if (Diff == 1)
00591     return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
00592 
00593   // 2)  (a < x) ? y-1 : y
00594   //  slti $reg1, a, x
00595   //  xor $reg1, $reg1, 1
00596   //  addiu $reg2, $reg1, y-1
00597   if (Diff == -1) {
00598     ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
00599     SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
00600                          SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
00601     return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
00602   }
00603 
00604   // Couldn't optimize.
00605   return SDValue();
00606 }
00607 
00608 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
00609                                  TargetLowering::DAGCombinerInfo &DCI,
00610                                  const MipsSubtarget *Subtarget) {
00611   // Pattern match EXT.
00612   //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
00613   //  => ext $dst, $src, size, pos
00614   if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert())
00615     return SDValue();
00616 
00617   SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
00618   unsigned ShiftRightOpc = ShiftRight.getOpcode();
00619 
00620   // Op's first operand must be a shift right.
00621   if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
00622     return SDValue();
00623 
00624   // The second operand of the shift must be an immediate.
00625   ConstantSDNode *CN;
00626   if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
00627     return SDValue();
00628 
00629   uint64_t Pos = CN->getZExtValue();
00630   uint64_t SMPos, SMSize;
00631 
00632   // Op's second operand must be a shifted mask.
00633   if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
00634       !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
00635     return SDValue();
00636 
00637   // Return if the shifted mask does not start at bit 0 or the sum of its size
00638   // and Pos exceeds the word's size.
00639   EVT ValTy = N->getValueType(0);
00640   if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
00641     return SDValue();
00642 
00643   return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
00644                      ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
00645                      DAG.getConstant(SMSize, MVT::i32));
00646 }
00647 
00648 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
00649                                 TargetLowering::DAGCombinerInfo &DCI,
00650                                 const MipsSubtarget *Subtarget) {
00651   // Pattern match INS.
00652   //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
00653   //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1
00654   //  => ins $dst, $src, size, pos, $src1
00655   if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert())
00656     return SDValue();
00657 
00658   SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
00659   uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
00660   ConstantSDNode *CN;
00661 
00662   // See if Op's first operand matches (and $src1 , mask0).
00663   if (And0.getOpcode() != ISD::AND)
00664     return SDValue();
00665 
00666   if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
00667       !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
00668     return SDValue();
00669 
00670   // See if Op's second operand matches (and (shl $src, pos), mask1).
00671   if (And1.getOpcode() != ISD::AND)
00672     return SDValue();
00673 
00674   if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
00675       !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
00676     return SDValue();
00677 
00678   // The shift masks must have the same position and size.
00679   if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
00680     return SDValue();
00681 
00682   SDValue Shl = And1.getOperand(0);
00683   if (Shl.getOpcode() != ISD::SHL)
00684     return SDValue();
00685 
00686   if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
00687     return SDValue();
00688 
00689   unsigned Shamt = CN->getZExtValue();
00690 
00691   // Return if the shift amount and the first bit position of mask are not the
00692   // same.
00693   EVT ValTy = N->getValueType(0);
00694   if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
00695     return SDValue();
00696 
00697   return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
00698                      DAG.getConstant(SMPos0, MVT::i32),
00699                      DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
00700 }
00701 
00702 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
00703                                  TargetLowering::DAGCombinerInfo &DCI,
00704                                  const MipsSubtarget *Subtarget) {
00705   // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
00706 
00707   if (DCI.isBeforeLegalizeOps())
00708     return SDValue();
00709 
00710   SDValue Add = N->getOperand(1);
00711 
00712   if (Add.getOpcode() != ISD::ADD)
00713     return SDValue();
00714 
00715   SDValue Lo = Add.getOperand(1);
00716 
00717   if ((Lo.getOpcode() != MipsISD::Lo) ||
00718       (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
00719     return SDValue();
00720 
00721   EVT ValTy = N->getValueType(0);
00722   SDLoc DL(N);
00723 
00724   SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
00725                              Add.getOperand(0));
00726   return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
00727 }
00728 
00729 SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
00730   const {
00731   SelectionDAG &DAG = DCI.DAG;
00732   unsigned Opc = N->getOpcode();
00733 
00734   switch (Opc) {
00735   default: break;
00736   case ISD::SDIVREM:
00737   case ISD::UDIVREM:
00738     return performDivRemCombine(N, DAG, DCI, Subtarget);
00739   case ISD::SELECT:
00740     return performSELECTCombine(N, DAG, DCI, Subtarget);
00741   case ISD::AND:
00742     return performANDCombine(N, DAG, DCI, Subtarget);
00743   case ISD::OR:
00744     return performORCombine(N, DAG, DCI, Subtarget);
00745   case ISD::ADD:
00746     return performADDCombine(N, DAG, DCI, Subtarget);
00747   }
00748 
00749   return SDValue();
00750 }
00751 
00752 void
00753 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
00754                                           SmallVectorImpl<SDValue> &Results,
00755                                           SelectionDAG &DAG) const {
00756   SDValue Res = LowerOperation(SDValue(N, 0), DAG);
00757 
00758   for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
00759     Results.push_back(Res.getValue(I));
00760 }
00761 
00762 void
00763 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
00764                                        SmallVectorImpl<SDValue> &Results,
00765                                        SelectionDAG &DAG) const {
00766   return LowerOperationWrapper(N, Results, DAG);
00767 }
00768 
00769 SDValue MipsTargetLowering::
00770 LowerOperation(SDValue Op, SelectionDAG &DAG) const
00771 {
00772   switch (Op.getOpcode())
00773   {
00774   case ISD::BR_JT:              return lowerBR_JT(Op, DAG);
00775   case ISD::BRCOND:             return lowerBRCOND(Op, DAG);
00776   case ISD::ConstantPool:       return lowerConstantPool(Op, DAG);
00777   case ISD::GlobalAddress:      return lowerGlobalAddress(Op, DAG);
00778   case ISD::BlockAddress:       return lowerBlockAddress(Op, DAG);
00779   case ISD::GlobalTLSAddress:   return lowerGlobalTLSAddress(Op, DAG);
00780   case ISD::JumpTable:          return lowerJumpTable(Op, DAG);
00781   case ISD::SELECT:             return lowerSELECT(Op, DAG);
00782   case ISD::SELECT_CC:          return lowerSELECT_CC(Op, DAG);
00783   case ISD::SETCC:              return lowerSETCC(Op, DAG);
00784   case ISD::VASTART:            return lowerVASTART(Op, DAG);
00785   case ISD::FCOPYSIGN:          return lowerFCOPYSIGN(Op, DAG);
00786   case ISD::FRAMEADDR:          return lowerFRAMEADDR(Op, DAG);
00787   case ISD::RETURNADDR:         return lowerRETURNADDR(Op, DAG);
00788   case ISD::EH_RETURN:          return lowerEH_RETURN(Op, DAG);
00789   case ISD::ATOMIC_FENCE:       return lowerATOMIC_FENCE(Op, DAG);
00790   case ISD::SHL_PARTS:          return lowerShiftLeftParts(Op, DAG);
00791   case ISD::SRA_PARTS:          return lowerShiftRightParts(Op, DAG, true);
00792   case ISD::SRL_PARTS:          return lowerShiftRightParts(Op, DAG, false);
00793   case ISD::LOAD:               return lowerLOAD(Op, DAG);
00794   case ISD::STORE:              return lowerSTORE(Op, DAG);
00795   case ISD::ADD:                return lowerADD(Op, DAG);
00796   case ISD::FP_TO_SINT:         return lowerFP_TO_SINT(Op, DAG);
00797   }
00798   return SDValue();
00799 }
00800 
00801 //===----------------------------------------------------------------------===//
00802 //  Lower helper functions
00803 //===----------------------------------------------------------------------===//
00804 
00805 // addLiveIn - This helper function adds the specified physical register to the
00806 // MachineFunction as a live in value.  It also creates a corresponding
00807 // virtual register for it.
00808 static unsigned
00809 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
00810 {
00811   unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
00812   MF.getRegInfo().addLiveIn(PReg, VReg);
00813   return VReg;
00814 }
00815 
00816 static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI,
00817                                           MachineBasicBlock &MBB,
00818                                           const TargetInstrInfo &TII,
00819                                           bool Is64Bit) {
00820   if (NoZeroDivCheck)
00821     return &MBB;
00822 
00823   // Insert instruction "teq $divisor_reg, $zero, 7".
00824   MachineBasicBlock::iterator I(MI);
00825   MachineInstrBuilder MIB;
00826   MachineOperand &Divisor = MI->getOperand(2);
00827   MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
00828     .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
00829     .addReg(Mips::ZERO).addImm(7);
00830 
00831   // Use the 32-bit sub-register if this is a 64-bit division.
00832   if (Is64Bit)
00833     MIB->getOperand(0).setSubReg(Mips::sub_32);
00834 
00835   // Clear Divisor's kill flag.
00836   Divisor.setIsKill(false);
00837   return &MBB;
00838 }
00839 
00840 MachineBasicBlock *
00841 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
00842                                                 MachineBasicBlock *BB) const {
00843   switch (MI->getOpcode()) {
00844   default:
00845     llvm_unreachable("Unexpected instr type to insert");
00846   case Mips::ATOMIC_LOAD_ADD_I8:
00847     return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
00848   case Mips::ATOMIC_LOAD_ADD_I16:
00849     return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
00850   case Mips::ATOMIC_LOAD_ADD_I32:
00851     return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
00852   case Mips::ATOMIC_LOAD_ADD_I64:
00853     return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
00854 
00855   case Mips::ATOMIC_LOAD_AND_I8:
00856     return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
00857   case Mips::ATOMIC_LOAD_AND_I16:
00858     return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
00859   case Mips::ATOMIC_LOAD_AND_I32:
00860     return emitAtomicBinary(MI, BB, 4, Mips::AND);
00861   case Mips::ATOMIC_LOAD_AND_I64:
00862     return emitAtomicBinary(MI, BB, 8, Mips::AND64);
00863 
00864   case Mips::ATOMIC_LOAD_OR_I8:
00865     return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
00866   case Mips::ATOMIC_LOAD_OR_I16:
00867     return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
00868   case Mips::ATOMIC_LOAD_OR_I32:
00869     return emitAtomicBinary(MI, BB, 4, Mips::OR);
00870   case Mips::ATOMIC_LOAD_OR_I64:
00871     return emitAtomicBinary(MI, BB, 8, Mips::OR64);
00872 
00873   case Mips::ATOMIC_LOAD_XOR_I8:
00874     return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
00875   case Mips::ATOMIC_LOAD_XOR_I16:
00876     return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
00877   case Mips::ATOMIC_LOAD_XOR_I32:
00878     return emitAtomicBinary(MI, BB, 4, Mips::XOR);
00879   case Mips::ATOMIC_LOAD_XOR_I64:
00880     return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
00881 
00882   case Mips::ATOMIC_LOAD_NAND_I8:
00883     return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
00884   case Mips::ATOMIC_LOAD_NAND_I16:
00885     return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
00886   case Mips::ATOMIC_LOAD_NAND_I32:
00887     return emitAtomicBinary(MI, BB, 4, 0, true);
00888   case Mips::ATOMIC_LOAD_NAND_I64:
00889     return emitAtomicBinary(MI, BB, 8, 0, true);
00890 
00891   case Mips::ATOMIC_LOAD_SUB_I8:
00892     return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
00893   case Mips::ATOMIC_LOAD_SUB_I16:
00894     return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
00895   case Mips::ATOMIC_LOAD_SUB_I32:
00896     return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
00897   case Mips::ATOMIC_LOAD_SUB_I64:
00898     return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
00899 
00900   case Mips::ATOMIC_SWAP_I8:
00901     return emitAtomicBinaryPartword(MI, BB, 1, 0);
00902   case Mips::ATOMIC_SWAP_I16:
00903     return emitAtomicBinaryPartword(MI, BB, 2, 0);
00904   case Mips::ATOMIC_SWAP_I32:
00905     return emitAtomicBinary(MI, BB, 4, 0);
00906   case Mips::ATOMIC_SWAP_I64:
00907     return emitAtomicBinary(MI, BB, 8, 0);
00908 
00909   case Mips::ATOMIC_CMP_SWAP_I8:
00910     return emitAtomicCmpSwapPartword(MI, BB, 1);
00911   case Mips::ATOMIC_CMP_SWAP_I16:
00912     return emitAtomicCmpSwapPartword(MI, BB, 2);
00913   case Mips::ATOMIC_CMP_SWAP_I32:
00914     return emitAtomicCmpSwap(MI, BB, 4);
00915   case Mips::ATOMIC_CMP_SWAP_I64:
00916     return emitAtomicCmpSwap(MI, BB, 8);
00917   case Mips::PseudoSDIV:
00918   case Mips::PseudoUDIV:
00919     return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false);
00920   case Mips::PseudoDSDIV:
00921   case Mips::PseudoDUDIV:
00922     return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true);
00923   }
00924 }
00925 
00926 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
00927 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
00928 MachineBasicBlock *
00929 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
00930                                      unsigned Size, unsigned BinOpcode,
00931                                      bool Nand) const {
00932   assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
00933 
00934   MachineFunction *MF = BB->getParent();
00935   MachineRegisterInfo &RegInfo = MF->getRegInfo();
00936   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
00937   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
00938   DebugLoc DL = MI->getDebugLoc();
00939   unsigned LL, SC, AND, NOR, ZERO, BEQ;
00940 
00941   if (Size == 4) {
00942     LL = isMicroMips ? Mips::LL_MM : Mips::LL;
00943     SC = isMicroMips ? Mips::SC_MM : Mips::SC;
00944     AND = Mips::AND;
00945     NOR = Mips::NOR;
00946     ZERO = Mips::ZERO;
00947     BEQ = Mips::BEQ;
00948   }
00949   else {
00950     LL = Mips::LLD;
00951     SC = Mips::SCD;
00952     AND = Mips::AND64;
00953     NOR = Mips::NOR64;
00954     ZERO = Mips::ZERO_64;
00955     BEQ = Mips::BEQ64;
00956   }
00957 
00958   unsigned OldVal = MI->getOperand(0).getReg();
00959   unsigned Ptr = MI->getOperand(1).getReg();
00960   unsigned Incr = MI->getOperand(2).getReg();
00961 
00962   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
00963   unsigned AndRes = RegInfo.createVirtualRegister(RC);
00964   unsigned Success = RegInfo.createVirtualRegister(RC);
00965 
00966   // insert new blocks after the current block
00967   const BasicBlock *LLVM_BB = BB->getBasicBlock();
00968   MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
00969   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
00970   MachineFunction::iterator It = BB;
00971   ++It;
00972   MF->insert(It, loopMBB);
00973   MF->insert(It, exitMBB);
00974 
00975   // Transfer the remainder of BB and its successor edges to exitMBB.
00976   exitMBB->splice(exitMBB->begin(), BB,
00977                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
00978   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
00979 
00980   //  thisMBB:
00981   //    ...
00982   //    fallthrough --> loopMBB
00983   BB->addSuccessor(loopMBB);
00984   loopMBB->addSuccessor(loopMBB);
00985   loopMBB->addSuccessor(exitMBB);
00986 
00987   //  loopMBB:
00988   //    ll oldval, 0(ptr)
00989   //    <binop> storeval, oldval, incr
00990   //    sc success, storeval, 0(ptr)
00991   //    beq success, $0, loopMBB
00992   BB = loopMBB;
00993   BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
00994   if (Nand) {
00995     //  and andres, oldval, incr
00996     //  nor storeval, $0, andres
00997     BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
00998     BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
00999   } else if (BinOpcode) {
01000     //  <binop> storeval, oldval, incr
01001     BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
01002   } else {
01003     StoreVal = Incr;
01004   }
01005   BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
01006   BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
01007 
01008   MI->eraseFromParent(); // The instruction is gone now.
01009 
01010   return exitMBB;
01011 }
01012 
01013 MachineBasicBlock *
01014 MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI,
01015                                              MachineBasicBlock *BB,
01016                                              unsigned Size, unsigned BinOpcode,
01017                                              bool Nand) const {
01018   assert((Size == 1 || Size == 2) &&
01019          "Unsupported size for EmitAtomicBinaryPartial.");
01020 
01021   MachineFunction *MF = BB->getParent();
01022   MachineRegisterInfo &RegInfo = MF->getRegInfo();
01023   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
01024   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
01025   DebugLoc DL = MI->getDebugLoc();
01026 
01027   unsigned Dest = MI->getOperand(0).getReg();
01028   unsigned Ptr = MI->getOperand(1).getReg();
01029   unsigned Incr = MI->getOperand(2).getReg();
01030 
01031   unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
01032   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
01033   unsigned Mask = RegInfo.createVirtualRegister(RC);
01034   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
01035   unsigned NewVal = RegInfo.createVirtualRegister(RC);
01036   unsigned OldVal = RegInfo.createVirtualRegister(RC);
01037   unsigned Incr2 = RegInfo.createVirtualRegister(RC);
01038   unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
01039   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
01040   unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
01041   unsigned AndRes = RegInfo.createVirtualRegister(RC);
01042   unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
01043   unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
01044   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
01045   unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
01046   unsigned SrlRes = RegInfo.createVirtualRegister(RC);
01047   unsigned SllRes = RegInfo.createVirtualRegister(RC);
01048   unsigned Success = RegInfo.createVirtualRegister(RC);
01049 
01050   // insert new blocks after the current block
01051   const BasicBlock *LLVM_BB = BB->getBasicBlock();
01052   MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01053   MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01054   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01055   MachineFunction::iterator It = BB;
01056   ++It;
01057   MF->insert(It, loopMBB);
01058   MF->insert(It, sinkMBB);
01059   MF->insert(It, exitMBB);
01060 
01061   // Transfer the remainder of BB and its successor edges to exitMBB.
01062   exitMBB->splice(exitMBB->begin(), BB,
01063                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
01064   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
01065 
01066   BB->addSuccessor(loopMBB);
01067   loopMBB->addSuccessor(loopMBB);
01068   loopMBB->addSuccessor(sinkMBB);
01069   sinkMBB->addSuccessor(exitMBB);
01070 
01071   //  thisMBB:
01072   //    addiu   masklsb2,$0,-4                # 0xfffffffc
01073   //    and     alignedaddr,ptr,masklsb2
01074   //    andi    ptrlsb2,ptr,3
01075   //    sll     shiftamt,ptrlsb2,3
01076   //    ori     maskupper,$0,255               # 0xff
01077   //    sll     mask,maskupper,shiftamt
01078   //    nor     mask2,$0,mask
01079   //    sll     incr2,incr,shiftamt
01080 
01081   int64_t MaskImm = (Size == 1) ? 255 : 65535;
01082   BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
01083     .addReg(Mips::ZERO).addImm(-4);
01084   BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
01085     .addReg(Ptr).addReg(MaskLSB2);
01086   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
01087   if (Subtarget->isLittle()) {
01088     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
01089   } else {
01090     unsigned Off = RegInfo.createVirtualRegister(RC);
01091     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
01092       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
01093     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
01094   }
01095   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
01096     .addReg(Mips::ZERO).addImm(MaskImm);
01097   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
01098     .addReg(MaskUpper).addReg(ShiftAmt);
01099   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
01100   BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
01101 
01102   // atomic.load.binop
01103   // loopMBB:
01104   //   ll      oldval,0(alignedaddr)
01105   //   binop   binopres,oldval,incr2
01106   //   and     newval,binopres,mask
01107   //   and     maskedoldval0,oldval,mask2
01108   //   or      storeval,maskedoldval0,newval
01109   //   sc      success,storeval,0(alignedaddr)
01110   //   beq     success,$0,loopMBB
01111 
01112   // atomic.swap
01113   // loopMBB:
01114   //   ll      oldval,0(alignedaddr)
01115   //   and     newval,incr2,mask
01116   //   and     maskedoldval0,oldval,mask2
01117   //   or      storeval,maskedoldval0,newval
01118   //   sc      success,storeval,0(alignedaddr)
01119   //   beq     success,$0,loopMBB
01120 
01121   BB = loopMBB;
01122   BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
01123   if (Nand) {
01124     //  and andres, oldval, incr2
01125     //  nor binopres, $0, andres
01126     //  and newval, binopres, mask
01127     BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
01128     BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
01129       .addReg(Mips::ZERO).addReg(AndRes);
01130     BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
01131   } else if (BinOpcode) {
01132     //  <binop> binopres, oldval, incr2
01133     //  and newval, binopres, mask
01134     BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
01135     BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
01136   } else { // atomic.swap
01137     //  and newval, incr2, mask
01138     BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
01139   }
01140 
01141   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
01142     .addReg(OldVal).addReg(Mask2);
01143   BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
01144     .addReg(MaskedOldVal0).addReg(NewVal);
01145   BuildMI(BB, DL, TII->get(Mips::SC), Success)
01146     .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
01147   BuildMI(BB, DL, TII->get(Mips::BEQ))
01148     .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
01149 
01150   //  sinkMBB:
01151   //    and     maskedoldval1,oldval,mask
01152   //    srl     srlres,maskedoldval1,shiftamt
01153   //    sll     sllres,srlres,24
01154   //    sra     dest,sllres,24
01155   BB = sinkMBB;
01156   int64_t ShiftImm = (Size == 1) ? 24 : 16;
01157 
01158   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
01159     .addReg(OldVal).addReg(Mask);
01160   BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
01161       .addReg(MaskedOldVal1).addReg(ShiftAmt);
01162   BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
01163       .addReg(SrlRes).addImm(ShiftImm);
01164   BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
01165       .addReg(SllRes).addImm(ShiftImm);
01166 
01167   MI->eraseFromParent(); // The instruction is gone now.
01168 
01169   return exitMBB;
01170 }
01171 
01172 MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
01173                                                           MachineBasicBlock *BB,
01174                                                           unsigned Size) const {
01175   assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
01176 
01177   MachineFunction *MF = BB->getParent();
01178   MachineRegisterInfo &RegInfo = MF->getRegInfo();
01179   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
01180   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
01181   DebugLoc DL = MI->getDebugLoc();
01182   unsigned LL, SC, ZERO, BNE, BEQ;
01183 
01184   if (Size == 4) {
01185     LL = isMicroMips ? Mips::LL_MM : Mips::LL;
01186     SC = isMicroMips ? Mips::SC_MM : Mips::SC;
01187     ZERO = Mips::ZERO;
01188     BNE = Mips::BNE;
01189     BEQ = Mips::BEQ;
01190   } else {
01191     LL = Mips::LLD;
01192     SC = Mips::SCD;
01193     ZERO = Mips::ZERO_64;
01194     BNE = Mips::BNE64;
01195     BEQ = Mips::BEQ64;
01196   }
01197 
01198   unsigned Dest    = MI->getOperand(0).getReg();
01199   unsigned Ptr     = MI->getOperand(1).getReg();
01200   unsigned OldVal  = MI->getOperand(2).getReg();
01201   unsigned NewVal  = MI->getOperand(3).getReg();
01202 
01203   unsigned Success = RegInfo.createVirtualRegister(RC);
01204 
01205   // insert new blocks after the current block
01206   const BasicBlock *LLVM_BB = BB->getBasicBlock();
01207   MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
01208   MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
01209   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01210   MachineFunction::iterator It = BB;
01211   ++It;
01212   MF->insert(It, loop1MBB);
01213   MF->insert(It, loop2MBB);
01214   MF->insert(It, exitMBB);
01215 
01216   // Transfer the remainder of BB and its successor edges to exitMBB.
01217   exitMBB->splice(exitMBB->begin(), BB,
01218                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
01219   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
01220 
01221   //  thisMBB:
01222   //    ...
01223   //    fallthrough --> loop1MBB
01224   BB->addSuccessor(loop1MBB);
01225   loop1MBB->addSuccessor(exitMBB);
01226   loop1MBB->addSuccessor(loop2MBB);
01227   loop2MBB->addSuccessor(loop1MBB);
01228   loop2MBB->addSuccessor(exitMBB);
01229 
01230   // loop1MBB:
01231   //   ll dest, 0(ptr)
01232   //   bne dest, oldval, exitMBB
01233   BB = loop1MBB;
01234   BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
01235   BuildMI(BB, DL, TII->get(BNE))
01236     .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
01237 
01238   // loop2MBB:
01239   //   sc success, newval, 0(ptr)
01240   //   beq success, $0, loop1MBB
01241   BB = loop2MBB;
01242   BuildMI(BB, DL, TII->get(SC), Success)
01243     .addReg(NewVal).addReg(Ptr).addImm(0);
01244   BuildMI(BB, DL, TII->get(BEQ))
01245     .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
01246 
01247   MI->eraseFromParent(); // The instruction is gone now.
01248 
01249   return exitMBB;
01250 }
01251 
01252 MachineBasicBlock *
01253 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
01254                                               MachineBasicBlock *BB,
01255                                               unsigned Size) const {
01256   assert((Size == 1 || Size == 2) &&
01257       "Unsupported size for EmitAtomicCmpSwapPartial.");
01258 
01259   MachineFunction *MF = BB->getParent();
01260   MachineRegisterInfo &RegInfo = MF->getRegInfo();
01261   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
01262   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
01263   DebugLoc DL = MI->getDebugLoc();
01264 
01265   unsigned Dest    = MI->getOperand(0).getReg();
01266   unsigned Ptr     = MI->getOperand(1).getReg();
01267   unsigned CmpVal  = MI->getOperand(2).getReg();
01268   unsigned NewVal  = MI->getOperand(3).getReg();
01269 
01270   unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
01271   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
01272   unsigned Mask = RegInfo.createVirtualRegister(RC);
01273   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
01274   unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
01275   unsigned OldVal = RegInfo.createVirtualRegister(RC);
01276   unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
01277   unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
01278   unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
01279   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
01280   unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
01281   unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
01282   unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
01283   unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
01284   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
01285   unsigned SrlRes = RegInfo.createVirtualRegister(RC);
01286   unsigned SllRes = RegInfo.createVirtualRegister(RC);
01287   unsigned Success = RegInfo.createVirtualRegister(RC);
01288 
01289   // insert new blocks after the current block
01290   const BasicBlock *LLVM_BB = BB->getBasicBlock();
01291   MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
01292   MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
01293   MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01294   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01295   MachineFunction::iterator It = BB;
01296   ++It;
01297   MF->insert(It, loop1MBB);
01298   MF->insert(It, loop2MBB);
01299   MF->insert(It, sinkMBB);
01300   MF->insert(It, exitMBB);
01301 
01302   // Transfer the remainder of BB and its successor edges to exitMBB.
01303   exitMBB->splice(exitMBB->begin(), BB,
01304                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
01305   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
01306 
01307   BB->addSuccessor(loop1MBB);
01308   loop1MBB->addSuccessor(sinkMBB);
01309   loop1MBB->addSuccessor(loop2MBB);
01310   loop2MBB->addSuccessor(loop1MBB);
01311   loop2MBB->addSuccessor(sinkMBB);
01312   sinkMBB->addSuccessor(exitMBB);
01313 
01314   // FIXME: computation of newval2 can be moved to loop2MBB.
01315   //  thisMBB:
01316   //    addiu   masklsb2,$0,-4                # 0xfffffffc
01317   //    and     alignedaddr,ptr,masklsb2
01318   //    andi    ptrlsb2,ptr,3
01319   //    sll     shiftamt,ptrlsb2,3
01320   //    ori     maskupper,$0,255               # 0xff
01321   //    sll     mask,maskupper,shiftamt
01322   //    nor     mask2,$0,mask
01323   //    andi    maskedcmpval,cmpval,255
01324   //    sll     shiftedcmpval,maskedcmpval,shiftamt
01325   //    andi    maskednewval,newval,255
01326   //    sll     shiftednewval,maskednewval,shiftamt
01327   int64_t MaskImm = (Size == 1) ? 255 : 65535;
01328   BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
01329     .addReg(Mips::ZERO).addImm(-4);
01330   BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
01331     .addReg(Ptr).addReg(MaskLSB2);
01332   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
01333   if (Subtarget->isLittle()) {
01334     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
01335   } else {
01336     unsigned Off = RegInfo.createVirtualRegister(RC);
01337     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
01338       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
01339     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
01340   }
01341   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
01342     .addReg(Mips::ZERO).addImm(MaskImm);
01343   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
01344     .addReg(MaskUpper).addReg(ShiftAmt);
01345   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
01346   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
01347     .addReg(CmpVal).addImm(MaskImm);
01348   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
01349     .addReg(MaskedCmpVal).addReg(ShiftAmt);
01350   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
01351     .addReg(NewVal).addImm(MaskImm);
01352   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
01353     .addReg(MaskedNewVal).addReg(ShiftAmt);
01354 
01355   //  loop1MBB:
01356   //    ll      oldval,0(alginedaddr)
01357   //    and     maskedoldval0,oldval,mask
01358   //    bne     maskedoldval0,shiftedcmpval,sinkMBB
01359   BB = loop1MBB;
01360   BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
01361   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
01362     .addReg(OldVal).addReg(Mask);
01363   BuildMI(BB, DL, TII->get(Mips::BNE))
01364     .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
01365 
01366   //  loop2MBB:
01367   //    and     maskedoldval1,oldval,mask2
01368   //    or      storeval,maskedoldval1,shiftednewval
01369   //    sc      success,storeval,0(alignedaddr)
01370   //    beq     success,$0,loop1MBB
01371   BB = loop2MBB;
01372   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
01373     .addReg(OldVal).addReg(Mask2);
01374   BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
01375     .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
01376   BuildMI(BB, DL, TII->get(Mips::SC), Success)
01377       .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
01378   BuildMI(BB, DL, TII->get(Mips::BEQ))
01379       .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
01380 
01381   //  sinkMBB:
01382   //    srl     srlres,maskedoldval0,shiftamt
01383   //    sll     sllres,srlres,24
01384   //    sra     dest,sllres,24
01385   BB = sinkMBB;
01386   int64_t ShiftImm = (Size == 1) ? 24 : 16;
01387 
01388   BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
01389       .addReg(MaskedOldVal0).addReg(ShiftAmt);
01390   BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
01391       .addReg(SrlRes).addImm(ShiftImm);
01392   BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
01393       .addReg(SllRes).addImm(ShiftImm);
01394 
01395   MI->eraseFromParent();   // The instruction is gone now.
01396 
01397   return exitMBB;
01398 }
01399 
01400 //===----------------------------------------------------------------------===//
01401 //  Misc Lower Operation implementation
01402 //===----------------------------------------------------------------------===//
01403 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
01404   SDValue Chain = Op.getOperand(0);
01405   SDValue Table = Op.getOperand(1);
01406   SDValue Index = Op.getOperand(2);
01407   SDLoc DL(Op);
01408   EVT PTy = getPointerTy();
01409   unsigned EntrySize =
01410     DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
01411 
01412   Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
01413                       DAG.getConstant(EntrySize, PTy));
01414   SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
01415 
01416   EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
01417   Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
01418                         MachinePointerInfo::getJumpTable(), MemVT, false, false,
01419                         0);
01420   Chain = Addr.getValue(1);
01421 
01422   if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || isN64()) {
01423     // For PIC, the sequence is:
01424     // BRIND(load(Jumptable + index) + RelocBase)
01425     // RelocBase can be JumpTable, GOT or some sort of global base.
01426     Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
01427                        getPICJumpTableRelocBase(Table, DAG));
01428   }
01429 
01430   return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
01431 }
01432 
01433 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
01434   // The first operand is the chain, the second is the condition, the third is
01435   // the block to branch to if the condition is true.
01436   SDValue Chain = Op.getOperand(0);
01437   SDValue Dest = Op.getOperand(2);
01438   SDLoc DL(Op);
01439 
01440   SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
01441 
01442   // Return if flag is not set by a floating point comparison.
01443   if (CondRes.getOpcode() != MipsISD::FPCmp)
01444     return Op;
01445 
01446   SDValue CCNode  = CondRes.getOperand(2);
01447   Mips::CondCode CC =
01448     (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
01449   unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
01450   SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
01451   SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
01452   return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
01453                      FCC0, Dest, CondRes);
01454 }
01455 
01456 SDValue MipsTargetLowering::
01457 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
01458 {
01459   SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
01460 
01461   // Return if flag is not set by a floating point comparison.
01462   if (Cond.getOpcode() != MipsISD::FPCmp)
01463     return Op;
01464 
01465   return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
01466                       SDLoc(Op));
01467 }
01468 
01469 SDValue MipsTargetLowering::
01470 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
01471 {
01472   SDLoc DL(Op);
01473   EVT Ty = Op.getOperand(0).getValueType();
01474   SDValue Cond = DAG.getNode(ISD::SETCC, DL,
01475                              getSetCCResultType(*DAG.getContext(), Ty),
01476                              Op.getOperand(0), Op.getOperand(1),
01477                              Op.getOperand(4));
01478 
01479   return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
01480                      Op.getOperand(3));
01481 }
01482 
01483 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
01484   SDValue Cond = createFPCmp(DAG, Op);
01485 
01486   assert(Cond.getOpcode() == MipsISD::FPCmp &&
01487          "Floating point operand expected.");
01488 
01489   SDValue True  = DAG.getConstant(1, MVT::i32);
01490   SDValue False = DAG.getConstant(0, MVT::i32);
01491 
01492   return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
01493 }
01494 
01495 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
01496                                                SelectionDAG &DAG) const {
01497   // FIXME there isn't actually debug info here
01498   SDLoc DL(Op);
01499   EVT Ty = Op.getValueType();
01500   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
01501   const GlobalValue *GV = N->getGlobal();
01502 
01503   if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !isN64()) {
01504     const MipsTargetObjectFile &TLOF =
01505       (const MipsTargetObjectFile&)getObjFileLowering();
01506 
01507     // %gp_rel relocation
01508     if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
01509       SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
01510                                               MipsII::MO_GPREL);
01511       SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL,
01512                                       DAG.getVTList(MVT::i32), &GA, 1);
01513       SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
01514       return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
01515     }
01516 
01517     // %hi/%lo relocation
01518     return getAddrNonPIC(N, Ty, DAG);
01519   }
01520 
01521   if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
01522     return getAddrLocal(N, Ty, DAG, isN32() || isN64());
01523 
01524   if (LargeGOT)
01525     return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16,
01526                                  MipsII::MO_GOT_LO16, DAG.getEntryNode(),
01527                                  MachinePointerInfo::getGOT());
01528 
01529   return getAddrGlobal(N, Ty, DAG, (isN32() || isN64()) ? MipsII::MO_GOT_DISP
01530                                                         : MipsII::MO_GOT16,
01531                        DAG.getEntryNode(), MachinePointerInfo::getGOT());
01532 }
01533 
01534 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
01535                                               SelectionDAG &DAG) const {
01536   BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
01537   EVT Ty = Op.getValueType();
01538 
01539   if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !isN64())
01540     return getAddrNonPIC(N, Ty, DAG);
01541 
01542   return getAddrLocal(N, Ty, DAG, isN32() || isN64());
01543 }
01544 
01545 SDValue MipsTargetLowering::
01546 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
01547 {
01548   // If the relocation model is PIC, use the General Dynamic TLS Model or
01549   // Local Dynamic TLS model, otherwise use the Initial Exec or
01550   // Local Exec TLS Model.
01551 
01552   GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
01553   SDLoc DL(GA);
01554   const GlobalValue *GV = GA->getGlobal();
01555   EVT PtrVT = getPointerTy();
01556 
01557   TLSModel::Model model = getTargetMachine().getTLSModel(GV);
01558 
01559   if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
01560     // General Dynamic and Local Dynamic TLS Model.
01561     unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
01562                                                       : MipsII::MO_TLSGD;
01563 
01564     SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
01565     SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
01566                                    getGlobalReg(DAG, PtrVT), TGA);
01567     unsigned PtrSize = PtrVT.getSizeInBits();
01568     IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
01569 
01570     SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
01571 
01572     ArgListTy Args;
01573     ArgListEntry Entry;
01574     Entry.Node = Argument;
01575     Entry.Ty = PtrTy;
01576     Args.push_back(Entry);
01577 
01578     TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
01579                   false, false, false, false, 0, CallingConv::C,
01580                   /*IsTailCall=*/false, /*doesNotRet=*/false,
01581                   /*isReturnValueUsed=*/true,
01582                   TlsGetAddr, Args, DAG, DL);
01583     std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
01584 
01585     SDValue Ret = CallResult.first;
01586 
01587     if (model != TLSModel::LocalDynamic)
01588       return Ret;
01589 
01590     SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
01591                                                MipsII::MO_DTPREL_HI);
01592     SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
01593     SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
01594                                                MipsII::MO_DTPREL_LO);
01595     SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
01596     SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
01597     return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
01598   }
01599 
01600   SDValue Offset;
01601   if (model == TLSModel::InitialExec) {
01602     // Initial Exec TLS Model
01603     SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
01604                                              MipsII::MO_GOTTPREL);
01605     TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
01606                       TGA);
01607     Offset = DAG.getLoad(PtrVT, DL,
01608                          DAG.getEntryNode(), TGA, MachinePointerInfo(),
01609                          false, false, false, 0);
01610   } else {
01611     // Local Exec TLS Model
01612     assert(model == TLSModel::LocalExec);
01613     SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
01614                                                MipsII::MO_TPREL_HI);
01615     SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
01616                                                MipsII::MO_TPREL_LO);
01617     SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
01618     SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
01619     Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
01620   }
01621 
01622   SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
01623   return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
01624 }
01625 
01626 SDValue MipsTargetLowering::
01627 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
01628 {
01629   JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
01630   EVT Ty = Op.getValueType();
01631 
01632   if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !isN64())
01633     return getAddrNonPIC(N, Ty, DAG);
01634 
01635   return getAddrLocal(N, Ty, DAG, isN32() || isN64());
01636 }
01637 
01638 SDValue MipsTargetLowering::
01639 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
01640 {
01641   // gp_rel relocation
01642   // FIXME: we should reference the constant pool using small data sections,
01643   // but the asm printer currently doesn't support this feature without
01644   // hacking it. This feature should come soon so we can uncomment the
01645   // stuff below.
01646   //if (IsInSmallSection(C->getType())) {
01647   //  SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
01648   //  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
01649   //  ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
01650   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
01651   EVT Ty = Op.getValueType();
01652 
01653   if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !isN64())
01654     return getAddrNonPIC(N, Ty, DAG);
01655 
01656   return getAddrLocal(N, Ty, DAG, isN32() || isN64());
01657 }
01658 
01659 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
01660   MachineFunction &MF = DAG.getMachineFunction();
01661   MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
01662 
01663   SDLoc DL(Op);
01664   SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
01665                                  getPointerTy());
01666 
01667   // vastart just stores the address of the VarArgsFrameIndex slot into the
01668   // memory location argument.
01669   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
01670   return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
01671                       MachinePointerInfo(SV), false, false, 0);
01672 }
01673 
01674 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
01675                                 bool HasExtractInsert) {
01676   EVT TyX = Op.getOperand(0).getValueType();
01677   EVT TyY = Op.getOperand(1).getValueType();
01678   SDValue Const1 = DAG.getConstant(1, MVT::i32);
01679   SDValue Const31 = DAG.getConstant(31, MVT::i32);
01680   SDLoc DL(Op);
01681   SDValue Res;
01682 
01683   // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
01684   // to i32.
01685   SDValue X = (TyX == MVT::f32) ?
01686     DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
01687     DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
01688                 Const1);
01689   SDValue Y = (TyY == MVT::f32) ?
01690     DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
01691     DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
01692                 Const1);
01693 
01694   if (HasExtractInsert) {
01695     // ext  E, Y, 31, 1  ; extract bit31 of Y
01696     // ins  X, E, 31, 1  ; insert extracted bit at bit31 of X
01697     SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
01698     Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
01699   } else {
01700     // sll SllX, X, 1
01701     // srl SrlX, SllX, 1
01702     // srl SrlY, Y, 31
01703     // sll SllY, SrlX, 31
01704     // or  Or, SrlX, SllY
01705     SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
01706     SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
01707     SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
01708     SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
01709     Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
01710   }
01711 
01712   if (TyX == MVT::f32)
01713     return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
01714 
01715   SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
01716                              Op.getOperand(0), DAG.getConstant(0, MVT::i32));
01717   return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
01718 }
01719 
01720 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
01721                                 bool HasExtractInsert) {
01722   unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
01723   unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
01724   EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
01725   SDValue Const1 = DAG.getConstant(1, MVT::i32);
01726   SDLoc DL(Op);
01727 
01728   // Bitcast to integer nodes.
01729   SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
01730   SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
01731 
01732   if (HasExtractInsert) {
01733     // ext  E, Y, width(Y) - 1, 1  ; extract bit width(Y)-1 of Y
01734     // ins  X, E, width(X) - 1, 1  ; insert extracted bit at bit width(X)-1 of X
01735     SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
01736                             DAG.getConstant(WidthY - 1, MVT::i32), Const1);
01737 
01738     if (WidthX > WidthY)
01739       E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
01740     else if (WidthY > WidthX)
01741       E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
01742 
01743     SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
01744                             DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
01745     return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
01746   }
01747 
01748   // (d)sll SllX, X, 1
01749   // (d)srl SrlX, SllX, 1
01750   // (d)srl SrlY, Y, width(Y)-1
01751   // (d)sll SllY, SrlX, width(Y)-1
01752   // or     Or, SrlX, SllY
01753   SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
01754   SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
01755   SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
01756                              DAG.getConstant(WidthY - 1, MVT::i32));
01757 
01758   if (WidthX > WidthY)
01759     SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
01760   else if (WidthY > WidthX)
01761     SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
01762 
01763   SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
01764                              DAG.getConstant(WidthX - 1, MVT::i32));
01765   SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
01766   return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
01767 }
01768 
01769 SDValue
01770 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
01771   if (Subtarget->isGP64bit())
01772     return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasExtractInsert());
01773 
01774   return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasExtractInsert());
01775 }
01776 
01777 SDValue MipsTargetLowering::
01778 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
01779   // check the depth
01780   assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
01781          "Frame address can only be determined for current frame.");
01782 
01783   MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
01784   MFI->setFrameAddressIsTaken(true);
01785   EVT VT = Op.getValueType();
01786   SDLoc DL(Op);
01787   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
01788                                          isN64() ? Mips::FP_64 : Mips::FP, VT);
01789   return FrameAddr;
01790 }
01791 
01792 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
01793                                             SelectionDAG &DAG) const {
01794   if (verifyReturnAddressArgumentIsConstant(Op, DAG))
01795     return SDValue();
01796 
01797   // check the depth
01798   assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
01799          "Return address can be determined only for current frame.");
01800 
01801   MachineFunction &MF = DAG.getMachineFunction();
01802   MachineFrameInfo *MFI = MF.getFrameInfo();
01803   MVT VT = Op.getSimpleValueType();
01804   unsigned RA = isN64() ? Mips::RA_64 : Mips::RA;
01805   MFI->setReturnAddressIsTaken(true);
01806 
01807   // Return RA, which contains the return address. Mark it an implicit live-in.
01808   unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
01809   return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
01810 }
01811 
01812 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
01813 // generated from __builtin_eh_return (offset, handler)
01814 // The effect of this is to adjust the stack pointer by "offset"
01815 // and then branch to "handler".
01816 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
01817                                                                      const {
01818   MachineFunction &MF = DAG.getMachineFunction();
01819   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
01820 
01821   MipsFI->setCallsEhReturn();
01822   SDValue Chain     = Op.getOperand(0);
01823   SDValue Offset    = Op.getOperand(1);
01824   SDValue Handler   = Op.getOperand(2);
01825   SDLoc DL(Op);
01826   EVT Ty = isN64() ? MVT::i64 : MVT::i32;
01827 
01828   // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
01829   // EH_RETURN nodes, so that instructions are emitted back-to-back.
01830   unsigned OffsetReg = isN64() ? Mips::V1_64 : Mips::V1;
01831   unsigned AddrReg = isN64() ? Mips::V0_64 : Mips::V0;
01832   Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
01833   Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
01834   return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
01835                      DAG.getRegister(OffsetReg, Ty),
01836                      DAG.getRegister(AddrReg, getPointerTy()),
01837                      Chain.getValue(1));
01838 }
01839 
01840 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
01841                                               SelectionDAG &DAG) const {
01842   // FIXME: Need pseudo-fence for 'singlethread' fences
01843   // FIXME: Set SType for weaker fences where supported/appropriate.
01844   unsigned SType = 0;
01845   SDLoc DL(Op);
01846   return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
01847                      DAG.getConstant(SType, MVT::i32));
01848 }
01849 
01850 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
01851                                                 SelectionDAG &DAG) const {
01852   SDLoc DL(Op);
01853   SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
01854   SDValue Shamt = Op.getOperand(2);
01855 
01856   // if shamt < 32:
01857   //  lo = (shl lo, shamt)
01858   //  hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
01859   // else:
01860   //  lo = 0
01861   //  hi = (shl lo, shamt[4:0])
01862   SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
01863                             DAG.getConstant(-1, MVT::i32));
01864   SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
01865                                       DAG.getConstant(1, MVT::i32));
01866   SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
01867                                      Not);
01868   SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
01869   SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
01870   SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
01871   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
01872                              DAG.getConstant(0x20, MVT::i32));
01873   Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
01874                    DAG.getConstant(0, MVT::i32), ShiftLeftLo);
01875   Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
01876 
01877   SDValue Ops[2] = {Lo, Hi};
01878   return DAG.getMergeValues(Ops, 2, DL);
01879 }
01880 
01881 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
01882                                                  bool IsSRA) const {
01883   SDLoc DL(Op);
01884   SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
01885   SDValue Shamt = Op.getOperand(2);
01886 
01887   // if shamt < 32:
01888   //  lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
01889   //  if isSRA:
01890   //    hi = (sra hi, shamt)
01891   //  else:
01892   //    hi = (srl hi, shamt)
01893   // else:
01894   //  if isSRA:
01895   //   lo = (sra hi, shamt[4:0])
01896   //   hi = (sra hi, 31)
01897   //  else:
01898   //   lo = (srl hi, shamt[4:0])
01899   //   hi = 0
01900   SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
01901                             DAG.getConstant(-1, MVT::i32));
01902   SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
01903                                      DAG.getConstant(1, MVT::i32));
01904   SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
01905   SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
01906   SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
01907   SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
01908                                      Hi, Shamt);
01909   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
01910                              DAG.getConstant(0x20, MVT::i32));
01911   SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
01912                                 DAG.getConstant(31, MVT::i32));
01913   Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
01914   Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
01915                    IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
01916                    ShiftRightHi);
01917 
01918   SDValue Ops[2] = {Lo, Hi};
01919   return DAG.getMergeValues(Ops, 2, DL);
01920 }
01921 
01922 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
01923                             SDValue Chain, SDValue Src, unsigned Offset) {
01924   SDValue Ptr = LD->getBasePtr();
01925   EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
01926   EVT BasePtrVT = Ptr.getValueType();
01927   SDLoc DL(LD);
01928   SDVTList VTList = DAG.getVTList(VT, MVT::Other);
01929 
01930   if (Offset)
01931     Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
01932                       DAG.getConstant(Offset, BasePtrVT));
01933 
01934   SDValue Ops[] = { Chain, Ptr, Src };
01935   return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
01936                                  LD->getMemOperand());
01937 }
01938 
01939 // Expand an unaligned 32 or 64-bit integer load node.
01940 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
01941   LoadSDNode *LD = cast<LoadSDNode>(Op);
01942   EVT MemVT = LD->getMemoryVT();
01943 
01944   // Return if load is aligned or if MemVT is neither i32 nor i64.
01945   if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
01946       ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
01947     return SDValue();
01948 
01949   bool IsLittle = Subtarget->isLittle();
01950   EVT VT = Op.getValueType();
01951   ISD::LoadExtType ExtType = LD->getExtensionType();
01952   SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
01953 
01954   assert((VT == MVT::i32) || (VT == MVT::i64));
01955 
01956   // Expand
01957   //  (set dst, (i64 (load baseptr)))
01958   // to
01959   //  (set tmp, (ldl (add baseptr, 7), undef))
01960   //  (set dst, (ldr baseptr, tmp))
01961   if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
01962     SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
01963                                IsLittle ? 7 : 0);
01964     return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
01965                         IsLittle ? 0 : 7);
01966   }
01967 
01968   SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
01969                              IsLittle ? 3 : 0);
01970   SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
01971                              IsLittle ? 0 : 3);
01972 
01973   // Expand
01974   //  (set dst, (i32 (load baseptr))) or
01975   //  (set dst, (i64 (sextload baseptr))) or
01976   //  (set dst, (i64 (extload baseptr)))
01977   // to
01978   //  (set tmp, (lwl (add baseptr, 3), undef))
01979   //  (set dst, (lwr baseptr, tmp))
01980   if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
01981       (ExtType == ISD::EXTLOAD))
01982     return LWR;
01983 
01984   assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
01985 
01986   // Expand
01987   //  (set dst, (i64 (zextload baseptr)))
01988   // to
01989   //  (set tmp0, (lwl (add baseptr, 3), undef))
01990   //  (set tmp1, (lwr baseptr, tmp0))
01991   //  (set tmp2, (shl tmp1, 32))
01992   //  (set dst, (srl tmp2, 32))
01993   SDLoc DL(LD);
01994   SDValue Const32 = DAG.getConstant(32, MVT::i32);
01995   SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
01996   SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
01997   SDValue Ops[] = { SRL, LWR.getValue(1) };
01998   return DAG.getMergeValues(Ops, 2, DL);
01999 }
02000 
02001 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
02002                              SDValue Chain, unsigned Offset) {
02003   SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
02004   EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
02005   SDLoc DL(SD);
02006   SDVTList VTList = DAG.getVTList(MVT::Other);
02007 
02008   if (Offset)
02009     Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
02010                       DAG.getConstant(Offset, BasePtrVT));
02011 
02012   SDValue Ops[] = { Chain, Value, Ptr };
02013   return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
02014                                  SD->getMemOperand());
02015 }
02016 
02017 // Expand an unaligned 32 or 64-bit integer store node.
02018 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
02019                                       bool IsLittle) {
02020   SDValue Value = SD->getValue(), Chain = SD->getChain();
02021   EVT VT = Value.getValueType();
02022 
02023   // Expand
02024   //  (store val, baseptr) or
02025   //  (truncstore val, baseptr)
02026   // to
02027   //  (swl val, (add baseptr, 3))
02028   //  (swr val, baseptr)
02029   if ((VT == MVT::i32) || SD->isTruncatingStore()) {
02030     SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
02031                                 IsLittle ? 3 : 0);
02032     return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
02033   }
02034 
02035   assert(VT == MVT::i64);
02036 
02037   // Expand
02038   //  (store val, baseptr)
02039   // to
02040   //  (sdl val, (add baseptr, 7))
02041   //  (sdr val, baseptr)
02042   SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
02043   return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
02044 }
02045 
02046 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
02047 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
02048   SDValue Val = SD->getValue();
02049 
02050   if (Val.getOpcode() != ISD::FP_TO_SINT)
02051     return SDValue();
02052 
02053   EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
02054   SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
02055                            Val.getOperand(0));
02056 
02057   return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
02058                       SD->getPointerInfo(), SD->isVolatile(),
02059                       SD->isNonTemporal(), SD->getAlignment());
02060 }
02061 
02062 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
02063   StoreSDNode *SD = cast<StoreSDNode>(Op);
02064   EVT MemVT = SD->getMemoryVT();
02065 
02066   // Lower unaligned integer stores.
02067   if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
02068       ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
02069     return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle());
02070 
02071   return lowerFP_TO_SINT_STORE(SD, DAG);
02072 }
02073 
02074 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
02075   if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
02076       || cast<ConstantSDNode>
02077         (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
02078       || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
02079     return SDValue();
02080 
02081   // The pattern
02082   //   (add (frameaddr 0), (frame_to_args_offset))
02083   // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
02084   //   (add FrameObject, 0)
02085   // where FrameObject is a fixed StackObject with offset 0 which points to
02086   // the old stack pointer.
02087   MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
02088   EVT ValTy = Op->getValueType(0);
02089   int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
02090   SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
02091   return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
02092                      DAG.getConstant(0, ValTy));
02093 }
02094 
02095 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
02096                                             SelectionDAG &DAG) const {
02097   EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
02098   SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
02099                               Op.getOperand(0));
02100   return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
02101 }
02102 
02103 //===----------------------------------------------------------------------===//
02104 //                      Calling Convention Implementation
02105 //===----------------------------------------------------------------------===//
02106 
02107 //===----------------------------------------------------------------------===//
02108 // TODO: Implement a generic logic using tblgen that can support this.
02109 // Mips O32 ABI rules:
02110 // ---
02111 // i32 - Passed in A0, A1, A2, A3 and stack
02112 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
02113 //       an argument. Otherwise, passed in A1, A2, A3 and stack.
02114 // f64 - Only passed in two aliased f32 registers if no int reg has been used
02115 //       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
02116 //       not used, it must be shadowed. If only A3 is avaiable, shadow it and
02117 //       go to stack.
02118 //
02119 //  For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
02120 //===----------------------------------------------------------------------===//
02121 
02122 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
02123                        CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
02124                        CCState &State, const MCPhysReg *F64Regs) {
02125 
02126   static const unsigned IntRegsSize = 4, FloatRegsSize = 2;
02127 
02128   static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
02129   static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
02130 
02131   // Do not process byval args here.
02132   if (ArgFlags.isByVal())
02133     return true;
02134 
02135   // Promote i8 and i16
02136   if (LocVT == MVT::i8 || LocVT == MVT::i16) {
02137     LocVT = MVT::i32;
02138     if (ArgFlags.isSExt())
02139       LocInfo = CCValAssign::SExt;
02140     else if (ArgFlags.isZExt())
02141       LocInfo = CCValAssign::ZExt;
02142     else
02143       LocInfo = CCValAssign::AExt;
02144   }
02145 
02146   unsigned Reg;
02147 
02148   // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
02149   // is true: function is vararg, argument is 3rd or higher, there is previous
02150   // argument which is not f32 or f64.
02151   bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
02152       || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
02153   unsigned OrigAlign = ArgFlags.getOrigAlign();
02154   bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
02155 
02156   if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
02157     Reg = State.AllocateReg(IntRegs, IntRegsSize);
02158     // If this is the first part of an i64 arg,
02159     // the allocated register must be either A0 or A2.
02160     if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
02161       Reg = State.AllocateReg(IntRegs, IntRegsSize);
02162     LocVT = MVT::i32;
02163   } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
02164     // Allocate int register and shadow next int register. If first
02165     // available register is Mips::A1 or Mips::A3, shadow it too.
02166     Reg = State.AllocateReg(IntRegs, IntRegsSize);
02167     if (Reg == Mips::A1 || Reg == Mips::A3)
02168       Reg = State.AllocateReg(IntRegs, IntRegsSize);
02169     State.AllocateReg(IntRegs, IntRegsSize);
02170     LocVT = MVT::i32;
02171   } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
02172     // we are guaranteed to find an available float register
02173     if (ValVT == MVT::f32) {
02174       Reg = State.AllocateReg(F32Regs, FloatRegsSize);
02175       // Shadow int register
02176       State.AllocateReg(IntRegs, IntRegsSize);
02177     } else {
02178       Reg = State.AllocateReg(F64Regs, FloatRegsSize);
02179       // Shadow int registers
02180       unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
02181       if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
02182         State.AllocateReg(IntRegs, IntRegsSize);
02183       State.AllocateReg(IntRegs, IntRegsSize);
02184     }
02185   } else
02186     llvm_unreachable("Cannot handle this ValVT.");
02187 
02188   if (!Reg) {
02189     unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
02190                                           OrigAlign);
02191     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
02192   } else
02193     State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
02194 
02195   return false;
02196 }
02197 
02198 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
02199                             MVT LocVT, CCValAssign::LocInfo LocInfo,
02200                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
02201   static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
02202 
02203   return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
02204 }
02205 
02206 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
02207                             MVT LocVT, CCValAssign::LocInfo LocInfo,
02208                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
02209   static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
02210 
02211   return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
02212 }
02213 
02214 #include "MipsGenCallingConv.inc"
02215 
02216 //===----------------------------------------------------------------------===//
02217 //                  Call Calling Convention Implementation
02218 //===----------------------------------------------------------------------===//
02219 
02220 // Return next O32 integer argument register.
02221 static unsigned getNextIntArgReg(unsigned Reg) {
02222   assert((Reg == Mips::A0) || (Reg == Mips::A2));
02223   return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
02224 }
02225 
02226 SDValue
02227 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
02228                                    SDValue Chain, SDValue Arg, SDLoc DL,
02229                                    bool IsTailCall, SelectionDAG &DAG) const {
02230   if (!IsTailCall) {
02231     SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
02232                                  DAG.getIntPtrConstant(Offset));
02233     return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
02234                         false, 0);
02235   }
02236 
02237   MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
02238   int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
02239   SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
02240   return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
02241                       /*isVolatile=*/ true, false, 0);
02242 }
02243 
02244 void MipsTargetLowering::
02245 getOpndList(SmallVectorImpl<SDValue> &Ops,
02246             std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
02247             bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
02248             CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
02249   // Insert node "GP copy globalreg" before call to function.
02250   //
02251   // R_MIPS_CALL* operators (emitted when non-internal functions are called
02252   // in PIC mode) allow symbols to be resolved via lazy binding.
02253   // The lazy binding stub requires GP to point to the GOT.
02254   if (IsPICCall && !InternalLinkage) {
02255     unsigned GPReg = isN64() ? Mips::GP_64 : Mips::GP;
02256     EVT Ty = isN64() ? MVT::i64 : MVT::i32;
02257     RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
02258   }
02259 
02260   // Build a sequence of copy-to-reg nodes chained together with token
02261   // chain and flag operands which copy the outgoing args into registers.
02262   // The InFlag in necessary since all emitted instructions must be
02263   // stuck together.
02264   SDValue InFlag;
02265 
02266   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
02267     Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
02268                                  RegsToPass[i].second, InFlag);
02269     InFlag = Chain.getValue(1);
02270   }
02271 
02272   // Add argument registers to the end of the list so that they are
02273   // known live into the call.
02274   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
02275     Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
02276                                       RegsToPass[i].second.getValueType()));
02277 
02278   // Add a register mask operand representing the call-preserved registers.
02279   const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
02280   const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
02281   assert(Mask && "Missing call preserved mask for calling convention");
02282   if (Subtarget->inMips16HardFloat()) {
02283     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
02284       llvm::StringRef Sym = G->getGlobal()->getName();
02285       Function *F = G->getGlobal()->getParent()->getFunction(Sym);
02286       if (F && F->hasFnAttribute("__Mips16RetHelper")) {
02287         Mask = MipsRegisterInfo::getMips16RetHelperMask();
02288       }
02289     }
02290   }
02291   Ops.push_back(CLI.DAG.getRegisterMask(Mask));
02292 
02293   if (InFlag.getNode())
02294     Ops.push_back(InFlag);
02295 }
02296 
02297 /// LowerCall - functions arguments are copied from virtual regs to
02298 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
02299 SDValue
02300 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
02301                               SmallVectorImpl<SDValue> &InVals) const {
02302   SelectionDAG &DAG                     = CLI.DAG;
02303   SDLoc DL                              = CLI.DL;
02304   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
02305   SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
02306   SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
02307   SDValue Chain                         = CLI.Chain;
02308   SDValue Callee                        = CLI.Callee;
02309   bool &IsTailCall                      = CLI.IsTailCall;
02310   CallingConv::ID CallConv              = CLI.CallConv;
02311   bool IsVarArg                         = CLI.IsVarArg;
02312 
02313   MachineFunction &MF = DAG.getMachineFunction();
02314   MachineFrameInfo *MFI = MF.getFrameInfo();
02315   const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
02316   MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
02317   bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
02318 
02319   // Analyze operands of the call, assigning locations to each operand.
02320   SmallVector<CCValAssign, 16> ArgLocs;
02321   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
02322                  getTargetMachine(), ArgLocs, *DAG.getContext());
02323   MipsCC::SpecialCallingConvType SpecialCallingConv =
02324     getSpecialCallingConv(Callee);
02325   MipsCC MipsCCInfo(CallConv, isO32(), Subtarget->isFP64bit(), CCInfo,
02326                     SpecialCallingConv);
02327 
02328   MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
02329                                  Subtarget->mipsSEUsesSoftFloat(),
02330                                  Callee.getNode(), CLI.Args);
02331 
02332   // Get a count of how many bytes are to be pushed on the stack.
02333   unsigned NextStackOffset = CCInfo.getNextStackOffset();
02334 
02335   // Check if it's really possible to do a tail call.
02336   if (IsTailCall)
02337     IsTailCall =
02338       isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
02339                                         *MF.getInfo<MipsFunctionInfo>());
02340 
02341   if (IsTailCall)
02342     ++NumTailCalls;
02343 
02344   // Chain is the output chain of the last Load/Store or CopyToReg node.
02345   // ByValChain is the output chain of the last Memcpy node created for copying
02346   // byval arguments to the stack.
02347   unsigned StackAlignment = TFL->getStackAlignment();
02348   NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
02349   SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
02350 
02351   if (!IsTailCall)
02352     Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
02353 
02354   SDValue StackPtr = DAG.getCopyFromReg(
02355       Chain, DL, isN64() ? Mips::SP_64 : Mips::SP, getPointerTy());
02356 
02357   // With EABI is it possible to have 16 args on registers.
02358   std::deque< std::pair<unsigned, SDValue> > RegsToPass;
02359   SmallVector<SDValue, 8> MemOpChains;
02360   MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
02361 
02362   // Walk the register/memloc assignments, inserting copies/loads.
02363   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
02364     SDValue Arg = OutVals[i];
02365     CCValAssign &VA = ArgLocs[i];
02366     MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
02367     ISD::ArgFlagsTy Flags = Outs[i].Flags;
02368 
02369     // ByVal Arg.
02370     if (Flags.isByVal()) {
02371       assert(Flags.getByValSize() &&
02372              "ByVal args of size 0 should have been ignored by front-end.");
02373       assert(ByValArg != MipsCCInfo.byval_end());
02374       assert(!IsTailCall &&
02375              "Do not tail-call optimize if there is a byval argument.");
02376       passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
02377                    MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
02378       ++ByValArg;
02379       continue;
02380     }
02381 
02382     // Promote the value if needed.
02383     switch (VA.getLocInfo()) {
02384     default: llvm_unreachable("Unknown loc info!");
02385     case CCValAssign::Full:
02386       if (VA.isRegLoc()) {
02387         if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
02388             (ValVT == MVT::f64 && LocVT == MVT::i64) ||
02389             (ValVT == MVT::i64 && LocVT == MVT::f64))
02390           Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
02391         else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
02392           SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
02393                                    Arg, DAG.getConstant(0, MVT::i32));
02394           SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
02395                                    Arg, DAG.getConstant(1, MVT::i32));
02396           if (!Subtarget->isLittle())
02397             std::swap(Lo, Hi);
02398           unsigned LocRegLo = VA.getLocReg();
02399           unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
02400           RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
02401           RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
02402           continue;
02403         }
02404       }
02405       break;
02406     case CCValAssign::SExt:
02407       Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
02408       break;
02409     case CCValAssign::ZExt:
02410       Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
02411       break;
02412     case CCValAssign::AExt:
02413       Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
02414       break;
02415     }
02416 
02417     // Arguments that can be passed on register must be kept at
02418     // RegsToPass vector
02419     if (VA.isRegLoc()) {
02420       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
02421       continue;
02422     }
02423 
02424     // Register can't get to this point...
02425     assert(VA.isMemLoc());
02426 
02427     // emit ISD::STORE whichs stores the
02428     // parameter value to a stack Location
02429     MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
02430                                          Chain, Arg, DL, IsTailCall, DAG));
02431   }
02432 
02433   // Transform all store nodes into one single node because all store
02434   // nodes are independent of each other.
02435   if (!MemOpChains.empty())
02436     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
02437                         &MemOpChains[0], MemOpChains.size());
02438 
02439   // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
02440   // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
02441   // node so that legalize doesn't hack it.
02442   bool IsPICCall = (isN64() || IsPIC); // true if calls are translated to
02443                                        // jalr $25
02444   bool GlobalOrExternal = false, InternalLinkage = false;
02445   SDValue CalleeLo;
02446   EVT Ty = Callee.getValueType();
02447 
02448   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
02449     if (IsPICCall) {
02450       const GlobalValue *Val = G->getGlobal();
02451       InternalLinkage = Val->hasInternalLinkage();
02452 
02453       if (InternalLinkage)
02454         Callee = getAddrLocal(G, Ty, DAG, isN32() || isN64());
02455       else if (LargeGOT)
02456         Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16,
02457                                        MipsII::MO_CALL_LO16, Chain,
02458                                        FuncInfo->callPtrInfo(Val));
02459       else
02460         Callee = getAddrGlobal(G, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
02461                                FuncInfo->callPtrInfo(Val));
02462     } else
02463       Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
02464                                           MipsII::MO_NO_FLAG);
02465     GlobalOrExternal = true;
02466   }
02467   else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
02468     const char *Sym = S->getSymbol();
02469 
02470     if (!isN64() && !IsPIC) // !N64 && static
02471       Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(),
02472                                             MipsII::MO_NO_FLAG);
02473     else if (LargeGOT)
02474       Callee = getAddrGlobalLargeGOT(S, Ty, DAG, MipsII::MO_CALL_HI16,
02475                                      MipsII::MO_CALL_LO16, Chain,
02476                                      FuncInfo->callPtrInfo(Sym));
02477     else // N64 || PIC
02478       Callee = getAddrGlobal(S, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
02479                              FuncInfo->callPtrInfo(Sym));
02480 
02481     GlobalOrExternal = true;
02482   }
02483 
02484   SmallVector<SDValue, 8> Ops(1, Chain);
02485   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
02486 
02487   getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
02488               CLI, Callee, Chain);
02489 
02490   if (IsTailCall)
02491     return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size());
02492 
02493   Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size());
02494   SDValue InFlag = Chain.getValue(1);
02495 
02496   // Create the CALLSEQ_END node.
02497   Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
02498                              DAG.getIntPtrConstant(0, true), InFlag, DL);
02499   InFlag = Chain.getValue(1);
02500 
02501   // Handle result values, copying them out of physregs into vregs that we
02502   // return.
02503   return LowerCallResult(Chain, InFlag, CallConv, IsVarArg,
02504                          Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy);
02505 }
02506 
02507 /// LowerCallResult - Lower the result values of a call into the
02508 /// appropriate copies out of appropriate physical registers.
02509 SDValue
02510 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
02511                                     CallingConv::ID CallConv, bool IsVarArg,
02512                                     const SmallVectorImpl<ISD::InputArg> &Ins,
02513                                     SDLoc DL, SelectionDAG &DAG,
02514                                     SmallVectorImpl<SDValue> &InVals,
02515                                     const SDNode *CallNode,
02516                                     const Type *RetTy) const {
02517   // Assign locations to each value returned by this call.
02518   SmallVector<CCValAssign, 16> RVLocs;
02519   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
02520                  getTargetMachine(), RVLocs, *DAG.getContext());
02521   MipsCC MipsCCInfo(CallConv, isO32(), Subtarget->isFP64bit(), CCInfo);
02522 
02523   MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(),
02524                                CallNode, RetTy);
02525 
02526   // Copy all of the result registers out of their specified physreg.
02527   for (unsigned i = 0; i != RVLocs.size(); ++i) {
02528     SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
02529                                      RVLocs[i].getLocVT(), InFlag);
02530     Chain = Val.getValue(1);
02531     InFlag = Val.getValue(2);
02532 
02533     if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
02534       Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val);
02535 
02536     InVals.push_back(Val);
02537   }
02538 
02539   return Chain;
02540 }
02541 
02542 //===----------------------------------------------------------------------===//
02543 //             Formal Arguments Calling Convention Implementation
02544 //===----------------------------------------------------------------------===//
02545 /// LowerFormalArguments - transform physical registers into virtual registers
02546 /// and generate load operations for arguments places on the stack.
02547 SDValue
02548 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
02549                                          CallingConv::ID CallConv,
02550                                          bool IsVarArg,
02551                                       const SmallVectorImpl<ISD::InputArg> &Ins,
02552                                          SDLoc DL, SelectionDAG &DAG,
02553                                          SmallVectorImpl<SDValue> &InVals)
02554                                           const {
02555   MachineFunction &MF = DAG.getMachineFunction();
02556   MachineFrameInfo *MFI = MF.getFrameInfo();
02557   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
02558 
02559   MipsFI->setVarArgsFrameIndex(0);
02560 
02561   // Used with vargs to acumulate store chains.
02562   std::vector<SDValue> OutChains;
02563 
02564   // Assign locations to all of the incoming arguments.
02565   SmallVector<CCValAssign, 16> ArgLocs;
02566   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
02567                  getTargetMachine(), ArgLocs, *DAG.getContext());
02568   MipsCC MipsCCInfo(CallConv, isO32(), Subtarget->isFP64bit(), CCInfo);
02569   Function::const_arg_iterator FuncArg =
02570     DAG.getMachineFunction().getFunction()->arg_begin();
02571   bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat();
02572 
02573   MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
02574   MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
02575                            MipsCCInfo.hasByValArg());
02576 
02577   unsigned CurArgIdx = 0;
02578   MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
02579 
02580   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
02581     CCValAssign &VA = ArgLocs[i];
02582     std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
02583     CurArgIdx = Ins[i].OrigArgIndex;
02584     EVT ValVT = VA.getValVT();
02585     ISD::ArgFlagsTy Flags = Ins[i].Flags;
02586     bool IsRegLoc = VA.isRegLoc();
02587 
02588     if (Flags.isByVal()) {
02589       assert(Flags.getByValSize() &&
02590              "ByVal args of size 0 should have been ignored by front-end.");
02591       assert(ByValArg != MipsCCInfo.byval_end());
02592       copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
02593                     MipsCCInfo, *ByValArg);
02594       ++ByValArg;
02595       continue;
02596     }
02597 
02598     // Arguments stored on registers
02599     if (IsRegLoc) {
02600       MVT RegVT = VA.getLocVT();
02601       unsigned ArgReg = VA.getLocReg();
02602       const TargetRegisterClass *RC = getRegClassFor(RegVT);
02603 
02604       // Transform the arguments stored on
02605       // physical registers into virtual ones
02606       unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
02607       SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
02608 
02609       // If this is an 8 or 16-bit value, it has been passed promoted
02610       // to 32 bits.  Insert an assert[sz]ext to capture this, then
02611       // truncate to the right size.
02612       if (VA.getLocInfo() != CCValAssign::Full) {
02613         unsigned Opcode = 0;
02614         if (VA.getLocInfo() == CCValAssign::SExt)
02615           Opcode = ISD::AssertSext;
02616         else if (VA.getLocInfo() == CCValAssign::ZExt)
02617           Opcode = ISD::AssertZext;
02618         if (Opcode)
02619           ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
02620                                  DAG.getValueType(ValVT));
02621         ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
02622       }
02623 
02624       // Handle floating point arguments passed in integer registers and
02625       // long double arguments passed in floating point registers.
02626       if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
02627           (RegVT == MVT::i64 && ValVT == MVT::f64) ||
02628           (RegVT == MVT::f64 && ValVT == MVT::i64))
02629         ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
02630       else if (isO32() && RegVT == MVT::i32 && ValVT == MVT::f64) {
02631         unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
02632                                   getNextIntArgReg(ArgReg), RC);
02633         SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
02634         if (!Subtarget->isLittle())
02635           std::swap(ArgValue, ArgValue2);
02636         ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
02637                                ArgValue, ArgValue2);
02638       }
02639 
02640       InVals.push_back(ArgValue);
02641     } else { // VA.isRegLoc()
02642 
02643       // sanity check
02644       assert(VA.isMemLoc());
02645 
02646       // The stack pointer offset is relative to the caller stack frame.
02647       int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
02648                                       VA.getLocMemOffset(), true);
02649 
02650       // Create load nodes to retrieve arguments from the stack
02651       SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
02652       SDValue Load = DAG.getLoad(ValVT, DL, Chain, FIN,
02653                                  MachinePointerInfo::getFixedStack(FI),
02654                                  false, false, false, 0);
02655       InVals.push_back(Load);
02656       OutChains.push_back(Load.getValue(1));
02657     }
02658   }
02659 
02660   // The mips ABIs for returning structs by value requires that we copy
02661   // the sret argument into $v0 for the return. Save the argument into
02662   // a virtual register so that we can access it from the return points.
02663   if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
02664     unsigned Reg = MipsFI->getSRetReturnReg();
02665     if (!Reg) {
02666       Reg = MF.getRegInfo().createVirtualRegister(
02667           getRegClassFor(isN64() ? MVT::i64 : MVT::i32));
02668       MipsFI->setSRetReturnReg(Reg);
02669     }
02670     SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
02671     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
02672   }
02673 
02674   if (IsVarArg)
02675     writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG);
02676 
02677   // All stores are grouped in one node to allow the matching between
02678   // the size of Ins and InVals. This only happens when on varg functions
02679   if (!OutChains.empty()) {
02680     OutChains.push_back(Chain);
02681     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
02682                         &OutChains[0], OutChains.size());
02683   }
02684 
02685   return Chain;
02686 }
02687 
02688 //===----------------------------------------------------------------------===//
02689 //               Return Value Calling Convention Implementation
02690 //===----------------------------------------------------------------------===//
02691 
02692 bool
02693 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
02694                                    MachineFunction &MF, bool IsVarArg,
02695                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
02696                                    LLVMContext &Context) const {
02697   SmallVector<CCValAssign, 16> RVLocs;
02698   CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(),
02699                  RVLocs, Context);
02700   return CCInfo.CheckReturn(Outs, RetCC_Mips);
02701 }
02702 
02703 SDValue
02704 MipsTargetLowering::LowerReturn(SDValue Chain,
02705                                 CallingConv::ID CallConv, bool IsVarArg,
02706                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
02707                                 const SmallVectorImpl<SDValue> &OutVals,
02708                                 SDLoc DL, SelectionDAG &DAG) const {
02709   // CCValAssign - represent the assignment of
02710   // the return value to a location
02711   SmallVector<CCValAssign, 16> RVLocs;
02712   MachineFunction &MF = DAG.getMachineFunction();
02713 
02714   // CCState - Info about the registers and stack slot.
02715   CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs,
02716                  *DAG.getContext());
02717   MipsCC MipsCCInfo(CallConv, isO32(), Subtarget->isFP64bit(), CCInfo);
02718 
02719   // Analyze return values.
02720   MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(),
02721                            MF.getFunction()->getReturnType());
02722 
02723   SDValue Flag;
02724   SmallVector<SDValue, 4> RetOps(1, Chain);
02725 
02726   // Copy the result values into the output registers.
02727   for (unsigned i = 0; i != RVLocs.size(); ++i) {
02728     SDValue Val = OutVals[i];
02729     CCValAssign &VA = RVLocs[i];
02730     assert(VA.isRegLoc() && "Can only return in registers!");
02731 
02732     if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
02733       Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
02734 
02735     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
02736 
02737     // Guarantee that all emitted copies are stuck together with flags.
02738     Flag = Chain.getValue(1);
02739     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
02740   }
02741 
02742   // The mips ABIs for returning structs by value requires that we copy
02743   // the sret argument into $v0 for the return. We saved the argument into
02744   // a virtual register in the entry block, so now we copy the value out
02745   // and into $v0.
02746   if (MF.getFunction()->hasStructRetAttr()) {
02747     MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
02748     unsigned Reg = MipsFI->getSRetReturnReg();
02749 
02750     if (!Reg)
02751       llvm_unreachable("sret virtual register not created in the entry block");
02752     SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
02753     unsigned V0 = isN64() ? Mips::V0_64 : Mips::V0;
02754 
02755     Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
02756     Flag = Chain.getValue(1);
02757     RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
02758   }
02759 
02760   RetOps[0] = Chain;  // Update chain.
02761 
02762   // Add the flag if we have it.
02763   if (Flag.getNode())
02764     RetOps.push_back(Flag);
02765 
02766   // Return on Mips is always a "jr $ra"
02767   return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size());
02768 }
02769 
02770 //===----------------------------------------------------------------------===//
02771 //                           Mips Inline Assembly Support
02772 //===----------------------------------------------------------------------===//
02773 
02774 /// getConstraintType - Given a constraint letter, return the type of
02775 /// constraint it is for this target.
02776 MipsTargetLowering::ConstraintType MipsTargetLowering::
02777 getConstraintType(const std::string &Constraint) const
02778 {
02779   // Mips specific constraints
02780   // GCC config/mips/constraints.md
02781   //
02782   // 'd' : An address register. Equivalent to r
02783   //       unless generating MIPS16 code.
02784   // 'y' : Equivalent to r; retained for
02785   //       backwards compatibility.
02786   // 'c' : A register suitable for use in an indirect
02787   //       jump. This will always be $25 for -mabicalls.
02788   // 'l' : The lo register. 1 word storage.
02789   // 'x' : The hilo register pair. Double word storage.
02790   if (Constraint.size() == 1) {
02791     switch (Constraint[0]) {
02792       default : break;
02793       case 'd':
02794       case 'y':
02795       case 'f':
02796       case 'c':
02797       case 'l':
02798       case 'x':
02799         return C_RegisterClass;
02800       case 'R':
02801         return C_Memory;
02802     }
02803   }
02804   return TargetLowering::getConstraintType(Constraint);
02805 }
02806 
02807 /// Examine constraint type and operand type and determine a weight value.
02808 /// This object must already have been set up with the operand type
02809 /// and the current alternative constraint selected.
02810 TargetLowering::ConstraintWeight
02811 MipsTargetLowering::getSingleConstraintMatchWeight(
02812     AsmOperandInfo &info, const char *constraint) const {
02813   ConstraintWeight weight = CW_Invalid;
02814   Value *CallOperandVal = info.CallOperandVal;
02815     // If we don't have a value, we can't do a match,
02816     // but allow it at the lowest weight.
02817   if (CallOperandVal == NULL)
02818     return CW_Default;
02819   Type *type = CallOperandVal->getType();
02820   // Look at the constraint type.
02821   switch (*constraint) {
02822   default:
02823     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
02824     break;
02825   case 'd':
02826   case 'y':
02827     if (type->isIntegerTy())
02828       weight = CW_Register;
02829     break;
02830   case 'f': // FPU or MSA register
02831     if (Subtarget->hasMSA() && type->isVectorTy() &&
02832         cast<VectorType>(type)->getBitWidth() == 128)
02833       weight = CW_Register;
02834     else if (type->isFloatTy())
02835       weight = CW_Register;
02836     break;
02837   case 'c': // $25 for indirect jumps
02838   case 'l': // lo register
02839   case 'x': // hilo register pair
02840     if (type->isIntegerTy())
02841       weight = CW_SpecificReg;
02842     break;
02843   case 'I': // signed 16 bit immediate
02844   case 'J': // integer zero
02845   case 'K': // unsigned 16 bit immediate
02846   case 'L': // signed 32 bit immediate where lower 16 bits are 0
02847   case 'N': // immediate in the range of -65535 to -1 (inclusive)
02848   case 'O': // signed 15 bit immediate (+- 16383)
02849   case 'P': // immediate in the range of 65535 to 1 (inclusive)
02850     if (isa<ConstantInt>(CallOperandVal))
02851       weight = CW_Constant;
02852     break;
02853   case 'R':
02854     weight = CW_Memory;
02855     break;
02856   }
02857   return weight;
02858 }
02859 
02860 /// This is a helper function to parse a physical register string and split it
02861 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
02862 /// that is returned indicates whether parsing was successful. The second flag
02863 /// is true if the numeric part exists.
02864 static std::pair<bool, bool>
02865 parsePhysicalReg(const StringRef &C, std::string &Prefix,
02866                  unsigned long long &Reg) {
02867   if (C.front() != '{' || C.back() != '}')
02868     return std::make_pair(false, false);
02869 
02870   // Search for the first numeric character.
02871   StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
02872   I = std::find_if(B, E, std::ptr_fun(isdigit));
02873 
02874   Prefix.assign(B, I - B);
02875 
02876   // The second flag is set to false if no numeric characters were found.
02877   if (I == E)
02878     return std::make_pair(true, false);
02879 
02880   // Parse the numeric characters.
02881   return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
02882                         true);
02883 }
02884 
02885 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
02886 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const {
02887   const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
02888   const TargetRegisterClass *RC;
02889   std::string Prefix;
02890   unsigned long long Reg;
02891 
02892   std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
02893 
02894   if (!R.first)
02895     return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
02896 
02897   if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
02898     // No numeric characters follow "hi" or "lo".
02899     if (R.second)
02900       return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
02901 
02902     RC = TRI->getRegClass(Prefix == "hi" ?
02903                           Mips::HI32RegClassID : Mips::LO32RegClassID);
02904     return std::make_pair(*(RC->begin()), RC);
02905   } else if (Prefix.compare(0, 4, "$msa") == 0) {
02906     // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
02907 
02908     // No numeric characters follow the name.
02909     if (R.second)
02910       return std::make_pair((unsigned)0, (const TargetRegisterClass *)0);
02911 
02912     Reg = StringSwitch<unsigned long long>(Prefix)
02913               .Case("$msair", Mips::MSAIR)
02914               .Case("$msacsr", Mips::MSACSR)
02915               .Case("$msaaccess", Mips::MSAAccess)
02916               .Case("$msasave", Mips::MSASave)
02917               .Case("$msamodify", Mips::MSAModify)
02918               .Case("$msarequest", Mips::MSARequest)
02919               .Case("$msamap", Mips::MSAMap)
02920               .Case("$msaunmap", Mips::MSAUnmap)
02921               .Default(0);
02922 
02923     if (!Reg)
02924       return std::make_pair((unsigned)0, (const TargetRegisterClass *)0);
02925 
02926     RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
02927     return std::make_pair(Reg, RC);
02928   }
02929 
02930   if (!R.second)
02931     return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
02932 
02933   if (Prefix == "$f") { // Parse $f0-$f31.
02934     // If the size of FP registers is 64-bit or Reg is an even number, select
02935     // the 64-bit register class. Otherwise, select the 32-bit register class.
02936     if (VT == MVT::Other)
02937       VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
02938 
02939     RC = getRegClassFor(VT);
02940 
02941     if (RC == &Mips::AFGR64RegClass) {
02942       assert(Reg % 2 == 0);
02943       Reg >>= 1;
02944     }
02945   } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
02946     RC = TRI->getRegClass(Mips::FCCRegClassID);
02947   else if (Prefix == "$w") { // Parse $w0-$w31.
02948     RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
02949   } else { // Parse $0-$31.
02950     assert(Prefix == "$");
02951     RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
02952   }
02953 
02954   assert(Reg < RC->getNumRegs());
02955   return std::make_pair(*(RC->begin() + Reg), RC);
02956 }
02957 
02958 /// Given a register class constraint, like 'r', if this corresponds directly
02959 /// to an LLVM register class, return a register of 0 and the register class
02960 /// pointer.
02961 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
02962 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
02963 {
02964   if (Constraint.size() == 1) {
02965     switch (Constraint[0]) {
02966     case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
02967     case 'y': // Same as 'r'. Exists for compatibility.
02968     case 'r':
02969       if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
02970         if (Subtarget->inMips16Mode())
02971           return std::make_pair(0U, &Mips::CPU16RegsRegClass);
02972         return std::make_pair(0U, &Mips::GPR32RegClass);
02973       }
02974       if (VT == MVT::i64 && !isGP64bit())
02975         return std::make_pair(0U, &Mips::GPR32RegClass);
02976       if (VT == MVT::i64 && isGP64bit())
02977         return std::make_pair(0U, &Mips::GPR64RegClass);
02978       // This will generate an error message
02979       return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
02980     case 'f': // FPU or MSA register
02981       if (VT == MVT::v16i8)
02982         return std::make_pair(0U, &Mips::MSA128BRegClass);
02983       else if (VT == MVT::v8i16 || VT == MVT::v8f16)
02984         return std::make_pair(0U, &Mips::MSA128HRegClass);
02985       else if (VT == MVT::v4i32 || VT == MVT::v4f32)
02986         return std::make_pair(0U, &Mips::MSA128WRegClass);
02987       else if (VT == MVT::v2i64 || VT == MVT::v2f64)
02988         return std::make_pair(0U, &Mips::MSA128DRegClass);
02989       else if (VT == MVT::f32)
02990         return std::make_pair(0U, &Mips::FGR32RegClass);
02991       else if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
02992         if (Subtarget->isFP64bit())
02993           return std::make_pair(0U, &Mips::FGR64RegClass);
02994         return std::make_pair(0U, &Mips::AFGR64RegClass);
02995       }
02996       break;
02997     case 'c': // register suitable for indirect jump
02998       if (VT == MVT::i32)
02999         return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
03000       assert(VT == MVT::i64 && "Unexpected type.");
03001       return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
03002     case 'l': // register suitable for indirect jump
03003       if (VT == MVT::i32)
03004         return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
03005       return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
03006     case 'x': // register suitable for indirect jump
03007       // Fixme: Not triggering the use of both hi and low
03008       // This will generate an error message
03009       return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
03010     }
03011   }
03012 
03013   std::pair<unsigned, const TargetRegisterClass *> R;
03014   R = parseRegForInlineAsmConstraint(Constraint, VT);
03015 
03016   if (R.second)
03017     return R;
03018 
03019   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
03020 }
03021 
03022 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
03023 /// vector.  If it is invalid, don't add anything to Ops.
03024 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
03025                                                      std::string &Constraint,
03026                                                      std::vector<SDValue>&Ops,
03027                                                      SelectionDAG &DAG) const {
03028   SDValue Result(0, 0);
03029 
03030   // Only support length 1 constraints for now.
03031   if (Constraint.length() > 1) return;
03032 
03033   char ConstraintLetter = Constraint[0];
03034   switch (ConstraintLetter) {
03035   default: break; // This will fall through to the generic implementation
03036   case 'I': // Signed 16 bit constant
03037     // If this fails, the parent routine will give an error
03038     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03039       EVT Type = Op.getValueType();
03040       int64_t Val = C->getSExtValue();
03041       if (isInt<16>(Val)) {
03042         Result = DAG.getTargetConstant(Val, Type);
03043         break;
03044       }
03045     }
03046     return;
03047   case 'J': // integer zero
03048     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03049       EVT Type = Op.getValueType();
03050       int64_t Val = C->getZExtValue();
03051       if (Val == 0) {
03052         Result = DAG.getTargetConstant(0, Type);
03053         break;
03054       }
03055     }
03056     return;
03057   case 'K': // unsigned 16 bit immediate
03058     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03059       EVT Type = Op.getValueType();
03060       uint64_t Val = (uint64_t)C->getZExtValue();
03061       if (isUInt<16>(Val)) {
03062         Result = DAG.getTargetConstant(Val, Type);
03063         break;
03064       }
03065     }
03066     return;
03067   case 'L': // signed 32 bit immediate where lower 16 bits are 0
03068     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03069       EVT Type = Op.getValueType();
03070       int64_t Val = C->getSExtValue();
03071       if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
03072         Result = DAG.getTargetConstant(Val, Type);
03073         break;
03074       }
03075     }
03076     return;
03077   case 'N': // immediate in the range of -65535 to -1 (inclusive)
03078     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03079       EVT Type = Op.getValueType();
03080       int64_t Val = C->getSExtValue();
03081       if ((Val >= -65535) && (Val <= -1)) {
03082         Result = DAG.getTargetConstant(Val, Type);
03083         break;
03084       }
03085     }
03086     return;
03087   case 'O': // signed 15 bit immediate
03088     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03089       EVT Type = Op.getValueType();
03090       int64_t Val = C->getSExtValue();
03091       if ((isInt<15>(Val))) {
03092         Result = DAG.getTargetConstant(Val, Type);
03093         break;
03094       }
03095     }
03096     return;
03097   case 'P': // immediate in the range of 1 to 65535 (inclusive)
03098     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03099       EVT Type = Op.getValueType();
03100       int64_t Val = C->getSExtValue();
03101       if ((Val <= 65535) && (Val >= 1)) {
03102         Result = DAG.getTargetConstant(Val, Type);
03103         break;
03104       }
03105     }
03106     return;
03107   }
03108 
03109   if (Result.getNode()) {
03110     Ops.push_back(Result);
03111     return;
03112   }
03113 
03114   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
03115 }
03116 
03117 bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM,
03118                                                Type *Ty) const {
03119   // No global is ever allowed as a base.
03120   if (AM.BaseGV)
03121     return false;
03122 
03123   switch (AM.Scale) {
03124   case 0: // "r+i" or just "i", depending on HasBaseReg.
03125     break;
03126   case 1:
03127     if (!AM.HasBaseReg) // allow "r+i".
03128       break;
03129     return false; // disallow "r+r" or "r+r+i".
03130   default:
03131     return false;
03132   }
03133 
03134   return true;
03135 }
03136 
03137 bool
03138 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
03139   // The Mips target isn't yet aware of offsets.
03140   return false;
03141 }
03142 
03143 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
03144                                             unsigned SrcAlign,
03145                                             bool IsMemset, bool ZeroMemset,
03146                                             bool MemcpyStrSrc,
03147                                             MachineFunction &MF) const {
03148   if (Subtarget->hasMips64())
03149     return MVT::i64;
03150 
03151   return MVT::i32;
03152 }
03153 
03154 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
03155   if (VT != MVT::f32 && VT != MVT::f64)
03156     return false;
03157   if (Imm.isNegZero())
03158     return false;
03159   return Imm.isZero();
03160 }
03161 
03162 unsigned MipsTargetLowering::getJumpTableEncoding() const {
03163   if (isN64())
03164     return MachineJumpTableInfo::EK_GPRel64BlockAddress;
03165 
03166   return TargetLowering::getJumpTableEncoding();
03167 }
03168 
03169 /// This function returns true if CallSym is a long double emulation routine.
03170 static bool isF128SoftLibCall(const char *CallSym) {
03171   const char *const LibCalls[] =
03172     {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2",
03173      "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi",
03174      "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf",
03175      "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2",
03176      "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3",
03177      "__trunctfdf2", "__trunctfsf2", "__unordtf2",
03178      "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl",
03179      "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl",
03180      "truncl"};
03181 
03182   const char *const *End = LibCalls + array_lengthof(LibCalls);
03183 
03184   // Check that LibCalls is sorted alphabetically.
03185   MipsTargetLowering::LTStr Comp;
03186 
03187 #ifndef NDEBUG
03188   for (const char *const *I = LibCalls; I < End - 1; ++I)
03189     assert(Comp(*I, *(I + 1)));
03190 #endif
03191 
03192   return std::binary_search(LibCalls, End, CallSym, Comp);
03193 }
03194 
03195 /// This function returns true if Ty is fp128 or i128 which was originally a
03196 /// fp128.
03197 static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) {
03198   if (Ty->isFP128Ty())
03199     return true;
03200 
03201   const ExternalSymbolSDNode *ES =
03202     dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode);
03203 
03204   // If the Ty is i128 and the function being called is a long double emulation
03205   // routine, then the original type is f128.
03206   return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol()));
03207 }
03208 
03209 MipsTargetLowering::MipsCC::SpecialCallingConvType
03210   MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const {
03211   MipsCC::SpecialCallingConvType SpecialCallingConv =
03212     MipsCC::NoSpecialCallingConv;
03213   if (Subtarget->inMips16HardFloat()) {
03214     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
03215       llvm::StringRef Sym = G->getGlobal()->getName();
03216       Function *F = G->getGlobal()->getParent()->getFunction(Sym);
03217       if (F && F->hasFnAttribute("__Mips16RetHelper")) {
03218         SpecialCallingConv = MipsCC::Mips16RetHelperConv;
03219       }
03220     }
03221   }
03222   return SpecialCallingConv;
03223 }
03224 
03225 MipsTargetLowering::MipsCC::MipsCC(
03226   CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info,
03227   MipsCC::SpecialCallingConvType SpecialCallingConv_)
03228   : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_),
03229     SpecialCallingConv(SpecialCallingConv_){
03230   // Pre-allocate reserved argument area.
03231   CCInfo.AllocateStack(reservedArgArea(), 1);
03232 }
03233 
03234 
03235 void MipsTargetLowering::MipsCC::
03236 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
03237                     bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode,
03238                     std::vector<ArgListEntry> &FuncArgs) {
03239   assert((CallConv != CallingConv::Fast || !IsVarArg) &&
03240          "CallingConv::Fast shouldn't be used for vararg functions.");
03241 
03242   unsigned NumOpnds = Args.size();
03243   llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
03244 
03245   for (unsigned I = 0; I != NumOpnds; ++I) {
03246     MVT ArgVT = Args[I].VT;
03247     ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
03248     bool R;
03249 
03250     if (ArgFlags.isByVal()) {
03251       handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
03252       continue;
03253     }
03254 
03255     if (IsVarArg && !Args[I].IsFixed)
03256       R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
03257     else {
03258       MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode,
03259                            IsSoftFloat);
03260       R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo);
03261     }
03262 
03263     if (R) {
03264 #ifndef NDEBUG
03265       dbgs() << "Call operand #" << I << " has unhandled type "
03266              << EVT(ArgVT).getEVTString();
03267 #endif
03268       llvm_unreachable(0);
03269     }
03270   }
03271 }
03272 
03273 void MipsTargetLowering::MipsCC::
03274 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
03275                        bool IsSoftFloat, Function::const_arg_iterator FuncArg) {
03276   unsigned NumArgs = Args.size();
03277   llvm::CCAssignFn *FixedFn = fixedArgFn();
03278   unsigned CurArgIdx = 0;
03279 
03280   for (unsigned I = 0; I != NumArgs; ++I) {
03281     MVT ArgVT = Args[I].VT;
03282     ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
03283     std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx);
03284     CurArgIdx = Args[I].OrigArgIndex;
03285 
03286     if (ArgFlags.isByVal()) {
03287       handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
03288       continue;
03289     }
03290 
03291     MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat);
03292 
03293     if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo))
03294       continue;
03295 
03296 #ifndef NDEBUG
03297     dbgs() << "Formal Arg #" << I << " has unhandled type "
03298            << EVT(ArgVT).getEVTString();
03299 #endif
03300     llvm_unreachable(0);
03301   }
03302 }
03303 
03304 template<typename Ty>
03305 void MipsTargetLowering::MipsCC::
03306 analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
03307               const SDNode *CallNode, const Type *RetTy) const {
03308   CCAssignFn *Fn;
03309 
03310   if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode))
03311     Fn = RetCC_F128Soft;
03312   else
03313     Fn = RetCC_Mips;
03314 
03315   for (unsigned I = 0, E = RetVals.size(); I < E; ++I) {
03316     MVT VT = RetVals[I].VT;
03317     ISD::ArgFlagsTy Flags = RetVals[I].Flags;
03318     MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat);
03319 
03320     if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) {
03321 #ifndef NDEBUG
03322       dbgs() << "Call result #" << I << " has unhandled type "
03323              << EVT(VT).getEVTString() << '\n';
03324 #endif
03325       llvm_unreachable(0);
03326     }
03327   }
03328 }
03329 
03330 void MipsTargetLowering::MipsCC::
03331 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat,
03332                   const SDNode *CallNode, const Type *RetTy) const {
03333   analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy);
03334 }
03335 
03336 void MipsTargetLowering::MipsCC::
03337 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
03338               const Type *RetTy) const {
03339   analyzeReturn(Outs, IsSoftFloat, 0, RetTy);
03340 }
03341 
03342 void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
03343                                                 MVT LocVT,
03344                                                 CCValAssign::LocInfo LocInfo,
03345                                                 ISD::ArgFlagsTy ArgFlags) {
03346   assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
03347 
03348   struct ByValArgInfo ByVal;
03349   unsigned RegSize = regSize();
03350   unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
03351   unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
03352                             RegSize * 2);
03353 
03354   if (useRegsForByval())
03355     allocateRegs(ByVal, ByValSize, Align);
03356 
03357   // Allocate space on caller's stack.
03358   ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
03359                                        Align);
03360   CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
03361                                     LocInfo));
03362   ByValArgs.push_back(ByVal);
03363 }
03364 
03365 unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
03366   return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
03367 }
03368 
03369 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
03370   return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
03371 }
03372 
03373 const MCPhysReg *MipsTargetLowering::MipsCC::intArgRegs() const {
03374   return IsO32 ? O32IntRegs : Mips64IntRegs;
03375 }
03376 
03377 llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
03378   if (CallConv == CallingConv::Fast)
03379     return CC_Mips_FastCC;
03380 
03381   if (SpecialCallingConv == Mips16RetHelperConv)
03382     return CC_Mips16RetHelper;
03383   return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN;
03384 }
03385 
03386 llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
03387   return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg;
03388 }
03389 
03390 const MCPhysReg *MipsTargetLowering::MipsCC::shadowRegs() const {
03391   return IsO32 ? O32IntRegs : Mips64DPRegs;
03392 }
03393 
03394 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
03395                                               unsigned ByValSize,
03396                                               unsigned Align) {
03397   unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
03398   const MCPhysReg *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
03399   assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
03400          "Byval argument's size and alignment should be a multiple of"
03401          "RegSize.");
03402 
03403   ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
03404 
03405   // If Align > RegSize, the first arg register must be even.
03406   if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
03407     CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
03408     ++ByVal.FirstIdx;
03409   }
03410 
03411   // Mark the registers allocated.
03412   for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
03413        ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
03414     CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
03415 }
03416 
03417 MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
03418                                          const SDNode *CallNode,
03419                                          bool IsSoftFloat) const {
03420   if (IsSoftFloat || IsO32)
03421     return VT;
03422 
03423   // Check if the original type was fp128.
03424   if (originalTypeIsF128(OrigTy, CallNode)) {
03425     assert(VT == MVT::i64);
03426     return MVT::f64;
03427   }
03428 
03429   return VT;
03430 }
03431 
03432 void MipsTargetLowering::
03433 copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
03434               SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
03435               SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
03436               const MipsCC &CC, const ByValArgInfo &ByVal) const {
03437   MachineFunction &MF = DAG.getMachineFunction();
03438   MachineFrameInfo *MFI = MF.getFrameInfo();
03439   unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
03440   unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
03441   int FrameObjOffset;
03442 
03443   if (RegAreaSize)
03444     FrameObjOffset = (int)CC.reservedArgArea() -
03445       (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
03446   else
03447     FrameObjOffset = ByVal.Address;
03448 
03449   // Create frame object.
03450   EVT PtrTy = getPointerTy();
03451   int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
03452   SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
03453   InVals.push_back(FIN);
03454 
03455   if (!ByVal.NumRegs)
03456     return;
03457 
03458   // Copy arg registers.
03459   MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
03460   const TargetRegisterClass *RC = getRegClassFor(RegTy);
03461 
03462   for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
03463     unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
03464     unsigned VReg = addLiveIn(MF, ArgReg, RC);
03465     unsigned Offset = I * CC.regSize();
03466     SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
03467                                    DAG.getConstant(Offset, PtrTy));
03468     SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
03469                                  StorePtr, MachinePointerInfo(FuncArg, Offset),
03470                                  false, false, 0);
03471     OutChains.push_back(Store);
03472   }
03473 }
03474 
03475 // Copy byVal arg to registers and stack.
03476 void MipsTargetLowering::
03477 passByValArg(SDValue Chain, SDLoc DL,
03478              std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
03479              SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
03480              MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
03481              const MipsCC &CC, const ByValArgInfo &ByVal,
03482              const ISD::ArgFlagsTy &Flags, bool isLittle) const {
03483   unsigned ByValSize = Flags.getByValSize();
03484   unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
03485   unsigned RegSize = CC.regSize();
03486   unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
03487   EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
03488 
03489   if (ByVal.NumRegs) {
03490     const MCPhysReg *ArgRegs = CC.intArgRegs();
03491     bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
03492     unsigned I = 0;
03493 
03494     // Copy words to registers.
03495     for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
03496       SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
03497                                     DAG.getConstant(Offset, PtrTy));
03498       SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
03499                                     MachinePointerInfo(), false, false, false,
03500                                     Alignment);
03501       MemOpChains.push_back(LoadVal.getValue(1));
03502       unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
03503       RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
03504     }
03505 
03506     // Return if the struct has been fully copied.
03507     if (ByValSize == Offset)
03508       return;
03509 
03510     // Copy the remainder of the byval argument with sub-word loads and shifts.
03511     if (LeftoverBytes) {
03512       assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
03513              "Size of the remainder should be smaller than RegSize.");
03514       SDValue Val;
03515 
03516       for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
03517            Offset < ByValSize; LoadSize /= 2) {
03518         unsigned RemSize = ByValSize - Offset;
03519 
03520         if (RemSize < LoadSize)
03521           continue;
03522 
03523         // Load subword.
03524         SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
03525                                       DAG.getConstant(Offset, PtrTy));
03526         SDValue LoadVal =
03527           DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
03528                          MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
03529                          false, false, Alignment);
03530         MemOpChains.push_back(LoadVal.getValue(1));
03531 
03532         // Shift the loaded value.
03533         unsigned Shamt;
03534 
03535         if (isLittle)
03536           Shamt = TotalSizeLoaded;
03537         else
03538           Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
03539 
03540         SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
03541                                     DAG.getConstant(Shamt, MVT::i32));
03542 
03543         if (Val.getNode())
03544           Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
03545         else
03546           Val = Shift;
03547 
03548         Offset += LoadSize;
03549         TotalSizeLoaded += LoadSize;
03550         Alignment = std::min(Alignment, LoadSize);
03551       }
03552 
03553       unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
03554       RegsToPass.push_back(std::make_pair(ArgReg, Val));
03555       return;
03556     }
03557   }
03558 
03559   // Copy remainder of byval arg to it with memcpy.
03560   unsigned MemCpySize = ByValSize - Offset;
03561   SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
03562                             DAG.getConstant(Offset, PtrTy));
03563   SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
03564                             DAG.getIntPtrConstant(ByVal.Address));
03565   Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
03566                         Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
03567                         MachinePointerInfo(), MachinePointerInfo());
03568   MemOpChains.push_back(Chain);
03569 }
03570 
03571 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
03572                                          const MipsCC &CC, SDValue Chain,
03573                                          SDLoc DL, SelectionDAG &DAG) const {
03574   unsigned NumRegs = CC.numIntArgRegs();
03575   const MCPhysReg *ArgRegs = CC.intArgRegs();
03576   const CCState &CCInfo = CC.getCCInfo();
03577   unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
03578   unsigned RegSize = CC.regSize();
03579   MVT RegTy = MVT::getIntegerVT(RegSize * 8);
03580   const TargetRegisterClass *RC = getRegClassFor(RegTy);
03581   MachineFunction &MF = DAG.getMachineFunction();
03582   MachineFrameInfo *MFI = MF.getFrameInfo();
03583   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
03584 
03585   // Offset of the first variable argument from stack pointer.
03586   int VaArgOffset;
03587 
03588   if (NumRegs == Idx)
03589     VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
03590   else
03591     VaArgOffset = (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
03592 
03593   // Record the frame index of the first variable argument
03594   // which is a value necessary to VASTART.
03595   int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
03596   MipsFI->setVarArgsFrameIndex(FI);
03597 
03598   // Copy the integer registers that have not been used for argument passing
03599   // to the argument register save area. For O32, the save area is allocated
03600   // in the caller's stack frame, while for N32/64, it is allocated in the
03601   // callee's stack frame.
03602   for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
03603     unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
03604     SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
03605     FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
03606     SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
03607     SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
03608                                  MachinePointerInfo(), false, false, 0);
03609     cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue((Value*)0);
03610     OutChains.push_back(Store);
03611   }
03612 }