LLVM API Documentation

MipsISelLowering.cpp
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00001 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines the interfaces that Mips uses to lower LLVM code into a
00011 // selection DAG.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 #include "MipsISelLowering.h"
00015 #include "InstPrinter/MipsInstPrinter.h"
00016 #include "MCTargetDesc/MipsBaseInfo.h"
00017 #include "MipsCCState.h"
00018 #include "MipsMachineFunction.h"
00019 #include "MipsSubtarget.h"
00020 #include "MipsTargetMachine.h"
00021 #include "MipsTargetObjectFile.h"
00022 #include "llvm/ADT/Statistic.h"
00023 #include "llvm/ADT/StringSwitch.h"
00024 #include "llvm/CodeGen/CallingConvLower.h"
00025 #include "llvm/CodeGen/MachineFrameInfo.h"
00026 #include "llvm/CodeGen/MachineFunction.h"
00027 #include "llvm/CodeGen/MachineInstrBuilder.h"
00028 #include "llvm/CodeGen/MachineJumpTableInfo.h"
00029 #include "llvm/CodeGen/MachineRegisterInfo.h"
00030 #include "llvm/CodeGen/SelectionDAGISel.h"
00031 #include "llvm/CodeGen/ValueTypes.h"
00032 #include "llvm/IR/CallingConv.h"
00033 #include "llvm/IR/DerivedTypes.h"
00034 #include "llvm/IR/GlobalVariable.h"
00035 #include "llvm/Support/CommandLine.h"
00036 #include "llvm/Support/Debug.h"
00037 #include "llvm/Support/ErrorHandling.h"
00038 #include "llvm/Support/raw_ostream.h"
00039 #include <cctype>
00040 
00041 using namespace llvm;
00042 
00043 #define DEBUG_TYPE "mips-lower"
00044 
00045 STATISTIC(NumTailCalls, "Number of tail calls");
00046 
00047 static cl::opt<bool>
00048 LargeGOT("mxgot", cl::Hidden,
00049          cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
00050 
00051 static cl::opt<bool>
00052 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
00053                cl::desc("MIPS: Don't trap on integer division by zero."),
00054                cl::init(false));
00055 
00056 cl::opt<bool>
00057 EnableMipsFastISel("mips-fast-isel", cl::Hidden,
00058   cl::desc("Allow mips-fast-isel to be used"),
00059   cl::init(false));
00060 
00061 static const MCPhysReg Mips64DPRegs[8] = {
00062   Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
00063   Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
00064 };
00065 
00066 // If I is a shifted mask, set the size (Size) and the first bit of the
00067 // mask (Pos), and return true.
00068 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
00069 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
00070   if (!isShiftedMask_64(I))
00071     return false;
00072 
00073   Size = CountPopulation_64(I);
00074   Pos = countTrailingZeros(I);
00075   return true;
00076 }
00077 
00078 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
00079   MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
00080   return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
00081 }
00082 
00083 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
00084                                           SelectionDAG &DAG,
00085                                           unsigned Flag) const {
00086   return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
00087 }
00088 
00089 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
00090                                           SelectionDAG &DAG,
00091                                           unsigned Flag) const {
00092   return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
00093 }
00094 
00095 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
00096                                           SelectionDAG &DAG,
00097                                           unsigned Flag) const {
00098   return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
00099 }
00100 
00101 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
00102                                           SelectionDAG &DAG,
00103                                           unsigned Flag) const {
00104   return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
00105 }
00106 
00107 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
00108                                           SelectionDAG &DAG,
00109                                           unsigned Flag) const {
00110   return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
00111                                    N->getOffset(), Flag);
00112 }
00113 
00114 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
00115   switch (Opcode) {
00116   case MipsISD::JmpLink:           return "MipsISD::JmpLink";
00117   case MipsISD::TailCall:          return "MipsISD::TailCall";
00118   case MipsISD::Hi:                return "MipsISD::Hi";
00119   case MipsISD::Lo:                return "MipsISD::Lo";
00120   case MipsISD::GPRel:             return "MipsISD::GPRel";
00121   case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
00122   case MipsISD::Ret:               return "MipsISD::Ret";
00123   case MipsISD::EH_RETURN:         return "MipsISD::EH_RETURN";
00124   case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
00125   case MipsISD::FPCmp:             return "MipsISD::FPCmp";
00126   case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
00127   case MipsISD::CMovFP_F:          return "MipsISD::CMovFP_F";
00128   case MipsISD::TruncIntFP:        return "MipsISD::TruncIntFP";
00129   case MipsISD::MFHI:              return "MipsISD::MFHI";
00130   case MipsISD::MFLO:              return "MipsISD::MFLO";
00131   case MipsISD::MTLOHI:            return "MipsISD::MTLOHI";
00132   case MipsISD::Mult:              return "MipsISD::Mult";
00133   case MipsISD::Multu:             return "MipsISD::Multu";
00134   case MipsISD::MAdd:              return "MipsISD::MAdd";
00135   case MipsISD::MAddu:             return "MipsISD::MAddu";
00136   case MipsISD::MSub:              return "MipsISD::MSub";
00137   case MipsISD::MSubu:             return "MipsISD::MSubu";
00138   case MipsISD::DivRem:            return "MipsISD::DivRem";
00139   case MipsISD::DivRemU:           return "MipsISD::DivRemU";
00140   case MipsISD::DivRem16:          return "MipsISD::DivRem16";
00141   case MipsISD::DivRemU16:         return "MipsISD::DivRemU16";
00142   case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64";
00143   case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
00144   case MipsISD::Wrapper:           return "MipsISD::Wrapper";
00145   case MipsISD::Sync:              return "MipsISD::Sync";
00146   case MipsISD::Ext:               return "MipsISD::Ext";
00147   case MipsISD::Ins:               return "MipsISD::Ins";
00148   case MipsISD::LWL:               return "MipsISD::LWL";
00149   case MipsISD::LWR:               return "MipsISD::LWR";
00150   case MipsISD::SWL:               return "MipsISD::SWL";
00151   case MipsISD::SWR:               return "MipsISD::SWR";
00152   case MipsISD::LDL:               return "MipsISD::LDL";
00153   case MipsISD::LDR:               return "MipsISD::LDR";
00154   case MipsISD::SDL:               return "MipsISD::SDL";
00155   case MipsISD::SDR:               return "MipsISD::SDR";
00156   case MipsISD::EXTP:              return "MipsISD::EXTP";
00157   case MipsISD::EXTPDP:            return "MipsISD::EXTPDP";
00158   case MipsISD::EXTR_S_H:          return "MipsISD::EXTR_S_H";
00159   case MipsISD::EXTR_W:            return "MipsISD::EXTR_W";
00160   case MipsISD::EXTR_R_W:          return "MipsISD::EXTR_R_W";
00161   case MipsISD::EXTR_RS_W:         return "MipsISD::EXTR_RS_W";
00162   case MipsISD::SHILO:             return "MipsISD::SHILO";
00163   case MipsISD::MTHLIP:            return "MipsISD::MTHLIP";
00164   case MipsISD::MULT:              return "MipsISD::MULT";
00165   case MipsISD::MULTU:             return "MipsISD::MULTU";
00166   case MipsISD::MADD_DSP:          return "MipsISD::MADD_DSP";
00167   case MipsISD::MADDU_DSP:         return "MipsISD::MADDU_DSP";
00168   case MipsISD::MSUB_DSP:          return "MipsISD::MSUB_DSP";
00169   case MipsISD::MSUBU_DSP:         return "MipsISD::MSUBU_DSP";
00170   case MipsISD::SHLL_DSP:          return "MipsISD::SHLL_DSP";
00171   case MipsISD::SHRA_DSP:          return "MipsISD::SHRA_DSP";
00172   case MipsISD::SHRL_DSP:          return "MipsISD::SHRL_DSP";
00173   case MipsISD::SETCC_DSP:         return "MipsISD::SETCC_DSP";
00174   case MipsISD::SELECT_CC_DSP:     return "MipsISD::SELECT_CC_DSP";
00175   case MipsISD::VALL_ZERO:         return "MipsISD::VALL_ZERO";
00176   case MipsISD::VANY_ZERO:         return "MipsISD::VANY_ZERO";
00177   case MipsISD::VALL_NONZERO:      return "MipsISD::VALL_NONZERO";
00178   case MipsISD::VANY_NONZERO:      return "MipsISD::VANY_NONZERO";
00179   case MipsISD::VCEQ:              return "MipsISD::VCEQ";
00180   case MipsISD::VCLE_S:            return "MipsISD::VCLE_S";
00181   case MipsISD::VCLE_U:            return "MipsISD::VCLE_U";
00182   case MipsISD::VCLT_S:            return "MipsISD::VCLT_S";
00183   case MipsISD::VCLT_U:            return "MipsISD::VCLT_U";
00184   case MipsISD::VSMAX:             return "MipsISD::VSMAX";
00185   case MipsISD::VSMIN:             return "MipsISD::VSMIN";
00186   case MipsISD::VUMAX:             return "MipsISD::VUMAX";
00187   case MipsISD::VUMIN:             return "MipsISD::VUMIN";
00188   case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
00189   case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
00190   case MipsISD::VNOR:              return "MipsISD::VNOR";
00191   case MipsISD::VSHF:              return "MipsISD::VSHF";
00192   case MipsISD::SHF:               return "MipsISD::SHF";
00193   case MipsISD::ILVEV:             return "MipsISD::ILVEV";
00194   case MipsISD::ILVOD:             return "MipsISD::ILVOD";
00195   case MipsISD::ILVL:              return "MipsISD::ILVL";
00196   case MipsISD::ILVR:              return "MipsISD::ILVR";
00197   case MipsISD::PCKEV:             return "MipsISD::PCKEV";
00198   case MipsISD::PCKOD:             return "MipsISD::PCKOD";
00199   case MipsISD::INSVE:             return "MipsISD::INSVE";
00200   default:                         return nullptr;
00201   }
00202 }
00203 
00204 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
00205                                        const MipsSubtarget &STI)
00206     : TargetLowering(TM), Subtarget(STI) {
00207   // Mips does not have i1 type, so use i32 for
00208   // setcc operations results (slt, sgt, ...).
00209   setBooleanContents(ZeroOrOneBooleanContent);
00210   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
00211   // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
00212   // does. Integer booleans still use 0 and 1.
00213   if (Subtarget.hasMips32r6())
00214     setBooleanContents(ZeroOrOneBooleanContent,
00215                        ZeroOrNegativeOneBooleanContent);
00216 
00217   // Load extented operations for i1 types must be promoted
00218   setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
00219   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
00220   setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
00221 
00222   // MIPS doesn't have extending float->double load/store
00223   setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
00224   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
00225 
00226   // Used by legalize types to correctly generate the setcc result.
00227   // Without this, every float setcc comes with a AND/OR with the result,
00228   // we don't want this, since the fpcmp result goes to a flag register,
00229   // which is used implicitly by brcond and select operations.
00230   AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
00231 
00232   // Mips Custom Operations
00233   setOperationAction(ISD::BR_JT,              MVT::Other, Custom);
00234   setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
00235   setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
00236   setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
00237   setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
00238   setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
00239   setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
00240   setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
00241   setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
00242   setOperationAction(ISD::SELECT_CC,          MVT::f32,   Custom);
00243   setOperationAction(ISD::SELECT_CC,          MVT::f64,   Custom);
00244   setOperationAction(ISD::SETCC,              MVT::f32,   Custom);
00245   setOperationAction(ISD::SETCC,              MVT::f64,   Custom);
00246   setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
00247   setOperationAction(ISD::FCOPYSIGN,          MVT::f32,   Custom);
00248   setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);
00249   setOperationAction(ISD::FP_TO_SINT,         MVT::i32,   Custom);
00250 
00251   if (Subtarget.isGP64bit()) {
00252     setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);
00253     setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
00254     setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);
00255     setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);
00256     setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);
00257     setOperationAction(ISD::SELECT,             MVT::i64,   Custom);
00258     setOperationAction(ISD::LOAD,               MVT::i64,   Custom);
00259     setOperationAction(ISD::STORE,              MVT::i64,   Custom);
00260     setOperationAction(ISD::FP_TO_SINT,         MVT::i64,   Custom);
00261   }
00262 
00263   if (!Subtarget.isGP64bit()) {
00264     setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);
00265     setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);
00266     setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);
00267   }
00268 
00269   setOperationAction(ISD::ADD,                MVT::i32,   Custom);
00270   if (Subtarget.isGP64bit())
00271     setOperationAction(ISD::ADD,                MVT::i64,   Custom);
00272 
00273   setOperationAction(ISD::SDIV, MVT::i32, Expand);
00274   setOperationAction(ISD::SREM, MVT::i32, Expand);
00275   setOperationAction(ISD::UDIV, MVT::i32, Expand);
00276   setOperationAction(ISD::UREM, MVT::i32, Expand);
00277   setOperationAction(ISD::SDIV, MVT::i64, Expand);
00278   setOperationAction(ISD::SREM, MVT::i64, Expand);
00279   setOperationAction(ISD::UDIV, MVT::i64, Expand);
00280   setOperationAction(ISD::UREM, MVT::i64, Expand);
00281 
00282   // Operations not directly supported by Mips.
00283   setOperationAction(ISD::BR_CC,             MVT::f32,   Expand);
00284   setOperationAction(ISD::BR_CC,             MVT::f64,   Expand);
00285   setOperationAction(ISD::BR_CC,             MVT::i32,   Expand);
00286   setOperationAction(ISD::BR_CC,             MVT::i64,   Expand);
00287   setOperationAction(ISD::SELECT_CC,         MVT::i32,   Expand);
00288   setOperationAction(ISD::SELECT_CC,         MVT::i64,   Expand);
00289   setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
00290   setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);
00291   setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
00292   setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);
00293   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
00294   if (Subtarget.hasCnMips()) {
00295     setOperationAction(ISD::CTPOP,           MVT::i32,   Legal);
00296     setOperationAction(ISD::CTPOP,           MVT::i64,   Legal);
00297   } else {
00298     setOperationAction(ISD::CTPOP,           MVT::i32,   Expand);
00299     setOperationAction(ISD::CTPOP,           MVT::i64,   Expand);
00300   }
00301   setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
00302   setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);
00303   setOperationAction(ISD::CTTZ_ZERO_UNDEF,   MVT::i32,   Expand);
00304   setOperationAction(ISD::CTTZ_ZERO_UNDEF,   MVT::i64,   Expand);
00305   setOperationAction(ISD::CTLZ_ZERO_UNDEF,   MVT::i32,   Expand);
00306   setOperationAction(ISD::CTLZ_ZERO_UNDEF,   MVT::i64,   Expand);
00307   setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
00308   setOperationAction(ISD::ROTL,              MVT::i64,   Expand);
00309   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);
00310   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);
00311 
00312   if (!Subtarget.hasMips32r2())
00313     setOperationAction(ISD::ROTR, MVT::i32,   Expand);
00314 
00315   if (!Subtarget.hasMips64r2())
00316     setOperationAction(ISD::ROTR, MVT::i64,   Expand);
00317 
00318   setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
00319   setOperationAction(ISD::FSIN,              MVT::f64,   Expand);
00320   setOperationAction(ISD::FCOS,              MVT::f32,   Expand);
00321   setOperationAction(ISD::FCOS,              MVT::f64,   Expand);
00322   setOperationAction(ISD::FSINCOS,           MVT::f32,   Expand);
00323   setOperationAction(ISD::FSINCOS,           MVT::f64,   Expand);
00324   setOperationAction(ISD::FPOWI,             MVT::f32,   Expand);
00325   setOperationAction(ISD::FPOW,              MVT::f32,   Expand);
00326   setOperationAction(ISD::FPOW,              MVT::f64,   Expand);
00327   setOperationAction(ISD::FLOG,              MVT::f32,   Expand);
00328   setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);
00329   setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);
00330   setOperationAction(ISD::FEXP,              MVT::f32,   Expand);
00331   setOperationAction(ISD::FMA,               MVT::f32,   Expand);
00332   setOperationAction(ISD::FMA,               MVT::f64,   Expand);
00333   setOperationAction(ISD::FREM,              MVT::f32,   Expand);
00334   setOperationAction(ISD::FREM,              MVT::f64,   Expand);
00335 
00336   setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
00337 
00338   setOperationAction(ISD::VASTART,           MVT::Other, Custom);
00339   setOperationAction(ISD::VAARG,             MVT::Other, Custom);
00340   setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
00341   setOperationAction(ISD::VAEND,             MVT::Other, Expand);
00342 
00343   // Use the default for now
00344   setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
00345   setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
00346 
00347   setOperationAction(ISD::ATOMIC_LOAD,       MVT::i32,    Expand);
00348   setOperationAction(ISD::ATOMIC_LOAD,       MVT::i64,    Expand);
00349   setOperationAction(ISD::ATOMIC_STORE,      MVT::i32,    Expand);
00350   setOperationAction(ISD::ATOMIC_STORE,      MVT::i64,    Expand);
00351 
00352   setInsertFencesForAtomic(true);
00353 
00354   if (!Subtarget.hasMips32r2()) {
00355     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
00356     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
00357   }
00358 
00359   // MIPS16 lacks MIPS32's clz and clo instructions.
00360   if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
00361     setOperationAction(ISD::CTLZ, MVT::i32, Expand);
00362   if (!Subtarget.hasMips64())
00363     setOperationAction(ISD::CTLZ, MVT::i64, Expand);
00364 
00365   if (!Subtarget.hasMips32r2())
00366     setOperationAction(ISD::BSWAP, MVT::i32, Expand);
00367   if (!Subtarget.hasMips64r2())
00368     setOperationAction(ISD::BSWAP, MVT::i64, Expand);
00369 
00370   if (Subtarget.isGP64bit()) {
00371     setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
00372     setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
00373     setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
00374     setTruncStoreAction(MVT::i64, MVT::i32, Custom);
00375   }
00376 
00377   setOperationAction(ISD::TRAP, MVT::Other, Legal);
00378 
00379   setTargetDAGCombine(ISD::SDIVREM);
00380   setTargetDAGCombine(ISD::UDIVREM);
00381   setTargetDAGCombine(ISD::SELECT);
00382   setTargetDAGCombine(ISD::AND);
00383   setTargetDAGCombine(ISD::OR);
00384   setTargetDAGCombine(ISD::ADD);
00385 
00386   setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
00387 
00388   // The arguments on the stack are defined in terms of 4-byte slots on O32
00389   // and 8-byte slots on N32/N64.
00390   setMinStackArgumentAlignment(
00391       (Subtarget.isABI_N32() || Subtarget.isABI_N64()) ? 8 : 4);
00392 
00393   setStackPointerRegisterToSaveRestore(Subtarget.isABI_N64() ? Mips::SP_64
00394                                                              : Mips::SP);
00395 
00396   setExceptionPointerRegister(Subtarget.isABI_N64() ? Mips::A0_64 : Mips::A0);
00397   setExceptionSelectorRegister(Subtarget.isABI_N64() ? Mips::A1_64 : Mips::A1);
00398 
00399   MaxStoresPerMemcpy = 16;
00400 
00401   isMicroMips = Subtarget.inMicroMipsMode();
00402 }
00403 
00404 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
00405                                                      const MipsSubtarget &STI) {
00406   if (STI.inMips16Mode())
00407     return llvm::createMips16TargetLowering(TM, STI);
00408 
00409   return llvm::createMipsSETargetLowering(TM, STI);
00410 }
00411 
00412 // Create a fast isel object.
00413 FastISel *
00414 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
00415                                   const TargetLibraryInfo *libInfo) const {
00416   if (!EnableMipsFastISel)
00417     return TargetLowering::createFastISel(funcInfo, libInfo);
00418   return Mips::createFastISel(funcInfo, libInfo);
00419 }
00420 
00421 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
00422   if (!VT.isVector())
00423     return MVT::i32;
00424   return VT.changeVectorElementTypeToInteger();
00425 }
00426 
00427 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
00428                                     TargetLowering::DAGCombinerInfo &DCI,
00429                                     const MipsSubtarget &Subtarget) {
00430   if (DCI.isBeforeLegalizeOps())
00431     return SDValue();
00432 
00433   EVT Ty = N->getValueType(0);
00434   unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
00435   unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
00436   unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
00437                                                   MipsISD::DivRemU16;
00438   SDLoc DL(N);
00439 
00440   SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
00441                                N->getOperand(0), N->getOperand(1));
00442   SDValue InChain = DAG.getEntryNode();
00443   SDValue InGlue = DivRem;
00444 
00445   // insert MFLO
00446   if (N->hasAnyUseOfValue(0)) {
00447     SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
00448                                             InGlue);
00449     DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
00450     InChain = CopyFromLo.getValue(1);
00451     InGlue = CopyFromLo.getValue(2);
00452   }
00453 
00454   // insert MFHI
00455   if (N->hasAnyUseOfValue(1)) {
00456     SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
00457                                             HI, Ty, InGlue);
00458     DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
00459   }
00460 
00461   return SDValue();
00462 }
00463 
00464 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
00465   switch (CC) {
00466   default: llvm_unreachable("Unknown fp condition code!");
00467   case ISD::SETEQ:
00468   case ISD::SETOEQ: return Mips::FCOND_OEQ;
00469   case ISD::SETUNE: return Mips::FCOND_UNE;
00470   case ISD::SETLT:
00471   case ISD::SETOLT: return Mips::FCOND_OLT;
00472   case ISD::SETGT:
00473   case ISD::SETOGT: return Mips::FCOND_OGT;
00474   case ISD::SETLE:
00475   case ISD::SETOLE: return Mips::FCOND_OLE;
00476   case ISD::SETGE:
00477   case ISD::SETOGE: return Mips::FCOND_OGE;
00478   case ISD::SETULT: return Mips::FCOND_ULT;
00479   case ISD::SETULE: return Mips::FCOND_ULE;
00480   case ISD::SETUGT: return Mips::FCOND_UGT;
00481   case ISD::SETUGE: return Mips::FCOND_UGE;
00482   case ISD::SETUO:  return Mips::FCOND_UN;
00483   case ISD::SETO:   return Mips::FCOND_OR;
00484   case ISD::SETNE:
00485   case ISD::SETONE: return Mips::FCOND_ONE;
00486   case ISD::SETUEQ: return Mips::FCOND_UEQ;
00487   }
00488 }
00489 
00490 
00491 /// This function returns true if the floating point conditional branches and
00492 /// conditional moves which use condition code CC should be inverted.
00493 static bool invertFPCondCodeUser(Mips::CondCode CC) {
00494   if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
00495     return false;
00496 
00497   assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
00498          "Illegal Condition Code");
00499 
00500   return true;
00501 }
00502 
00503 // Creates and returns an FPCmp node from a setcc node.
00504 // Returns Op if setcc is not a floating point comparison.
00505 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
00506   // must be a SETCC node
00507   if (Op.getOpcode() != ISD::SETCC)
00508     return Op;
00509 
00510   SDValue LHS = Op.getOperand(0);
00511 
00512   if (!LHS.getValueType().isFloatingPoint())
00513     return Op;
00514 
00515   SDValue RHS = Op.getOperand(1);
00516   SDLoc DL(Op);
00517 
00518   // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
00519   // node if necessary.
00520   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
00521 
00522   return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
00523                      DAG.getConstant(condCodeToFCC(CC), MVT::i32));
00524 }
00525 
00526 // Creates and returns a CMovFPT/F node.
00527 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
00528                             SDValue False, SDLoc DL) {
00529   ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
00530   bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
00531   SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
00532 
00533   return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
00534                      True.getValueType(), True, FCC0, False, Cond);
00535 }
00536 
00537 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
00538                                     TargetLowering::DAGCombinerInfo &DCI,
00539                                     const MipsSubtarget &Subtarget) {
00540   if (DCI.isBeforeLegalizeOps())
00541     return SDValue();
00542 
00543   SDValue SetCC = N->getOperand(0);
00544 
00545   if ((SetCC.getOpcode() != ISD::SETCC) ||
00546       !SetCC.getOperand(0).getValueType().isInteger())
00547     return SDValue();
00548 
00549   SDValue False = N->getOperand(2);
00550   EVT FalseTy = False.getValueType();
00551 
00552   if (!FalseTy.isInteger())
00553     return SDValue();
00554 
00555   ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
00556 
00557   // If the RHS (False) is 0, we swap the order of the operands
00558   // of ISD::SELECT (obviously also inverting the condition) so that we can
00559   // take advantage of conditional moves using the $0 register.
00560   // Example:
00561   //   return (a != 0) ? x : 0;
00562   //     load $reg, x
00563   //     movz $reg, $0, a
00564   if (!FalseC)
00565     return SDValue();
00566 
00567   const SDLoc DL(N);
00568 
00569   if (!FalseC->getZExtValue()) {
00570     ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
00571     SDValue True = N->getOperand(1);
00572 
00573     SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
00574                          SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
00575 
00576     return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
00577   }
00578 
00579   // If both operands are integer constants there's a possibility that we
00580   // can do some interesting optimizations.
00581   SDValue True = N->getOperand(1);
00582   ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
00583 
00584   if (!TrueC || !True.getValueType().isInteger())
00585     return SDValue();
00586 
00587   // We'll also ignore MVT::i64 operands as this optimizations proves
00588   // to be ineffective because of the required sign extensions as the result
00589   // of a SETCC operator is always MVT::i32 for non-vector types.
00590   if (True.getValueType() == MVT::i64)
00591     return SDValue();
00592 
00593   int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
00594 
00595   // 1)  (a < x) ? y : y-1
00596   //  slti $reg1, a, x
00597   //  addiu $reg2, $reg1, y-1
00598   if (Diff == 1)
00599     return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
00600 
00601   // 2)  (a < x) ? y-1 : y
00602   //  slti $reg1, a, x
00603   //  xor $reg1, $reg1, 1
00604   //  addiu $reg2, $reg1, y-1
00605   if (Diff == -1) {
00606     ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
00607     SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
00608                          SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
00609     return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
00610   }
00611 
00612   // Couldn't optimize.
00613   return SDValue();
00614 }
00615 
00616 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
00617                                  TargetLowering::DAGCombinerInfo &DCI,
00618                                  const MipsSubtarget &Subtarget) {
00619   // Pattern match EXT.
00620   //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
00621   //  => ext $dst, $src, size, pos
00622   if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
00623     return SDValue();
00624 
00625   SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
00626   unsigned ShiftRightOpc = ShiftRight.getOpcode();
00627 
00628   // Op's first operand must be a shift right.
00629   if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
00630     return SDValue();
00631 
00632   // The second operand of the shift must be an immediate.
00633   ConstantSDNode *CN;
00634   if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
00635     return SDValue();
00636 
00637   uint64_t Pos = CN->getZExtValue();
00638   uint64_t SMPos, SMSize;
00639 
00640   // Op's second operand must be a shifted mask.
00641   if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
00642       !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
00643     return SDValue();
00644 
00645   // Return if the shifted mask does not start at bit 0 or the sum of its size
00646   // and Pos exceeds the word's size.
00647   EVT ValTy = N->getValueType(0);
00648   if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
00649     return SDValue();
00650 
00651   return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
00652                      ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
00653                      DAG.getConstant(SMSize, MVT::i32));
00654 }
00655 
00656 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
00657                                 TargetLowering::DAGCombinerInfo &DCI,
00658                                 const MipsSubtarget &Subtarget) {
00659   // Pattern match INS.
00660   //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
00661   //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1
00662   //  => ins $dst, $src, size, pos, $src1
00663   if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
00664     return SDValue();
00665 
00666   SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
00667   uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
00668   ConstantSDNode *CN;
00669 
00670   // See if Op's first operand matches (and $src1 , mask0).
00671   if (And0.getOpcode() != ISD::AND)
00672     return SDValue();
00673 
00674   if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
00675       !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
00676     return SDValue();
00677 
00678   // See if Op's second operand matches (and (shl $src, pos), mask1).
00679   if (And1.getOpcode() != ISD::AND)
00680     return SDValue();
00681 
00682   if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
00683       !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
00684     return SDValue();
00685 
00686   // The shift masks must have the same position and size.
00687   if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
00688     return SDValue();
00689 
00690   SDValue Shl = And1.getOperand(0);
00691   if (Shl.getOpcode() != ISD::SHL)
00692     return SDValue();
00693 
00694   if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
00695     return SDValue();
00696 
00697   unsigned Shamt = CN->getZExtValue();
00698 
00699   // Return if the shift amount and the first bit position of mask are not the
00700   // same.
00701   EVT ValTy = N->getValueType(0);
00702   if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
00703     return SDValue();
00704 
00705   return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
00706                      DAG.getConstant(SMPos0, MVT::i32),
00707                      DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
00708 }
00709 
00710 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
00711                                  TargetLowering::DAGCombinerInfo &DCI,
00712                                  const MipsSubtarget &Subtarget) {
00713   // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
00714 
00715   if (DCI.isBeforeLegalizeOps())
00716     return SDValue();
00717 
00718   SDValue Add = N->getOperand(1);
00719 
00720   if (Add.getOpcode() != ISD::ADD)
00721     return SDValue();
00722 
00723   SDValue Lo = Add.getOperand(1);
00724 
00725   if ((Lo.getOpcode() != MipsISD::Lo) ||
00726       (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
00727     return SDValue();
00728 
00729   EVT ValTy = N->getValueType(0);
00730   SDLoc DL(N);
00731 
00732   SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
00733                              Add.getOperand(0));
00734   return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
00735 }
00736 
00737 SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
00738   const {
00739   SelectionDAG &DAG = DCI.DAG;
00740   unsigned Opc = N->getOpcode();
00741 
00742   switch (Opc) {
00743   default: break;
00744   case ISD::SDIVREM:
00745   case ISD::UDIVREM:
00746     return performDivRemCombine(N, DAG, DCI, Subtarget);
00747   case ISD::SELECT:
00748     return performSELECTCombine(N, DAG, DCI, Subtarget);
00749   case ISD::AND:
00750     return performANDCombine(N, DAG, DCI, Subtarget);
00751   case ISD::OR:
00752     return performORCombine(N, DAG, DCI, Subtarget);
00753   case ISD::ADD:
00754     return performADDCombine(N, DAG, DCI, Subtarget);
00755   }
00756 
00757   return SDValue();
00758 }
00759 
00760 void
00761 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
00762                                           SmallVectorImpl<SDValue> &Results,
00763                                           SelectionDAG &DAG) const {
00764   SDValue Res = LowerOperation(SDValue(N, 0), DAG);
00765 
00766   for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
00767     Results.push_back(Res.getValue(I));
00768 }
00769 
00770 void
00771 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
00772                                        SmallVectorImpl<SDValue> &Results,
00773                                        SelectionDAG &DAG) const {
00774   return LowerOperationWrapper(N, Results, DAG);
00775 }
00776 
00777 SDValue MipsTargetLowering::
00778 LowerOperation(SDValue Op, SelectionDAG &DAG) const
00779 {
00780   switch (Op.getOpcode())
00781   {
00782   case ISD::BR_JT:              return lowerBR_JT(Op, DAG);
00783   case ISD::BRCOND:             return lowerBRCOND(Op, DAG);
00784   case ISD::ConstantPool:       return lowerConstantPool(Op, DAG);
00785   case ISD::GlobalAddress:      return lowerGlobalAddress(Op, DAG);
00786   case ISD::BlockAddress:       return lowerBlockAddress(Op, DAG);
00787   case ISD::GlobalTLSAddress:   return lowerGlobalTLSAddress(Op, DAG);
00788   case ISD::JumpTable:          return lowerJumpTable(Op, DAG);
00789   case ISD::SELECT:             return lowerSELECT(Op, DAG);
00790   case ISD::SELECT_CC:          return lowerSELECT_CC(Op, DAG);
00791   case ISD::SETCC:              return lowerSETCC(Op, DAG);
00792   case ISD::VASTART:            return lowerVASTART(Op, DAG);
00793   case ISD::VAARG:              return lowerVAARG(Op, DAG);
00794   case ISD::FCOPYSIGN:          return lowerFCOPYSIGN(Op, DAG);
00795   case ISD::FRAMEADDR:          return lowerFRAMEADDR(Op, DAG);
00796   case ISD::RETURNADDR:         return lowerRETURNADDR(Op, DAG);
00797   case ISD::EH_RETURN:          return lowerEH_RETURN(Op, DAG);
00798   case ISD::ATOMIC_FENCE:       return lowerATOMIC_FENCE(Op, DAG);
00799   case ISD::SHL_PARTS:          return lowerShiftLeftParts(Op, DAG);
00800   case ISD::SRA_PARTS:          return lowerShiftRightParts(Op, DAG, true);
00801   case ISD::SRL_PARTS:          return lowerShiftRightParts(Op, DAG, false);
00802   case ISD::LOAD:               return lowerLOAD(Op, DAG);
00803   case ISD::STORE:              return lowerSTORE(Op, DAG);
00804   case ISD::ADD:                return lowerADD(Op, DAG);
00805   case ISD::FP_TO_SINT:         return lowerFP_TO_SINT(Op, DAG);
00806   }
00807   return SDValue();
00808 }
00809 
00810 //===----------------------------------------------------------------------===//
00811 //  Lower helper functions
00812 //===----------------------------------------------------------------------===//
00813 
00814 // addLiveIn - This helper function adds the specified physical register to the
00815 // MachineFunction as a live in value.  It also creates a corresponding
00816 // virtual register for it.
00817 static unsigned
00818 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
00819 {
00820   unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
00821   MF.getRegInfo().addLiveIn(PReg, VReg);
00822   return VReg;
00823 }
00824 
00825 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI,
00826                                               MachineBasicBlock &MBB,
00827                                               const TargetInstrInfo &TII,
00828                                               bool Is64Bit) {
00829   if (NoZeroDivCheck)
00830     return &MBB;
00831 
00832   // Insert instruction "teq $divisor_reg, $zero, 7".
00833   MachineBasicBlock::iterator I(MI);
00834   MachineInstrBuilder MIB;
00835   MachineOperand &Divisor = MI->getOperand(2);
00836   MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
00837     .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
00838     .addReg(Mips::ZERO).addImm(7);
00839 
00840   // Use the 32-bit sub-register if this is a 64-bit division.
00841   if (Is64Bit)
00842     MIB->getOperand(0).setSubReg(Mips::sub_32);
00843 
00844   // Clear Divisor's kill flag.
00845   Divisor.setIsKill(false);
00846 
00847   // We would normally delete the original instruction here but in this case
00848   // we only needed to inject an additional instruction rather than replace it.
00849 
00850   return &MBB;
00851 }
00852 
00853 MachineBasicBlock *
00854 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
00855                                                 MachineBasicBlock *BB) const {
00856   switch (MI->getOpcode()) {
00857   default:
00858     llvm_unreachable("Unexpected instr type to insert");
00859   case Mips::ATOMIC_LOAD_ADD_I8:
00860     return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
00861   case Mips::ATOMIC_LOAD_ADD_I16:
00862     return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
00863   case Mips::ATOMIC_LOAD_ADD_I32:
00864     return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
00865   case Mips::ATOMIC_LOAD_ADD_I64:
00866     return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
00867 
00868   case Mips::ATOMIC_LOAD_AND_I8:
00869     return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
00870   case Mips::ATOMIC_LOAD_AND_I16:
00871     return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
00872   case Mips::ATOMIC_LOAD_AND_I32:
00873     return emitAtomicBinary(MI, BB, 4, Mips::AND);
00874   case Mips::ATOMIC_LOAD_AND_I64:
00875     return emitAtomicBinary(MI, BB, 8, Mips::AND64);
00876 
00877   case Mips::ATOMIC_LOAD_OR_I8:
00878     return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
00879   case Mips::ATOMIC_LOAD_OR_I16:
00880     return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
00881   case Mips::ATOMIC_LOAD_OR_I32:
00882     return emitAtomicBinary(MI, BB, 4, Mips::OR);
00883   case Mips::ATOMIC_LOAD_OR_I64:
00884     return emitAtomicBinary(MI, BB, 8, Mips::OR64);
00885 
00886   case Mips::ATOMIC_LOAD_XOR_I8:
00887     return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
00888   case Mips::ATOMIC_LOAD_XOR_I16:
00889     return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
00890   case Mips::ATOMIC_LOAD_XOR_I32:
00891     return emitAtomicBinary(MI, BB, 4, Mips::XOR);
00892   case Mips::ATOMIC_LOAD_XOR_I64:
00893     return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
00894 
00895   case Mips::ATOMIC_LOAD_NAND_I8:
00896     return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
00897   case Mips::ATOMIC_LOAD_NAND_I16:
00898     return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
00899   case Mips::ATOMIC_LOAD_NAND_I32:
00900     return emitAtomicBinary(MI, BB, 4, 0, true);
00901   case Mips::ATOMIC_LOAD_NAND_I64:
00902     return emitAtomicBinary(MI, BB, 8, 0, true);
00903 
00904   case Mips::ATOMIC_LOAD_SUB_I8:
00905     return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
00906   case Mips::ATOMIC_LOAD_SUB_I16:
00907     return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
00908   case Mips::ATOMIC_LOAD_SUB_I32:
00909     return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
00910   case Mips::ATOMIC_LOAD_SUB_I64:
00911     return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
00912 
00913   case Mips::ATOMIC_SWAP_I8:
00914     return emitAtomicBinaryPartword(MI, BB, 1, 0);
00915   case Mips::ATOMIC_SWAP_I16:
00916     return emitAtomicBinaryPartword(MI, BB, 2, 0);
00917   case Mips::ATOMIC_SWAP_I32:
00918     return emitAtomicBinary(MI, BB, 4, 0);
00919   case Mips::ATOMIC_SWAP_I64:
00920     return emitAtomicBinary(MI, BB, 8, 0);
00921 
00922   case Mips::ATOMIC_CMP_SWAP_I8:
00923     return emitAtomicCmpSwapPartword(MI, BB, 1);
00924   case Mips::ATOMIC_CMP_SWAP_I16:
00925     return emitAtomicCmpSwapPartword(MI, BB, 2);
00926   case Mips::ATOMIC_CMP_SWAP_I32:
00927     return emitAtomicCmpSwap(MI, BB, 4);
00928   case Mips::ATOMIC_CMP_SWAP_I64:
00929     return emitAtomicCmpSwap(MI, BB, 8);
00930   case Mips::PseudoSDIV:
00931   case Mips::PseudoUDIV:
00932   case Mips::DIV:
00933   case Mips::DIVU:
00934   case Mips::MOD:
00935   case Mips::MODU:
00936     return insertDivByZeroTrap(
00937         MI, *BB, *getTargetMachine().getSubtargetImpl()->getInstrInfo(), false);
00938   case Mips::PseudoDSDIV:
00939   case Mips::PseudoDUDIV:
00940   case Mips::DDIV:
00941   case Mips::DDIVU:
00942   case Mips::DMOD:
00943   case Mips::DMODU:
00944     return insertDivByZeroTrap(
00945         MI, *BB, *getTargetMachine().getSubtargetImpl()->getInstrInfo(), true);
00946   case Mips::SEL_D:
00947     return emitSEL_D(MI, BB);
00948   }
00949 }
00950 
00951 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
00952 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
00953 MachineBasicBlock *
00954 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
00955                                      unsigned Size, unsigned BinOpcode,
00956                                      bool Nand) const {
00957   assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
00958 
00959   MachineFunction *MF = BB->getParent();
00960   MachineRegisterInfo &RegInfo = MF->getRegInfo();
00961   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
00962   const TargetInstrInfo *TII =
00963       getTargetMachine().getSubtargetImpl()->getInstrInfo();
00964   DebugLoc DL = MI->getDebugLoc();
00965   unsigned LL, SC, AND, NOR, ZERO, BEQ;
00966 
00967   if (Size == 4) {
00968     if (isMicroMips) {
00969       LL = Mips::LL_MM;
00970       SC = Mips::SC_MM;
00971     } else {
00972       LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
00973       SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
00974     }
00975     AND = Mips::AND;
00976     NOR = Mips::NOR;
00977     ZERO = Mips::ZERO;
00978     BEQ = Mips::BEQ;
00979   } else {
00980     LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
00981     SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
00982     AND = Mips::AND64;
00983     NOR = Mips::NOR64;
00984     ZERO = Mips::ZERO_64;
00985     BEQ = Mips::BEQ64;
00986   }
00987 
00988   unsigned OldVal = MI->getOperand(0).getReg();
00989   unsigned Ptr = MI->getOperand(1).getReg();
00990   unsigned Incr = MI->getOperand(2).getReg();
00991 
00992   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
00993   unsigned AndRes = RegInfo.createVirtualRegister(RC);
00994   unsigned Success = RegInfo.createVirtualRegister(RC);
00995 
00996   // insert new blocks after the current block
00997   const BasicBlock *LLVM_BB = BB->getBasicBlock();
00998   MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
00999   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01000   MachineFunction::iterator It = BB;
01001   ++It;
01002   MF->insert(It, loopMBB);
01003   MF->insert(It, exitMBB);
01004 
01005   // Transfer the remainder of BB and its successor edges to exitMBB.
01006   exitMBB->splice(exitMBB->begin(), BB,
01007                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
01008   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
01009 
01010   //  thisMBB:
01011   //    ...
01012   //    fallthrough --> loopMBB
01013   BB->addSuccessor(loopMBB);
01014   loopMBB->addSuccessor(loopMBB);
01015   loopMBB->addSuccessor(exitMBB);
01016 
01017   //  loopMBB:
01018   //    ll oldval, 0(ptr)
01019   //    <binop> storeval, oldval, incr
01020   //    sc success, storeval, 0(ptr)
01021   //    beq success, $0, loopMBB
01022   BB = loopMBB;
01023   BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
01024   if (Nand) {
01025     //  and andres, oldval, incr
01026     //  nor storeval, $0, andres
01027     BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
01028     BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
01029   } else if (BinOpcode) {
01030     //  <binop> storeval, oldval, incr
01031     BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
01032   } else {
01033     StoreVal = Incr;
01034   }
01035   BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
01036   BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
01037 
01038   MI->eraseFromParent(); // The instruction is gone now.
01039 
01040   return exitMBB;
01041 }
01042 
01043 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
01044     MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
01045     unsigned SrcReg) const {
01046   const TargetInstrInfo *TII =
01047       getTargetMachine().getSubtargetImpl()->getInstrInfo();
01048   DebugLoc DL = MI->getDebugLoc();
01049 
01050   if (Subtarget.hasMips32r2() && Size == 1) {
01051     BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
01052     return BB;
01053   }
01054 
01055   if (Subtarget.hasMips32r2() && Size == 2) {
01056     BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
01057     return BB;
01058   }
01059 
01060   MachineFunction *MF = BB->getParent();
01061   MachineRegisterInfo &RegInfo = MF->getRegInfo();
01062   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
01063   unsigned ScrReg = RegInfo.createVirtualRegister(RC);
01064 
01065   assert(Size < 32);
01066   int64_t ShiftImm = 32 - (Size * 8);
01067 
01068   BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
01069   BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
01070 
01071   return BB;
01072 }
01073 
01074 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
01075     MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
01076     bool Nand) const {
01077   assert((Size == 1 || Size == 2) &&
01078          "Unsupported size for EmitAtomicBinaryPartial.");
01079 
01080   MachineFunction *MF = BB->getParent();
01081   MachineRegisterInfo &RegInfo = MF->getRegInfo();
01082   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
01083   const TargetInstrInfo *TII =
01084       getTargetMachine().getSubtargetImpl()->getInstrInfo();
01085   DebugLoc DL = MI->getDebugLoc();
01086 
01087   unsigned Dest = MI->getOperand(0).getReg();
01088   unsigned Ptr = MI->getOperand(1).getReg();
01089   unsigned Incr = MI->getOperand(2).getReg();
01090 
01091   unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
01092   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
01093   unsigned Mask = RegInfo.createVirtualRegister(RC);
01094   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
01095   unsigned NewVal = RegInfo.createVirtualRegister(RC);
01096   unsigned OldVal = RegInfo.createVirtualRegister(RC);
01097   unsigned Incr2 = RegInfo.createVirtualRegister(RC);
01098   unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
01099   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
01100   unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
01101   unsigned AndRes = RegInfo.createVirtualRegister(RC);
01102   unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
01103   unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
01104   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
01105   unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
01106   unsigned SrlRes = RegInfo.createVirtualRegister(RC);
01107   unsigned Success = RegInfo.createVirtualRegister(RC);
01108 
01109   // insert new blocks after the current block
01110   const BasicBlock *LLVM_BB = BB->getBasicBlock();
01111   MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01112   MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01113   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01114   MachineFunction::iterator It = BB;
01115   ++It;
01116   MF->insert(It, loopMBB);
01117   MF->insert(It, sinkMBB);
01118   MF->insert(It, exitMBB);
01119 
01120   // Transfer the remainder of BB and its successor edges to exitMBB.
01121   exitMBB->splice(exitMBB->begin(), BB,
01122                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
01123   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
01124 
01125   BB->addSuccessor(loopMBB);
01126   loopMBB->addSuccessor(loopMBB);
01127   loopMBB->addSuccessor(sinkMBB);
01128   sinkMBB->addSuccessor(exitMBB);
01129 
01130   //  thisMBB:
01131   //    addiu   masklsb2,$0,-4                # 0xfffffffc
01132   //    and     alignedaddr,ptr,masklsb2
01133   //    andi    ptrlsb2,ptr,3
01134   //    sll     shiftamt,ptrlsb2,3
01135   //    ori     maskupper,$0,255               # 0xff
01136   //    sll     mask,maskupper,shiftamt
01137   //    nor     mask2,$0,mask
01138   //    sll     incr2,incr,shiftamt
01139 
01140   int64_t MaskImm = (Size == 1) ? 255 : 65535;
01141   BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
01142     .addReg(Mips::ZERO).addImm(-4);
01143   BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
01144     .addReg(Ptr).addReg(MaskLSB2);
01145   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
01146   if (Subtarget.isLittle()) {
01147     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
01148   } else {
01149     unsigned Off = RegInfo.createVirtualRegister(RC);
01150     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
01151       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
01152     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
01153   }
01154   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
01155     .addReg(Mips::ZERO).addImm(MaskImm);
01156   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
01157     .addReg(MaskUpper).addReg(ShiftAmt);
01158   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
01159   BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
01160 
01161   // atomic.load.binop
01162   // loopMBB:
01163   //   ll      oldval,0(alignedaddr)
01164   //   binop   binopres,oldval,incr2
01165   //   and     newval,binopres,mask
01166   //   and     maskedoldval0,oldval,mask2
01167   //   or      storeval,maskedoldval0,newval
01168   //   sc      success,storeval,0(alignedaddr)
01169   //   beq     success,$0,loopMBB
01170 
01171   // atomic.swap
01172   // loopMBB:
01173   //   ll      oldval,0(alignedaddr)
01174   //   and     newval,incr2,mask
01175   //   and     maskedoldval0,oldval,mask2
01176   //   or      storeval,maskedoldval0,newval
01177   //   sc      success,storeval,0(alignedaddr)
01178   //   beq     success,$0,loopMBB
01179 
01180   BB = loopMBB;
01181   BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
01182   if (Nand) {
01183     //  and andres, oldval, incr2
01184     //  nor binopres, $0, andres
01185     //  and newval, binopres, mask
01186     BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
01187     BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
01188       .addReg(Mips::ZERO).addReg(AndRes);
01189     BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
01190   } else if (BinOpcode) {
01191     //  <binop> binopres, oldval, incr2
01192     //  and newval, binopres, mask
01193     BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
01194     BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
01195   } else { // atomic.swap
01196     //  and newval, incr2, mask
01197     BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
01198   }
01199 
01200   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
01201     .addReg(OldVal).addReg(Mask2);
01202   BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
01203     .addReg(MaskedOldVal0).addReg(NewVal);
01204   BuildMI(BB, DL, TII->get(Mips::SC), Success)
01205     .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
01206   BuildMI(BB, DL, TII->get(Mips::BEQ))
01207     .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
01208 
01209   //  sinkMBB:
01210   //    and     maskedoldval1,oldval,mask
01211   //    srl     srlres,maskedoldval1,shiftamt
01212   //    sign_extend dest,srlres
01213   BB = sinkMBB;
01214 
01215   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
01216     .addReg(OldVal).addReg(Mask);
01217   BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
01218       .addReg(MaskedOldVal1).addReg(ShiftAmt);
01219   BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
01220 
01221   MI->eraseFromParent(); // The instruction is gone now.
01222 
01223   return exitMBB;
01224 }
01225 
01226 MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
01227                                                           MachineBasicBlock *BB,
01228                                                           unsigned Size) const {
01229   assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
01230 
01231   MachineFunction *MF = BB->getParent();
01232   MachineRegisterInfo &RegInfo = MF->getRegInfo();
01233   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
01234   const TargetInstrInfo *TII =
01235       getTargetMachine().getSubtargetImpl()->getInstrInfo();
01236   DebugLoc DL = MI->getDebugLoc();
01237   unsigned LL, SC, ZERO, BNE, BEQ;
01238 
01239   if (Size == 4) {
01240     LL = isMicroMips ? Mips::LL_MM : Mips::LL;
01241     SC = isMicroMips ? Mips::SC_MM : Mips::SC;
01242     ZERO = Mips::ZERO;
01243     BNE = Mips::BNE;
01244     BEQ = Mips::BEQ;
01245   } else {
01246     LL = Mips::LLD;
01247     SC = Mips::SCD;
01248     ZERO = Mips::ZERO_64;
01249     BNE = Mips::BNE64;
01250     BEQ = Mips::BEQ64;
01251   }
01252 
01253   unsigned Dest    = MI->getOperand(0).getReg();
01254   unsigned Ptr     = MI->getOperand(1).getReg();
01255   unsigned OldVal  = MI->getOperand(2).getReg();
01256   unsigned NewVal  = MI->getOperand(3).getReg();
01257 
01258   unsigned Success = RegInfo.createVirtualRegister(RC);
01259 
01260   // insert new blocks after the current block
01261   const BasicBlock *LLVM_BB = BB->getBasicBlock();
01262   MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
01263   MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
01264   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01265   MachineFunction::iterator It = BB;
01266   ++It;
01267   MF->insert(It, loop1MBB);
01268   MF->insert(It, loop2MBB);
01269   MF->insert(It, exitMBB);
01270 
01271   // Transfer the remainder of BB and its successor edges to exitMBB.
01272   exitMBB->splice(exitMBB->begin(), BB,
01273                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
01274   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
01275 
01276   //  thisMBB:
01277   //    ...
01278   //    fallthrough --> loop1MBB
01279   BB->addSuccessor(loop1MBB);
01280   loop1MBB->addSuccessor(exitMBB);
01281   loop1MBB->addSuccessor(loop2MBB);
01282   loop2MBB->addSuccessor(loop1MBB);
01283   loop2MBB->addSuccessor(exitMBB);
01284 
01285   // loop1MBB:
01286   //   ll dest, 0(ptr)
01287   //   bne dest, oldval, exitMBB
01288   BB = loop1MBB;
01289   BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
01290   BuildMI(BB, DL, TII->get(BNE))
01291     .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
01292 
01293   // loop2MBB:
01294   //   sc success, newval, 0(ptr)
01295   //   beq success, $0, loop1MBB
01296   BB = loop2MBB;
01297   BuildMI(BB, DL, TII->get(SC), Success)
01298     .addReg(NewVal).addReg(Ptr).addImm(0);
01299   BuildMI(BB, DL, TII->get(BEQ))
01300     .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
01301 
01302   MI->eraseFromParent(); // The instruction is gone now.
01303 
01304   return exitMBB;
01305 }
01306 
01307 MachineBasicBlock *
01308 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
01309                                               MachineBasicBlock *BB,
01310                                               unsigned Size) const {
01311   assert((Size == 1 || Size == 2) &&
01312       "Unsupported size for EmitAtomicCmpSwapPartial.");
01313 
01314   MachineFunction *MF = BB->getParent();
01315   MachineRegisterInfo &RegInfo = MF->getRegInfo();
01316   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
01317   const TargetInstrInfo *TII =
01318       getTargetMachine().getSubtargetImpl()->getInstrInfo();
01319   DebugLoc DL = MI->getDebugLoc();
01320 
01321   unsigned Dest    = MI->getOperand(0).getReg();
01322   unsigned Ptr     = MI->getOperand(1).getReg();
01323   unsigned CmpVal  = MI->getOperand(2).getReg();
01324   unsigned NewVal  = MI->getOperand(3).getReg();
01325 
01326   unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
01327   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
01328   unsigned Mask = RegInfo.createVirtualRegister(RC);
01329   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
01330   unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
01331   unsigned OldVal = RegInfo.createVirtualRegister(RC);
01332   unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
01333   unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
01334   unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
01335   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
01336   unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
01337   unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
01338   unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
01339   unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
01340   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
01341   unsigned SrlRes = RegInfo.createVirtualRegister(RC);
01342   unsigned Success = RegInfo.createVirtualRegister(RC);
01343 
01344   // insert new blocks after the current block
01345   const BasicBlock *LLVM_BB = BB->getBasicBlock();
01346   MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
01347   MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
01348   MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01349   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
01350   MachineFunction::iterator It = BB;
01351   ++It;
01352   MF->insert(It, loop1MBB);
01353   MF->insert(It, loop2MBB);
01354   MF->insert(It, sinkMBB);
01355   MF->insert(It, exitMBB);
01356 
01357   // Transfer the remainder of BB and its successor edges to exitMBB.
01358   exitMBB->splice(exitMBB->begin(), BB,
01359                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
01360   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
01361 
01362   BB->addSuccessor(loop1MBB);
01363   loop1MBB->addSuccessor(sinkMBB);
01364   loop1MBB->addSuccessor(loop2MBB);
01365   loop2MBB->addSuccessor(loop1MBB);
01366   loop2MBB->addSuccessor(sinkMBB);
01367   sinkMBB->addSuccessor(exitMBB);
01368 
01369   // FIXME: computation of newval2 can be moved to loop2MBB.
01370   //  thisMBB:
01371   //    addiu   masklsb2,$0,-4                # 0xfffffffc
01372   //    and     alignedaddr,ptr,masklsb2
01373   //    andi    ptrlsb2,ptr,3
01374   //    sll     shiftamt,ptrlsb2,3
01375   //    ori     maskupper,$0,255               # 0xff
01376   //    sll     mask,maskupper,shiftamt
01377   //    nor     mask2,$0,mask
01378   //    andi    maskedcmpval,cmpval,255
01379   //    sll     shiftedcmpval,maskedcmpval,shiftamt
01380   //    andi    maskednewval,newval,255
01381   //    sll     shiftednewval,maskednewval,shiftamt
01382   int64_t MaskImm = (Size == 1) ? 255 : 65535;
01383   BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
01384     .addReg(Mips::ZERO).addImm(-4);
01385   BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
01386     .addReg(Ptr).addReg(MaskLSB2);
01387   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
01388   if (Subtarget.isLittle()) {
01389     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
01390   } else {
01391     unsigned Off = RegInfo.createVirtualRegister(RC);
01392     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
01393       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
01394     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
01395   }
01396   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
01397     .addReg(Mips::ZERO).addImm(MaskImm);
01398   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
01399     .addReg(MaskUpper).addReg(ShiftAmt);
01400   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
01401   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
01402     .addReg(CmpVal).addImm(MaskImm);
01403   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
01404     .addReg(MaskedCmpVal).addReg(ShiftAmt);
01405   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
01406     .addReg(NewVal).addImm(MaskImm);
01407   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
01408     .addReg(MaskedNewVal).addReg(ShiftAmt);
01409 
01410   //  loop1MBB:
01411   //    ll      oldval,0(alginedaddr)
01412   //    and     maskedoldval0,oldval,mask
01413   //    bne     maskedoldval0,shiftedcmpval,sinkMBB
01414   BB = loop1MBB;
01415   BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
01416   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
01417     .addReg(OldVal).addReg(Mask);
01418   BuildMI(BB, DL, TII->get(Mips::BNE))
01419     .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
01420 
01421   //  loop2MBB:
01422   //    and     maskedoldval1,oldval,mask2
01423   //    or      storeval,maskedoldval1,shiftednewval
01424   //    sc      success,storeval,0(alignedaddr)
01425   //    beq     success,$0,loop1MBB
01426   BB = loop2MBB;
01427   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
01428     .addReg(OldVal).addReg(Mask2);
01429   BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
01430     .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
01431   BuildMI(BB, DL, TII->get(Mips::SC), Success)
01432       .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
01433   BuildMI(BB, DL, TII->get(Mips::BEQ))
01434       .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
01435 
01436   //  sinkMBB:
01437   //    srl     srlres,maskedoldval0,shiftamt
01438   //    sign_extend dest,srlres
01439   BB = sinkMBB;
01440 
01441   BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
01442       .addReg(MaskedOldVal0).addReg(ShiftAmt);
01443   BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
01444 
01445   MI->eraseFromParent();   // The instruction is gone now.
01446 
01447   return exitMBB;
01448 }
01449 
01450 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI,
01451                                                  MachineBasicBlock *BB) const {
01452   MachineFunction *MF = BB->getParent();
01453   const TargetRegisterInfo *TRI =
01454       getTargetMachine().getSubtargetImpl()->getRegisterInfo();
01455   const TargetInstrInfo *TII =
01456       getTargetMachine().getSubtargetImpl()->getInstrInfo();
01457   MachineRegisterInfo &RegInfo = MF->getRegInfo();
01458   DebugLoc DL = MI->getDebugLoc();
01459   MachineBasicBlock::iterator II(MI);
01460 
01461   unsigned Fc = MI->getOperand(1).getReg();
01462   const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
01463 
01464   unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
01465 
01466   BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
01467       .addImm(0)
01468       .addReg(Fc)
01469       .addImm(Mips::sub_lo);
01470 
01471   // We don't erase the original instruction, we just replace the condition
01472   // register with the 64-bit super-register.
01473   MI->getOperand(1).setReg(Fc2);
01474 
01475   return BB;
01476 }
01477 
01478 //===----------------------------------------------------------------------===//
01479 //  Misc Lower Operation implementation
01480 //===----------------------------------------------------------------------===//
01481 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
01482   SDValue Chain = Op.getOperand(0);
01483   SDValue Table = Op.getOperand(1);
01484   SDValue Index = Op.getOperand(2);
01485   SDLoc DL(Op);
01486   EVT PTy = getPointerTy();
01487   unsigned EntrySize =
01488     DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
01489 
01490   Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
01491                       DAG.getConstant(EntrySize, PTy));
01492   SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
01493 
01494   EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
01495   Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
01496                         MachinePointerInfo::getJumpTable(), MemVT, false, false,
01497                         false, 0);
01498   Chain = Addr.getValue(1);
01499 
01500   if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) ||
01501       Subtarget.isABI_N64()) {
01502     // For PIC, the sequence is:
01503     // BRIND(load(Jumptable + index) + RelocBase)
01504     // RelocBase can be JumpTable, GOT or some sort of global base.
01505     Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
01506                        getPICJumpTableRelocBase(Table, DAG));
01507   }
01508 
01509   return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
01510 }
01511 
01512 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
01513   // The first operand is the chain, the second is the condition, the third is
01514   // the block to branch to if the condition is true.
01515   SDValue Chain = Op.getOperand(0);
01516   SDValue Dest = Op.getOperand(2);
01517   SDLoc DL(Op);
01518 
01519   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
01520   SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
01521 
01522   // Return if flag is not set by a floating point comparison.
01523   if (CondRes.getOpcode() != MipsISD::FPCmp)
01524     return Op;
01525 
01526   SDValue CCNode  = CondRes.getOperand(2);
01527   Mips::CondCode CC =
01528     (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
01529   unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
01530   SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
01531   SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
01532   return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
01533                      FCC0, Dest, CondRes);
01534 }
01535 
01536 SDValue MipsTargetLowering::
01537 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
01538 {
01539   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
01540   SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
01541 
01542   // Return if flag is not set by a floating point comparison.
01543   if (Cond.getOpcode() != MipsISD::FPCmp)
01544     return Op;
01545 
01546   return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
01547                       SDLoc(Op));
01548 }
01549 
01550 SDValue MipsTargetLowering::
01551 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
01552 {
01553   SDLoc DL(Op);
01554   EVT Ty = Op.getOperand(0).getValueType();
01555   SDValue Cond = DAG.getNode(ISD::SETCC, DL,
01556                              getSetCCResultType(*DAG.getContext(), Ty),
01557                              Op.getOperand(0), Op.getOperand(1),
01558                              Op.getOperand(4));
01559 
01560   return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
01561                      Op.getOperand(3));
01562 }
01563 
01564 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
01565   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
01566   SDValue Cond = createFPCmp(DAG, Op);
01567 
01568   assert(Cond.getOpcode() == MipsISD::FPCmp &&
01569          "Floating point operand expected.");
01570 
01571   SDValue True  = DAG.getConstant(1, MVT::i32);
01572   SDValue False = DAG.getConstant(0, MVT::i32);
01573 
01574   return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
01575 }
01576 
01577 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
01578                                                SelectionDAG &DAG) const {
01579   EVT Ty = Op.getValueType();
01580   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
01581   const GlobalValue *GV = N->getGlobal();
01582 
01583   if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
01584       !Subtarget.isABI_N64()) {
01585     const MipsTargetObjectFile &TLOF =
01586       (const MipsTargetObjectFile&)getObjFileLowering();
01587 
01588     if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine()))
01589       // %gp_rel relocation
01590       return getAddrGPRel(N, Ty, DAG);
01591 
01592     // %hi/%lo relocation
01593     return getAddrNonPIC(N, Ty, DAG);
01594   }
01595 
01596   if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
01597     return getAddrLocal(N, Ty, DAG,
01598                         Subtarget.isABI_N32() || Subtarget.isABI_N64());
01599 
01600   if (LargeGOT)
01601     return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16,
01602                                  MipsII::MO_GOT_LO16, DAG.getEntryNode(),
01603                                  MachinePointerInfo::getGOT());
01604 
01605   return getAddrGlobal(N, Ty, DAG,
01606                        (Subtarget.isABI_N32() || Subtarget.isABI_N64())
01607                            ? MipsII::MO_GOT_DISP
01608                            : MipsII::MO_GOT16,
01609                        DAG.getEntryNode(), MachinePointerInfo::getGOT());
01610 }
01611 
01612 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
01613                                               SelectionDAG &DAG) const {
01614   BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
01615   EVT Ty = Op.getValueType();
01616 
01617   if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
01618       !Subtarget.isABI_N64())
01619     return getAddrNonPIC(N, Ty, DAG);
01620 
01621   return getAddrLocal(N, Ty, DAG,
01622                       Subtarget.isABI_N32() || Subtarget.isABI_N64());
01623 }
01624 
01625 SDValue MipsTargetLowering::
01626 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
01627 {
01628   // If the relocation model is PIC, use the General Dynamic TLS Model or
01629   // Local Dynamic TLS model, otherwise use the Initial Exec or
01630   // Local Exec TLS Model.
01631 
01632   GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
01633   SDLoc DL(GA);
01634   const GlobalValue *GV = GA->getGlobal();
01635   EVT PtrVT = getPointerTy();
01636 
01637   TLSModel::Model model = getTargetMachine().getTLSModel(GV);
01638 
01639   if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
01640     // General Dynamic and Local Dynamic TLS Model.
01641     unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
01642                                                       : MipsII::MO_TLSGD;
01643 
01644     SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
01645     SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
01646                                    getGlobalReg(DAG, PtrVT), TGA);
01647     unsigned PtrSize = PtrVT.getSizeInBits();
01648     IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
01649 
01650     SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
01651 
01652     ArgListTy Args;
01653     ArgListEntry Entry;
01654     Entry.Node = Argument;
01655     Entry.Ty = PtrTy;
01656     Args.push_back(Entry);
01657 
01658     TargetLowering::CallLoweringInfo CLI(DAG);
01659     CLI.setDebugLoc(DL).setChain(DAG.getEntryNode())
01660       .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0);
01661     std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
01662 
01663     SDValue Ret = CallResult.first;
01664 
01665     if (model != TLSModel::LocalDynamic)
01666       return Ret;
01667 
01668     SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
01669                                                MipsII::MO_DTPREL_HI);
01670     SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
01671     SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
01672                                                MipsII::MO_DTPREL_LO);
01673     SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
01674     SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
01675     return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
01676   }
01677 
01678   SDValue Offset;
01679   if (model == TLSModel::InitialExec) {
01680     // Initial Exec TLS Model
01681     SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
01682                                              MipsII::MO_GOTTPREL);
01683     TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
01684                       TGA);
01685     Offset = DAG.getLoad(PtrVT, DL,
01686                          DAG.getEntryNode(), TGA, MachinePointerInfo(),
01687                          false, false, false, 0);
01688   } else {
01689     // Local Exec TLS Model
01690     assert(model == TLSModel::LocalExec);
01691     SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
01692                                                MipsII::MO_TPREL_HI);
01693     SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
01694                                                MipsII::MO_TPREL_LO);
01695     SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
01696     SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
01697     Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
01698   }
01699 
01700   SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
01701   return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
01702 }
01703 
01704 SDValue MipsTargetLowering::
01705 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
01706 {
01707   JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
01708   EVT Ty = Op.getValueType();
01709 
01710   if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
01711       !Subtarget.isABI_N64())
01712     return getAddrNonPIC(N, Ty, DAG);
01713 
01714   return getAddrLocal(N, Ty, DAG,
01715                       Subtarget.isABI_N32() || Subtarget.isABI_N64());
01716 }
01717 
01718 SDValue MipsTargetLowering::
01719 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
01720 {
01721   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
01722   EVT Ty = Op.getValueType();
01723 
01724   if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
01725       !Subtarget.isABI_N64()) {
01726     const MipsTargetObjectFile &TLOF =
01727       (const MipsTargetObjectFile&)getObjFileLowering();
01728 
01729     if (TLOF.IsConstantInSmallSection(N->getConstVal(), getTargetMachine()))
01730       // %gp_rel relocation
01731       return getAddrGPRel(N, Ty, DAG);
01732 
01733     return getAddrNonPIC(N, Ty, DAG);
01734   }
01735 
01736   return getAddrLocal(N, Ty, DAG,
01737                       Subtarget.isABI_N32() || Subtarget.isABI_N64());
01738 }
01739 
01740 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
01741   MachineFunction &MF = DAG.getMachineFunction();
01742   MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
01743 
01744   SDLoc DL(Op);
01745   SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
01746                                  getPointerTy());
01747 
01748   // vastart just stores the address of the VarArgsFrameIndex slot into the
01749   // memory location argument.
01750   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
01751   return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
01752                       MachinePointerInfo(SV), false, false, 0);
01753 }
01754 
01755 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
01756   SDNode *Node = Op.getNode();
01757   EVT VT = Node->getValueType(0);
01758   SDValue Chain = Node->getOperand(0);
01759   SDValue VAListPtr = Node->getOperand(1);
01760   unsigned Align = Node->getConstantOperandVal(3);
01761   const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
01762   SDLoc DL(Node);
01763   unsigned ArgSlotSizeInBytes =
01764       (Subtarget.isABI_N32() || Subtarget.isABI_N64()) ? 8 : 4;
01765 
01766   SDValue VAListLoad = DAG.getLoad(getPointerTy(), DL, Chain, VAListPtr,
01767                                    MachinePointerInfo(SV), false, false, false,
01768                                    0);
01769   SDValue VAList = VAListLoad;
01770 
01771   // Re-align the pointer if necessary.
01772   // It should only ever be necessary for 64-bit types on O32 since the minimum
01773   // argument alignment is the same as the maximum type alignment for N32/N64.
01774   //
01775   // FIXME: We currently align too often. The code generator doesn't notice
01776   //        when the pointer is still aligned from the last va_arg (or pair of
01777   //        va_args for the i64 on O32 case).
01778   if (Align > getMinStackArgumentAlignment()) {
01779     assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
01780 
01781     VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
01782                          DAG.getConstant(Align - 1,
01783                                          VAList.getValueType()));
01784 
01785     VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
01786                          DAG.getConstant(-(int64_t)Align,
01787                                          VAList.getValueType()));
01788   }
01789 
01790   // Increment the pointer, VAList, to the next vaarg.
01791   unsigned ArgSizeInBytes = getDataLayout()->getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
01792   SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
01793                              DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes, ArgSlotSizeInBytes),
01794                                              VAList.getValueType()));
01795   // Store the incremented VAList to the legalized pointer
01796   Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
01797                       MachinePointerInfo(SV), false, false, 0);
01798 
01799   // In big-endian mode we must adjust the pointer when the load size is smaller
01800   // than the argument slot size. We must also reduce the known alignment to
01801   // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
01802   // the correct half of the slot, and reduce the alignment from 8 (slot
01803   // alignment) down to 4 (type alignment).
01804   if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
01805     unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
01806     VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
01807                          DAG.getIntPtrConstant(Adjustment));
01808   }
01809   // Load the actual argument out of the pointer VAList
01810   return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
01811                      false, 0);
01812 }
01813 
01814 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
01815                                 bool HasExtractInsert) {
01816   EVT TyX = Op.getOperand(0).getValueType();
01817   EVT TyY = Op.getOperand(1).getValueType();
01818   SDValue Const1 = DAG.getConstant(1, MVT::i32);
01819   SDValue Const31 = DAG.getConstant(31, MVT::i32);
01820   SDLoc DL(Op);
01821   SDValue Res;
01822 
01823   // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
01824   // to i32.
01825   SDValue X = (TyX == MVT::f32) ?
01826     DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
01827     DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
01828                 Const1);
01829   SDValue Y = (TyY == MVT::f32) ?
01830     DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
01831     DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
01832                 Const1);
01833 
01834   if (HasExtractInsert) {
01835     // ext  E, Y, 31, 1  ; extract bit31 of Y
01836     // ins  X, E, 31, 1  ; insert extracted bit at bit31 of X
01837     SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
01838     Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
01839   } else {
01840     // sll SllX, X, 1
01841     // srl SrlX, SllX, 1
01842     // srl SrlY, Y, 31
01843     // sll SllY, SrlX, 31
01844     // or  Or, SrlX, SllY
01845     SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
01846     SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
01847     SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
01848     SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
01849     Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
01850   }
01851 
01852   if (TyX == MVT::f32)
01853     return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
01854 
01855   SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
01856                              Op.getOperand(0), DAG.getConstant(0, MVT::i32));
01857   return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
01858 }
01859 
01860 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
01861                                 bool HasExtractInsert) {
01862   unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
01863   unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
01864   EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
01865   SDValue Const1 = DAG.getConstant(1, MVT::i32);
01866   SDLoc DL(Op);
01867 
01868   // Bitcast to integer nodes.
01869   SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
01870   SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
01871 
01872   if (HasExtractInsert) {
01873     // ext  E, Y, width(Y) - 1, 1  ; extract bit width(Y)-1 of Y
01874     // ins  X, E, width(X) - 1, 1  ; insert extracted bit at bit width(X)-1 of X
01875     SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
01876                             DAG.getConstant(WidthY - 1, MVT::i32), Const1);
01877 
01878     if (WidthX > WidthY)
01879       E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
01880     else if (WidthY > WidthX)
01881       E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
01882 
01883     SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
01884                             DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
01885     return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
01886   }
01887 
01888   // (d)sll SllX, X, 1
01889   // (d)srl SrlX, SllX, 1
01890   // (d)srl SrlY, Y, width(Y)-1
01891   // (d)sll SllY, SrlX, width(Y)-1
01892   // or     Or, SrlX, SllY
01893   SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
01894   SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
01895   SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
01896                              DAG.getConstant(WidthY - 1, MVT::i32));
01897 
01898   if (WidthX > WidthY)
01899     SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
01900   else if (WidthY > WidthX)
01901     SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
01902 
01903   SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
01904                              DAG.getConstant(WidthX - 1, MVT::i32));
01905   SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
01906   return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
01907 }
01908 
01909 SDValue
01910 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
01911   if (Subtarget.isGP64bit())
01912     return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
01913 
01914   return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
01915 }
01916 
01917 SDValue MipsTargetLowering::
01918 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
01919   // check the depth
01920   assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
01921          "Frame address can only be determined for current frame.");
01922 
01923   MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
01924   MFI->setFrameAddressIsTaken(true);
01925   EVT VT = Op.getValueType();
01926   SDLoc DL(Op);
01927   SDValue FrameAddr =
01928       DAG.getCopyFromReg(DAG.getEntryNode(), DL,
01929                          Subtarget.isABI_N64() ? Mips::FP_64 : Mips::FP, VT);
01930   return FrameAddr;
01931 }
01932 
01933 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
01934                                             SelectionDAG &DAG) const {
01935   if (verifyReturnAddressArgumentIsConstant(Op, DAG))
01936     return SDValue();
01937 
01938   // check the depth
01939   assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
01940          "Return address can be determined only for current frame.");
01941 
01942   MachineFunction &MF = DAG.getMachineFunction();
01943   MachineFrameInfo *MFI = MF.getFrameInfo();
01944   MVT VT = Op.getSimpleValueType();
01945   unsigned RA = Subtarget.isABI_N64() ? Mips::RA_64 : Mips::RA;
01946   MFI->setReturnAddressIsTaken(true);
01947 
01948   // Return RA, which contains the return address. Mark it an implicit live-in.
01949   unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
01950   return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
01951 }
01952 
01953 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
01954 // generated from __builtin_eh_return (offset, handler)
01955 // The effect of this is to adjust the stack pointer by "offset"
01956 // and then branch to "handler".
01957 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
01958                                                                      const {
01959   MachineFunction &MF = DAG.getMachineFunction();
01960   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
01961 
01962   MipsFI->setCallsEhReturn();
01963   SDValue Chain     = Op.getOperand(0);
01964   SDValue Offset    = Op.getOperand(1);
01965   SDValue Handler   = Op.getOperand(2);
01966   SDLoc DL(Op);
01967   EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32;
01968 
01969   // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
01970   // EH_RETURN nodes, so that instructions are emitted back-to-back.
01971   unsigned OffsetReg = Subtarget.isABI_N64() ? Mips::V1_64 : Mips::V1;
01972   unsigned AddrReg = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0;
01973   Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
01974   Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
01975   return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
01976                      DAG.getRegister(OffsetReg, Ty),
01977                      DAG.getRegister(AddrReg, getPointerTy()),
01978                      Chain.getValue(1));
01979 }
01980 
01981 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
01982                                               SelectionDAG &DAG) const {
01983   // FIXME: Need pseudo-fence for 'singlethread' fences
01984   // FIXME: Set SType for weaker fences where supported/appropriate.
01985   unsigned SType = 0;
01986   SDLoc DL(Op);
01987   return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
01988                      DAG.getConstant(SType, MVT::i32));
01989 }
01990 
01991 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
01992                                                 SelectionDAG &DAG) const {
01993   SDLoc DL(Op);
01994   SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
01995   SDValue Shamt = Op.getOperand(2);
01996 
01997   // if shamt < 32:
01998   //  lo = (shl lo, shamt)
01999   //  hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
02000   // else:
02001   //  lo = 0
02002   //  hi = (shl lo, shamt[4:0])
02003   SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
02004                             DAG.getConstant(-1, MVT::i32));
02005   SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
02006                                       DAG.getConstant(1, MVT::i32));
02007   SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
02008                                      Not);
02009   SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
02010   SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
02011   SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
02012   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
02013                              DAG.getConstant(0x20, MVT::i32));
02014   Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
02015                    DAG.getConstant(0, MVT::i32), ShiftLeftLo);
02016   Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
02017 
02018   SDValue Ops[2] = {Lo, Hi};
02019   return DAG.getMergeValues(Ops, DL);
02020 }
02021 
02022 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
02023                                                  bool IsSRA) const {
02024   SDLoc DL(Op);
02025   SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
02026   SDValue Shamt = Op.getOperand(2);
02027 
02028   // if shamt < 32:
02029   //  lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
02030   //  if isSRA:
02031   //    hi = (sra hi, shamt)
02032   //  else:
02033   //    hi = (srl hi, shamt)
02034   // else:
02035   //  if isSRA:
02036   //   lo = (sra hi, shamt[4:0])
02037   //   hi = (sra hi, 31)
02038   //  else:
02039   //   lo = (srl hi, shamt[4:0])
02040   //   hi = 0
02041   SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
02042                             DAG.getConstant(-1, MVT::i32));
02043   SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
02044                                      DAG.getConstant(1, MVT::i32));
02045   SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
02046   SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
02047   SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
02048   SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
02049                                      Hi, Shamt);
02050   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
02051                              DAG.getConstant(0x20, MVT::i32));
02052   SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
02053                                 DAG.getConstant(31, MVT::i32));
02054   Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
02055   Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
02056                    IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
02057                    ShiftRightHi);
02058 
02059   SDValue Ops[2] = {Lo, Hi};
02060   return DAG.getMergeValues(Ops, DL);
02061 }
02062 
02063 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
02064                             SDValue Chain, SDValue Src, unsigned Offset) {
02065   SDValue Ptr = LD->getBasePtr();
02066   EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
02067   EVT BasePtrVT = Ptr.getValueType();
02068   SDLoc DL(LD);
02069   SDVTList VTList = DAG.getVTList(VT, MVT::Other);
02070 
02071   if (Offset)
02072     Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
02073                       DAG.getConstant(Offset, BasePtrVT));
02074 
02075   SDValue Ops[] = { Chain, Ptr, Src };
02076   return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
02077                                  LD->getMemOperand());
02078 }
02079 
02080 // Expand an unaligned 32 or 64-bit integer load node.
02081 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
02082   LoadSDNode *LD = cast<LoadSDNode>(Op);
02083   EVT MemVT = LD->getMemoryVT();
02084 
02085   if (Subtarget.systemSupportsUnalignedAccess())
02086     return Op;
02087 
02088   // Return if load is aligned or if MemVT is neither i32 nor i64.
02089   if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
02090       ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
02091     return SDValue();
02092 
02093   bool IsLittle = Subtarget.isLittle();
02094   EVT VT = Op.getValueType();
02095   ISD::LoadExtType ExtType = LD->getExtensionType();
02096   SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
02097 
02098   assert((VT == MVT::i32) || (VT == MVT::i64));
02099 
02100   // Expand
02101   //  (set dst, (i64 (load baseptr)))
02102   // to
02103   //  (set tmp, (ldl (add baseptr, 7), undef))
02104   //  (set dst, (ldr baseptr, tmp))
02105   if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
02106     SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
02107                                IsLittle ? 7 : 0);
02108     return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
02109                         IsLittle ? 0 : 7);
02110   }
02111 
02112   SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
02113                              IsLittle ? 3 : 0);
02114   SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
02115                              IsLittle ? 0 : 3);
02116 
02117   // Expand
02118   //  (set dst, (i32 (load baseptr))) or
02119   //  (set dst, (i64 (sextload baseptr))) or
02120   //  (set dst, (i64 (extload baseptr)))
02121   // to
02122   //  (set tmp, (lwl (add baseptr, 3), undef))
02123   //  (set dst, (lwr baseptr, tmp))
02124   if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
02125       (ExtType == ISD::EXTLOAD))
02126     return LWR;
02127 
02128   assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
02129 
02130   // Expand
02131   //  (set dst, (i64 (zextload baseptr)))
02132   // to
02133   //  (set tmp0, (lwl (add baseptr, 3), undef))
02134   //  (set tmp1, (lwr baseptr, tmp0))
02135   //  (set tmp2, (shl tmp1, 32))
02136   //  (set dst, (srl tmp2, 32))
02137   SDLoc DL(LD);
02138   SDValue Const32 = DAG.getConstant(32, MVT::i32);
02139   SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
02140   SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
02141   SDValue Ops[] = { SRL, LWR.getValue(1) };
02142   return DAG.getMergeValues(Ops, DL);
02143 }
02144 
02145 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
02146                              SDValue Chain, unsigned Offset) {
02147   SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
02148   EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
02149   SDLoc DL(SD);
02150   SDVTList VTList = DAG.getVTList(MVT::Other);
02151 
02152   if (Offset)
02153     Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
02154                       DAG.getConstant(Offset, BasePtrVT));
02155 
02156   SDValue Ops[] = { Chain, Value, Ptr };
02157   return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
02158                                  SD->getMemOperand());
02159 }
02160 
02161 // Expand an unaligned 32 or 64-bit integer store node.
02162 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
02163                                       bool IsLittle) {
02164   SDValue Value = SD->getValue(), Chain = SD->getChain();
02165   EVT VT = Value.getValueType();
02166 
02167   // Expand
02168   //  (store val, baseptr) or
02169   //  (truncstore val, baseptr)
02170   // to
02171   //  (swl val, (add baseptr, 3))
02172   //  (swr val, baseptr)
02173   if ((VT == MVT::i32) || SD->isTruncatingStore()) {
02174     SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
02175                                 IsLittle ? 3 : 0);
02176     return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
02177   }
02178 
02179   assert(VT == MVT::i64);
02180 
02181   // Expand
02182   //  (store val, baseptr)
02183   // to
02184   //  (sdl val, (add baseptr, 7))
02185   //  (sdr val, baseptr)
02186   SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
02187   return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
02188 }
02189 
02190 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
02191 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
02192   SDValue Val = SD->getValue();
02193 
02194   if (Val.getOpcode() != ISD::FP_TO_SINT)
02195     return SDValue();
02196 
02197   EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
02198   SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
02199                            Val.getOperand(0));
02200 
02201   return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
02202                       SD->getPointerInfo(), SD->isVolatile(),
02203                       SD->isNonTemporal(), SD->getAlignment());
02204 }
02205 
02206 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
02207   StoreSDNode *SD = cast<StoreSDNode>(Op);
02208   EVT MemVT = SD->getMemoryVT();
02209 
02210   // Lower unaligned integer stores.
02211   if (!Subtarget.systemSupportsUnalignedAccess() &&
02212       (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
02213       ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
02214     return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
02215 
02216   return lowerFP_TO_SINT_STORE(SD, DAG);
02217 }
02218 
02219 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
02220   if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
02221       || cast<ConstantSDNode>
02222         (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
02223       || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
02224     return SDValue();
02225 
02226   // The pattern
02227   //   (add (frameaddr 0), (frame_to_args_offset))
02228   // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
02229   //   (add FrameObject, 0)
02230   // where FrameObject is a fixed StackObject with offset 0 which points to
02231   // the old stack pointer.
02232   MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
02233   EVT ValTy = Op->getValueType(0);
02234   int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
02235   SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
02236   return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
02237                      DAG.getConstant(0, ValTy));
02238 }
02239 
02240 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
02241                                             SelectionDAG &DAG) const {
02242   EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
02243   SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
02244                               Op.getOperand(0));
02245   return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
02246 }
02247 
02248 //===----------------------------------------------------------------------===//
02249 //                      Calling Convention Implementation
02250 //===----------------------------------------------------------------------===//
02251 
02252 //===----------------------------------------------------------------------===//
02253 // TODO: Implement a generic logic using tblgen that can support this.
02254 // Mips O32 ABI rules:
02255 // ---
02256 // i32 - Passed in A0, A1, A2, A3 and stack
02257 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
02258 //       an argument. Otherwise, passed in A1, A2, A3 and stack.
02259 // f64 - Only passed in two aliased f32 registers if no int reg has been used
02260 //       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
02261 //       not used, it must be shadowed. If only A3 is available, shadow it and
02262 //       go to stack.
02263 //
02264 //  For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
02265 //===----------------------------------------------------------------------===//
02266 
02267 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
02268                        CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
02269                        CCState &State, const MCPhysReg *F64Regs) {
02270 
02271   static const unsigned IntRegsSize = 4, FloatRegsSize = 2;
02272 
02273   static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
02274   static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
02275 
02276   // Do not process byval args here.
02277   if (ArgFlags.isByVal())
02278     return true;
02279 
02280   // Promote i8 and i16
02281   if (LocVT == MVT::i8 || LocVT == MVT::i16) {
02282     LocVT = MVT::i32;
02283     if (ArgFlags.isSExt())
02284       LocInfo = CCValAssign::SExt;
02285     else if (ArgFlags.isZExt())
02286       LocInfo = CCValAssign::ZExt;
02287     else
02288       LocInfo = CCValAssign::AExt;
02289   }
02290 
02291   unsigned Reg;
02292 
02293   // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
02294   // is true: function is vararg, argument is 3rd or higher, there is previous
02295   // argument which is not f32 or f64.
02296   bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
02297       || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
02298   unsigned OrigAlign = ArgFlags.getOrigAlign();
02299   bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
02300 
02301   if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
02302     Reg = State.AllocateReg(IntRegs, IntRegsSize);
02303     // If this is the first part of an i64 arg,
02304     // the allocated register must be either A0 or A2.
02305     if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
02306       Reg = State.AllocateReg(IntRegs, IntRegsSize);
02307     LocVT = MVT::i32;
02308   } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
02309     // Allocate int register and shadow next int register. If first
02310     // available register is Mips::A1 or Mips::A3, shadow it too.
02311     Reg = State.AllocateReg(IntRegs, IntRegsSize);
02312     if (Reg == Mips::A1 || Reg == Mips::A3)
02313       Reg = State.AllocateReg(IntRegs, IntRegsSize);
02314     State.AllocateReg(IntRegs, IntRegsSize);
02315     LocVT = MVT::i32;
02316   } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
02317     // we are guaranteed to find an available float register
02318     if (ValVT == MVT::f32) {
02319       Reg = State.AllocateReg(F32Regs, FloatRegsSize);
02320       // Shadow int register
02321       State.AllocateReg(IntRegs, IntRegsSize);
02322     } else {
02323       Reg = State.AllocateReg(F64Regs, FloatRegsSize);
02324       // Shadow int registers
02325       unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
02326       if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
02327         State.AllocateReg(IntRegs, IntRegsSize);
02328       State.AllocateReg(IntRegs, IntRegsSize);
02329     }
02330   } else
02331     llvm_unreachable("Cannot handle this ValVT.");
02332 
02333   if (!Reg) {
02334     unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
02335                                           OrigAlign);
02336     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
02337   } else
02338     State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
02339 
02340   return false;
02341 }
02342 
02343 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
02344                             MVT LocVT, CCValAssign::LocInfo LocInfo,
02345                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
02346   static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
02347 
02348   return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
02349 }
02350 
02351 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
02352                             MVT LocVT, CCValAssign::LocInfo LocInfo,
02353                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
02354   static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
02355 
02356   return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
02357 }
02358 
02359 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
02360                        CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
02361                        CCState &State) LLVM_ATTRIBUTE_UNUSED;
02362 
02363 #include "MipsGenCallingConv.inc"
02364 
02365 //===----------------------------------------------------------------------===//
02366 //                  Call Calling Convention Implementation
02367 //===----------------------------------------------------------------------===//
02368 
02369 // Return next O32 integer argument register.
02370 static unsigned getNextIntArgReg(unsigned Reg) {
02371   assert((Reg == Mips::A0) || (Reg == Mips::A2));
02372   return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
02373 }
02374 
02375 SDValue
02376 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
02377                                    SDValue Chain, SDValue Arg, SDLoc DL,
02378                                    bool IsTailCall, SelectionDAG &DAG) const {
02379   if (!IsTailCall) {
02380     SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
02381                                  DAG.getIntPtrConstant(Offset));
02382     return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
02383                         false, 0);
02384   }
02385 
02386   MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
02387   int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
02388   SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
02389   return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
02390                       /*isVolatile=*/ true, false, 0);
02391 }
02392 
02393 void MipsTargetLowering::
02394 getOpndList(SmallVectorImpl<SDValue> &Ops,
02395             std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
02396             bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
02397             bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
02398             SDValue Chain) const {
02399   // Insert node "GP copy globalreg" before call to function.
02400   //
02401   // R_MIPS_CALL* operators (emitted when non-internal functions are called
02402   // in PIC mode) allow symbols to be resolved via lazy binding.
02403   // The lazy binding stub requires GP to point to the GOT.
02404   // Note that we don't need GP to point to the GOT for indirect calls
02405   // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
02406   // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
02407   // used for the function (that is, Mips linker doesn't generate lazy binding
02408   // stub for a function whose address is taken in the program).
02409   if (IsPICCall && !InternalLinkage && IsCallReloc) {
02410     unsigned GPReg = Subtarget.isABI_N64() ? Mips::GP_64 : Mips::GP;
02411     EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32;
02412     RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
02413   }
02414 
02415   // Build a sequence of copy-to-reg nodes chained together with token
02416   // chain and flag operands which copy the outgoing args into registers.
02417   // The InFlag in necessary since all emitted instructions must be
02418   // stuck together.
02419   SDValue InFlag;
02420 
02421   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
02422     Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
02423                                  RegsToPass[i].second, InFlag);
02424     InFlag = Chain.getValue(1);
02425   }
02426 
02427   // Add argument registers to the end of the list so that they are
02428   // known live into the call.
02429   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
02430     Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
02431                                       RegsToPass[i].second.getValueType()));
02432 
02433   // Add a register mask operand representing the call-preserved registers.
02434   const TargetRegisterInfo *TRI =
02435       getTargetMachine().getSubtargetImpl()->getRegisterInfo();
02436   const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
02437   assert(Mask && "Missing call preserved mask for calling convention");
02438   if (Subtarget.inMips16HardFloat()) {
02439     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
02440       llvm::StringRef Sym = G->getGlobal()->getName();
02441       Function *F = G->getGlobal()->getParent()->getFunction(Sym);
02442       if (F && F->hasFnAttribute("__Mips16RetHelper")) {
02443         Mask = MipsRegisterInfo::getMips16RetHelperMask();
02444       }
02445     }
02446   }
02447   Ops.push_back(CLI.DAG.getRegisterMask(Mask));
02448 
02449   if (InFlag.getNode())
02450     Ops.push_back(InFlag);
02451 }
02452 
02453 /// LowerCall - functions arguments are copied from virtual regs to
02454 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
02455 SDValue
02456 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
02457                               SmallVectorImpl<SDValue> &InVals) const {
02458   SelectionDAG &DAG                     = CLI.DAG;
02459   SDLoc DL                              = CLI.DL;
02460   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
02461   SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
02462   SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
02463   SDValue Chain                         = CLI.Chain;
02464   SDValue Callee                        = CLI.Callee;
02465   bool &IsTailCall                      = CLI.IsTailCall;
02466   CallingConv::ID CallConv              = CLI.CallConv;
02467   bool IsVarArg                         = CLI.IsVarArg;
02468 
02469   MachineFunction &MF = DAG.getMachineFunction();
02470   MachineFrameInfo *MFI = MF.getFrameInfo();
02471   const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
02472   MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
02473   bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
02474 
02475   // Analyze operands of the call, assigning locations to each operand.
02476   SmallVector<CCValAssign, 16> ArgLocs;
02477   MipsCCState CCInfo(
02478       CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
02479       MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
02480 
02481   // Allocate the reserved argument area. It seems strange to do this from the
02482   // caller side but removing it breaks the frame size calculation.
02483   const MipsABIInfo &ABI = Subtarget.getABI();
02484   CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
02485 
02486   CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode());
02487 
02488   // Get a count of how many bytes are to be pushed on the stack.
02489   unsigned NextStackOffset = CCInfo.getNextStackOffset();
02490 
02491   // Check if it's really possible to do a tail call.
02492   if (IsTailCall)
02493     IsTailCall = isEligibleForTailCallOptimization(
02494         CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
02495 
02496   if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
02497     report_fatal_error("failed to perform tail call elimination on a call "
02498                        "site marked musttail");
02499 
02500   if (IsTailCall)
02501     ++NumTailCalls;
02502 
02503   // Chain is the output chain of the last Load/Store or CopyToReg node.
02504   // ByValChain is the output chain of the last Memcpy node created for copying
02505   // byval arguments to the stack.
02506   unsigned StackAlignment = TFL->getStackAlignment();
02507   NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
02508   SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
02509 
02510   if (!IsTailCall)
02511     Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
02512 
02513   SDValue StackPtr = DAG.getCopyFromReg(
02514       Chain, DL, Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP,
02515       getPointerTy());
02516 
02517   // With EABI is it possible to have 16 args on registers.
02518   std::deque< std::pair<unsigned, SDValue> > RegsToPass;
02519   SmallVector<SDValue, 8> MemOpChains;
02520 
02521   CCInfo.rewindByValRegsInfo();
02522 
02523   // Walk the register/memloc assignments, inserting copies/loads.
02524   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
02525     SDValue Arg = OutVals[i];
02526     CCValAssign &VA = ArgLocs[i];
02527     MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
02528     ISD::ArgFlagsTy Flags = Outs[i].Flags;
02529     bool UseUpperBits = false;
02530 
02531     // ByVal Arg.
02532     if (Flags.isByVal()) {
02533       unsigned FirstByValReg, LastByValReg;
02534       unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
02535       CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
02536 
02537       assert(Flags.getByValSize() &&
02538              "ByVal args of size 0 should have been ignored by front-end.");
02539       assert(ByValIdx < CCInfo.getInRegsParamsCount());
02540       assert(!IsTailCall &&
02541              "Do not tail-call optimize if there is a byval argument.");
02542       passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
02543                    FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
02544                    VA);
02545       CCInfo.nextInRegsParam();
02546       continue;
02547     }
02548 
02549     // Promote the value if needed.
02550     switch (VA.getLocInfo()) {
02551     default:
02552       llvm_unreachable("Unknown loc info!");
02553     case CCValAssign::Full:
02554       if (VA.isRegLoc()) {
02555         if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
02556             (ValVT == MVT::f64 && LocVT == MVT::i64) ||
02557             (ValVT == MVT::i64 && LocVT == MVT::f64))
02558           Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
02559         else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
02560           SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
02561                                    Arg, DAG.getConstant(0, MVT::i32));
02562           SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
02563                                    Arg, DAG.getConstant(1, MVT::i32));
02564           if (!Subtarget.isLittle())
02565             std::swap(Lo, Hi);
02566           unsigned LocRegLo = VA.getLocReg();
02567           unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
02568           RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
02569           RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
02570           continue;
02571         }
02572       }
02573       break;
02574     case CCValAssign::BCvt:
02575       Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
02576       break;
02577     case CCValAssign::SExtUpper:
02578       UseUpperBits = true;
02579       // Fallthrough
02580     case CCValAssign::SExt:
02581       Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
02582       break;
02583     case CCValAssign::ZExtUpper:
02584       UseUpperBits = true;
02585       // Fallthrough
02586     case CCValAssign::ZExt:
02587       Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
02588       break;
02589     case CCValAssign::AExtUpper:
02590       UseUpperBits = true;
02591       // Fallthrough
02592     case CCValAssign::AExt:
02593       Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
02594       break;
02595     }
02596 
02597     if (UseUpperBits) {
02598       unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
02599       unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
02600       Arg = DAG.getNode(
02601           ISD::SHL, DL, VA.getLocVT(), Arg,
02602           DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
02603     }
02604 
02605     // Arguments that can be passed on register must be kept at
02606     // RegsToPass vector
02607     if (VA.isRegLoc()) {
02608       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
02609       continue;
02610     }
02611 
02612     // Register can't get to this point...
02613     assert(VA.isMemLoc());
02614 
02615     // emit ISD::STORE whichs stores the
02616     // parameter value to a stack Location
02617     MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
02618                                          Chain, Arg, DL, IsTailCall, DAG));
02619   }
02620 
02621   // Transform all store nodes into one single node because all store
02622   // nodes are independent of each other.
02623   if (!MemOpChains.empty())
02624     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
02625 
02626   // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
02627   // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
02628   // node so that legalize doesn't hack it.
02629   bool IsPICCall =
02630       (Subtarget.isABI_N64() || IsPIC); // true if calls are translated to
02631                                          // jalr $25
02632   bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false;
02633   SDValue CalleeLo;
02634   EVT Ty = Callee.getValueType();
02635 
02636   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
02637     if (IsPICCall) {
02638       const GlobalValue *Val = G->getGlobal();
02639       InternalLinkage = Val->hasInternalLinkage();
02640 
02641       if (InternalLinkage)
02642         Callee = getAddrLocal(G, Ty, DAG,
02643                               Subtarget.isABI_N32() || Subtarget.isABI_N64());
02644       else if (LargeGOT) {
02645         Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16,
02646                                        MipsII::MO_CALL_LO16, Chain,
02647                                        FuncInfo->callPtrInfo(Val));
02648         IsCallReloc = true;
02649       } else {
02650         Callee = getAddrGlobal(G, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
02651                                FuncInfo->callPtrInfo(Val));
02652         IsCallReloc = true;
02653       }
02654     } else
02655       Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
02656                                           MipsII::MO_NO_FLAG);
02657     GlobalOrExternal = true;
02658   }
02659   else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
02660     const char *Sym = S->getSymbol();
02661 
02662     if (!Subtarget.isABI_N64() && !IsPIC) // !N64 && static
02663       Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(),
02664                                             MipsII::MO_NO_FLAG);
02665     else if (LargeGOT) {
02666       Callee = getAddrGlobalLargeGOT(S, Ty, DAG, MipsII::MO_CALL_HI16,
02667                                      MipsII::MO_CALL_LO16, Chain,
02668                                      FuncInfo->callPtrInfo(Sym));
02669       IsCallReloc = true;
02670     } else { // N64 || PIC
02671       Callee = getAddrGlobal(S, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
02672                              FuncInfo->callPtrInfo(Sym));
02673       IsCallReloc = true;
02674     }
02675 
02676     GlobalOrExternal = true;
02677   }
02678 
02679   SmallVector<SDValue, 8> Ops(1, Chain);
02680   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
02681 
02682   getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
02683               IsCallReloc, CLI, Callee, Chain);
02684 
02685   if (IsTailCall)
02686     return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
02687 
02688   Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
02689   SDValue InFlag = Chain.getValue(1);
02690 
02691   // Create the CALLSEQ_END node.
02692   Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
02693                              DAG.getIntPtrConstant(0, true), InFlag, DL);
02694   InFlag = Chain.getValue(1);
02695 
02696   // Handle result values, copying them out of physregs into vregs that we
02697   // return.
02698   return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
02699                          InVals, CLI);
02700 }
02701 
02702 /// LowerCallResult - Lower the result values of a call into the
02703 /// appropriate copies out of appropriate physical registers.
02704 SDValue MipsTargetLowering::LowerCallResult(
02705     SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
02706     const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
02707     SmallVectorImpl<SDValue> &InVals,
02708     TargetLowering::CallLoweringInfo &CLI) const {
02709   // Assign locations to each value returned by this call.
02710   SmallVector<CCValAssign, 16> RVLocs;
02711   MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
02712                      *DAG.getContext());
02713   CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI);
02714 
02715   // Copy all of the result registers out of their specified physreg.
02716   for (unsigned i = 0; i != RVLocs.size(); ++i) {
02717     CCValAssign &VA = RVLocs[i];
02718     assert(VA.isRegLoc() && "Can only return in registers!");
02719 
02720     SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
02721                                      RVLocs[i].getLocVT(), InFlag);
02722     Chain = Val.getValue(1);
02723     InFlag = Val.getValue(2);
02724 
02725     if (VA.isUpperBitsInLoc()) {
02726       unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
02727       unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
02728       unsigned Shift =
02729           VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
02730       Val = DAG.getNode(
02731           Shift, DL, VA.getLocVT(), Val,
02732           DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
02733     }
02734 
02735     switch (VA.getLocInfo()) {
02736     default:
02737       llvm_unreachable("Unknown loc info!");
02738     case CCValAssign::Full:
02739       break;
02740     case CCValAssign::BCvt:
02741       Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
02742       break;
02743     case CCValAssign::AExt:
02744     case CCValAssign::AExtUpper:
02745       Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
02746       break;
02747     case CCValAssign::ZExt:
02748     case CCValAssign::ZExtUpper:
02749       Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
02750                         DAG.getValueType(VA.getValVT()));
02751       Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
02752       break;
02753     case CCValAssign::SExt:
02754     case CCValAssign::SExtUpper:
02755       Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
02756                         DAG.getValueType(VA.getValVT()));
02757       Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
02758       break;
02759     }
02760 
02761     InVals.push_back(Val);
02762   }
02763 
02764   return Chain;
02765 }
02766 
02767 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
02768                                       EVT ArgVT, SDLoc DL, SelectionDAG &DAG) {
02769   MVT LocVT = VA.getLocVT();
02770   EVT ValVT = VA.getValVT();
02771 
02772   // Shift into the upper bits if necessary.
02773   switch (VA.getLocInfo()) {
02774   default:
02775     break;
02776   case CCValAssign::AExtUpper:
02777   case CCValAssign::SExtUpper:
02778   case CCValAssign::ZExtUpper: {
02779     unsigned ValSizeInBits = ArgVT.getSizeInBits();
02780     unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
02781     unsigned Opcode =
02782         VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
02783     Val = DAG.getNode(
02784         Opcode, DL, VA.getLocVT(), Val,
02785         DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
02786     break;
02787   }
02788   }
02789 
02790   // If this is an value smaller than the argument slot size (32-bit for O32,
02791   // 64-bit for N32/N64), it has been promoted in some way to the argument slot
02792   // size. Extract the value and insert any appropriate assertions regarding
02793   // sign/zero extension.
02794   switch (VA.getLocInfo()) {
02795   default:
02796     llvm_unreachable("Unknown loc info!");
02797   case CCValAssign::Full:
02798     break;
02799   case CCValAssign::AExtUpper:
02800   case CCValAssign::AExt:
02801     Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
02802     break;
02803   case CCValAssign::SExtUpper:
02804   case CCValAssign::SExt:
02805     Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
02806     Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
02807     break;
02808   case CCValAssign::ZExtUpper:
02809   case CCValAssign::ZExt:
02810     Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
02811     Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
02812     break;
02813   case CCValAssign::BCvt:
02814     Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
02815     break;
02816   }
02817 
02818   return Val;
02819 }
02820 
02821 //===----------------------------------------------------------------------===//
02822 //             Formal Arguments Calling Convention Implementation
02823 //===----------------------------------------------------------------------===//
02824 /// LowerFormalArguments - transform physical registers into virtual registers
02825 /// and generate load operations for arguments places on the stack.
02826 SDValue
02827 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
02828                                          CallingConv::ID CallConv,
02829                                          bool IsVarArg,
02830                                       const SmallVectorImpl<ISD::InputArg> &Ins,
02831                                          SDLoc DL, SelectionDAG &DAG,
02832                                          SmallVectorImpl<SDValue> &InVals)
02833                                           const {
02834   MachineFunction &MF = DAG.getMachineFunction();
02835   MachineFrameInfo *MFI = MF.getFrameInfo();
02836   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
02837 
02838   MipsFI->setVarArgsFrameIndex(0);
02839 
02840   // Used with vargs to acumulate store chains.
02841   std::vector<SDValue> OutChains;
02842 
02843   // Assign locations to all of the incoming arguments.
02844   SmallVector<CCValAssign, 16> ArgLocs;
02845   MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
02846                      *DAG.getContext());
02847   const MipsABIInfo &ABI = Subtarget.getABI();
02848   CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
02849   Function::const_arg_iterator FuncArg =
02850     DAG.getMachineFunction().getFunction()->arg_begin();
02851 
02852   CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
02853   MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
02854                            CCInfo.getInRegsParamsCount() > 0);
02855 
02856   unsigned CurArgIdx = 0;
02857   CCInfo.rewindByValRegsInfo();
02858 
02859   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
02860     CCValAssign &VA = ArgLocs[i];
02861     std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
02862     CurArgIdx = Ins[i].OrigArgIndex;
02863     EVT ValVT = VA.getValVT();
02864     ISD::ArgFlagsTy Flags = Ins[i].Flags;
02865     bool IsRegLoc = VA.isRegLoc();
02866 
02867     if (Flags.isByVal()) {
02868       unsigned FirstByValReg, LastByValReg;
02869       unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
02870       CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
02871 
02872       assert(Flags.getByValSize() &&
02873              "ByVal args of size 0 should have been ignored by front-end.");
02874       assert(ByValIdx < CCInfo.getInRegsParamsCount());
02875       copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
02876                     FirstByValReg, LastByValReg, VA, CCInfo);
02877       CCInfo.nextInRegsParam();
02878       continue;
02879     }
02880 
02881     // Arguments stored on registers
02882     if (IsRegLoc) {
02883       MVT RegVT = VA.getLocVT();
02884       unsigned ArgReg = VA.getLocReg();
02885       const TargetRegisterClass *RC = getRegClassFor(RegVT);
02886 
02887       // Transform the arguments stored on
02888       // physical registers into virtual ones
02889       unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
02890       SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
02891 
02892       ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
02893 
02894       // Handle floating point arguments passed in integer registers and
02895       // long double arguments passed in floating point registers.
02896       if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
02897           (RegVT == MVT::i64 && ValVT == MVT::f64) ||
02898           (RegVT == MVT::f64 && ValVT == MVT::i64))
02899         ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
02900       else if (Subtarget.isABI_O32() && RegVT == MVT::i32 &&
02901                ValVT == MVT::f64) {
02902         unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
02903                                   getNextIntArgReg(ArgReg), RC);
02904         SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
02905         if (!Subtarget.isLittle())
02906           std::swap(ArgValue, ArgValue2);
02907         ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
02908                                ArgValue, ArgValue2);
02909       }
02910 
02911       InVals.push_back(ArgValue);
02912     } else { // VA.isRegLoc()
02913       MVT LocVT = VA.getLocVT();
02914 
02915       if (Subtarget.isABI_O32()) {
02916         // We ought to be able to use LocVT directly but O32 sets it to i32
02917         // when allocating floating point values to integer registers.
02918         // This shouldn't influence how we load the value into registers unless
02919         // we are targetting softfloat.
02920         if (VA.getValVT().isFloatingPoint() && !Subtarget.abiUsesSoftFloat())
02921           LocVT = VA.getValVT();
02922       }
02923 
02924       // sanity check
02925       assert(VA.isMemLoc());
02926 
02927       // The stack pointer offset is relative to the caller stack frame.
02928       int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
02929                                       VA.getLocMemOffset(), true);
02930 
02931       // Create load nodes to retrieve arguments from the stack
02932       SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
02933       SDValue ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
02934                                      MachinePointerInfo::getFixedStack(FI),
02935                                      false, false, false, 0);
02936       OutChains.push_back(ArgValue.getValue(1));
02937 
02938       ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
02939 
02940       InVals.push_back(ArgValue);
02941     }
02942   }
02943 
02944   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
02945     // The mips ABIs for returning structs by value requires that we copy
02946     // the sret argument into $v0 for the return. Save the argument into
02947     // a virtual register so that we can access it from the return points.
02948     if (Ins[i].Flags.isSRet()) {
02949       unsigned Reg = MipsFI->getSRetReturnReg();
02950       if (!Reg) {
02951         Reg = MF.getRegInfo().createVirtualRegister(
02952             getRegClassFor(Subtarget.isABI_N64() ? MVT::i64 : MVT::i32));
02953         MipsFI->setSRetReturnReg(Reg);
02954       }
02955       SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
02956       Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
02957       break;
02958     }
02959   }
02960 
02961   if (IsVarArg)
02962     writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
02963 
02964   // All stores are grouped in one node to allow the matching between
02965   // the size of Ins and InVals. This only happens when on varg functions
02966   if (!OutChains.empty()) {
02967     OutChains.push_back(Chain);
02968     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
02969   }
02970 
02971   return Chain;
02972 }
02973 
02974 //===----------------------------------------------------------------------===//
02975 //               Return Value Calling Convention Implementation
02976 //===----------------------------------------------------------------------===//
02977 
02978 bool
02979 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
02980                                    MachineFunction &MF, bool IsVarArg,
02981                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
02982                                    LLVMContext &Context) const {
02983   SmallVector<CCValAssign, 16> RVLocs;
02984   MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
02985   return CCInfo.CheckReturn(Outs, RetCC_Mips);
02986 }
02987 
02988 SDValue
02989 MipsTargetLowering::LowerReturn(SDValue Chain,
02990                                 CallingConv::ID CallConv, bool IsVarArg,
02991                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
02992                                 const SmallVectorImpl<SDValue> &OutVals,
02993                                 SDLoc DL, SelectionDAG &DAG) const {
02994   // CCValAssign - represent the assignment of
02995   // the return value to a location
02996   SmallVector<CCValAssign, 16> RVLocs;
02997   MachineFunction &MF = DAG.getMachineFunction();
02998 
02999   // CCState - Info about the registers and stack slot.
03000   MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
03001 
03002   // Analyze return values.
03003   CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
03004 
03005   SDValue Flag;
03006   SmallVector<SDValue, 4> RetOps(1, Chain);
03007 
03008   // Copy the result values into the output registers.
03009   for (unsigned i = 0; i != RVLocs.size(); ++i) {
03010     SDValue Val = OutVals[i];
03011     CCValAssign &VA = RVLocs[i];
03012     assert(VA.isRegLoc() && "Can only return in registers!");
03013     bool UseUpperBits = false;
03014 
03015     switch (VA.getLocInfo()) {
03016     default:
03017       llvm_unreachable("Unknown loc info!");
03018     case CCValAssign::Full:
03019       break;
03020     case CCValAssign::BCvt:
03021       Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
03022       break;
03023     case CCValAssign::AExtUpper:
03024       UseUpperBits = true;
03025       // Fallthrough
03026     case CCValAssign::AExt:
03027       Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
03028       break;
03029     case CCValAssign::ZExtUpper:
03030       UseUpperBits = true;
03031       // Fallthrough
03032     case CCValAssign::ZExt:
03033       Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
03034       break;
03035     case CCValAssign::SExtUpper:
03036       UseUpperBits = true;
03037       // Fallthrough
03038     case CCValAssign::SExt:
03039       Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
03040       break;
03041     }
03042 
03043     if (UseUpperBits) {
03044       unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
03045       unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
03046       Val = DAG.getNode(
03047           ISD::SHL, DL, VA.getLocVT(), Val,
03048           DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT()));
03049     }
03050 
03051     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
03052 
03053     // Guarantee that all emitted copies are stuck together with flags.
03054     Flag = Chain.getValue(1);
03055     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
03056   }
03057 
03058   // The mips ABIs for returning structs by value requires that we copy
03059   // the sret argument into $v0 for the return. We saved the argument into
03060   // a virtual register in the entry block, so now we copy the value out
03061   // and into $v0.
03062   if (MF.getFunction()->hasStructRetAttr()) {
03063     MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
03064     unsigned Reg = MipsFI->getSRetReturnReg();
03065 
03066     if (!Reg)
03067       llvm_unreachable("sret virtual register not created in the entry block");
03068     SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
03069     unsigned V0 = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0;
03070 
03071     Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
03072     Flag = Chain.getValue(1);
03073     RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
03074   }
03075 
03076   RetOps[0] = Chain;  // Update chain.
03077 
03078   // Add the flag if we have it.
03079   if (Flag.getNode())
03080     RetOps.push_back(Flag);
03081 
03082   // Return on Mips is always a "jr $ra"
03083   return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
03084 }
03085 
03086 //===----------------------------------------------------------------------===//
03087 //                           Mips Inline Assembly Support
03088 //===----------------------------------------------------------------------===//
03089 
03090 /// getConstraintType - Given a constraint letter, return the type of
03091 /// constraint it is for this target.
03092 MipsTargetLowering::ConstraintType MipsTargetLowering::
03093 getConstraintType(const std::string &Constraint) const
03094 {
03095   // Mips specific constraints
03096   // GCC config/mips/constraints.md
03097   //
03098   // 'd' : An address register. Equivalent to r
03099   //       unless generating MIPS16 code.
03100   // 'y' : Equivalent to r; retained for
03101   //       backwards compatibility.
03102   // 'c' : A register suitable for use in an indirect
03103   //       jump. This will always be $25 for -mabicalls.
03104   // 'l' : The lo register. 1 word storage.
03105   // 'x' : The hilo register pair. Double word storage.
03106   if (Constraint.size() == 1) {
03107     switch (Constraint[0]) {
03108       default : break;
03109       case 'd':
03110       case 'y':
03111       case 'f':
03112       case 'c':
03113       case 'l':
03114       case 'x':
03115         return C_RegisterClass;
03116       case 'R':
03117         return C_Memory;
03118     }
03119   }
03120   return TargetLowering::getConstraintType(Constraint);
03121 }
03122 
03123 /// Examine constraint type and operand type and determine a weight value.
03124 /// This object must already have been set up with the operand type
03125 /// and the current alternative constraint selected.
03126 TargetLowering::ConstraintWeight
03127 MipsTargetLowering::getSingleConstraintMatchWeight(
03128     AsmOperandInfo &info, const char *constraint) const {
03129   ConstraintWeight weight = CW_Invalid;
03130   Value *CallOperandVal = info.CallOperandVal;
03131     // If we don't have a value, we can't do a match,
03132     // but allow it at the lowest weight.
03133   if (!CallOperandVal)
03134     return CW_Default;
03135   Type *type = CallOperandVal->getType();
03136   // Look at the constraint type.
03137   switch (*constraint) {
03138   default:
03139     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
03140     break;
03141   case 'd':
03142   case 'y':
03143     if (type->isIntegerTy())
03144       weight = CW_Register;
03145     break;
03146   case 'f': // FPU or MSA register
03147     if (Subtarget.hasMSA() && type->isVectorTy() &&
03148         cast<VectorType>(type)->getBitWidth() == 128)
03149       weight = CW_Register;
03150     else if (type->isFloatTy())
03151       weight = CW_Register;
03152     break;
03153   case 'c': // $25 for indirect jumps
03154   case 'l': // lo register
03155   case 'x': // hilo register pair
03156     if (type->isIntegerTy())
03157       weight = CW_SpecificReg;
03158     break;
03159   case 'I': // signed 16 bit immediate
03160   case 'J': // integer zero
03161   case 'K': // unsigned 16 bit immediate
03162   case 'L': // signed 32 bit immediate where lower 16 bits are 0
03163   case 'N': // immediate in the range of -65535 to -1 (inclusive)
03164   case 'O': // signed 15 bit immediate (+- 16383)
03165   case 'P': // immediate in the range of 65535 to 1 (inclusive)
03166     if (isa<ConstantInt>(CallOperandVal))
03167       weight = CW_Constant;
03168     break;
03169   case 'R':
03170     weight = CW_Memory;
03171     break;
03172   }
03173   return weight;
03174 }
03175 
03176 /// This is a helper function to parse a physical register string and split it
03177 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
03178 /// that is returned indicates whether parsing was successful. The second flag
03179 /// is true if the numeric part exists.
03180 static std::pair<bool, bool>
03181 parsePhysicalReg(StringRef C, std::string &Prefix,
03182                  unsigned long long &Reg) {
03183   if (C.front() != '{' || C.back() != '}')
03184     return std::make_pair(false, false);
03185 
03186   // Search for the first numeric character.
03187   StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
03188   I = std::find_if(B, E, std::ptr_fun(isdigit));
03189 
03190   Prefix.assign(B, I - B);
03191 
03192   // The second flag is set to false if no numeric characters were found.
03193   if (I == E)
03194     return std::make_pair(true, false);
03195 
03196   // Parse the numeric characters.
03197   return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
03198                         true);
03199 }
03200 
03201 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
03202 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
03203   const TargetRegisterInfo *TRI =
03204       getTargetMachine().getSubtargetImpl()->getRegisterInfo();
03205   const TargetRegisterClass *RC;
03206   std::string Prefix;
03207   unsigned long long Reg;
03208 
03209   std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
03210 
03211   if (!R.first)
03212     return std::make_pair(0U, nullptr);
03213 
03214   if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
03215     // No numeric characters follow "hi" or "lo".
03216     if (R.second)
03217       return std::make_pair(0U, nullptr);
03218 
03219     RC = TRI->getRegClass(Prefix == "hi" ?
03220                           Mips::HI32RegClassID : Mips::LO32RegClassID);
03221     return std::make_pair(*(RC->begin()), RC);
03222   } else if (Prefix.compare(0, 4, "$msa") == 0) {
03223     // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
03224 
03225     // No numeric characters follow the name.
03226     if (R.second)
03227       return std::make_pair(0U, nullptr);
03228 
03229     Reg = StringSwitch<unsigned long long>(Prefix)
03230               .Case("$msair", Mips::MSAIR)
03231               .Case("$msacsr", Mips::MSACSR)
03232               .Case("$msaaccess", Mips::MSAAccess)
03233               .Case("$msasave", Mips::MSASave)
03234               .Case("$msamodify", Mips::MSAModify)
03235               .Case("$msarequest", Mips::MSARequest)
03236               .Case("$msamap", Mips::MSAMap)
03237               .Case("$msaunmap", Mips::MSAUnmap)
03238               .Default(0);
03239 
03240     if (!Reg)
03241       return std::make_pair(0U, nullptr);
03242 
03243     RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
03244     return std::make_pair(Reg, RC);
03245   }
03246 
03247   if (!R.second)
03248     return std::make_pair(0U, nullptr);
03249 
03250   if (Prefix == "$f") { // Parse $f0-$f31.
03251     // If the size of FP registers is 64-bit or Reg is an even number, select
03252     // the 64-bit register class. Otherwise, select the 32-bit register class.
03253     if (VT == MVT::Other)
03254       VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
03255 
03256     RC = getRegClassFor(VT);
03257 
03258     if (RC == &Mips::AFGR64RegClass) {
03259       assert(Reg % 2 == 0);
03260       Reg >>= 1;
03261     }
03262   } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
03263     RC = TRI->getRegClass(Mips::FCCRegClassID);
03264   else if (Prefix == "$w") { // Parse $w0-$w31.
03265     RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
03266   } else { // Parse $0-$31.
03267     assert(Prefix == "$");
03268     RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
03269   }
03270 
03271   assert(Reg < RC->getNumRegs());
03272   return std::make_pair(*(RC->begin() + Reg), RC);
03273 }
03274 
03275 /// Given a register class constraint, like 'r', if this corresponds directly
03276 /// to an LLVM register class, return a register of 0 and the register class
03277 /// pointer.
03278 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
03279 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
03280 {
03281   if (Constraint.size() == 1) {
03282     switch (Constraint[0]) {
03283     case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
03284     case 'y': // Same as 'r'. Exists for compatibility.
03285     case 'r':
03286       if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
03287         if (Subtarget.inMips16Mode())
03288           return std::make_pair(0U, &Mips::CPU16RegsRegClass);
03289         return std::make_pair(0U, &Mips::GPR32RegClass);
03290       }
03291       if (VT == MVT::i64 && !Subtarget.isGP64bit())
03292         return std::make_pair(0U, &Mips::GPR32RegClass);
03293       if (VT == MVT::i64 && Subtarget.isGP64bit())
03294         return std::make_pair(0U, &Mips::GPR64RegClass);
03295       // This will generate an error message
03296       return std::make_pair(0U, nullptr);
03297     case 'f': // FPU or MSA register
03298       if (VT == MVT::v16i8)
03299         return std::make_pair(0U, &Mips::MSA128BRegClass);
03300       else if (VT == MVT::v8i16 || VT == MVT::v8f16)
03301         return std::make_pair(0U, &Mips::MSA128HRegClass);
03302       else if (VT == MVT::v4i32 || VT == MVT::v4f32)
03303         return std::make_pair(0U, &Mips::MSA128WRegClass);
03304       else if (VT == MVT::v2i64 || VT == MVT::v2f64)
03305         return std::make_pair(0U, &Mips::MSA128DRegClass);
03306       else if (VT == MVT::f32)
03307         return std::make_pair(0U, &Mips::FGR32RegClass);
03308       else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
03309         if (Subtarget.isFP64bit())
03310           return std::make_pair(0U, &Mips::FGR64RegClass);
03311         return std::make_pair(0U, &Mips::AFGR64RegClass);
03312       }
03313       break;
03314     case 'c': // register suitable for indirect jump
03315       if (VT == MVT::i32)
03316         return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
03317       assert(VT == MVT::i64 && "Unexpected type.");
03318       return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
03319     case 'l': // register suitable for indirect jump
03320       if (VT == MVT::i32)
03321         return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
03322       return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
03323     case 'x': // register suitable for indirect jump
03324       // Fixme: Not triggering the use of both hi and low
03325       // This will generate an error message
03326       return std::make_pair(0U, nullptr);
03327     }
03328   }
03329 
03330   std::pair<unsigned, const TargetRegisterClass *> R;
03331   R = parseRegForInlineAsmConstraint(Constraint, VT);
03332 
03333   if (R.second)
03334     return R;
03335 
03336   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
03337 }
03338 
03339 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
03340 /// vector.  If it is invalid, don't add anything to Ops.
03341 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
03342                                                      std::string &Constraint,
03343                                                      std::vector<SDValue>&Ops,
03344                                                      SelectionDAG &DAG) const {
03345   SDValue Result;
03346 
03347   // Only support length 1 constraints for now.
03348   if (Constraint.length() > 1) return;
03349 
03350   char ConstraintLetter = Constraint[0];
03351   switch (ConstraintLetter) {
03352   default: break; // This will fall through to the generic implementation
03353   case 'I': // Signed 16 bit constant
03354     // If this fails, the parent routine will give an error
03355     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03356       EVT Type = Op.getValueType();
03357       int64_t Val = C->getSExtValue();
03358       if (isInt<16>(Val)) {
03359         Result = DAG.getTargetConstant(Val, Type);
03360         break;
03361       }
03362     }
03363     return;
03364   case 'J': // integer zero
03365     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03366       EVT Type = Op.getValueType();
03367       int64_t Val = C->getZExtValue();
03368       if (Val == 0) {
03369         Result = DAG.getTargetConstant(0, Type);
03370         break;
03371       }
03372     }
03373     return;
03374   case 'K': // unsigned 16 bit immediate
03375     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03376       EVT Type = Op.getValueType();
03377       uint64_t Val = (uint64_t)C->getZExtValue();
03378       if (isUInt<16>(Val)) {
03379         Result = DAG.getTargetConstant(Val, Type);
03380         break;
03381       }
03382     }
03383     return;
03384   case 'L': // signed 32 bit immediate where lower 16 bits are 0
03385     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03386       EVT Type = Op.getValueType();
03387       int64_t Val = C->getSExtValue();
03388       if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
03389         Result = DAG.getTargetConstant(Val, Type);
03390         break;
03391       }
03392     }
03393     return;
03394   case 'N': // immediate in the range of -65535 to -1 (inclusive)
03395     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03396       EVT Type = Op.getValueType();
03397       int64_t Val = C->getSExtValue();
03398       if ((Val >= -65535) && (Val <= -1)) {
03399         Result = DAG.getTargetConstant(Val, Type);
03400         break;
03401       }
03402     }
03403     return;
03404   case 'O': // signed 15 bit immediate
03405     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03406       EVT Type = Op.getValueType();
03407       int64_t Val = C->getSExtValue();
03408       if ((isInt<15>(Val))) {
03409         Result = DAG.getTargetConstant(Val, Type);
03410         break;
03411       }
03412     }
03413     return;
03414   case 'P': // immediate in the range of 1 to 65535 (inclusive)
03415     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
03416       EVT Type = Op.getValueType();
03417       int64_t Val = C->getSExtValue();
03418       if ((Val <= 65535) && (Val >= 1)) {
03419         Result = DAG.getTargetConstant(Val, Type);
03420         break;
03421       }
03422     }
03423     return;
03424   }
03425 
03426   if (Result.getNode()) {
03427     Ops.push_back(Result);
03428     return;
03429   }
03430 
03431   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
03432 }
03433 
03434 bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM,
03435                                                Type *Ty) const {
03436   // No global is ever allowed as a base.
03437   if (AM.BaseGV)
03438     return false;
03439 
03440   switch (AM.Scale) {
03441   case 0: // "r+i" or just "i", depending on HasBaseReg.
03442     break;
03443   case 1:
03444     if (!AM.HasBaseReg) // allow "r+i".
03445       break;
03446     return false; // disallow "r+r" or "r+r+i".
03447   default:
03448     return false;
03449   }
03450 
03451   return true;
03452 }
03453 
03454 bool
03455 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
03456   // The Mips target isn't yet aware of offsets.
03457   return false;
03458 }
03459 
03460 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
03461                                             unsigned SrcAlign,
03462                                             bool IsMemset, bool ZeroMemset,
03463                                             bool MemcpyStrSrc,
03464                                             MachineFunction &MF) const {
03465   if (Subtarget.hasMips64())
03466     return MVT::i64;
03467 
03468   return MVT::i32;
03469 }
03470 
03471 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
03472   if (VT != MVT::f32 && VT != MVT::f64)
03473     return false;
03474   if (Imm.isNegZero())
03475     return false;
03476   return Imm.isZero();
03477 }
03478 
03479 unsigned MipsTargetLowering::getJumpTableEncoding() const {
03480   if (Subtarget.isABI_N64())
03481     return MachineJumpTableInfo::EK_GPRel64BlockAddress;
03482 
03483   return TargetLowering::getJumpTableEncoding();
03484 }
03485 
03486 void MipsTargetLowering::copyByValRegs(
03487     SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
03488     const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
03489     const Argument *FuncArg, unsigned FirstReg, unsigned LastReg,
03490     const CCValAssign &VA, MipsCCState &State) const {
03491   MachineFunction &MF = DAG.getMachineFunction();
03492   MachineFrameInfo *MFI = MF.getFrameInfo();
03493   unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
03494   unsigned NumRegs = LastReg - FirstReg;
03495   unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
03496   unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
03497   int FrameObjOffset;
03498   const MipsABIInfo &ABI = Subtarget.getABI();
03499   ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
03500 
03501   if (RegAreaSize)
03502     FrameObjOffset =
03503         (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
03504         (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
03505   else
03506     FrameObjOffset = VA.getLocMemOffset();
03507 
03508   // Create frame object.
03509   EVT PtrTy = getPointerTy();
03510   int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
03511   SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
03512   InVals.push_back(FIN);
03513 
03514   if (!NumRegs)
03515     return;
03516 
03517   // Copy arg registers.
03518   MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
03519   const TargetRegisterClass *RC = getRegClassFor(RegTy);
03520 
03521   for (unsigned I = 0; I < NumRegs; ++I) {
03522     unsigned ArgReg = ByValArgRegs[FirstReg + I];
03523     unsigned VReg = addLiveIn(MF, ArgReg, RC);
03524     unsigned Offset = I * GPRSizeInBytes;
03525     SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
03526                                    DAG.getConstant(Offset, PtrTy));
03527     SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
03528                                  StorePtr, MachinePointerInfo(FuncArg, Offset),
03529                                  false, false, 0);
03530     OutChains.push_back(Store);
03531   }
03532 }
03533 
03534 // Copy byVal arg to registers and stack.
03535 void MipsTargetLowering::passByValArg(
03536     SDValue Chain, SDLoc DL,
03537     std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
03538     SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
03539     MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
03540     unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
03541     const CCValAssign &VA) const {
03542   unsigned ByValSizeInBytes = Flags.getByValSize();
03543   unsigned OffsetInBytes = 0; // From beginning of struct
03544   unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
03545   unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
03546   EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
03547   unsigned NumRegs = LastReg - FirstReg;
03548 
03549   if (NumRegs) {
03550     const ArrayRef<MCPhysReg> ArgRegs = Subtarget.getABI().GetByValArgRegs();
03551     bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
03552     unsigned I = 0;
03553 
03554     // Copy words to registers.
03555     for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
03556       SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
03557                                     DAG.getConstant(OffsetInBytes, PtrTy));
03558       SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
03559                                     MachinePointerInfo(), false, false, false,
03560                                     Alignment);
03561       MemOpChains.push_back(LoadVal.getValue(1));
03562       unsigned ArgReg = ArgRegs[FirstReg + I];
03563       RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
03564     }
03565 
03566     // Return if the struct has been fully copied.
03567     if (ByValSizeInBytes == OffsetInBytes)
03568       return;
03569 
03570     // Copy the remainder of the byval argument with sub-word loads and shifts.
03571     if (LeftoverBytes) {
03572       SDValue Val;
03573 
03574       for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
03575            OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
03576         unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
03577 
03578         if (RemainingSizeInBytes < LoadSizeInBytes)
03579           continue;
03580 
03581         // Load subword.
03582         SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
03583                                       DAG.getConstant(OffsetInBytes, PtrTy));
03584         SDValue LoadVal = DAG.getExtLoad(
03585             ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
03586             MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
03587             Alignment);
03588         MemOpChains.push_back(LoadVal.getValue(1));
03589 
03590         // Shift the loaded value.
03591         unsigned Shamt;
03592 
03593         if (isLittle)
03594           Shamt = TotalBytesLoaded * 8;
03595         else
03596           Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
03597 
03598         SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
03599                                     DAG.getConstant(Shamt, MVT::i32));
03600 
03601         if (Val.getNode())
03602           Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
03603         else
03604           Val = Shift;
03605 
03606         OffsetInBytes += LoadSizeInBytes;
03607         TotalBytesLoaded += LoadSizeInBytes;
03608         Alignment = std::min(Alignment, LoadSizeInBytes);
03609       }
03610 
03611       unsigned ArgReg = ArgRegs[FirstReg + I];
03612       RegsToPass.push_back(std::make_pair(ArgReg, Val));
03613       return;
03614     }
03615   }
03616 
03617   // Copy remainder of byval arg to it with memcpy.
03618   unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
03619   SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
03620                             DAG.getConstant(OffsetInBytes, PtrTy));
03621   SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
03622                             DAG.getIntPtrConstant(VA.getLocMemOffset()));
03623   Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy),
03624                         Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
03625                         MachinePointerInfo(), MachinePointerInfo());
03626   MemOpChains.push_back(Chain);
03627 }
03628 
03629 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
03630                                          SDValue Chain, SDLoc DL,
03631                                          SelectionDAG &DAG,
03632                                          CCState &State) const {
03633   const ArrayRef<MCPhysReg> ArgRegs = Subtarget.getABI().GetVarArgRegs();
03634   unsigned Idx = State.getFirstUnallocated(ArgRegs.data(), ArgRegs.size());
03635   unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
03636   MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
03637   const TargetRegisterClass *RC = getRegClassFor(RegTy);
03638   MachineFunction &MF = DAG.getMachineFunction();
03639   MachineFrameInfo *MFI = MF.getFrameInfo();
03640   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
03641 
03642   // Offset of the first variable argument from stack pointer.
03643   int VaArgOffset;
03644 
03645   if (ArgRegs.size() == Idx)
03646     VaArgOffset =
03647         RoundUpToAlignment(State.getNextStackOffset(), RegSizeInBytes);
03648   else {
03649     const MipsABIInfo &ABI = Subtarget.getABI();
03650     VaArgOffset =
03651         (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
03652         (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
03653   }
03654 
03655   // Record the frame index of the first variable argument
03656   // which is a value necessary to VASTART.
03657   int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
03658   MipsFI->setVarArgsFrameIndex(FI);
03659 
03660   // Copy the integer registers that have not been used for argument passing
03661   // to the argument register save area. For O32, the save area is allocated
03662   // in the caller's stack frame, while for N32/64, it is allocated in the
03663   // callee's stack frame.
03664   for (unsigned I = Idx; I < ArgRegs.size();
03665        ++I, VaArgOffset += RegSizeInBytes) {
03666     unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
03667     SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
03668     FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
03669     SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
03670     SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
03671                                  MachinePointerInfo(), false, false, 0);
03672     cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
03673         (Value *)nullptr);
03674     OutChains.push_back(Store);
03675   }
03676 }
03677 
03678 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
03679                                      unsigned Align) const {
03680   MachineFunction &MF = State->getMachineFunction();
03681   const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
03682 
03683   assert(Size && "Byval argument's size shouldn't be 0.");
03684 
03685   Align = std::min(Align, TFL->getStackAlignment());
03686 
03687   unsigned FirstReg = 0;
03688   unsigned NumRegs = 0;
03689 
03690   if (State->getCallingConv() != CallingConv::Fast) {
03691     unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
03692     const ArrayRef<MCPhysReg> IntArgRegs = Subtarget.getABI().GetByValArgRegs();
03693     // FIXME: The O32 case actually describes no shadow registers.
03694     const MCPhysReg *ShadowRegs =
03695         Subtarget.isABI_O32() ? IntArgRegs.data() : Mips64DPRegs;
03696 
03697     // We used to check the size as well but we can't do that anymore since
03698     // CCState::HandleByVal() rounds up the size after calling this function.
03699     assert(!(Align % RegSizeInBytes) &&
03700            "Byval argument's alignment should be a multiple of"
03701            "RegSizeInBytes.");
03702 
03703     FirstReg = State->getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size());
03704 
03705     // If Align > RegSizeInBytes, the first arg register must be even.
03706     // FIXME: This condition happens to do the right thing but it's not the
03707     //        right way to test it. We want to check that the stack frame offset
03708     //        of the register is aligned.
03709     if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
03710       State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
03711       ++FirstReg;
03712     }
03713 
03714     // Mark the registers allocated.
03715     Size = RoundUpToAlignment(Size, RegSizeInBytes);
03716     for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
03717          Size -= RegSizeInBytes, ++I, ++NumRegs)
03718       State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
03719   }
03720 
03721   State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
03722 }