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AArch64AsmBackend.cpp
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1 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AArch64.h"
12 #include "llvm/ADT/Triple.h"
14 #include "llvm/MC/MCAsmBackend.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCDirectives.h"
20 #include "llvm/MC/MCObjectWriter.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSectionELF.h"
23 #include "llvm/MC/MCSectionMachO.h"
24 #include "llvm/MC/MCValue.h"
26 using namespace llvm;
27 
28 namespace {
29 
30 class AArch64AsmBackend : public MCAsmBackend {
31  static const unsigned PCRelFlagVal =
33  Triple TheTriple;
34 
35 public:
36  AArch64AsmBackend(const Target &T, const Triple &TT, bool IsLittleEndian)
37  : MCAsmBackend(IsLittleEndian ? support::little : support::big),
38  TheTriple(TT) {}
39 
40  unsigned getNumFixupKinds() const override {
42  }
43 
44  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
45  const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
46  // This table *must* be in the order that the fixup_* kinds are defined
47  // in AArch64FixupKinds.h.
48  //
49  // Name Offset (bits) Size (bits) Flags
50  {"fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal},
51  {"fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal},
52  {"fixup_aarch64_add_imm12", 10, 12, 0},
53  {"fixup_aarch64_ldst_imm12_scale1", 10, 12, 0},
54  {"fixup_aarch64_ldst_imm12_scale2", 10, 12, 0},
55  {"fixup_aarch64_ldst_imm12_scale4", 10, 12, 0},
56  {"fixup_aarch64_ldst_imm12_scale8", 10, 12, 0},
57  {"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0},
58  {"fixup_aarch64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal},
59  {"fixup_aarch64_movw", 5, 16, 0},
60  {"fixup_aarch64_pcrel_branch14", 5, 14, PCRelFlagVal},
61  {"fixup_aarch64_pcrel_branch19", 5, 19, PCRelFlagVal},
62  {"fixup_aarch64_pcrel_branch26", 0, 26, PCRelFlagVal},
63  {"fixup_aarch64_pcrel_call26", 0, 26, PCRelFlagVal},
64  {"fixup_aarch64_tlsdesc_call", 0, 0, 0}};
65 
66  if (Kind < FirstTargetFixupKind)
67  return MCAsmBackend::getFixupKindInfo(Kind);
68 
69  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
70  "Invalid kind!");
71  return Infos[Kind - FirstTargetFixupKind];
72  }
73 
74  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
76  uint64_t Value, bool IsResolved,
77  const MCSubtargetInfo *STI) const override;
78 
79  bool mayNeedRelaxation(const MCInst &Inst,
80  const MCSubtargetInfo &STI) const override;
81  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
82  const MCRelaxableFragment *DF,
83  const MCAsmLayout &Layout) const override;
84  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
85  MCInst &Res) const override;
86  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
87 
88  void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
89 
90  unsigned getPointerSize() const { return 8; }
91 
92  unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;
93 
94  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
95  const MCValue &Target) override;
96 };
97 
98 } // end anonymous namespace
99 
100 /// The number of bytes the fixup may change.
101 static unsigned getFixupKindNumBytes(unsigned Kind) {
102  switch (Kind) {
103  default:
104  llvm_unreachable("Unknown fixup kind!");
105 
107  return 0;
108 
109  case FK_Data_1:
110  return 1;
111 
112  case FK_Data_2:
113  case FK_SecRel_2:
114  return 2;
115 
126  return 3;
127 
132  case FK_Data_4:
133  case FK_SecRel_4:
134  return 4;
135 
136  case FK_Data_8:
137  return 8;
138  }
139 }
140 
141 static unsigned AdrImmBits(unsigned Value) {
142  unsigned lo2 = Value & 0x3;
143  unsigned hi19 = (Value & 0x1ffffc) >> 2;
144  return (hi19 << 5) | (lo2 << 29);
145 }
146 
147 static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target,
148  uint64_t Value, MCContext &Ctx,
149  const Triple &TheTriple, bool IsResolved) {
150  unsigned Kind = Fixup.getKind();
151  int64_t SignedValue = static_cast<int64_t>(Value);
152  switch (Kind) {
153  default:
154  llvm_unreachable("Unknown fixup kind!");
156  if (SignedValue > 2097151 || SignedValue < -2097152)
157  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
158  return AdrImmBits(Value & 0x1fffffULL);
160  assert(!IsResolved);
161  if (TheTriple.isOSBinFormatCOFF())
162  return AdrImmBits(Value & 0x1fffffULL);
163  return AdrImmBits((Value & 0x1fffff000ULL) >> 12);
166  // Signed 21-bit immediate
167  if (SignedValue > 2097151 || SignedValue < -2097152)
168  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
169  if (Value & 0x3)
170  Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
171  // Low two bits are not encoded.
172  return (Value >> 2) & 0x7ffff;
175  if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
176  Value &= 0xfff;
177  // Unsigned 12-bit immediate
178  if (Value >= 0x1000)
179  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
180  return Value;
182  if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
183  Value &= 0xfff;
184  // Unsigned 12-bit immediate which gets multiplied by 2
185  if (Value >= 0x2000)
186  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
187  if (Value & 0x1)
188  Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned");
189  return Value >> 1;
191  if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
192  Value &= 0xfff;
193  // Unsigned 12-bit immediate which gets multiplied by 4
194  if (Value >= 0x4000)
195  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
196  if (Value & 0x3)
197  Ctx.reportError(Fixup.getLoc(), "fixup must be 4-byte aligned");
198  return Value >> 2;
200  if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
201  Value &= 0xfff;
202  // Unsigned 12-bit immediate which gets multiplied by 8
203  if (Value >= 0x8000)
204  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
205  if (Value & 0x7)
206  Ctx.reportError(Fixup.getLoc(), "fixup must be 8-byte aligned");
207  return Value >> 3;
209  if (TheTriple.isOSBinFormatCOFF() && !IsResolved)
210  Value &= 0xfff;
211  // Unsigned 12-bit immediate which gets multiplied by 16
212  if (Value >= 0x10000)
213  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
214  if (Value & 0xf)
215  Ctx.reportError(Fixup.getLoc(), "fixup must be 16-byte aligned");
216  return Value >> 4;
219  static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
222  // VK_GOTTPREL, VK_TPREL, VK_DTPREL are movw fixups, but they can't
223  // ever be resolved in the assembler.
224  Ctx.reportError(Fixup.getLoc(),
225  "relocation for a thread-local variable points to an "
226  "absolute symbol");
227  return Value;
228  }
229 
230  if (!IsResolved) {
231  // FIXME: Figure out when this can actually happen, and verify our
232  // behavior.
233  Ctx.reportError(Fixup.getLoc(), "unresolved movw fixup not yet "
234  "implemented");
235  return Value;
236  }
237 
239  switch (AArch64MCExpr::getAddressFrag(RefKind)) {
241  break;
243  SignedValue = SignedValue >> 16;
244  break;
246  SignedValue = SignedValue >> 32;
247  break;
249  SignedValue = SignedValue >> 48;
250  break;
251  default:
252  llvm_unreachable("Variant kind doesn't correspond to fixup");
253  }
254 
255  } else {
256  switch (AArch64MCExpr::getAddressFrag(RefKind)) {
258  break;
260  Value = Value >> 16;
261  break;
263  Value = Value >> 32;
264  break;
266  Value = Value >> 48;
267  break;
268  default:
269  llvm_unreachable("Variant kind doesn't correspond to fixup");
270  }
271  }
272 
273  if (RefKind & AArch64MCExpr::VK_NC) {
274  Value &= 0xFFFF;
275  }
277  if (SignedValue > 0xFFFF || SignedValue < -0xFFFF)
278  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
279 
280  // Invert the negative immediate because it will feed into a MOVN.
281  if (SignedValue < 0)
282  SignedValue = ~SignedValue;
283  Value = static_cast<uint64_t>(SignedValue);
284  }
285  else if (Value > 0xFFFF) {
286  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
287  }
288  return Value;
289  }
291  // Signed 16-bit immediate
292  if (SignedValue > 32767 || SignedValue < -32768)
293  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
294  // Low two bits are not encoded (4-byte alignment assumed).
295  if (Value & 0x3)
296  Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
297  return (Value >> 2) & 0x3fff;
300  // Signed 28-bit immediate
301  if (SignedValue > 134217727 || SignedValue < -134217728)
302  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
303  // Low two bits are not encoded (4-byte alignment assumed).
304  if (Value & 0x3)
305  Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
306  return (Value >> 2) & 0x3ffffff;
307  case FK_Data_1:
308  case FK_Data_2:
309  case FK_Data_4:
310  case FK_Data_8:
311  case FK_SecRel_2:
312  case FK_SecRel_4:
313  return Value;
314  }
315 }
316 
317 /// getFixupKindContainereSizeInBytes - The number of bytes of the
318 /// container involved in big endian or 0 if the item is little endian
319 unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {
320  if (Endian == support::little)
321  return 0;
322 
323  switch (Kind) {
324  default:
325  llvm_unreachable("Unknown fixup kind!");
326 
327  case FK_Data_1:
328  return 1;
329  case FK_Data_2:
330  return 2;
331  case FK_Data_4:
332  return 4;
333  case FK_Data_8:
334  return 8;
335 
351  // Instructions are always little endian
352  return 0;
353  }
354 }
355 
356 void AArch64AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
357  const MCValue &Target,
358  MutableArrayRef<char> Data, uint64_t Value,
359  bool IsResolved,
360  const MCSubtargetInfo *STI) const {
361  unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
362  if (!Value)
363  return; // Doesn't change encoding.
364  MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
365  MCContext &Ctx = Asm.getContext();
366  int64_t SignedValue = static_cast<int64_t>(Value);
367  // Apply any target-specific value adjustments.
368  Value = adjustFixupValue(Fixup, Target, Value, Ctx, TheTriple, IsResolved);
369 
370  // Shift the value into position.
371  Value <<= Info.TargetOffset;
372 
373  unsigned Offset = Fixup.getOffset();
374  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
375 
376  // Used to point to big endian bytes.
377  unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(Fixup.getKind());
378 
379  // For each byte of the fragment that the fixup touches, mask in the
380  // bits from the fixup value.
381  if (FulleSizeInBytes == 0) {
382  // Handle as little-endian
383  for (unsigned i = 0; i != NumBytes; ++i) {
384  Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
385  }
386  } else {
387  // Handle as big-endian
388  assert((Offset + FulleSizeInBytes) <= Data.size() && "Invalid fixup size!");
389  assert(NumBytes <= FulleSizeInBytes && "Invalid fixup size!");
390  for (unsigned i = 0; i != NumBytes; ++i) {
391  unsigned Idx = FulleSizeInBytes - 1 - i;
392  Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
393  }
394  }
395 
396  // FIXME: getFixupKindInfo() and getFixupKindNumBytes() could be fixed to
397  // handle this more cleanly. This may affect the output of -show-mc-encoding.
399  static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
401  // If the immediate is negative, generate MOVN else MOVZ.
402  // (Bit 30 = 0) ==> MOVN, (Bit 30 = 1) ==> MOVZ.
403  if (SignedValue < 0)
404  Data[Offset + 3] &= ~(1 << 6);
405  else
406  Data[Offset + 3] |= (1 << 6);
407  }
408 }
409 
410 bool AArch64AsmBackend::mayNeedRelaxation(const MCInst &Inst,
411  const MCSubtargetInfo &STI) const {
412  return false;
413 }
414 
415 bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
416  uint64_t Value,
417  const MCRelaxableFragment *DF,
418  const MCAsmLayout &Layout) const {
419  // FIXME: This isn't correct for AArch64. Just moving the "generic" logic
420  // into the targets for now.
421  //
422  // Relax if the value is too big for a (signed) i8.
423  return int64_t(Value) != int64_t(int8_t(Value));
424 }
425 
426 void AArch64AsmBackend::relaxInstruction(const MCInst &Inst,
427  const MCSubtargetInfo &STI,
428  MCInst &Res) const {
429  llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
430 }
431 
432 bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
433  // If the count is not 4-byte aligned, we must be writing data into the text
434  // section (otherwise we have unaligned instructions, and thus have far
435  // bigger problems), so just write zeros instead.
436  OS.write_zeros(Count % 4);
437 
438  // We are properly aligned, so write NOPs as requested.
439  Count /= 4;
440  for (uint64_t i = 0; i != Count; ++i)
441  support::endian::write<uint32_t>(OS, 0xd503201f, Endian);
442  return true;
443 }
444 
445 bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
446  const MCFixup &Fixup,
447  const MCValue &Target) {
448  // The ADRP instruction adds some multiple of 0x1000 to the current PC &
449  // ~0xfff. This means that the required offset to reach a symbol can vary by
450  // up to one step depending on where the ADRP is in memory. For example:
451  //
452  // ADRP x0, there
453  // there:
454  //
455  // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
456  // we'll need that as an offset. At any other address "there" will be in the
457  // same page as the ADRP and the instruction should encode 0x0. Assuming the
458  // section isn't 0x1000-aligned, we therefore need to delegate this decision
459  // to the linker -- a relocation!
461  return true;
462 
464  static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
466  // LDR GOT relocations need a relocation
468  SymLoc == AArch64MCExpr::VK_GOT)
469  return true;
470  return false;
471 }
472 
473 namespace {
474 
475 namespace CU {
476 
477 /// Compact unwind encoding values.
479  /// A "frameless" leaf function, where no non-volatile registers are
480  /// saved. The return remains in LR throughout the function.
481  UNWIND_ARM64_MODE_FRAMELESS = 0x02000000,
482 
483  /// No compact unwind encoding available. Instead the low 23-bits of
484  /// the compact unwind encoding is the offset of the DWARF FDE in the
485  /// __eh_frame section. This mode is never used in object files. It is only
486  /// generated by the linker in final linked images, which have only DWARF info
487  /// for a function.
488  UNWIND_ARM64_MODE_DWARF = 0x03000000,
489 
490  /// This is a standard arm64 prologue where FP/LR are immediately
491  /// pushed on the stack, then SP is copied to FP. If there are any
492  /// non-volatile register saved, they are copied into the stack fame in pairs
493  /// in a contiguous ranger right below the saved FP/LR pair. Any subset of the
494  /// five X pairs and four D pairs can be saved, but the memory layout must be
495  /// in register number order.
496  UNWIND_ARM64_MODE_FRAME = 0x04000000,
497 
498  /// Frame register pair encodings.
499  UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001,
500  UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002,
501  UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004,
502  UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008,
503  UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010,
504  UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100,
505  UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200,
506  UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400,
507  UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800
508 };
509 
510 } // end CU namespace
511 
512 // FIXME: This should be in a separate file.
513 class DarwinAArch64AsmBackend : public AArch64AsmBackend {
514  const MCRegisterInfo &MRI;
515 
516  /// Encode compact unwind stack adjustment for frameless functions.
517  /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.
518  /// The stack size always needs to be 16 byte aligned.
519  uint32_t encodeStackAdjustment(uint32_t StackSize) const {
520  return (StackSize / 16) << 12;
521  }
522 
523 public:
524  DarwinAArch64AsmBackend(const Target &T, const Triple &TT,
525  const MCRegisterInfo &MRI)
526  : AArch64AsmBackend(T, TT, /*IsLittleEndian*/ true), MRI(MRI) {}
527 
528  std::unique_ptr<MCObjectTargetWriter>
529  createObjectTargetWriter() const override {
532  }
533 
534  /// Generate the compact unwind encoding from the CFI directives.
535  uint32_t generateCompactUnwindEncoding(
536  ArrayRef<MCCFIInstruction> Instrs) const override {
537  if (Instrs.empty())
538  return CU::UNWIND_ARM64_MODE_FRAMELESS;
539 
540  bool HasFP = false;
541  unsigned StackSize = 0;
542 
543  uint32_t CompactUnwindEncoding = 0;
544  for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
545  const MCCFIInstruction &Inst = Instrs[i];
546 
547  switch (Inst.getOperation()) {
548  default:
549  // Cannot handle this directive: bail out.
550  return CU::UNWIND_ARM64_MODE_DWARF;
552  // Defines a frame pointer.
553  unsigned XReg =
554  getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true));
555 
556  // Other CFA registers than FP are not supported by compact unwind.
557  // Fallback on DWARF.
558  // FIXME: When opt-remarks are supported in MC, add a remark to notify
559  // the user.
560  if (XReg != AArch64::FP)
561  return CU::UNWIND_ARM64_MODE_DWARF;
562 
563  assert(XReg == AArch64::FP && "Invalid frame pointer!");
564  assert(i + 2 < e && "Insufficient CFI instructions to define a frame!");
565 
566  const MCCFIInstruction &LRPush = Instrs[++i];
568  "Link register not pushed!");
569  const MCCFIInstruction &FPPush = Instrs[++i];
570  assert(FPPush.getOperation() == MCCFIInstruction::OpOffset &&
571  "Frame pointer not pushed!");
572 
573  unsigned LRReg = MRI.getLLVMRegNum(LRPush.getRegister(), true);
574  unsigned FPReg = MRI.getLLVMRegNum(FPPush.getRegister(), true);
575 
576  LRReg = getXRegFromWReg(LRReg);
577  FPReg = getXRegFromWReg(FPReg);
578 
579  assert(LRReg == AArch64::LR && FPReg == AArch64::FP &&
580  "Pushing invalid registers for frame!");
581 
582  // Indicate that the function has a frame.
583  CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME;
584  HasFP = true;
585  break;
586  }
588  assert(StackSize == 0 && "We already have the CFA offset!");
589  StackSize = std::abs(Inst.getOffset());
590  break;
591  }
593  // Registers are saved in pairs. We expect there to be two consecutive
594  // `.cfi_offset' instructions with the appropriate registers specified.
595  unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
596  if (i + 1 == e)
597  return CU::UNWIND_ARM64_MODE_DWARF;
598 
599  const MCCFIInstruction &Inst2 = Instrs[++i];
601  return CU::UNWIND_ARM64_MODE_DWARF;
602  unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
603 
604  // N.B. The encodings must be in register number order, and the X
605  // registers before the D registers.
606 
607  // X19/X20 pair = 0x00000001,
608  // X21/X22 pair = 0x00000002,
609  // X23/X24 pair = 0x00000004,
610  // X25/X26 pair = 0x00000008,
611  // X27/X28 pair = 0x00000010
612  Reg1 = getXRegFromWReg(Reg1);
613  Reg2 = getXRegFromWReg(Reg2);
614 
615  if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
616  (CompactUnwindEncoding & 0xF1E) == 0)
617  CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR;
618  else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
619  (CompactUnwindEncoding & 0xF1C) == 0)
620  CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR;
621  else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
622  (CompactUnwindEncoding & 0xF18) == 0)
623  CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR;
624  else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
625  (CompactUnwindEncoding & 0xF10) == 0)
626  CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR;
627  else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
628  (CompactUnwindEncoding & 0xF00) == 0)
629  CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR;
630  else {
631  Reg1 = getDRegFromBReg(Reg1);
632  Reg2 = getDRegFromBReg(Reg2);
633 
634  // D8/D9 pair = 0x00000100,
635  // D10/D11 pair = 0x00000200,
636  // D12/D13 pair = 0x00000400,
637  // D14/D15 pair = 0x00000800
638  if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 &&
639  (CompactUnwindEncoding & 0xE00) == 0)
640  CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR;
641  else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 &&
642  (CompactUnwindEncoding & 0xC00) == 0)
643  CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR;
644  else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 &&
645  (CompactUnwindEncoding & 0x800) == 0)
646  CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR;
647  else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)
648  CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR;
649  else
650  // A pair was pushed which we cannot handle.
651  return CU::UNWIND_ARM64_MODE_DWARF;
652  }
653 
654  break;
655  }
656  }
657  }
658 
659  if (!HasFP) {
660  // With compact unwind info we can only represent stack adjustments of up
661  // to 65520 bytes.
662  if (StackSize > 65520)
663  return CU::UNWIND_ARM64_MODE_DWARF;
664 
665  CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS;
666  CompactUnwindEncoding |= encodeStackAdjustment(StackSize);
667  }
668 
669  return CompactUnwindEncoding;
670  }
671 };
672 
673 } // end anonymous namespace
674 
675 namespace {
676 
677 class ELFAArch64AsmBackend : public AArch64AsmBackend {
678 public:
679  uint8_t OSABI;
680  bool IsILP32;
681 
682  ELFAArch64AsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
683  bool IsLittleEndian, bool IsILP32)
684  : AArch64AsmBackend(T, TT, IsLittleEndian), OSABI(OSABI),
685  IsILP32(IsILP32) {}
686 
687  std::unique_ptr<MCObjectTargetWriter>
688  createObjectTargetWriter() const override {
689  return createAArch64ELFObjectWriter(OSABI, IsILP32);
690  }
691 };
692 
693 }
694 
695 namespace {
696 class COFFAArch64AsmBackend : public AArch64AsmBackend {
697 public:
698  COFFAArch64AsmBackend(const Target &T, const Triple &TheTriple)
699  : AArch64AsmBackend(T, TheTriple, /*IsLittleEndian*/ true) {}
700 
701  std::unique_ptr<MCObjectTargetWriter>
702  createObjectTargetWriter() const override {
704  }
705 };
706 }
707 
709  const MCSubtargetInfo &STI,
710  const MCRegisterInfo &MRI,
711  const MCTargetOptions &Options) {
712  const Triple &TheTriple = STI.getTargetTriple();
713  if (TheTriple.isOSBinFormatMachO())
714  return new DarwinAArch64AsmBackend(T, TheTriple, MRI);
715 
716  if (TheTriple.isOSBinFormatCOFF())
717  return new COFFAArch64AsmBackend(T, TheTriple);
718 
719  assert(TheTriple.isOSBinFormatELF() && "Invalid target");
720 
721  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
722  bool IsILP32 = Options.getABIName() == "ilp32";
723  return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/true,
724  IsILP32);
725 }
726 
728  const MCSubtargetInfo &STI,
729  const MCRegisterInfo &MRI,
730  const MCTargetOptions &Options) {
731  const Triple &TheTriple = STI.getTargetTriple();
732  assert(TheTriple.isOSBinFormatELF() &&
733  "Big endian is only supported for ELF targets!");
734  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
735  bool IsILP32 = Options.getABIName() == "ilp32";
736  return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/false,
737  IsILP32);
738 }
This class represents lattice values for constants.
Definition: AllocatorList.h:23
This represents an "assembler immediate".
Definition: MCValue.h:39
std::unique_ptr< MCObjectTargetWriter > createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype)
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:614
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:300
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert &#39;NumZeros&#39; nulls.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
static unsigned getXRegFromWReg(unsigned Reg)
unsigned TargetOffset
The bit offset to write the relocation into.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:73
const Triple & getTargetTriple() const
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
MCContext & getContext() const
Definition: MCAssembler.h:284
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
A four-byte section relative fixup.
Definition: MCFixup.h:41
A four-byte fixup.
Definition: MCFixup.h:25
Context object for machine code objects.
Definition: MCContext.h:62
A two-byte section relative fixup.
Definition: MCFixup.h:40
CompactUnwindEncodings
Compact unwind encoding values.
static uint64_t getPointerSize(const Value *V, const DataLayout &DL, const TargetLibraryInfo &TLI, const Function *F)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
static VariantKind getAddressFrag(VariantKind Kind)
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
unsigned const MachineRegisterInfo * MRI
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:290
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:619
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
int getOffset() const
Definition: MCDwarf.h:590
OpType getOperation() const
Definition: MCDwarf.h:574
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:641
Should this fixup kind force a 4-byte aligned effective PC value?
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
uint32_t getOffset() const
Definition: MCFixup.h:124
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:624
static unsigned AdrImmBits(unsigned Value)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A one-byte fixup.
Definition: MCFixup.h:23
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
PowerPC TLS Dynamic Call Fixup
unsigned getRegister() const
Definition: MCDwarf.h:577
SMLoc getLoc() const
Definition: MCFixup.h:165
Target - Wrapper for Target specific information.
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
static unsigned getDRegFromBReg(unsigned Reg)
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
MCAssemblerFlag
Definition: MCDirectives.h:48
std::unique_ptr< MCObjectTargetWriter > createAArch64WinCOFFObjectWriter()
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1212
Generic base class for all target subtargets.
A eight-byte fixup.
Definition: MCFixup.h:26
Target independent information on a fixup kind.
uint32_t getRefKind() const
Definition: MCValue.h:49
static VariantKind getSymbolLoc(VariantKind Kind)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
A two-byte fixup.
Definition: MCFixup.h:24
int getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
MCFixupKind getKind() const
Definition: MCFixup.h:122
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143