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ARMAsmBackend.cpp
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1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/BinaryFormat/ELF.h"
20 #include "llvm/MC/MCAsmBackend.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCDirectives.h"
25 #include "llvm/MC/MCExpr.h"
27 #include "llvm/MC/MCObjectWriter.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCSectionELF.h"
30 #include "llvm/MC/MCSectionMachO.h"
32 #include "llvm/MC/MCValue.h"
33 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/Format.h"
38 using namespace llvm;
39 
40 namespace {
41 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
42 public:
43  ARMELFObjectWriter(uint8_t OSABI)
44  : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
45  /*HasRelocationAddend*/ false) {}
46 };
47 } // end anonymous namespace
48 
50  const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
51  // This table *must* be in the order that the fixup_* kinds are defined in
52  // ARMFixupKinds.h.
53  //
54  // Name Offset (bits) Size (bits) Flags
55  {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
56  {"fixup_t2_ldst_pcrel_12", 0, 32,
59  {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
60  {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
61  {"fixup_t2_pcrel_10", 0, 32,
64  {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
65  {"fixup_t2_pcrel_9", 0, 32,
68  {"fixup_thumb_adr_pcrel_10", 0, 8,
71  {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
72  {"fixup_t2_adr_pcrel_12", 0, 32,
75  {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
76  {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
77  {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
78  {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
79  {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
80  {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
81  {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
82  {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
83  {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
84  {"fixup_arm_thumb_blx", 0, 32,
87  {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
88  {"fixup_arm_thumb_cp", 0, 8,
91  {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
92  // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
93  // - 19.
94  {"fixup_arm_movt_hi16", 0, 20, 0},
95  {"fixup_arm_movw_lo16", 0, 20, 0},
96  {"fixup_t2_movt_hi16", 0, 20, 0},
97  {"fixup_t2_movw_lo16", 0, 20, 0},
98  {"fixup_arm_mod_imm", 0, 12, 0},
99  {"fixup_t2_so_imm", 0, 26, 0},
100  };
101  const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
102  // This table *must* be in the order that the fixup_* kinds are defined in
103  // ARMFixupKinds.h.
104  //
105  // Name Offset (bits) Size (bits) Flags
106  {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
107  {"fixup_t2_ldst_pcrel_12", 0, 32,
110  {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
111  {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
112  {"fixup_t2_pcrel_10", 0, 32,
115  {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
116  {"fixup_t2_pcrel_9", 0, 32,
119  {"fixup_thumb_adr_pcrel_10", 8, 8,
122  {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
123  {"fixup_t2_adr_pcrel_12", 0, 32,
126  {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
127  {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
128  {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
129  {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
130  {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
131  {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
132  {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
133  {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
134  {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
135  {"fixup_arm_thumb_blx", 0, 32,
138  {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
139  {"fixup_arm_thumb_cp", 8, 8,
142  {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
143  // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
144  // - 19.
145  {"fixup_arm_movt_hi16", 12, 20, 0},
146  {"fixup_arm_movw_lo16", 12, 20, 0},
147  {"fixup_t2_movt_hi16", 12, 20, 0},
148  {"fixup_t2_movw_lo16", 12, 20, 0},
149  {"fixup_arm_mod_imm", 20, 12, 0},
150  {"fixup_t2_so_imm", 26, 6, 0},
151  };
152 
153  if (Kind < FirstTargetFixupKind)
154  return MCAsmBackend::getFixupKindInfo(Kind);
155 
156  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
157  "Invalid kind!");
158  return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind];
159 }
160 
162  switch (Flag) {
163  default:
164  break;
165  case MCAF_Code16:
166  setIsThumb(true);
167  break;
168  case MCAF_Code32:
169  setIsThumb(false);
170  break;
171  }
172 }
173 
174 unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const {
175  bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2];
176  bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps];
177 
178  switch (Op) {
179  default:
180  return Op;
181  case ARM::tBcc:
182  return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
183  case ARM::tLDRpci:
184  return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
185  case ARM::tADR:
186  return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
187  case ARM::tB:
188  return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op;
189  case ARM::tCBZ:
190  return ARM::tHINT;
191  case ARM::tCBNZ:
192  return ARM::tHINT;
193  }
194 }
195 
196 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
197  if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
198  return true;
199  return false;
200 }
201 
203  uint64_t Value) const {
204  switch ((unsigned)Fixup.getKind()) {
206  // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
207  // low bit being an implied zero. There's an implied +4 offset for the
208  // branch, so we adjust the other way here to determine what's
209  // encodable.
210  //
211  // Relax if the value is too big for a (signed) i8.
212  int64_t Offset = int64_t(Value) - 4;
213  if (Offset > 2046 || Offset < -2048)
214  return "out of range pc-relative fixup value";
215  break;
216  }
218  // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
219  // low bit being an implied zero. There's an implied +4 offset for the
220  // branch, so we adjust the other way here to determine what's
221  // encodable.
222  //
223  // Relax if the value is too big for a (signed) i8.
224  int64_t Offset = int64_t(Value) - 4;
225  if (Offset > 254 || Offset < -256)
226  return "out of range pc-relative fixup value";
227  break;
228  }
231  // If the immediate is negative, greater than 1020, or not a multiple
232  // of four, the wide version of the instruction must be used.
233  int64_t Offset = int64_t(Value) - 4;
234  if (Offset & 3)
235  return "misaligned pc-relative fixup value";
236  else if (Offset > 1020 || Offset < 0)
237  return "out of range pc-relative fixup value";
238  break;
239  }
241  // If we have a Thumb CBZ or CBNZ instruction and its target is the next
242  // instruction it is is actually out of range for the instruction.
243  // It will be changed to a NOP.
244  int64_t Offset = (Value & ~1);
245  if (Offset == 2)
246  return "will be converted to nop";
247  break;
248  }
249  default:
250  llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!");
251  }
252  return nullptr;
253 }
254 
256  const MCRelaxableFragment *DF,
257  const MCAsmLayout &Layout) const {
258  return reasonForFixupRelaxation(Fixup, Value);
259 }
260 
262  const MCSubtargetInfo &STI,
263  MCInst &Res) const {
264  unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
265 
266  // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
267  if (RelaxedOp == Inst.getOpcode()) {
268  SmallString<256> Tmp;
269  raw_svector_ostream OS(Tmp);
270  Inst.dump_pretty(OS);
271  OS << "\n";
272  report_fatal_error("unexpected instruction to relax: " + OS.str());
273  }
274 
275  // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
276  // have to change the operands too.
277  if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
278  RelaxedOp == ARM::tHINT) {
279  Res.setOpcode(RelaxedOp);
283  return;
284  }
285 
286  // The rest of instructions we're relaxing have the same operands.
287  // We just need to update to the proper opcode.
288  Res = Inst;
289  Res.setOpcode(RelaxedOp);
290 }
291 
292 bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
293  const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
294  const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
295  const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
296  const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
297  if (isThumb()) {
298  const uint16_t nopEncoding =
299  hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
300  uint64_t NumNops = Count / 2;
301  for (uint64_t i = 0; i != NumNops; ++i)
302  OW->write16(nopEncoding);
303  if (Count & 1)
304  OW->write8(0);
305  return true;
306  }
307  // ARM mode
308  const uint32_t nopEncoding =
309  hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
310  uint64_t NumNops = Count / 4;
311  for (uint64_t i = 0; i != NumNops; ++i)
312  OW->write32(nopEncoding);
313  // FIXME: should this function return false when unable to write exactly
314  // 'Count' bytes with NOP encodings?
315  switch (Count % 4) {
316  default:
317  break; // No leftover bytes to write
318  case 1:
319  OW->write8(0);
320  break;
321  case 2:
322  OW->write16(0);
323  break;
324  case 3:
325  OW->write16(0);
326  OW->write8(0xa0);
327  break;
328  }
329 
330  return true;
331 }
332 
333 static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
334  if (IsLittleEndian) {
335  // Note that the halfwords are stored high first and low second in thumb;
336  // so we need to swap the fixup value here to map properly.
337  uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
338  Swapped |= (Value & 0x0000FFFF) << 16;
339  return Swapped;
340  } else
341  return Value;
342 }
343 
344 static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
345  bool IsLittleEndian) {
346  uint32_t Value;
347 
348  if (IsLittleEndian) {
349  Value = (SecondHalf & 0xFFFF) << 16;
350  Value |= (FirstHalf & 0xFFFF);
351  } else {
352  Value = (SecondHalf & 0xFFFF);
353  Value |= (FirstHalf & 0xFFFF) << 16;
354  }
355 
356  return Value;
357 }
358 
360  const MCFixup &Fixup,
361  const MCValue &Target, uint64_t Value,
362  bool IsResolved, MCContext &Ctx,
363  bool IsLittleEndian) const {
364  unsigned Kind = Fixup.getKind();
365 
366  // MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
367  // and .word relocations they put the Thumb bit into the addend if possible.
368  // Other relocation types don't want this bit though (branches couldn't encode
369  // it if it *was* present, and no other relocations exist) and it can
370  // interfere with checking valid expressions.
371  if (const MCSymbolRefExpr *A = Target.getSymA()) {
372  if (A->hasSubsectionsViaSymbols() && Asm.isThumbFunc(&A->getSymbol()) &&
373  (Kind == FK_Data_4 || Kind == ARM::fixup_arm_movw_lo16 ||
375  Kind == ARM::fixup_t2_movt_hi16))
376  Value |= 1;
377  }
378 
379  switch (Kind) {
380  default:
381  Ctx.reportError(Fixup.getLoc(), "bad relocation fixup type");
382  return 0;
383  case FK_Data_1:
384  case FK_Data_2:
385  case FK_Data_4:
386  return Value;
387  case FK_SecRel_2:
388  return Value;
389  case FK_SecRel_4:
390  return Value;
392  if (IsResolved || !STI.getTargetTriple().isOSBinFormatELF())
393  Value >>= 16;
396  unsigned Hi4 = (Value & 0xF000) >> 12;
397  unsigned Lo12 = Value & 0x0FFF;
398  // inst{19-16} = Hi4;
399  // inst{11-0} = Lo12;
400  Value = (Hi4 << 16) | (Lo12);
401  return Value;
402  }
404  if (IsResolved || !STI.getTargetTriple().isOSBinFormatELF())
405  Value >>= 16;
408  unsigned Hi4 = (Value & 0xF000) >> 12;
409  unsigned i = (Value & 0x800) >> 11;
410  unsigned Mid3 = (Value & 0x700) >> 8;
411  unsigned Lo8 = Value & 0x0FF;
412  // inst{19-16} = Hi4;
413  // inst{26} = i;
414  // inst{14-12} = Mid3;
415  // inst{7-0} = Lo8;
416  Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
417  return swapHalfWords(Value, IsLittleEndian);
418  }
420  // ARM PC-relative values are offset by 8.
421  Value -= 4;
424  // Offset by 4, adjusted by two due to the half-word ordering of thumb.
425  Value -= 4;
426  bool isAdd = true;
427  if ((int64_t)Value < 0) {
428  Value = -Value;
429  isAdd = false;
430  }
431  if (Value >= 4096) {
432  Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
433  return 0;
434  }
435  Value |= isAdd << 23;
436 
437  // Same addressing mode as fixup_arm_pcrel_10,
438  // but with 16-bit halfwords swapped.
439  if (Kind == ARM::fixup_t2_ldst_pcrel_12)
440  return swapHalfWords(Value, IsLittleEndian);
441 
442  return Value;
443  }
445  // ARM PC-relative values are offset by 8.
446  Value -= 8;
447  unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
448  if ((int64_t)Value < 0) {
449  Value = -Value;
450  opc = 2; // 0b0010
451  }
452  if (ARM_AM::getSOImmVal(Value) == -1) {
453  Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
454  return 0;
455  }
456  // Encode the immediate and shift the opcode into place.
457  return ARM_AM::getSOImmVal(Value) | (opc << 21);
458  }
459 
461  Value -= 4;
462  unsigned opc = 0;
463  if ((int64_t)Value < 0) {
464  Value = -Value;
465  opc = 5;
466  }
467 
468  uint32_t out = (opc << 21);
469  out |= (Value & 0x800) << 15;
470  out |= (Value & 0x700) << 4;
471  out |= (Value & 0x0FF);
472 
473  return swapHalfWords(out, IsLittleEndian);
474  }
475 
480  case ARM::fixup_arm_blx:
481  // These values don't encode the low two bits since they're always zero.
482  // Offset by 8 just as above.
483  if (const MCSymbolRefExpr *SRE =
484  dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
485  if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
486  return 0;
487  return 0xffffff & ((Value - 8) >> 2);
489  Value = Value - 4;
490  Value >>= 1; // Low bit is not encoded.
491 
492  uint32_t out = 0;
493  bool I = Value & 0x800000;
494  bool J1 = Value & 0x400000;
495  bool J2 = Value & 0x200000;
496  J1 ^= I;
497  J2 ^= I;
498 
499  out |= I << 26; // S bit
500  out |= !J1 << 13; // J1 bit
501  out |= !J2 << 11; // J2 bit
502  out |= (Value & 0x1FF800) << 5; // imm6 field
503  out |= (Value & 0x0007FF); // imm11 field
504 
505  return swapHalfWords(out, IsLittleEndian);
506  }
508  Value = Value - 4;
509  Value >>= 1; // Low bit is not encoded.
510 
511  uint64_t out = 0;
512  out |= (Value & 0x80000) << 7; // S bit
513  out |= (Value & 0x40000) >> 7; // J2 bit
514  out |= (Value & 0x20000) >> 4; // J1 bit
515  out |= (Value & 0x1F800) << 5; // imm6 field
516  out |= (Value & 0x007FF); // imm11 field
517 
518  return swapHalfWords(out, IsLittleEndian);
519  }
521  // FIXME: We get both thumb1 and thumb2 in here, so we can only check for
522  // the less strict thumb2 value.
523  if (!isInt<26>(Value - 4)) {
524  Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
525  return 0;
526  }
527 
528  // The value doesn't encode the low bit (always zero) and is offset by
529  // four. The 32-bit immediate value is encoded as
530  // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
531  // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
532  // The value is encoded into disjoint bit positions in the destination
533  // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
534  // J = either J1 or J2 bit
535  //
536  // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
537  //
538  // Note that the halfwords are stored high first, low second; so we need
539  // to transpose the fixup value here to map properly.
540  uint32_t offset = (Value - 4) >> 1;
541  uint32_t signBit = (offset & 0x800000) >> 23;
542  uint32_t I1Bit = (offset & 0x400000) >> 22;
543  uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
544  uint32_t I2Bit = (offset & 0x200000) >> 21;
545  uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
546  uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
547  uint32_t imm11Bits = (offset & 0x000007FF);
548 
549  uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
550  uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
551  (uint16_t)imm11Bits);
552  return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
553  }
555  // The value doesn't encode the low two bits (always zero) and is offset by
556  // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
557  // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
558  // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
559  // The value is encoded into disjoint bit positions in the destination
560  // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
561  // J = either J1 or J2 bit, 0 = zero.
562  //
563  // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
564  //
565  // Note that the halfwords are stored high first, low second; so we need
566  // to transpose the fixup value here to map properly.
567  if (Value % 4 != 0) {
568  Ctx.reportError(Fixup.getLoc(), "misaligned ARM call destination");
569  return 0;
570  }
571 
572  uint32_t offset = (Value - 4) >> 2;
573  if (const MCSymbolRefExpr *SRE =
574  dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
575  if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
576  offset = 0;
577  uint32_t signBit = (offset & 0x400000) >> 22;
578  uint32_t I1Bit = (offset & 0x200000) >> 21;
579  uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
580  uint32_t I2Bit = (offset & 0x100000) >> 20;
581  uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
582  uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
583  uint32_t imm10LBits = (offset & 0x3FF);
584 
585  uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
586  uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
587  ((uint16_t)imm10LBits) << 1);
588  return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
589  }
592  // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we
593  // could have an error on our hands.
594  if (!STI.getFeatureBits()[ARM::FeatureThumb2] && IsResolved) {
595  const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
596  if (FixupDiagnostic) {
597  Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
598  return 0;
599  }
600  }
601  // Offset by 4, and don't encode the low two bits.
602  return ((Value - 4) >> 2) & 0xff;
604  // CB instructions can only branch to offsets in [4, 126] in multiples of 2
605  // so ensure that the raw value LSB is zero and it lies in [2, 130].
606  // An offset of 2 will be relaxed to a NOP.
607  if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) {
608  Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
609  return 0;
610  }
611  // Offset by 4 and don't encode the lower bit, which is always 0.
612  // FIXME: diagnose if no Thumb2
613  uint32_t Binary = (Value - 4) >> 1;
614  return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
615  }
617  // Offset by 4 and don't encode the lower bit, which is always 0.
618  if (!STI.getFeatureBits()[ARM::FeatureThumb2] &&
619  !STI.getFeatureBits()[ARM::HasV8MBaselineOps]) {
620  const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
621  if (FixupDiagnostic) {
622  Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
623  return 0;
624  }
625  }
626  return ((Value - 4) >> 1) & 0x7ff;
628  // Offset by 4 and don't encode the lower bit, which is always 0.
629  if (!STI.getFeatureBits()[ARM::FeatureThumb2]) {
630  const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
631  if (FixupDiagnostic) {
632  Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
633  return 0;
634  }
635  }
636  return ((Value - 4) >> 1) & 0xff;
638  Value = Value - 8; // ARM fixups offset by an additional word and don't
639  // need to adjust for the half-word ordering.
640  bool isAdd = true;
641  if ((int64_t)Value < 0) {
642  Value = -Value;
643  isAdd = false;
644  }
645  // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
646  if (Value >= 256) {
647  Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
648  return 0;
649  }
650  Value = (Value & 0xf) | ((Value & 0xf0) << 4);
651  return Value | (isAdd << 23);
652  }
654  Value = Value - 4; // ARM fixups offset by an additional word and don't
655  // need to adjust for the half-word ordering.
657  case ARM::fixup_t2_pcrel_10: {
658  // Offset by 4, adjusted by two due to the half-word ordering of thumb.
659  Value = Value - 4;
660  bool isAdd = true;
661  if ((int64_t)Value < 0) {
662  Value = -Value;
663  isAdd = false;
664  }
665  // These values don't encode the low two bits since they're always zero.
666  Value >>= 2;
667  if (Value >= 256) {
668  Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
669  return 0;
670  }
671  Value |= isAdd << 23;
672 
673  // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
674  // swapped.
675  if (Kind == ARM::fixup_t2_pcrel_10)
676  return swapHalfWords(Value, IsLittleEndian);
677 
678  return Value;
679  }
681  Value = Value - 4; // ARM fixups offset by an additional word and don't
682  // need to adjust for the half-word ordering.
684  case ARM::fixup_t2_pcrel_9: {
685  // Offset by 4, adjusted by two due to the half-word ordering of thumb.
686  Value = Value - 4;
687  bool isAdd = true;
688  if ((int64_t)Value < 0) {
689  Value = -Value;
690  isAdd = false;
691  }
692  // These values don't encode the low bit since it's always zero.
693  if (Value & 1) {
694  Ctx.reportError(Fixup.getLoc(), "invalid value for this fixup");
695  return 0;
696  }
697  Value >>= 1;
698  if (Value >= 256) {
699  Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
700  return 0;
701  }
702  Value |= isAdd << 23;
703 
704  // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
705  // swapped.
706  if (Kind == ARM::fixup_t2_pcrel_9)
707  return swapHalfWords(Value, IsLittleEndian);
708 
709  return Value;
710  }
712  Value = ARM_AM::getSOImmVal(Value);
713  if (Value >> 12) {
714  Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
715  return 0;
716  }
717  return Value;
718  case ARM::fixup_t2_so_imm: {
719  Value = ARM_AM::getT2SOImmVal(Value);
720  if ((int64_t)Value < 0) {
721  Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
722  return 0;
723  }
724  // Value will contain a 12-bit value broken up into a 4-bit shift in bits
725  // 11:8 and the 8-bit immediate in 0:7. The instruction has the immediate
726  // in 0:7. The 4-bit shift is split up into i:imm3 where i is placed at bit
727  // 10 of the upper half-word and imm3 is placed at 14:12 of the lower
728  // half-word.
729  uint64_t EncValue = 0;
730  EncValue |= (Value & 0x800) << 15;
731  EncValue |= (Value & 0x700) << 4;
732  EncValue |= (Value & 0xff);
733  return swapHalfWords(EncValue, IsLittleEndian);
734  }
735  }
736 }
737 
739  const MCFixup &Fixup,
740  const MCValue &Target) {
741  const MCSymbolRefExpr *A = Target.getSymA();
742  const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;
743  const unsigned FixupKind = Fixup.getKind() ;
744  if ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) {
745  assert(Sym && "How did we resolve this?");
746 
747  // If the symbol is external the linker will handle it.
748  // FIXME: Should we handle it as an optimization?
749 
750  // If the symbol is out of range, produce a relocation and hope the
751  // linker can handle it. GNU AS produces an error in this case.
752  if (Sym->isExternal())
753  return true;
754  }
755  // Create relocations for unconditional branches to function symbols with
756  // different execution mode in ELF binaries.
757  if (Sym && Sym->isELF()) {
758  unsigned Type = dyn_cast<MCSymbolELF>(Sym)->getType();
759  if ((Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC)) {
760  if (Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_uncondbranch))
761  return true;
762  if (!Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_thumb_br ||
763  FixupKind == ARM::fixup_arm_thumb_bl ||
764  FixupKind == ARM::fixup_t2_condbranch ||
765  FixupKind == ARM::fixup_t2_uncondbranch))
766  return true;
767  }
768  }
769  // We must always generate a relocation for BL/BLX instructions if we have
770  // a symbol to reference, as the linker relies on knowing the destination
771  // symbol's thumb-ness to get interworking right.
772  if (A && (FixupKind == ARM::fixup_arm_thumb_blx ||
773  FixupKind == ARM::fixup_arm_blx ||
774  FixupKind == ARM::fixup_arm_uncondbl ||
775  FixupKind == ARM::fixup_arm_condbl))
776  return true;
777  return false;
778 }
779 
780 /// getFixupKindNumBytes - The number of bytes the fixup may change.
781 static unsigned getFixupKindNumBytes(unsigned Kind) {
782  switch (Kind) {
783  default:
784  llvm_unreachable("Unknown fixup kind!");
785 
786  case FK_Data_1:
790  return 1;
791 
792  case FK_Data_2:
796  return 2;
797 
805  case ARM::fixup_arm_blx:
808  return 3;
809 
810  case FK_Data_4:
824  return 4;
825 
826  case FK_SecRel_2:
827  return 2;
828  case FK_SecRel_4:
829  return 4;
830  }
831 }
832 
833 /// getFixupKindContainerSizeBytes - The number of bytes of the
834 /// container involved in big endian.
835 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
836  switch (Kind) {
837  default:
838  llvm_unreachable("Unknown fixup kind!");
839 
840  case FK_Data_1:
841  return 1;
842  case FK_Data_2:
843  return 2;
844  case FK_Data_4:
845  return 4;
846 
852  // Instruction size is 2 bytes.
853  return 2;
854 
861  case ARM::fixup_arm_blx:
877  // Instruction size is 4 bytes.
878  return 4;
879  }
880 }
881 
883  const MCValue &Target,
884  MutableArrayRef<char> Data, uint64_t Value,
885  bool IsResolved) const {
886  unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
887  MCContext &Ctx = Asm.getContext();
888  Value = adjustFixupValue(Asm, Fixup, Target, Value, IsResolved, Ctx,
889  IsLittleEndian);
890  if (!Value)
891  return; // Doesn't change encoding.
892 
893  unsigned Offset = Fixup.getOffset();
894  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
895 
896  // Used to point to big endian bytes.
897  unsigned FullSizeBytes;
898  if (!IsLittleEndian) {
899  FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind());
900  assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!");
901  assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
902  }
903 
904  // For each byte of the fragment that the fixup touches, mask in the bits from
905  // the fixup value. The Value has been "split up" into the appropriate
906  // bitfields above.
907  for (unsigned i = 0; i != NumBytes; ++i) {
908  unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i);
909  Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
910  }
911 }
912 
913 namespace CU {
914 
915 /// \brief Compact unwind encoding values.
917  UNWIND_ARM_MODE_MASK = 0x0F000000,
918  UNWIND_ARM_MODE_FRAME = 0x01000000,
920  UNWIND_ARM_MODE_DWARF = 0x04000000,
921 
923 
927 
933 
935 
937 };
938 
939 } // end CU namespace
940 
941 /// Generate compact unwind encoding for the function based on the CFI
942 /// instructions. If the CFI instructions describe a frame that cannot be
943 /// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which
944 /// tells the runtime to fallback and unwind using dwarf.
946  ArrayRef<MCCFIInstruction> Instrs) const {
947  DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n");
948  // Only armv7k uses CFI based unwinding.
949  if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K)
950  return 0;
951  // No .cfi directives means no frame.
952  if (Instrs.empty())
953  return 0;
954  // Start off assuming CFA is at SP+0.
955  int CFARegister = ARM::SP;
956  int CFARegisterOffset = 0;
957  // Mark savable registers as initially unsaved
958  DenseMap<unsigned, int> RegOffsets;
959  int FloatRegCount = 0;
960  // Process each .cfi directive and build up compact unwind info.
961  for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
962  int Reg;
963  const MCCFIInstruction &Inst = Instrs[i];
964  switch (Inst.getOperation()) {
965  case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
966  CFARegisterOffset = -Inst.getOffset();
967  CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true);
968  break;
969  case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset
970  CFARegisterOffset = -Inst.getOffset();
971  break;
972  case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register
973  CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true);
974  break;
975  case MCCFIInstruction::OpOffset: // DW_CFA_offset
976  Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
977  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
978  RegOffsets[Reg] = Inst.getOffset();
979  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
980  RegOffsets[Reg] = Inst.getOffset();
981  ++FloatRegCount;
982  } else {
983  DEBUG_WITH_TYPE("compact-unwind",
984  llvm::dbgs() << ".cfi_offset on unknown register="
985  << Inst.getRegister() << "\n");
987  }
988  break;
989  case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc
990  // Ignore
991  break;
992  default:
993  // Directive not convertable to compact unwind, bail out.
994  DEBUG_WITH_TYPE("compact-unwind",
995  llvm::dbgs()
996  << "CFI directive not compatiable with comact "
997  "unwind encoding, opcode=" << Inst.getOperation()
998  << "\n");
1000  break;
1001  }
1002  }
1003 
1004  // If no frame set up, return no unwind info.
1005  if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
1006  return 0;
1007 
1008  // Verify standard frame (lr/r7) was used.
1009  if (CFARegister != ARM::R7) {
1010  DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is "
1011  << CFARegister
1012  << " instead of r7\n");
1014  }
1015  int StackAdjust = CFARegisterOffset - 8;
1016  if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) {
1017  DEBUG_WITH_TYPE("compact-unwind",
1018  llvm::dbgs()
1019  << "LR not saved as standard frame, StackAdjust="
1020  << StackAdjust
1021  << ", CFARegisterOffset=" << CFARegisterOffset
1022  << ", lr save at offset=" << RegOffsets[14] << "\n");
1024  }
1025  if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) {
1026  DEBUG_WITH_TYPE("compact-unwind",
1027  llvm::dbgs() << "r7 not saved as standard frame\n");
1029  }
1030  uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME;
1031 
1032  // If var-args are used, there may be a stack adjust required.
1033  switch (StackAdjust) {
1034  case 0:
1035  break;
1036  case 4:
1037  CompactUnwindEncoding |= 0x00400000;
1038  break;
1039  case 8:
1040  CompactUnwindEncoding |= 0x00800000;
1041  break;
1042  case 12:
1043  CompactUnwindEncoding |= 0x00C00000;
1044  break;
1045  default:
1046  DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs()
1047  << ".cfi_def_cfa stack adjust ("
1048  << StackAdjust << ") out of range\n");
1050  }
1051 
1052  // If r6 is saved, it must be right below r7.
1053  static struct {
1054  unsigned Reg;
1055  unsigned Encoding;
1056  } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6},
1064 
1065  int CurOffset = -8 - StackAdjust;
1066  for (auto CSReg : GPRCSRegs) {
1067  auto Offset = RegOffsets.find(CSReg.Reg);
1068  if (Offset == RegOffsets.end())
1069  continue;
1070 
1071  int RegOffset = Offset->second;
1072  if (RegOffset != CurOffset - 4) {
1073  DEBUG_WITH_TYPE("compact-unwind",
1074  llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at "
1075  << RegOffset << " but only supported at "
1076  << CurOffset << "\n");
1078  }
1079  CompactUnwindEncoding |= CSReg.Encoding;
1080  CurOffset -= 4;
1081  }
1082 
1083  // If no floats saved, we are done.
1084  if (FloatRegCount == 0)
1085  return CompactUnwindEncoding;
1086 
1087  // Switch mode to include D register saving.
1088  CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK;
1089  CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D;
1090 
1091  // FIXME: supporting more than 4 saved D-registers compactly would be trivial,
1092  // but needs coordination with the linker and libunwind.
1093  if (FloatRegCount > 4) {
1094  DEBUG_WITH_TYPE("compact-unwind",
1095  llvm::dbgs() << "unsupported number of D registers saved ("
1096  << FloatRegCount << ")\n");
1098  }
1099 
1100  // Floating point registers must either be saved sequentially, or we defer to
1101  // DWARF. No gaps allowed here so check that each saved d-register is
1102  // precisely where it should be.
1103  static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
1104  for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
1105  auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
1106  if (Offset == RegOffsets.end()) {
1107  DEBUG_WITH_TYPE("compact-unwind",
1108  llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1109  << MRI.getName(FPRCSRegs[Idx])
1110  << " not saved\n");
1112  } else if (Offset->second != CurOffset - 8) {
1113  DEBUG_WITH_TYPE("compact-unwind",
1114  llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1115  << MRI.getName(FPRCSRegs[Idx])
1116  << " saved at " << Offset->second
1117  << ", expected at " << CurOffset - 8
1118  << "\n");
1120  }
1121  CurOffset -= 8;
1122  }
1123 
1124  return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
1125 }
1126 
1128  ARM::ArchKind AK = ARM::parseArch(Arch);
1129  switch (AK) {
1130  default:
1132  case ARM::ArchKind::ARMV4T:
1134  case ARM::ArchKind::ARMV5T:
1135  case ARM::ArchKind::ARMV5TE:
1136  case ARM::ArchKind::ARMV5TEJ:
1138  case ARM::ArchKind::ARMV6:
1139  case ARM::ArchKind::ARMV6K:
1141  case ARM::ArchKind::ARMV7A:
1143  case ARM::ArchKind::ARMV7S:
1145  case ARM::ArchKind::ARMV7K:
1147  case ARM::ArchKind::ARMV6M:
1149  case ARM::ArchKind::ARMV7M:
1151  case ARM::ArchKind::ARMV7EM:
1153  }
1154 }
1155 
1157  const MCSubtargetInfo &STI,
1158  const MCRegisterInfo &MRI,
1159  const MCTargetOptions &Options,
1160  bool isLittle) {
1161  const Triple &TheTriple = STI.getTargetTriple();
1162  switch (TheTriple.getObjectFormat()) {
1163  default:
1164  llvm_unreachable("unsupported object format");
1165  case Triple::MachO: {
1167  return new ARMAsmBackendDarwin(T, STI, MRI, CS);
1168  }
1169  case Triple::COFF:
1170  assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
1171  return new ARMAsmBackendWinCOFF(T, STI);
1172  case Triple::ELF:
1173  assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
1174  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
1175  return new ARMAsmBackendELF(T, STI, OSABI, isLittle);
1176  }
1177 }
1178 
1180  const MCSubtargetInfo &STI,
1181  const MCRegisterInfo &MRI,
1182  const MCTargetOptions &Options) {
1183  return createARMAsmBackend(T, STI, MRI, Options, true);
1184 }
1185 
1187  const MCSubtargetInfo &STI,
1188  const MCRegisterInfo &MRI,
1189  const MCTargetOptions &Options) {
1190  return createARMAsmBackend(T, STI, MRI, Options, false);
1191 }
1192 
1194  const MCSubtargetInfo &STI,
1195  const MCRegisterInfo &MRI,
1196  const MCTargetOptions &Options) {
1197  return createARMAsmBackend(T, STI, MRI, Options, true);
1198 }
1199 
1201  const MCSubtargetInfo &STI,
1202  const MCRegisterInfo &MRI,
1203  const MCTargetOptions &Options) {
1204  return createARMAsmBackend(T, STI, MRI, Options, false);
1205 }
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCAsmBackend * createThumbLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
#define R4(n)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
This represents an "assembler immediate".
Definition: MCValue.h:40
MCAsmBackend * createARMAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options, bool IsLittleEndian)
const char * reasonForFixupRelaxation(const MCFixup &Fixup, uint64_t Value) const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:294
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ") const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
Definition: MCInst.cpp:54
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:489
static Lanai::Fixups FixupKind(const MCExpr *Expr)
Defines the object file and target independent interfaces used by the assembler backend to write nati...
static bool isThumb(const MCSubtargetInfo &STI)
void write8(uint8_t Value)
return AArch64::GPR64RegClass contains(Reg)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:66
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
Definition: Debug.h:64
MCContext & getContext() const
Definition: MCAssembler.h:273
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch)
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:29
Reg
All possible values of the reg field in the ModR/M byte.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:165
bool mayNeedRelaxation(const MCInst &Inst) const override
Check whether the given instruction may need relaxation.
A four-byte section relative fixup.
Definition: MCFixup.h:42
A four-byte fixup.
Definition: MCFixup.h:26
Context object for machine code objects.
Definition: MCContext.h:61
A two-byte section relative fixup.
Definition: MCFixup.h:41
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:51
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:146
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:562
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:257
void write32(uint32_t Value)
uint32_t generateCompactUnwindEncoding(ArrayRef< MCCFIInstruction > Instrs) const override
Generate compact unwind encoding for the function based on the CFI instructions.
unsigned const MachineRegisterInfo * MRI
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:291
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
CompactUnwindEncodings
Compact unwind encoding values.
static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
int getOffset() const
Definition: MCDwarf.h:501
const MCSymbolRefExpr * getSymA() const
Definition: MCValue.h:48
OpType getOperation() const
Definition: MCDwarf.h:485
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:573
Should this fixup kind force a 4-byte aligned effective PC value?
uint32_t getOffset() const
Definition: MCFixup.h:95
bool isExternal() const
Definition: MCSymbol.h:391
static wasm::ValType getType(const TargetRegisterClass *RC)
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A one-byte fixup.
Definition: MCFixup.h:24
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
void write16(uint16_t Value)
unsigned getRegister() const
Definition: MCDwarf.h:488
MCAsmBackend * createThumbBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
SMLoc getLoc() const
Definition: MCFixup.h:112
static unsigned getFixupKindContainerSizeBytes(unsigned Kind)
getFixupKindContainerSizeBytes - The number of bytes of the container involved in big endian...
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
Definition: Triple.cpp:942
void setOpcode(unsigned Op)
Definition: MCInst.h:171
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
#define R6(n)
const MCSymbol & getSymbol() const
Definition: MCExpr.h:326
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override
Write an (optimal) nop sequence of Count bytes to the given output.
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, MCInst &Res) const override
Relax the instruction in the given fragment to the next wider instruction.
StringRef str()
Return a StringRef for the vector contents.
Definition: raw_ostream.h:514
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Target - Wrapper for Target specific information.
bool isThumbFunc(const MCSymbol *Func) const
Check whether a given symbol has been flagged with .thumb_func.
unsigned getRelaxedOpcode(unsigned Op) const
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:52
void handleAssemblerFlag(MCAssemblerFlag Flag) override
Handle any target-specific assembler flags. By default, do nothing.
ObjectFormatType getObjectFormat() const
getFormat - Get the object format for this triple.
Definition: Triple.h:315
MCAssemblerFlag
Definition: MCDirectives.h:48
static unsigned getRelaxedOpcode(const MCInst &Inst, bool is16BitMode)
#define I(x, y, z)
Definition: MD5.cpp:58
iterator end()
Definition: DenseMap.h:79
MCSubtargetInfo - Generic base class for all target subtargets.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
Target independent information on a fixup kind.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:181
ArchKind parseArch(StringRef Arch)
unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, uint64_t Value, bool IsResolved, MCContext &Ctx, bool IsLittleEndian) const
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:40
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
const MCExpr * getValue() const
Definition: MCFixup.h:98
void addOperand(const MCOperand &Op)
Definition: MCInst.h:184
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool isELF() const
Definition: MCSymbol.h:281
unsigned getOpcode() const
Definition: MCInst.h:172
static unsigned getFixupKindNumBytes(unsigned Kind)
getFixupKindNumBytes - The number of bytes the fixup may change.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
A two-byte fixup.
Definition: MCFixup.h:25
static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, bool IsLittleEndian)
MCFixupKind getKind() const
Definition: MCFixup.h:93
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.