LLVM  7.0.0svn
ARMAsmBackend.cpp
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1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/BinaryFormat/ELF.h"
20 #include "llvm/MC/MCAsmBackend.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCDirectives.h"
25 #include "llvm/MC/MCExpr.h"
27 #include "llvm/MC/MCObjectWriter.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCSectionELF.h"
30 #include "llvm/MC/MCSectionMachO.h"
32 #include "llvm/MC/MCValue.h"
33 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/Format.h"
39 using namespace llvm;
40 
41 namespace {
42 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
43 public:
44  ARMELFObjectWriter(uint8_t OSABI)
45  : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
46  /*HasRelocationAddend*/ false) {}
47 };
48 } // end anonymous namespace
49 
51  const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
52  // This table *must* be in the order that the fixup_* kinds are defined in
53  // ARMFixupKinds.h.
54  //
55  // Name Offset (bits) Size (bits) Flags
56  {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
57  {"fixup_t2_ldst_pcrel_12", 0, 32,
60  {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
61  {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
62  {"fixup_t2_pcrel_10", 0, 32,
65  {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
66  {"fixup_t2_pcrel_9", 0, 32,
69  {"fixup_thumb_adr_pcrel_10", 0, 8,
72  {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
73  {"fixup_t2_adr_pcrel_12", 0, 32,
76  {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
77  {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
78  {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
79  {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
80  {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
81  {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
82  {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
83  {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
84  {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
85  {"fixup_arm_thumb_blx", 0, 32,
88  {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
89  {"fixup_arm_thumb_cp", 0, 8,
92  {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
93  // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
94  // - 19.
95  {"fixup_arm_movt_hi16", 0, 20, 0},
96  {"fixup_arm_movw_lo16", 0, 20, 0},
97  {"fixup_t2_movt_hi16", 0, 20, 0},
98  {"fixup_t2_movw_lo16", 0, 20, 0},
99  {"fixup_arm_mod_imm", 0, 12, 0},
100  {"fixup_t2_so_imm", 0, 26, 0},
101  };
102  const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
103  // This table *must* be in the order that the fixup_* kinds are defined in
104  // ARMFixupKinds.h.
105  //
106  // Name Offset (bits) Size (bits) Flags
107  {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
108  {"fixup_t2_ldst_pcrel_12", 0, 32,
111  {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
112  {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
113  {"fixup_t2_pcrel_10", 0, 32,
116  {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
117  {"fixup_t2_pcrel_9", 0, 32,
120  {"fixup_thumb_adr_pcrel_10", 8, 8,
123  {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
124  {"fixup_t2_adr_pcrel_12", 0, 32,
127  {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
128  {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
129  {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
130  {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
131  {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
132  {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
133  {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
134  {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
135  {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
136  {"fixup_arm_thumb_blx", 0, 32,
139  {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
140  {"fixup_arm_thumb_cp", 8, 8,
143  {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
144  // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
145  // - 19.
146  {"fixup_arm_movt_hi16", 12, 20, 0},
147  {"fixup_arm_movw_lo16", 12, 20, 0},
148  {"fixup_t2_movt_hi16", 12, 20, 0},
149  {"fixup_t2_movw_lo16", 12, 20, 0},
150  {"fixup_arm_mod_imm", 20, 12, 0},
151  {"fixup_t2_so_imm", 26, 6, 0},
152  };
153 
154  if (Kind < FirstTargetFixupKind)
155  return MCAsmBackend::getFixupKindInfo(Kind);
156 
157  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
158  "Invalid kind!");
159  return (Endian == support::little ? InfosLE
160  : InfosBE)[Kind - FirstTargetFixupKind];
161 }
162 
164  switch (Flag) {
165  default:
166  break;
167  case MCAF_Code16:
168  setIsThumb(true);
169  break;
170  case MCAF_Code32:
171  setIsThumb(false);
172  break;
173  }
174 }
175 
177  const MCSubtargetInfo &STI) const {
178  bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2];
179  bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps];
180 
181  switch (Op) {
182  default:
183  return Op;
184  case ARM::tBcc:
185  return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
186  case ARM::tLDRpci:
187  return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
188  case ARM::tADR:
189  return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
190  case ARM::tB:
191  return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op;
192  case ARM::tCBZ:
193  return ARM::tHINT;
194  case ARM::tCBNZ:
195  return ARM::tHINT;
196  }
197 }
198 
200  const MCSubtargetInfo &STI) const {
201  if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode())
202  return true;
203  return false;
204 }
205 
207  uint64_t Value) const {
208  switch ((unsigned)Fixup.getKind()) {
210  // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
211  // low bit being an implied zero. There's an implied +4 offset for the
212  // branch, so we adjust the other way here to determine what's
213  // encodable.
214  //
215  // Relax if the value is too big for a (signed) i8.
216  int64_t Offset = int64_t(Value) - 4;
217  if (Offset > 2046 || Offset < -2048)
218  return "out of range pc-relative fixup value";
219  break;
220  }
222  // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
223  // low bit being an implied zero. There's an implied +4 offset for the
224  // branch, so we adjust the other way here to determine what's
225  // encodable.
226  //
227  // Relax if the value is too big for a (signed) i8.
228  int64_t Offset = int64_t(Value) - 4;
229  if (Offset > 254 || Offset < -256)
230  return "out of range pc-relative fixup value";
231  break;
232  }
235  // If the immediate is negative, greater than 1020, or not a multiple
236  // of four, the wide version of the instruction must be used.
237  int64_t Offset = int64_t(Value) - 4;
238  if (Offset & 3)
239  return "misaligned pc-relative fixup value";
240  else if (Offset > 1020 || Offset < 0)
241  return "out of range pc-relative fixup value";
242  break;
243  }
245  // If we have a Thumb CBZ or CBNZ instruction and its target is the next
246  // instruction it is actually out of range for the instruction.
247  // It will be changed to a NOP.
248  int64_t Offset = (Value & ~1);
249  if (Offset == 2)
250  return "will be converted to nop";
251  break;
252  }
253  default:
254  llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!");
255  }
256  return nullptr;
257 }
258 
260  const MCRelaxableFragment *DF,
261  const MCAsmLayout &Layout) const {
262  return reasonForFixupRelaxation(Fixup, Value);
263 }
264 
266  const MCSubtargetInfo &STI,
267  MCInst &Res) const {
268  unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI);
269 
270  // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
271  if (RelaxedOp == Inst.getOpcode()) {
272  SmallString<256> Tmp;
273  raw_svector_ostream OS(Tmp);
274  Inst.dump_pretty(OS);
275  OS << "\n";
276  report_fatal_error("unexpected instruction to relax: " + OS.str());
277  }
278 
279  // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
280  // have to change the operands too.
281  if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
282  RelaxedOp == ARM::tHINT) {
283  Res.setOpcode(RelaxedOp);
287  return;
288  }
289 
290  // The rest of instructions we're relaxing have the same operands.
291  // We just need to update to the proper opcode.
292  Res = Inst;
293  Res.setOpcode(RelaxedOp);
294 }
295 
296 bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
297  const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
298  const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
299  const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
300  const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
301  if (isThumb()) {
302  const uint16_t nopEncoding =
303  hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
304  uint64_t NumNops = Count / 2;
305  for (uint64_t i = 0; i != NumNops; ++i)
306  support::endian::write(OS, nopEncoding, Endian);
307  if (Count & 1)
308  OS << '\0';
309  return true;
310  }
311  // ARM mode
312  const uint32_t nopEncoding =
313  hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
314  uint64_t NumNops = Count / 4;
315  for (uint64_t i = 0; i != NumNops; ++i)
316  support::endian::write(OS, nopEncoding, Endian);
317  // FIXME: should this function return false when unable to write exactly
318  // 'Count' bytes with NOP encodings?
319  switch (Count % 4) {
320  default:
321  break; // No leftover bytes to write
322  case 1:
323  OS << '\0';
324  break;
325  case 2:
326  OS.write("\0\0", 2);
327  break;
328  case 3:
329  OS.write("\0\0\xa0", 3);
330  break;
331  }
332 
333  return true;
334 }
335 
336 static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
337  if (IsLittleEndian) {
338  // Note that the halfwords are stored high first and low second in thumb;
339  // so we need to swap the fixup value here to map properly.
340  uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
341  Swapped |= (Value & 0x0000FFFF) << 16;
342  return Swapped;
343  } else
344  return Value;
345 }
346 
347 static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
348  bool IsLittleEndian) {
349  uint32_t Value;
350 
351  if (IsLittleEndian) {
352  Value = (SecondHalf & 0xFFFF) << 16;
353  Value |= (FirstHalf & 0xFFFF);
354  } else {
355  Value = (SecondHalf & 0xFFFF);
356  Value |= (FirstHalf & 0xFFFF) << 16;
357  }
358 
359  return Value;
360 }
361 
363  const MCFixup &Fixup,
364  const MCValue &Target, uint64_t Value,
365  bool IsResolved, MCContext &Ctx,
366  const MCSubtargetInfo* STI) const {
367  unsigned Kind = Fixup.getKind();
368 
369  // MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
370  // and .word relocations they put the Thumb bit into the addend if possible.
371  // Other relocation types don't want this bit though (branches couldn't encode
372  // it if it *was* present, and no other relocations exist) and it can
373  // interfere with checking valid expressions.
374  if (const MCSymbolRefExpr *A = Target.getSymA()) {
375  if (A->hasSubsectionsViaSymbols() && Asm.isThumbFunc(&A->getSymbol()) &&
376  (Kind == FK_Data_4 || Kind == ARM::fixup_arm_movw_lo16 ||
378  Kind == ARM::fixup_t2_movt_hi16))
379  Value |= 1;
380  }
381 
382  switch (Kind) {
383  default:
384  Ctx.reportError(Fixup.getLoc(), "bad relocation fixup type");
385  return 0;
386  case FK_Data_1:
387  case FK_Data_2:
388  case FK_Data_4:
389  return Value;
390  case FK_SecRel_2:
391  return Value;
392  case FK_SecRel_4:
393  return Value;
395  assert(STI != nullptr);
396  if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
397  Value >>= 16;
400  unsigned Hi4 = (Value & 0xF000) >> 12;
401  unsigned Lo12 = Value & 0x0FFF;
402  // inst{19-16} = Hi4;
403  // inst{11-0} = Lo12;
404  Value = (Hi4 << 16) | (Lo12);
405  return Value;
406  }
408  assert(STI != nullptr);
409  if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
410  Value >>= 16;
413  unsigned Hi4 = (Value & 0xF000) >> 12;
414  unsigned i = (Value & 0x800) >> 11;
415  unsigned Mid3 = (Value & 0x700) >> 8;
416  unsigned Lo8 = Value & 0x0FF;
417  // inst{19-16} = Hi4;
418  // inst{26} = i;
419  // inst{14-12} = Mid3;
420  // inst{7-0} = Lo8;
421  Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
422  return swapHalfWords(Value, Endian == support::little);
423  }
425  // ARM PC-relative values are offset by 8.
426  Value -= 4;
429  // Offset by 4, adjusted by two due to the half-word ordering of thumb.
430  Value -= 4;
431  bool isAdd = true;
432  if ((int64_t)Value < 0) {
433  Value = -Value;
434  isAdd = false;
435  }
436  if (Value >= 4096) {
437  Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
438  return 0;
439  }
440  Value |= isAdd << 23;
441 
442  // Same addressing mode as fixup_arm_pcrel_10,
443  // but with 16-bit halfwords swapped.
444  if (Kind == ARM::fixup_t2_ldst_pcrel_12)
445  return swapHalfWords(Value, Endian == support::little);
446 
447  return Value;
448  }
450  // ARM PC-relative values are offset by 8.
451  Value -= 8;
452  unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
453  if ((int64_t)Value < 0) {
454  Value = -Value;
455  opc = 2; // 0b0010
456  }
457  if (ARM_AM::getSOImmVal(Value) == -1) {
458  Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
459  return 0;
460  }
461  // Encode the immediate and shift the opcode into place.
462  return ARM_AM::getSOImmVal(Value) | (opc << 21);
463  }
464 
466  Value -= 4;
467  unsigned opc = 0;
468  if ((int64_t)Value < 0) {
469  Value = -Value;
470  opc = 5;
471  }
472 
473  uint32_t out = (opc << 21);
474  out |= (Value & 0x800) << 15;
475  out |= (Value & 0x700) << 4;
476  out |= (Value & 0x0FF);
477 
478  return swapHalfWords(out, Endian == support::little);
479  }
480 
485  case ARM::fixup_arm_blx:
486  // These values don't encode the low two bits since they're always zero.
487  // Offset by 8 just as above.
488  if (const MCSymbolRefExpr *SRE =
489  dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
490  if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
491  return 0;
492  return 0xffffff & ((Value - 8) >> 2);
494  Value = Value - 4;
495  if (!isInt<25>(Value)) {
496  Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
497  return 0;
498  }
499 
500  Value >>= 1; // Low bit is not encoded.
501 
502  uint32_t out = 0;
503  bool I = Value & 0x800000;
504  bool J1 = Value & 0x400000;
505  bool J2 = Value & 0x200000;
506  J1 ^= I;
507  J2 ^= I;
508 
509  out |= I << 26; // S bit
510  out |= !J1 << 13; // J1 bit
511  out |= !J2 << 11; // J2 bit
512  out |= (Value & 0x1FF800) << 5; // imm6 field
513  out |= (Value & 0x0007FF); // imm11 field
514 
515  return swapHalfWords(out, Endian == support::little);
516  }
518  Value = Value - 4;
519  if (!isInt<21>(Value)) {
520  Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
521  return 0;
522  }
523 
524  Value >>= 1; // Low bit is not encoded.
525 
526  uint64_t out = 0;
527  out |= (Value & 0x80000) << 7; // S bit
528  out |= (Value & 0x40000) >> 7; // J2 bit
529  out |= (Value & 0x20000) >> 4; // J1 bit
530  out |= (Value & 0x1F800) << 5; // imm6 field
531  out |= (Value & 0x007FF); // imm11 field
532 
533  return swapHalfWords(out, Endian == support::little);
534  }
536  if (!isInt<25>(Value - 4) ||
537  (!STI->getFeatureBits()[ARM::FeatureThumb2] &&
538  !STI->getFeatureBits()[ARM::HasV8MBaselineOps] &&
539  !STI->getFeatureBits()[ARM::HasV6MOps] &&
540  !isInt<23>(Value - 4))) {
541  Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
542  return 0;
543  }
544 
545  // The value doesn't encode the low bit (always zero) and is offset by
546  // four. The 32-bit immediate value is encoded as
547  // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
548  // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
549  // The value is encoded into disjoint bit positions in the destination
550  // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
551  // J = either J1 or J2 bit
552  //
553  // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
554  //
555  // Note that the halfwords are stored high first, low second; so we need
556  // to transpose the fixup value here to map properly.
557  uint32_t offset = (Value - 4) >> 1;
558  uint32_t signBit = (offset & 0x800000) >> 23;
559  uint32_t I1Bit = (offset & 0x400000) >> 22;
560  uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
561  uint32_t I2Bit = (offset & 0x200000) >> 21;
562  uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
563  uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
564  uint32_t imm11Bits = (offset & 0x000007FF);
565 
566  uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
567  uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
568  (uint16_t)imm11Bits);
569  return joinHalfWords(FirstHalf, SecondHalf, Endian == support::little);
570  }
572  // The value doesn't encode the low two bits (always zero) and is offset by
573  // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
574  // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
575  // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
576  // The value is encoded into disjoint bit positions in the destination
577  // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
578  // J = either J1 or J2 bit, 0 = zero.
579  //
580  // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
581  //
582  // Note that the halfwords are stored high first, low second; so we need
583  // to transpose the fixup value here to map properly.
584  if (Value % 4 != 0) {
585  Ctx.reportError(Fixup.getLoc(), "misaligned ARM call destination");
586  return 0;
587  }
588 
589  uint32_t offset = (Value - 4) >> 2;
590  if (const MCSymbolRefExpr *SRE =
591  dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
592  if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
593  offset = 0;
594  uint32_t signBit = (offset & 0x400000) >> 22;
595  uint32_t I1Bit = (offset & 0x200000) >> 21;
596  uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
597  uint32_t I2Bit = (offset & 0x100000) >> 20;
598  uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
599  uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
600  uint32_t imm10LBits = (offset & 0x3FF);
601 
602  uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
603  uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
604  ((uint16_t)imm10LBits) << 1);
605  return joinHalfWords(FirstHalf, SecondHalf, Endian == support::little);
606  }
609  // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we
610  // could have an error on our hands.
611  assert(STI != nullptr);
612  if (!STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) {
613  const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
614  if (FixupDiagnostic) {
615  Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
616  return 0;
617  }
618  }
619  // Offset by 4, and don't encode the low two bits.
620  return ((Value - 4) >> 2) & 0xff;
622  // CB instructions can only branch to offsets in [4, 126] in multiples of 2
623  // so ensure that the raw value LSB is zero and it lies in [2, 130].
624  // An offset of 2 will be relaxed to a NOP.
625  if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) {
626  Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
627  return 0;
628  }
629  // Offset by 4 and don't encode the lower bit, which is always 0.
630  // FIXME: diagnose if no Thumb2
631  uint32_t Binary = (Value - 4) >> 1;
632  return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
633  }
635  // Offset by 4 and don't encode the lower bit, which is always 0.
636  assert(STI != nullptr);
637  if (!STI->getFeatureBits()[ARM::FeatureThumb2] &&
638  !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) {
639  const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
640  if (FixupDiagnostic) {
641  Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
642  return 0;
643  }
644  }
645  return ((Value - 4) >> 1) & 0x7ff;
647  // Offset by 4 and don't encode the lower bit, which is always 0.
648  assert(STI != nullptr);
649  if (!STI->getFeatureBits()[ARM::FeatureThumb2]) {
650  const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
651  if (FixupDiagnostic) {
652  Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
653  return 0;
654  }
655  }
656  return ((Value - 4) >> 1) & 0xff;
658  Value = Value - 8; // ARM fixups offset by an additional word and don't
659  // need to adjust for the half-word ordering.
660  bool isAdd = true;
661  if ((int64_t)Value < 0) {
662  Value = -Value;
663  isAdd = false;
664  }
665  // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
666  if (Value >= 256) {
667  Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
668  return 0;
669  }
670  Value = (Value & 0xf) | ((Value & 0xf0) << 4);
671  return Value | (isAdd << 23);
672  }
674  Value = Value - 4; // ARM fixups offset by an additional word and don't
675  // need to adjust for the half-word ordering.
677  case ARM::fixup_t2_pcrel_10: {
678  // Offset by 4, adjusted by two due to the half-word ordering of thumb.
679  Value = Value - 4;
680  bool isAdd = true;
681  if ((int64_t)Value < 0) {
682  Value = -Value;
683  isAdd = false;
684  }
685  // These values don't encode the low two bits since they're always zero.
686  Value >>= 2;
687  if (Value >= 256) {
688  Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
689  return 0;
690  }
691  Value |= isAdd << 23;
692 
693  // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
694  // swapped.
695  if (Kind == ARM::fixup_t2_pcrel_10)
696  return swapHalfWords(Value, Endian == support::little);
697 
698  return Value;
699  }
701  Value = Value - 4; // ARM fixups offset by an additional word and don't
702  // need to adjust for the half-word ordering.
704  case ARM::fixup_t2_pcrel_9: {
705  // Offset by 4, adjusted by two due to the half-word ordering of thumb.
706  Value = Value - 4;
707  bool isAdd = true;
708  if ((int64_t)Value < 0) {
709  Value = -Value;
710  isAdd = false;
711  }
712  // These values don't encode the low bit since it's always zero.
713  if (Value & 1) {
714  Ctx.reportError(Fixup.getLoc(), "invalid value for this fixup");
715  return 0;
716  }
717  Value >>= 1;
718  if (Value >= 256) {
719  Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
720  return 0;
721  }
722  Value |= isAdd << 23;
723 
724  // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
725  // swapped.
726  if (Kind == ARM::fixup_t2_pcrel_9)
727  return swapHalfWords(Value, Endian == support::little);
728 
729  return Value;
730  }
732  Value = ARM_AM::getSOImmVal(Value);
733  if (Value >> 12) {
734  Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
735  return 0;
736  }
737  return Value;
738  case ARM::fixup_t2_so_imm: {
739  Value = ARM_AM::getT2SOImmVal(Value);
740  if ((int64_t)Value < 0) {
741  Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
742  return 0;
743  }
744  // Value will contain a 12-bit value broken up into a 4-bit shift in bits
745  // 11:8 and the 8-bit immediate in 0:7. The instruction has the immediate
746  // in 0:7. The 4-bit shift is split up into i:imm3 where i is placed at bit
747  // 10 of the upper half-word and imm3 is placed at 14:12 of the lower
748  // half-word.
749  uint64_t EncValue = 0;
750  EncValue |= (Value & 0x800) << 15;
751  EncValue |= (Value & 0x700) << 4;
752  EncValue |= (Value & 0xff);
753  return swapHalfWords(EncValue, Endian == support::little);
754  }
755  }
756 }
757 
759  const MCFixup &Fixup,
760  const MCValue &Target) {
761  const MCSymbolRefExpr *A = Target.getSymA();
762  const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;
763  const unsigned FixupKind = Fixup.getKind() ;
764  if ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) {
765  assert(Sym && "How did we resolve this?");
766 
767  // If the symbol is external the linker will handle it.
768  // FIXME: Should we handle it as an optimization?
769 
770  // If the symbol is out of range, produce a relocation and hope the
771  // linker can handle it. GNU AS produces an error in this case.
772  if (Sym->isExternal())
773  return true;
774  }
775  // Create relocations for unconditional branches to function symbols with
776  // different execution mode in ELF binaries.
777  if (Sym && Sym->isELF()) {
778  unsigned Type = cast<MCSymbolELF>(Sym)->getType();
779  if ((Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC)) {
780  if (Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_uncondbranch))
781  return true;
782  if (!Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_thumb_br ||
783  FixupKind == ARM::fixup_arm_thumb_bl ||
784  FixupKind == ARM::fixup_t2_condbranch ||
785  FixupKind == ARM::fixup_t2_uncondbranch))
786  return true;
787  }
788  }
789  // We must always generate a relocation for BL/BLX instructions if we have
790  // a symbol to reference, as the linker relies on knowing the destination
791  // symbol's thumb-ness to get interworking right.
792  if (A && (FixupKind == ARM::fixup_arm_thumb_blx ||
793  FixupKind == ARM::fixup_arm_blx ||
794  FixupKind == ARM::fixup_arm_uncondbl ||
795  FixupKind == ARM::fixup_arm_condbl))
796  return true;
797  return false;
798 }
799 
800 /// getFixupKindNumBytes - The number of bytes the fixup may change.
801 static unsigned getFixupKindNumBytes(unsigned Kind) {
802  switch (Kind) {
803  default:
804  llvm_unreachable("Unknown fixup kind!");
805 
806  case FK_Data_1:
810  return 1;
811 
812  case FK_Data_2:
816  return 2;
817 
825  case ARM::fixup_arm_blx:
828  return 3;
829 
830  case FK_Data_4:
844  return 4;
845 
846  case FK_SecRel_2:
847  return 2;
848  case FK_SecRel_4:
849  return 4;
850  }
851 }
852 
853 /// getFixupKindContainerSizeBytes - The number of bytes of the
854 /// container involved in big endian.
855 static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
856  switch (Kind) {
857  default:
858  llvm_unreachable("Unknown fixup kind!");
859 
860  case FK_Data_1:
861  return 1;
862  case FK_Data_2:
863  return 2;
864  case FK_Data_4:
865  return 4;
866 
872  // Instruction size is 2 bytes.
873  return 2;
874 
881  case ARM::fixup_arm_blx:
897  // Instruction size is 4 bytes.
898  return 4;
899  }
900 }
901 
903  const MCValue &Target,
904  MutableArrayRef<char> Data, uint64_t Value,
905  bool IsResolved,
906  const MCSubtargetInfo* STI) const {
907  unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
908  MCContext &Ctx = Asm.getContext();
909  Value = adjustFixupValue(Asm, Fixup, Target, Value, IsResolved, Ctx, STI);
910  if (!Value)
911  return; // Doesn't change encoding.
912 
913  unsigned Offset = Fixup.getOffset();
914  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
915 
916  // Used to point to big endian bytes.
917  unsigned FullSizeBytes;
918  if (Endian == support::big) {
919  FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind());
920  assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!");
921  assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
922  }
923 
924  // For each byte of the fragment that the fixup touches, mask in the bits from
925  // the fixup value. The Value has been "split up" into the appropriate
926  // bitfields above.
927  for (unsigned i = 0; i != NumBytes; ++i) {
928  unsigned Idx = Endian == support::little ? i : (FullSizeBytes - 1 - i);
929  Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
930  }
931 }
932 
933 namespace CU {
934 
935 /// Compact unwind encoding values.
937  UNWIND_ARM_MODE_MASK = 0x0F000000,
938  UNWIND_ARM_MODE_FRAME = 0x01000000,
940  UNWIND_ARM_MODE_DWARF = 0x04000000,
941 
943 
947 
953 
955 
957 };
958 
959 } // end CU namespace
960 
961 /// Generate compact unwind encoding for the function based on the CFI
962 /// instructions. If the CFI instructions describe a frame that cannot be
963 /// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which
964 /// tells the runtime to fallback and unwind using dwarf.
966  ArrayRef<MCCFIInstruction> Instrs) const {
967  DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n");
968  // Only armv7k uses CFI based unwinding.
969  if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K)
970  return 0;
971  // No .cfi directives means no frame.
972  if (Instrs.empty())
973  return 0;
974  // Start off assuming CFA is at SP+0.
975  int CFARegister = ARM::SP;
976  int CFARegisterOffset = 0;
977  // Mark savable registers as initially unsaved
978  DenseMap<unsigned, int> RegOffsets;
979  int FloatRegCount = 0;
980  // Process each .cfi directive and build up compact unwind info.
981  for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
982  int Reg;
983  const MCCFIInstruction &Inst = Instrs[i];
984  switch (Inst.getOperation()) {
985  case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
986  CFARegisterOffset = -Inst.getOffset();
987  CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true);
988  break;
989  case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset
990  CFARegisterOffset = -Inst.getOffset();
991  break;
992  case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register
993  CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true);
994  break;
995  case MCCFIInstruction::OpOffset: // DW_CFA_offset
996  Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
997  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
998  RegOffsets[Reg] = Inst.getOffset();
999  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
1000  RegOffsets[Reg] = Inst.getOffset();
1001  ++FloatRegCount;
1002  } else {
1003  DEBUG_WITH_TYPE("compact-unwind",
1004  llvm::dbgs() << ".cfi_offset on unknown register="
1005  << Inst.getRegister() << "\n");
1007  }
1008  break;
1009  case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc
1010  // Ignore
1011  break;
1012  default:
1013  // Directive not convertable to compact unwind, bail out.
1014  DEBUG_WITH_TYPE("compact-unwind",
1015  llvm::dbgs()
1016  << "CFI directive not compatiable with comact "
1017  "unwind encoding, opcode=" << Inst.getOperation()
1018  << "\n");
1020  break;
1021  }
1022  }
1023 
1024  // If no frame set up, return no unwind info.
1025  if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
1026  return 0;
1027 
1028  // Verify standard frame (lr/r7) was used.
1029  if (CFARegister != ARM::R7) {
1030  DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is "
1031  << CFARegister
1032  << " instead of r7\n");
1034  }
1035  int StackAdjust = CFARegisterOffset - 8;
1036  if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) {
1037  DEBUG_WITH_TYPE("compact-unwind",
1038  llvm::dbgs()
1039  << "LR not saved as standard frame, StackAdjust="
1040  << StackAdjust
1041  << ", CFARegisterOffset=" << CFARegisterOffset
1042  << ", lr save at offset=" << RegOffsets[14] << "\n");
1044  }
1045  if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) {
1046  DEBUG_WITH_TYPE("compact-unwind",
1047  llvm::dbgs() << "r7 not saved as standard frame\n");
1049  }
1050  uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME;
1051 
1052  // If var-args are used, there may be a stack adjust required.
1053  switch (StackAdjust) {
1054  case 0:
1055  break;
1056  case 4:
1057  CompactUnwindEncoding |= 0x00400000;
1058  break;
1059  case 8:
1060  CompactUnwindEncoding |= 0x00800000;
1061  break;
1062  case 12:
1063  CompactUnwindEncoding |= 0x00C00000;
1064  break;
1065  default:
1066  DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs()
1067  << ".cfi_def_cfa stack adjust ("
1068  << StackAdjust << ") out of range\n");
1070  }
1071 
1072  // If r6 is saved, it must be right below r7.
1073  static struct {
1074  unsigned Reg;
1075  unsigned Encoding;
1076  } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6},
1084 
1085  int CurOffset = -8 - StackAdjust;
1086  for (auto CSReg : GPRCSRegs) {
1087  auto Offset = RegOffsets.find(CSReg.Reg);
1088  if (Offset == RegOffsets.end())
1089  continue;
1090 
1091  int RegOffset = Offset->second;
1092  if (RegOffset != CurOffset - 4) {
1093  DEBUG_WITH_TYPE("compact-unwind",
1094  llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at "
1095  << RegOffset << " but only supported at "
1096  << CurOffset << "\n");
1098  }
1099  CompactUnwindEncoding |= CSReg.Encoding;
1100  CurOffset -= 4;
1101  }
1102 
1103  // If no floats saved, we are done.
1104  if (FloatRegCount == 0)
1105  return CompactUnwindEncoding;
1106 
1107  // Switch mode to include D register saving.
1108  CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK;
1109  CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D;
1110 
1111  // FIXME: supporting more than 4 saved D-registers compactly would be trivial,
1112  // but needs coordination with the linker and libunwind.
1113  if (FloatRegCount > 4) {
1114  DEBUG_WITH_TYPE("compact-unwind",
1115  llvm::dbgs() << "unsupported number of D registers saved ("
1116  << FloatRegCount << ")\n");
1118  }
1119 
1120  // Floating point registers must either be saved sequentially, or we defer to
1121  // DWARF. No gaps allowed here so check that each saved d-register is
1122  // precisely where it should be.
1123  static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
1124  for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
1125  auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
1126  if (Offset == RegOffsets.end()) {
1127  DEBUG_WITH_TYPE("compact-unwind",
1128  llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1129  << MRI.getName(FPRCSRegs[Idx])
1130  << " not saved\n");
1132  } else if (Offset->second != CurOffset - 8) {
1133  DEBUG_WITH_TYPE("compact-unwind",
1134  llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1135  << MRI.getName(FPRCSRegs[Idx])
1136  << " saved at " << Offset->second
1137  << ", expected at " << CurOffset - 8
1138  << "\n");
1140  }
1141  CurOffset -= 8;
1142  }
1143 
1144  return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
1145 }
1146 
1148  ARM::ArchKind AK = ARM::parseArch(Arch);
1149  switch (AK) {
1150  default:
1152  case ARM::ArchKind::ARMV4T:
1154  case ARM::ArchKind::ARMV5T:
1155  case ARM::ArchKind::ARMV5TE:
1156  case ARM::ArchKind::ARMV5TEJ:
1158  case ARM::ArchKind::ARMV6:
1159  case ARM::ArchKind::ARMV6K:
1161  case ARM::ArchKind::ARMV7A:
1163  case ARM::ArchKind::ARMV7S:
1165  case ARM::ArchKind::ARMV7K:
1167  case ARM::ArchKind::ARMV6M:
1169  case ARM::ArchKind::ARMV7M:
1171  case ARM::ArchKind::ARMV7EM:
1173  }
1174 }
1175 
1177  const MCSubtargetInfo &STI,
1178  const MCRegisterInfo &MRI,
1179  const MCTargetOptions &Options,
1180  support::endianness Endian) {
1181  const Triple &TheTriple = STI.getTargetTriple();
1182  switch (TheTriple.getObjectFormat()) {
1183  default:
1184  llvm_unreachable("unsupported object format");
1185  case Triple::MachO: {
1187  return new ARMAsmBackendDarwin(T, STI, MRI, CS);
1188  }
1189  case Triple::COFF:
1190  assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
1191  return new ARMAsmBackendWinCOFF(T, STI);
1192  case Triple::ELF:
1193  assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
1194  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
1195  return new ARMAsmBackendELF(T, STI, OSABI, Endian);
1196  }
1197 }
1198 
1200  const MCSubtargetInfo &STI,
1201  const MCRegisterInfo &MRI,
1202  const MCTargetOptions &Options) {
1203  return createARMAsmBackend(T, STI, MRI, Options, support::little);
1204 }
1205 
1207  const MCSubtargetInfo &STI,
1208  const MCRegisterInfo &MRI,
1209  const MCTargetOptions &Options) {
1210  return createARMAsmBackend(T, STI, MRI, Options, support::big);
1211 }
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const
#define R4(n)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
This represents an "assembler immediate".
Definition: MCValue.h:40
const char * reasonForFixupRelaxation(const MCFixup &Fixup, uint64_t Value) const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:586
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:292
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ") const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
Definition: MCInst.cpp:73
unsigned Reg
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:504
static Lanai::Fixups FixupKind(const MCExpr *Expr)
static bool isThumb(const MCSubtargetInfo &STI)
return AArch64::GPR64RegClass contains(Reg)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:74
const Triple & getTargetTriple() const
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
Definition: Debug.h:65
MCContext & getContext() const
Definition: MCAssembler.h:278
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
const FeatureBitset & getFeatureBits() const
static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch)
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:29
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:166
A four-byte section relative fixup.
Definition: MCFixup.h:42
A four-byte fixup.
Definition: MCFixup.h:26
Context object for machine code objects.
Definition: MCContext.h:63
A two-byte section relative fixup.
Definition: MCFixup.h:41
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:51
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
static MCAsmBackend * createARMAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options, support::endianness Endian)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:118
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:146
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:100
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:560
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
uint32_t generateCompactUnwindEncoding(ArrayRef< MCCFIInstruction > Instrs) const override
Generate compact unwind encoding for the function based on the CFI instructions.
unsigned const MachineRegisterInfo * MRI
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:291
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
CompactUnwindEncodings
Compact unwind encoding values.
static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:149
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
int getOffset() const
Definition: MCDwarf.h:561
const MCSymbolRefExpr * getSymA() const
Definition: MCValue.h:48
OpType getOperation() const
Definition: MCDwarf.h:545
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:590
Should this fixup kind force a 4-byte aligned effective PC value?
uint32_t getOffset() const
Definition: MCFixup.h:125
unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, uint64_t Value, bool IsResolved, MCContext &Ctx, const MCSubtargetInfo *STI) const
bool writeNopData(raw_ostream &OS, uint64_t Count) const override
Write an (optimal) nop sequence of Count bytes to the given output.
bool isExternal() const
Definition: MCSymbol.h:393
static wasm::ValType getType(const TargetRegisterClass *RC)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A one-byte fixup.
Definition: MCFixup.h:24
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
raw_ostream & write(unsigned char C)
unsigned getRegister() const
Definition: MCDwarf.h:548
SMLoc getLoc() const
Definition: MCFixup.h:166
static unsigned getFixupKindContainerSizeBytes(unsigned Kind)
getFixupKindContainerSizeBytes - The number of bytes of the container involved in big endian...
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
Definition: Triple.cpp:938
void setOpcode(unsigned Op)
Definition: MCInst.h:173
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
#define R6(n)
const MCSymbol & getSymbol() const
Definition: MCExpr.h:334
void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, MCInst &Res) const override
Relax the instruction in the given fragment to the next wider instruction.
StringRef str()
Return a StringRef for the vector contents.
Definition: raw_ostream.h:529
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
Target - Wrapper for Target specific information.
bool isThumbFunc(const MCSymbol *Func) const
Check whether a given symbol has been flagged with .thumb_func.
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:52
void handleAssemblerFlag(MCAssemblerFlag Flag) override
Handle any target-specific assembler flags. By default, do nothing.
ObjectFormatType getObjectFormat() const
getFormat - Get the object format for this triple.
Definition: Triple.h:313
MCAssemblerFlag
Definition: MCDirectives.h:48
static unsigned getRelaxedOpcode(const MCInst &Inst, bool is16BitMode)
#define I(x, y, z)
Definition: MD5.cpp:58
iterator end()
Definition: DenseMap.h:79
Generic base class for all target subtargets.
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
Target independent information on a fixup kind.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:181
ArchKind parseArch(StringRef Arch)
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
LLVM Value Representation.
Definition: Value.h:73
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
const MCExpr * getValue() const
Definition: MCFixup.h:128
void addOperand(const MCOperand &Op)
Definition: MCInst.h:186
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool isELF() const
Definition: MCSymbol.h:281
unsigned getOpcode() const
Definition: MCInst.h:174
static unsigned getFixupKindNumBytes(unsigned Kind)
getFixupKindNumBytes - The number of bytes the fixup may change.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
A two-byte fixup.
Definition: MCFixup.h:25
static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, bool IsLittleEndian)
MCFixupKind getKind() const
Definition: MCFixup.h:123
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:144
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.