LLVM  6.0.0svn
GCNRegPressure.h
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1 //===- GCNRegPressure.h -----------------------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
11 #define LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
12 
13 #include "AMDGPUSubtarget.h"
14 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/MC/LaneBitmask.h"
20 #include "llvm/Support/Debug.h"
21 #include <algorithm>
22 #include <limits>
23 
24 namespace llvm {
25 
26 class MachineRegisterInfo;
27 class raw_ostream;
28 
30  enum RegKind {
36  };
37 
39  clear();
40  }
41 
42  bool empty() const { return getSGPRNum() == 0 && getVGPRNum() == 0; }
43 
44  void clear() { std::fill(&Value[0], &Value[TOTAL_KINDS], 0); }
45 
46  unsigned getSGPRNum() const { return Value[SGPR32]; }
47  unsigned getVGPRNum() const { return Value[VGPR32]; }
48 
49  unsigned getVGPRTuplesWeight() const { return Value[VGPR_TUPLE]; }
50  unsigned getSGPRTuplesWeight() const { return Value[SGPR_TUPLE]; }
51 
52  unsigned getOccupancy(const SISubtarget &ST) const {
53  return std::min(ST.getOccupancyWithNumSGPRs(getSGPRNum()),
55  }
56 
57  void inc(unsigned Reg,
58  LaneBitmask PrevMask,
59  LaneBitmask NewMask,
60  const MachineRegisterInfo &MRI);
61 
62  bool higherOccupancy(const SISubtarget &ST, const GCNRegPressure& O) const {
63  return getOccupancy(ST) > O.getOccupancy(ST);
64  }
65 
66  bool less(const SISubtarget &ST, const GCNRegPressure& O,
67  unsigned MaxOccupancy = std::numeric_limits<unsigned>::max()) const;
68 
69  bool operator==(const GCNRegPressure &O) const {
70  return std::equal(&Value[0], &Value[TOTAL_KINDS], O.Value);
71  }
72 
73  bool operator!=(const GCNRegPressure &O) const {
74  return !(*this == O);
75  }
76 
77  void print(raw_ostream &OS, const SISubtarget *ST = nullptr) const;
78  void dump() const { print(dbgs()); }
79 
80 private:
81  unsigned Value[TOTAL_KINDS];
82 
83  static unsigned getRegKind(unsigned Reg, const MachineRegisterInfo &MRI);
84 
85  friend GCNRegPressure max(const GCNRegPressure &P1,
86  const GCNRegPressure &P2);
87 };
88 
89 inline GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2) {
90  GCNRegPressure Res;
91  for (unsigned I = 0; I < GCNRegPressure::TOTAL_KINDS; ++I)
92  Res.Value[I] = std::max(P1.Value[I], P2.Value[I]);
93  return Res;
94 }
95 
96 class GCNRPTracker {
97 public:
99 
100 protected:
104  const MachineInstr *LastTrackedMI = nullptr;
105  mutable const MachineRegisterInfo *MRI = nullptr;
106 
107  GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {}
108 
109 public:
110  // live regs for the current state
111  const decltype(LiveRegs) &getLiveRegs() const { return LiveRegs; }
112  const MachineInstr *getLastTrackedMI() const { return LastTrackedMI; }
113 
114  void clearMaxPressure() { MaxPressure.clear(); }
115 
116  // returns MaxPressure, resetting it
117  decltype(MaxPressure) moveMaxPressure() {
118  auto Res = MaxPressure;
119  MaxPressure.clear();
120  return Res;
121  }
122 
123  decltype(LiveRegs) moveLiveRegs() {
124  return std::move(LiveRegs);
125  }
126 
127  static void printLiveRegs(raw_ostream &OS, const LiveRegSet& LiveRegs,
128  const MachineRegisterInfo &MRI);
129 };
130 
132 public:
134 
135  // reset tracker to the point just below MI
136  // filling live regs upon this point using LIS
137  void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
138 
139  // move to the state just above the MI
140  void recede(const MachineInstr &MI);
141 
142  // checks whether the tracker's state after receding MI corresponds
143  // to reported by LIS
144  bool isValid() const;
145 };
146 
148  // Last position of reset or advanceBeforeNext
150 
152 
153 public:
155 
156  const MachineBasicBlock::const_iterator getNext() const { return NextMI; }
157 
158  // Reset tracker to the point before the MI
159  // filling live regs upon this point using LIS.
160  // Returns false if block is empty except debug values.
161  bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
162 
163  // Move to the state right before the next MI. Returns false if reached
164  // end of the block.
165  bool advanceBeforeNext();
166 
167  // Move to the state at the MI, advanceBeforeNext has to be called first.
168  void advanceToNext();
169 
170  // Move to the state at the next MI. Returns false if reached end of block.
171  bool advance();
172 
173  // Advance instructions until before End.
175 
176  // Reset to Begin and advance to End.
177  bool advance(MachineBasicBlock::const_iterator Begin,
179  const LiveRegSet *LiveRegsCopy = nullptr);
180 };
181 
183  SlotIndex SI,
184  const LiveIntervals &LIS,
185  const MachineRegisterInfo &MRI);
186 
188  const LiveIntervals &LIS,
189  const MachineRegisterInfo &MRI);
190 
192  const LiveIntervals &LIS) {
193  return getLiveRegs(LIS.getInstructionIndex(MI).getDeadSlot(), LIS,
194  MI.getParent()->getParent()->getRegInfo());
195 }
196 
198  const LiveIntervals &LIS) {
199  return getLiveRegs(LIS.getInstructionIndex(MI).getBaseIndex(), LIS,
200  MI.getParent()->getParent()->getRegInfo());
201 }
202 
203 template <typename Range>
205  Range &&LiveRegs) {
206  GCNRegPressure Res;
207  for (const auto &RM : LiveRegs)
208  Res.inc(RM.first, LaneBitmask::getNone(), RM.second, MRI);
209  return Res;
210 }
211 
212 void printLivesAt(SlotIndex SI,
213  const LiveIntervals &LIS,
214  const MachineRegisterInfo &MRI);
215 
216 } // end namespace llvm
217 
218 #endif // LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
A common definition of LaneBitmask for use in TableGen and CodeGen.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool higherOccupancy(const SISubtarget &ST, const GCNRegPressure &O) const
AMDGPU specific subclass of TargetSubtarget.
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
Definition: SlotIndexes.h:242
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
decltype(MaxPressure) moveMaxPressure()
unsigned getSGPRTuplesWeight() const
GCNRPTracker(const LiveIntervals &LIS_)
GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
friend GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
const LiveIntervals & LIS
decltype(LiveRegs) moveLiveRegs()
bool operator!=(const GCNRegPressure &O) const
decltype(LiveRegs) const & getLiveRegs() const
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:260
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOccupancy(const SISubtarget &ST) const
void inc(unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask, const MachineRegisterInfo &MRI)
unsigned getVGPRTuplesWeight() const
GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI, const LiveIntervals &LIS)
const MachineBasicBlock::const_iterator getNext() const
void print(raw_ostream &OS, const SISubtarget *ST=nullptr) const
unsigned const MachineRegisterInfo * MRI
const MachineInstr * getLastTrackedMI() const
unsigned getSGPRNum() const
static const unsigned End
GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI, const LiveIntervals &LIS)
unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const
Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs.
GCNUpwardRPTracker(const LiveIntervals &LIS_)
void printLivesAt(SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
unsigned getVGPRNum() const
static LaneBitmask getNone()
Definition: LaneBitmask.h:83
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const
Return the maximum number of waves per SIMD for kernels using SGPRs SGPRs.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, Range &&LiveRegs)
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:58
LaneBitmask getLiveLaneMask(unsigned Reg, SlotIndex SI, const LiveIntervals &LIS, const MachineRegisterInfo &MRI)
bool operator==(const GCNRegPressure &O) const
LLVM Value Representation.
Definition: Value.h:73
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
GCNRegPressure MaxPressure
GCNDownwardRPTracker(const LiveIntervals &LIS_)
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:84
bool less(const SISubtarget &ST, const GCNRegPressure &O, unsigned MaxOccupancy=std::numeric_limits< unsigned >::max()) const