AMDGPUDisassembler.cpp File Reference

This file contains definition for AMDGPU ISA disassembler. More...

#include "Disassembler/AMDGPUDisassembler.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIDefines.h"
#include "SIRegisterInfo.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUAsmUtils.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm-c/DisassemblerTypes.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDecoderOps.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "AMDGPUGenDisassemblerTables.inc"

Go to the source code of this file.

Classes
struct	VOPModifiers

Macros
#define	DEBUG_TYPE   "amdgpu-disassembler"
#define	SGPR_MAX
#define	DECODE_OPERAND(StaticDecoderName, DecoderName)
#define	DECODE_OPERAND_REG_8(RegClass)
#define	DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, ImmWidth)
#define	DECODE_OPERAND_REG_7(RegClass, OpWidth)    DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
#define	DECODE_SDWA(DecName)   DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
#define	GET_FIELD(MASK)   (AMDHSA_BITS_GET(FourByteBuffer, MASK))
#define	PRINT_DIRECTIVE(DIRECTIVE, MASK)
#define	PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK)
#define	CHECK_RESERVED_BITS_IMPL(MASK, DESC, MSG)
#define	CHECK_RESERVED_BITS(MASK)   CHECK_RESERVED_BITS_IMPL(MASK, #MASK, "")
#define	CHECK_RESERVED_BITS_MSG(MASK, MSG)    CHECK_RESERVED_BITS_IMPL(MASK, #MASK, ", " MSG)
#define	CHECK_RESERVED_BITS_DESC(MASK, DESC)    CHECK_RESERVED_BITS_IMPL(MASK, DESC, "")
#define	CHECK_RESERVED_BITS_DESC_MSG(MASK, DESC, MSG)    CHECK_RESERVED_BITS_IMPL(MASK, DESC, ", " MSG)
#define	PRINT_DIRECTIVE(DIRECTIVE, MASK)

Typedefs
using	DecodeStatus = llvm::MCDisassembler::DecodeStatus

Functions
static const MCSubtargetInfo &	addDefaultWaveSize (const MCSubtargetInfo &STI, MCContext &Ctx)
static MCDisassembler::DecodeStatus	addOperand (MCInst &Inst, const MCOperand &Opnd)
static int	insertNamedMCOperand (MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
static DecodeStatus	decodeSOPPBrTarget (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeSMEMOffset (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeBoolReg (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeSplitBarrier (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeDpp8FI (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeSrcOp (MCInst &Inst, unsigned EncSize, AMDGPUDisassembler::OpWidthTy OpWidth, unsigned Imm, unsigned EncImm, bool MandatoryLiteral, unsigned ImmWidth, AMDGPU::OperandSemantics Sema, const MCDisassembler *Decoder)
template<AMDGPUDisassembler::OpWidthTy OpWidth>
static DecodeStatus	decodeAV10 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<AMDGPUDisassembler::OpWidthTy OpWidth>
static DecodeStatus	decodeSrcReg9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<AMDGPUDisassembler::OpWidthTy OpWidth>
static DecodeStatus	decodeSrcA9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<AMDGPUDisassembler::OpWidthTy OpWidth>
static DecodeStatus	decodeSrcAV10 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, unsigned OperandSemantics>
static DecodeStatus	decodeSrcRegOrImm9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, unsigned OperandSemantics>
static DecodeStatus	decodeSrcRegOrImmA9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, unsigned OperandSemantics>
static DecodeStatus	decodeSrcRegOrImmDeferred9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	DecodeVGPR_16RegisterClass (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	DecodeVGPR_16_Lo128RegisterClass (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperand_VSrcT16_Lo128 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperand_VSrcT16 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperand_KImmFP (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperandVOPDDstY (MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
static bool	IsAGPROperand (const MCInst &Inst, int OpIdx, const MCRegisterInfo *MRI)
static DecodeStatus	decodeAVLdSt (MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, const MCDisassembler *Decoder)
template<AMDGPUDisassembler::OpWidthTy Opw>
static DecodeStatus	decodeAVLdSt (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperand_VSrc_f64 (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeVersionImm (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<typename T >
static T	eatBytes (ArrayRef< uint8_t > &Bytes)
static DecoderUInt128	eat12Bytes (ArrayRef< uint8_t > &Bytes)
static VOPModifiers	collectVOPModifiers (const MCInst &MI, bool IsVOP3P=false)
static int64_t	getInlineImmVal32 (unsigned Imm)
static int64_t	getInlineImmVal64 (unsigned Imm)
static int64_t	getInlineImmValF16 (unsigned Imm)
static int64_t	getInlineImmValBF16 (unsigned Imm)
static int64_t	getInlineImmVal16 (unsigned Imm, AMDGPU::OperandSemantics Sema)
static SmallString< 32 >	getBitRangeFromMask (uint32_t Mask, unsigned BaseBytes)
	Print a string describing the reserved bit range specified by Mask with offset BaseBytes for use in error comments.
static Error	createReservedKDBitsError (uint32_t Mask, unsigned BaseBytes, const char *Msg="")
	Create an error object to return from onSymbolStart for reserved kernel descriptor bits being set.
static Error	createReservedKDBytesError (unsigned BaseInBytes, unsigned WidthInBytes)
	Create an error object to return from onSymbolStart for reserved kernel descriptor bytes being set.
static MCSymbolizer *	createAMDGPUSymbolizer (const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static MCDisassembler *	createAMDGPUDisassembler (const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
LLVM_EXTERNAL_VISIBILITY void	LLVMInitializeAMDGPUDisassembler ()

Detailed Description

This file contains definition for AMDGPU ISA disassembler.

Definition in file AMDGPUDisassembler.cpp.

Macro Definition Documentation

CHECK_RESERVED_BITS

#define CHECK_RESERVED_BITS

(

MASK

)

CHECK_RESERVED_BITS_IMPL(MASK, #MASK, "")

Definition at line 1882 of file AMDGPUDisassembler.cpp.

CHECK_RESERVED_BITS_DESC

#define CHECK_RESERVED_BITS_DESC	(		MASK,
			DESC
	)		CHECK_RESERVED_BITS_IMPL(MASK, DESC, "")

Definition at line 1885 of file AMDGPUDisassembler.cpp.

CHECK_RESERVED_BITS_DESC_MSG

#define CHECK_RESERVED_BITS_DESC_MSG	(		MASK,
			DESC,
			MSG
	)		CHECK_RESERVED_BITS_IMPL(MASK, DESC, ", " MSG)

Definition at line 1887 of file AMDGPUDisassembler.cpp.

CHECK_RESERVED_BITS_IMPL

#define CHECK_RESERVED_BITS_IMPL	(		MASK,
			DESC,
			MSG
	)

Value:

  do {                                                                         \
    if (FourByteBuffer & (MASK)) {                                             \
      return createStringError(std::errc::invalid_argument,                    \
                               "kernel descriptor " DESC                       \
                               " reserved %s set" MSG,                         \
                               getBitRangeFromMask((MASK), 0).c_str());        \
    }                                                                          \
  } while (0)

Definition at line 1872 of file AMDGPUDisassembler.cpp.

CHECK_RESERVED_BITS_MSG

#define CHECK_RESERVED_BITS_MSG	(		MASK,
			MSG
	)		CHECK_RESERVED_BITS_IMPL(MASK, #MASK, ", " MSG)

Definition at line 1883 of file AMDGPUDisassembler.cpp.

DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-disassembler"

Definition at line 40 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND

#define DECODE_OPERAND	(		StaticDecoderName,
			DecoderName
	)

Value:

  static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm,            \
                                        uint64_t /*Addr*/,                     \
                                        const MCDisassembler *Decoder) {       \
    auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
    return addOperand(Inst, DAsm->DecoderName(Imm));                           \
  }

Definition at line 152 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_REG_7

#define DECODE_OPERAND_REG_7	(		RegClass,
			OpWidth
	)		DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)

Definition at line 197 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_REG_8

#define DECODE_OPERAND_REG_8

(

RegClass

)

Value:

  static DecodeStatus Decode##RegClass##RegisterClass(                         \
      MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,                           \
      const MCDisassembler *Decoder) {                                         \
    assert(Imm < (1 << 8) && "8-bit encoding");                                \
    auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
    return addOperand(                                                         \
        Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
  }

Definition at line 162 of file AMDGPUDisassembler.cpp.

DECODE_SDWA

#define DECODE_SDWA

(

DecName

)

DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)

Definition at line 441 of file AMDGPUDisassembler.cpp.

DECODE_SrcOp

#define DECODE_SrcOp	(		Name,
			EncSize,
			OpWidth,
			EncImm,
			MandatoryLiteral,
			ImmWidth
	)

Value:

  static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,      \
                           const MCDisassembler *Decoder) {                    \
    assert(Imm < (1 << EncSize) && #EncSize "-bit encoding");                  \
    auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
    return addOperand(Inst,                                                    \
                      DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm,   \
                                        MandatoryLiteral, ImmWidth));          \
  }

Definition at line 172 of file AMDGPUDisassembler.cpp.

GET_FIELD

#define GET_FIELD

(

MASK

)

(AMDHSA_BITS_GET(FourByteBuffer, MASK))

Definition at line 1861 of file AMDGPUDisassembler.cpp.

PRINT_DIRECTIVE [1/2]

#define PRINT_DIRECTIVE	(		DIRECTIVE,
			MASK
	)

Value:

  do {                                                                         \
    KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n';            \
  } while (0)

Definition at line 1862 of file AMDGPUDisassembler.cpp.

PRINT_DIRECTIVE [2/2]

#define PRINT_DIRECTIVE	(		DIRECTIVE,
			MASK
	)

Value:

  do {                                                                         \
    KdStream << Indent << DIRECTIVE " "                                        \
             << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n';            \
  } while (0)

Definition at line 1862 of file AMDGPUDisassembler.cpp.

PRINT_PSEUDO_DIRECTIVE_COMMENT

#define PRINT_PSEUDO_DIRECTIVE_COMMENT	(		DIRECTIVE,
			MASK
	)

Value:

  do {                                                                         \
    KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " "       \
             << GET_FIELD(MASK) << '\n';                                       \
  } while (0)

Definition at line 1866 of file AMDGPUDisassembler.cpp.

SGPR_MAX

#define SGPR_MAX

Value:

  (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10                           \
                 : AMDGPU::EncValues::SGPR_MAX_SI)

Definition at line 42 of file AMDGPUDisassembler.cpp.

Typedef Documentation

DecodeStatus

using DecodeStatus = llvm::MCDisassembler::DecodeStatus

Definition at line 46 of file AMDGPUDisassembler.cpp.

Function Documentation

addDefaultWaveSize()

static const MCSubtargetInfo & addDefaultWaveSize ( const MCSubtargetInfo &  STI, MCContext &  Ctx  )

static

Definition at line 48 of file AMDGPUDisassembler.cpp.

References llvm::MCContext::getSubtargetCopy(), llvm::MCSubtargetInfo::hasFeature(), and llvm::MCSubtargetInfo::ToggleFeature().

addOperand()

static MCDisassembler::DecodeStatus addOperand ( MCInst &  Inst, const MCOperand &  Opnd  )

inlinestatic

Definition at line 86 of file AMDGPUDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::MCDisassembler::Fail, llvm::MCOperand::isValid(), and llvm::MCDisassembler::Success.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), decodeAVLdSt(), decodeBoolReg(), decodeDpp8FI(), decodeOperand_KImmFP(), decodeOperand_VSrc_f64(), decodeOperand_VSrcT16(), decodeOperand_VSrcT16_Lo128(), decodeOperandVOPDDstY(), decodeSMEMOffset(), decodeSOPPBrTarget(), decodeSplitBarrier(), decodeSrcOp(), decodeVersionImm(), DecodeVGPR_16_Lo128RegisterClass(), DecodeVGPR_16RegisterClass(), llvm::VPReplicateRecipe::VPReplicateRecipe(), llvm::VPWidenIntOrFpInductionRecipe::VPWidenIntOrFpInductionRecipe(), and llvm::VPWidenPointerInductionRecipe::VPWidenPointerInductionRecipe().

collectVOPModifiers()

static VOPModifiers collectVOPModifiers ( const MCInst &  MI, bool  IsVOP3P = false  )

static

Definition at line 804 of file AMDGPUDisassembler.cpp.

References llvm::SISrcMods::DST_OP_SEL, llvm::AMDGPU::getNamedOperandIdx(), MI, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, VOPModifiers::NegHi, VOPModifiers::NegLo, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, VOPModifiers::OpSel, and VOPModifiers::OpSelHi.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), and llvm::AMDGPUDisassembler::convertVOP3PDPPInst().

createAMDGPUDisassembler()

static MCDisassembler * createAMDGPUDisassembler ( const Target &  T, const MCSubtargetInfo &  STI, MCContext &  Ctx  )

static

Definition at line 2448 of file AMDGPUDisassembler.cpp.

Referenced by LLVMInitializeAMDGPUDisassembler().

createAMDGPUSymbolizer()

static MCSymbolizer * createAMDGPUSymbolizer ( const Triple &  , LLVMOpInfoCallback  , LLVMSymbolLookupCallback  , void *  DisInfo, MCContext *  Ctx, std::unique_ptr< MCRelocationInfo > &&  RelInfo  )

static

Definition at line 2439 of file AMDGPUDisassembler.cpp.

Referenced by LLVMInitializeAMDGPUDisassembler().

createReservedKDBitsError()

static Error createReservedKDBitsError ( uint32_t  Mask, unsigned  BaseBytes, const char *  Msg = ""  )

static

Create an error object to return from onSymbolStart for reserved kernel descriptor bits being set.

Definition at line 2141 of file AMDGPUDisassembler.cpp.

References llvm::c_str(), llvm::createStringError(), and getBitRangeFromMask().

Referenced by llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective().

createReservedKDBytesError()

static Error createReservedKDBytesError ( unsigned  BaseInBytes, unsigned  WidthInBytes  )

static

Create an error object to return from onSymbolStart for reserved kernel descriptor bytes being set.

Definition at line 2150 of file AMDGPUDisassembler.cpp.

References llvm::createStringError().

Referenced by llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective().

decodeAV10()

template<AMDGPUDisassembler::OpWidthTy OpWidth>

static DecodeStatus decodeAV10 ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 205 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), llvm::AMDGPU::INT, and llvm::AMDGPU::EncValues::IS_VGPR.

decodeAVLdSt() [1/2]

static DecodeStatus decodeAVLdSt ( MCInst &  Inst, unsigned  Imm, AMDGPUDisassembler::OpWidthTy  Opw, const MCDisassembler *  Decoder  )

static

Definition at line 390 of file AMDGPUDisassembler.cpp.

References addOperand(), llvm::SIInstrFlags::DS, llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), IsAGPROperand(), and MRI.

Referenced by decodeAVLdSt().

decodeAVLdSt() [2/2]

template<AMDGPUDisassembler::OpWidthTy Opw>

static DecodeStatus decodeAVLdSt ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 425 of file AMDGPUDisassembler.cpp.

References decodeAVLdSt().

decodeBoolReg()

static DecodeStatus decodeBoolReg ( MCInst &  Inst, unsigned  Val, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 133 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeDpp8FI()

static DecodeStatus decodeDpp8FI ( MCInst &  Inst, unsigned  Val, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 146 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeOperand_KImmFP()

static DecodeStatus decodeOperand_KImmFP ( MCInst &  Inst, unsigned  Imm, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 363 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeOperand_VSrc_f64()

static DecodeStatus decodeOperand_VSrc_f64 ( MCInst &  Inst, unsigned  Imm, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 431 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), llvm::AMDGPU::FP64, and llvm::AMDGPUDisassembler::OPW64.

decodeOperand_VSrcT16()

static DecodeStatus decodeOperand_VSrcT16 ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 347 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), and llvm::AMDGPUDisassembler::OPW16.

decodeOperand_VSrcT16_Lo128()

static DecodeStatus decodeOperand_VSrcT16_Lo128 ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 331 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), and llvm::AMDGPUDisassembler::OPW16.

decodeOperandVOPDDstY()

static DecodeStatus decodeOperandVOPDDstY ( MCInst &  Inst, unsigned  Val, uint64_t  Addr, const void *  Decoder  )

static

Definition at line 370 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeSMEMOffset()

static DecodeStatus decodeSMEMOffset ( MCInst &  Inst, unsigned  Imm, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 119 of file AMDGPUDisassembler.cpp.

References addOperand(), llvm::MCOperand::createImm(), and llvm::Offset.

decodeSOPPBrTarget()

static DecodeStatus decodeSOPPBrTarget ( MCInst &  Inst, unsigned  Imm, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 104 of file AMDGPUDisassembler.cpp.

References addOperand(), Addr, llvm::MCOperand::createImm(), llvm::Offset, llvm::APInt::sext(), and llvm::MCDisassembler::Success.

decodeSplitBarrier()

static DecodeStatus decodeSplitBarrier ( MCInst &  Inst, unsigned  Val, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 139 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeSrcA9()

template<AMDGPUDisassembler::OpWidthTy OpWidth>

static DecodeStatus decodeSrcA9 ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 224 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and llvm::AMDGPU::INT.

decodeSrcAV10()

template<AMDGPUDisassembler::OpWidthTy OpWidth>

static DecodeStatus decodeSrcAV10 ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 233 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and llvm::AMDGPU::INT.

decodeSrcOp()

static DecodeStatus decodeSrcOp ( MCInst &  Inst, unsigned  EncSize, AMDGPUDisassembler::OpWidthTy  OpWidth, unsigned  Imm, unsigned  EncImm, bool  MandatoryLiteral, unsigned  ImmWidth, AMDGPU::OperandSemantics  Sema, const MCDisassembler *  Decoder  )

static

Definition at line 183 of file AMDGPUDisassembler.cpp.

References addOperand(), and assert().

Referenced by decodeAV10(), decodeSrcA9(), decodeSrcAV10(), decodeSrcReg9(), decodeSrcRegOrImm9(), decodeSrcRegOrImmA9(), and decodeSrcRegOrImmDeferred9().

decodeSrcReg9()

template<AMDGPUDisassembler::OpWidthTy OpWidth>

static DecodeStatus decodeSrcReg9 ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 213 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and llvm::AMDGPU::INT.

decodeSrcRegOrImm9()

template<AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, unsigned OperandSemantics>

static DecodeStatus decodeSrcRegOrImm9 ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 247 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

decodeSrcRegOrImmA9()

template<AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, unsigned OperandSemantics>

static DecodeStatus decodeSrcRegOrImmA9 ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 258 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

decodeSrcRegOrImmDeferred9()

template<AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, unsigned OperandSemantics>

static DecodeStatus decodeSrcRegOrImmDeferred9 ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 267 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

decodeVersionImm()

static DecodeStatus decodeVersionImm ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 448 of file AMDGPUDisassembler.cpp.

References addOperand().

DecodeVGPR_16_Lo128RegisterClass()

static DecodeStatus DecodeVGPR_16_Lo128RegisterClass ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 321 of file AMDGPUDisassembler.cpp.

References addOperand(), and assert().

DecodeVGPR_16RegisterClass()

static DecodeStatus DecodeVGPR_16RegisterClass ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 308 of file AMDGPUDisassembler.cpp.

References addOperand(), and assert().

eat12Bytes()

static DecoderUInt128 eat12Bytes ( ArrayRef< uint8_t > &  Bytes )

inlinestatic

Definition at line 469 of file AMDGPUDisassembler.cpp.

References assert(), llvm::ArrayRef< T >::data(), llvm::Hi, llvm::Lo, llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

Referenced by llvm::AMDGPUDisassembler::getInstruction().

eatBytes()

template<typename T >

static T eatBytes ( ArrayRef< uint8_t > &  Bytes )

inlinestatic

Definition at line 461 of file AMDGPUDisassembler.cpp.

References assert(), llvm::ArrayRef< T >::data(), llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

getBitRangeFromMask()

static SmallString< 32 > getBitRangeFromMask ( uint32_t  Mask, unsigned  BaseBytes  )

static

Print a string describing the reserved bit range specified by Mask with offset BaseBytes for use in error comments.

Mask is a single continuous range of 1s surrounded by zeros. The format here is meant to align with the tables that describe these bits in llvm.org/docs/AMDGPUUsage.html.

Definition at line 1843 of file AMDGPUDisassembler.cpp.

References llvm::countr_zero(), and llvm::popcount().

Referenced by createReservedKDBitsError().

getInlineImmVal16()

static int64_t getInlineImmVal16 ( unsigned  Imm, AMDGPU::OperandSemantics  Sema  )

static

Definition at line 1387 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::BF16, getInlineImmValBF16(), and getInlineImmValF16().

Referenced by llvm::AMDGPUDisassembler::decodeFPImmed().

getInlineImmVal32()

static int64_t getInlineImmVal32 ( unsigned  Imm )

static

Definition at line 1287 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPUDisassembler::decodeFPImmed().

getInlineImmVal64()

static int64_t getInlineImmVal64 ( unsigned  Imm )

static

Definition at line 1312 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPUDisassembler::decodeFPImmed().

getInlineImmValBF16()

static int64_t getInlineImmValBF16 ( unsigned  Imm )

static

Definition at line 1362 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by getInlineImmVal16().

getInlineImmValF16()

static int64_t getInlineImmValF16 ( unsigned  Imm )

static

Definition at line 1337 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by getInlineImmVal16().

insertNamedMCOperand()

static int insertNamedMCOperand ( MCInst &  MI, const MCOperand &  Op, uint16_t  NameIdx  )

static

Definition at line 93 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), I, and MI.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertEXPInst(), llvm::AMDGPUDisassembler::convertFMAanyK(), llvm::AMDGPUDisassembler::convertMacDPPInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::AMDGPUDisassembler::convertVINTERPInst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), and llvm::AMDGPUDisassembler::getInstruction().

IsAGPROperand()

static bool IsAGPROperand ( const MCInst &  Inst, int  OpIdx, const MCRegisterInfo *  MRI  )

static

Definition at line 376 of file AMDGPUDisassembler.cpp.

References llvm::MCInst::getOperand(), and MRI.

LLVMInitializeAMDGPUDisassembler()

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler

(

)

Definition at line 2454 of file AMDGPUDisassembler.cpp.

References createAMDGPUDisassembler(), createAMDGPUSymbolizer(), llvm::getTheGCNTarget(), llvm::TargetRegistry::RegisterMCDisassembler(), and llvm::TargetRegistry::RegisterMCSymbolizer().