LLVM 20.0.0git
DeadMachineInstructionElim.cpp
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1//===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This is an extremely simple MachineInstr-level dead-code-elimination pass.
10//
11//===----------------------------------------------------------------------===//
12
15#include "llvm/ADT/Statistic.h"
21#include "llvm/Pass.h"
22#include "llvm/Support/Debug.h"
24
25using namespace llvm;
26
27#define DEBUG_TYPE "dead-mi-elimination"
28
29STATISTIC(NumDeletes, "Number of dead instructions deleted");
30
31namespace {
32class DeadMachineInstructionElimImpl {
33 const MachineRegisterInfo *MRI = nullptr;
34 const TargetInstrInfo *TII = nullptr;
36
37public:
38 bool runImpl(MachineFunction &MF);
39
40private:
41 bool isDead(const MachineInstr *MI) const;
42 bool eliminateDeadMI(MachineFunction &MF);
43};
44
45class DeadMachineInstructionElim : public MachineFunctionPass {
46public:
47 static char ID; // Pass identification, replacement for typeid
48
49 DeadMachineInstructionElim() : MachineFunctionPass(ID) {
51 }
52
53 bool runOnMachineFunction(MachineFunction &MF) override {
54 if (skipFunction(MF.getFunction()))
55 return false;
56 return DeadMachineInstructionElimImpl().runImpl(MF);
57 }
58
59 void getAnalysisUsage(AnalysisUsage &AU) const override {
60 AU.setPreservesCFG();
62 }
63};
64} // namespace
65
69 if (!DeadMachineInstructionElimImpl().runImpl(MF))
73 return PA;
74}
75
76char DeadMachineInstructionElim::ID = 0;
77char &llvm::DeadMachineInstructionElimID = DeadMachineInstructionElim::ID;
78
79INITIALIZE_PASS(DeadMachineInstructionElim, DEBUG_TYPE,
80 "Remove dead machine instructions", false, false)
81
82bool DeadMachineInstructionElimImpl::isDead(const MachineInstr *MI) const {
83 // Instructions without side-effects are dead iff they only define dead regs.
84 // This function is hot and this loop returns early in the common case,
85 // so only perform additional checks before this if absolutely necessary.
86 for (const MachineOperand &MO : MI->all_defs()) {
87 Register Reg = MO.getReg();
88 if (Reg.isPhysical()) {
89 // Don't delete live physreg defs, or any reserved register defs.
90 if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
91 return false;
92 } else {
93 if (MO.isDead()) {
94#ifndef NDEBUG
95 // Basic check on the register. All of them should be 'undef'.
96 for (auto &U : MRI->use_nodbg_operands(Reg))
97 assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");
98#endif
99 continue;
100 }
101 for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
102 if (&Use != MI)
103 // This def has a non-debug use. Don't delete the instruction!
104 return false;
105 }
106 }
107 }
108
109 // Technically speaking inline asm without side effects and no defs can still
110 // be deleted. But there is so much bad inline asm code out there, we should
111 // let them be.
112 if (MI->isInlineAsm())
113 return false;
114
115 // FIXME: See issue #105950 for why LIFETIME markers are considered dead here.
116 if (MI->isLifetimeMarker())
117 return true;
118
119 // If there are no defs with uses, the instruction might be dead.
120 return MI->wouldBeTriviallyDead();
121}
122
123bool DeadMachineInstructionElimImpl::runImpl(MachineFunction &MF) {
124 MRI = &MF.getRegInfo();
125
126 const TargetSubtargetInfo &ST = MF.getSubtarget();
127 TII = ST.getInstrInfo();
128 LivePhysRegs.init(*ST.getRegisterInfo());
129
130 bool AnyChanges = eliminateDeadMI(MF);
131 while (AnyChanges && eliminateDeadMI(MF))
132 ;
133 return AnyChanges;
134}
135
136bool DeadMachineInstructionElimImpl::eliminateDeadMI(MachineFunction &MF) {
137 bool AnyChanges = false;
138
139 // Loop over all instructions in all blocks, from bottom to top, so that it's
140 // more likely that chains of dependent but ultimately dead instructions will
141 // be cleaned up.
142 for (MachineBasicBlock *MBB : post_order(&MF)) {
144
145 // Now scan the instructions and delete dead ones, tracking physreg
146 // liveness as we go.
148 // If the instruction is dead, delete it!
149 if (isDead(&MI)) {
150 LLVM_DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << MI);
151 // It is possible that some DBG_VALUE instructions refer to this
152 // instruction. They will be deleted in the live debug variable
153 // analysis.
154 MI.eraseFromParent();
155 AnyChanges = true;
156 ++NumDeletes;
157 continue;
158 }
159
161 }
162 }
163
165 return AnyChanges;
166}
unsigned const MachineRegisterInfo * MRI
aarch64 promote const
MachineBasicBlock & MBB
#define LLVM_DEBUG(...)
Definition: Debug.h:106
static bool runImpl(Function &F, const TargetLowering &TLI)
#define DEBUG_TYPE
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
A set of register units.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:166
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:253
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:256
Represents analyses that only rely on functions' control flow.
Definition: Analysis.h:72
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
bool skipFunction(const Function &F) const
Optional passes call this function to check whether the pass should be skipped.
Definition: Pass.cpp:178
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:52
void clear()
Clears the set.
Definition: LivePhysRegs.h:77
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
void init(const TargetRegisterInfo &TRI)
(re-)initializes and clears the set.
Definition: LivePhysRegs.h:70
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
A set of analyses that are preserved following a run of a transformation pass.
Definition: Analysis.h:111
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Definition: Analysis.h:117
void preserveSet()
Mark an analysis set as preserved.
Definition: Analysis.h:146
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
TargetInstrInfo - Interface to description of machine instruction set.
TargetSubtargetInfo - Generic base class for all target subtargets.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:657
iterator_range< po_iterator< T > > post_order(const T &G)
void initializeDeadMachineInstructionElimPass(PassRegistry &)
PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:420
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.