13#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H
14#define LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H
49 #include "MipsGenDAGISel.inc"
94 unsigned MinSizeInBits)
const;
126 bool selectVecAddAsVecSubIfProfitable(
SDNode *
Node);
139 bool SelectInlineAsmMemoryOperand(
const SDValue &
Op,
141 std::vector<SDValue> &OutOps)
override;
142 bool isUnneededShiftMask(
SDNode *
N,
unsigned ShAmtBits)
const;
amdgpu AMDGPU Register Bank Select
Class for arbitrary precision integers.
Represent the analysis usage information of a pass.
This class represents an Operation in the Expression.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool runOnMachineFunction(MachineFunction &MF) override
MipsDAGToDAGISel()=delete
const MipsSubtarget * Subtarget
Keep a pointer to the MipsSubtarget around so that we can make the right decision when generating cod...
SDNode * getGlobalBaseReg()
getGlobalBaseReg - Output the instructions required to put the GOT address into a register.
MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOptLevel OL)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
This is an optimization pass for GlobalISel generic memory operations.
CodeGenOptLevel
Code generation optimization level.