37#define DEBUG_TYPE "mccodeemitter"
39#define GET_INSTRMAP_INFO
40#include "MipsGenInstrInfo.inc"
41#undef GET_INSTRMAP_INFO
91void MipsMCCodeEmitter::LowerCompactBranch(
MCInst& Inst)
const {
102 assert(Reg0 != Reg1 &&
"Instruction has bad operands ($rs == $rt)!");
108 }
else if (Inst.
getOpcode() == Mips::BNVC_MMR6 ||
120 return STI.
hasFeature(Mips::FeatureMicroMips);
142 switch (
MI.getOpcode()) {
156 case Mips::BOVC_MMR6:
158 case Mips::BNVC_MMR6:
159 LowerCompactBranch(TmpInst);
162 size_t N = Fixups.size();
168 const unsigned Opcode = TmpInst.
getOpcode();
169 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
170 (Opcode != Mips::SLL_MM) && (Opcode != Mips::SLL_MMR6) && !Binary)
174 if (isMicroMips(STI)) {
175 if (isMips32r6(STI)) {
176 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
178 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
181 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
185 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
187 if (NewOpcode != -1) {
188 if (Fixups.size() >
N)
195 if (((
MI.getOpcode() == Mips::MOVEP_MM) ||
196 (
MI.getOpcode() == Mips::MOVEP_MMR6))) {
198 Binary = (Binary & 0xFFFFFC7F) | (RegPair << 7);
212 support::endian::write<uint16_t>(CB, Binary,
Endian);
213 }
else if (IsLittleEndian && isMicroMips(STI)) {
214 support::endian::write<uint16_t>(CB, Binary >> 16,
Endian);
215 support::endian::write<uint16_t>(CB, Binary & 0xffff,
Endian);
217 support::endian::write<uint32_t>(CB, Binary,
Endian);
234 "getBranchTargetOpValue expects only expressions or immediates");
256 "getBranchTargetOpValue expects only expressions or immediates");
279 "getBranchTargetOpValueMMR6 expects only expressions or immediates");
302 "getBranchTargetOpValueLsl2MMR6 expects only expressions or immediates");
324 "getBranchTargetOpValueMM expects only expressions or immediates");
345 "getBranchTargetOpValuePC10 expects only expressions or immediates");
366 "getBranchTargetOpValueMM expects only expressions or immediates");
371 fixup_MICROMIPS_PC16_S1)));
388 "getBranchTarget21OpValue expects only expressions or immediates");
410 "getBranchTarget21OpValueMM expects only expressions or immediates");
432 "getBranchTarget26OpValue expects only expressions or immediates");
454 "getBranchTarget26OpValueMM expects only expressions or immediates");
475 "getJumpOffset16OpValue expects only expressions or an immediate");
496 "getJumpTargetOpValue expects only expressions or an immediate");
513 "getJumpTargetOpValueMM expects only expressions or an immediate");
534 "getUImm5Lsl2Encoding expects only expressions or an immediate");
571 unsigned Binary = (MO.
getImm() >> 2) & 0x0000ffff;
572 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
583 if (Expr->evaluateAsAbsolute(Res))
588 return cast<MCConstantExpr>(Expr)->getValue();
594 Res +=
getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
599 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
727 unsigned Reg = MO.
getReg();
730 }
else if (MO.
isImm()) {
731 return static_cast<unsigned>(MO.
getImm());
733 return static_cast<unsigned>(bit_cast<double>(MO.
getDFPImm()));
742template <
unsigned ShiftAmount>
747 assert(
MI.getOperand(OpNo).isReg());
753 OffBits >>= ShiftAmount;
755 return (OffBits & 0xFFFF) | RegBits;
763 assert(
MI.getOperand(OpNo).isReg());
769 return (OffBits & 0xF) | RegBits;
777 assert(
MI.getOperand(OpNo).isReg());
783 return (OffBits & 0xF) | RegBits;
791 assert(
MI.getOperand(OpNo).isReg());
797 return (OffBits & 0xF) | RegBits;
805 assert(
MI.getOperand(OpNo).isReg() &&
806 (
MI.getOperand(OpNo).getReg() == Mips::SP ||
807 MI.getOperand(OpNo).getReg() == Mips::SP_64) &&
808 "Unexpected base register!");
812 return OffBits & 0x1F;
820 assert(
MI.getOperand(OpNo).isReg() &&
821 MI.getOperand(OpNo).getReg() == Mips::GP &&
822 "Unexpected base register!");
827 return OffBits & 0x7F;
835 assert(
MI.getOperand(OpNo).isReg());
841 return (OffBits & 0x1FF) | RegBits;
849 assert(
MI.getOperand(OpNo).isReg());
854 return (OffBits & 0x07FF) | RegBits;
863 switch (
MI.getOpcode()) {
868 OpNo =
MI.getNumOperands() - 2;
873 assert(
MI.getOperand(OpNo).isReg());
878 return (OffBits & 0x0FFF) | RegBits;
886 assert(
MI.getOperand(OpNo).isReg());
891 return (OffBits & 0xFFFF) | RegBits;
900 switch (
MI.getOpcode()) {
904 case Mips::SWM16_MMR6:
906 case Mips::LWM16_MMR6:
907 OpNo =
MI.getNumOperands() - 2;
912 assert(
MI.getOperand(OpNo).isReg());
914 assert(
MI.getOperand(OpNo+1).isImm());
917 return ((OffBits >> 2) & 0x0F);
926 assert(
MI.getOperand(OpNo-1).isImm());
927 assert(
MI.getOperand(OpNo).isImm());
931 return Position +
Size - 1;
934template <
unsigned Bits,
int Offset>
939 assert(
MI.getOperand(OpNo).isImm());
958 "getSimm19Lsl2Encoding expects only expressions or an immediate");
980 "getSimm18Lsl2Encoding expects only expressions or an immediate");
993 assert(
MI.getOperand(OpNo).isImm());
1002 assert(
MI.getOperand(OpNo).isImm());
1006 case 128:
return 0x0;
1013 case 15:
return 0x7;
1014 case 16:
return 0x8;
1015 case 31:
return 0x9;
1016 case 32:
return 0xa;
1017 case 63:
return 0xb;
1018 case 64:
return 0xc;
1019 case 255:
return 0xd;
1020 case 32768:
return 0xe;
1021 case 65535:
return 0xf;
1035 for (
unsigned I = OpNo, E =
MI.getNumOperands() - 2;
I < E; ++
I) {
1036 unsigned Reg =
MI.getOperand(
I).getReg();
1050 return (
MI.getNumOperands() - 4);
1059 if (
MI.getOperand(0).getReg() == Mips::A1 &&
1060 MI.getOperand(1).getReg() == Mips::A2)
1062 else if (
MI.getOperand(0).getReg() == Mips::A1 &&
1063 MI.getOperand(1).getReg() == Mips::A3)
1065 else if (
MI.getOperand(0).getReg() == Mips::A2 &&
1066 MI.getOperand(1).getReg() == Mips::A3)
1068 else if (
MI.getOperand(0).getReg() == Mips::A0 &&
1069 MI.getOperand(1).getReg() == Mips::S5)
1071 else if (
MI.getOperand(0).getReg() == Mips::A0 &&
1072 MI.getOperand(1).getReg() == Mips::S6)
1074 else if (
MI.getOperand(0).getReg() == Mips::A0 &&
1075 MI.getOperand(1).getReg() == Mips::A1)
1077 else if (
MI.getOperand(0).getReg() == Mips::A0 &&
1078 MI.getOperand(1).getReg() == Mips::A2)
1080 else if (
MI.getOperand(0).getReg() == Mips::A0 &&
1081 MI.getOperand(1).getReg() == Mips::A3)
1091 assert(((OpNo == 2) || (OpNo == 3)) &&
1092 "Unexpected OpNo for movep operand encoding!");
1095 assert(
Op.isReg() &&
"Operand of movep is not a register!");
1096 switch (
Op.getReg()) {
1099 case Mips::ZERO:
return 0;
1100 case Mips::S1:
return 1;
1101 case Mips::V0:
return 2;
1102 case Mips::V1:
return 3;
1103 case Mips::S0:
return 4;
1104 case Mips::S2:
return 5;
1105 case Mips::S3:
return 6;
1106 case Mips::S4:
return 7;
1115 assert(MO.
isImm() &&
"getSimm23Lsl2Encoding expects only an immediate");
1117 unsigned Res =
static_cast<unsigned>(MO.
getImm());
1122#include "MipsGenMCCodeEmitter.inc"
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
static void LowerLargeShift(MCInst &Inst)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This class represents an Operation in the Expression.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCCodeEmitter - Generic instruction encoding interface.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
void reportError(SMLoc L, const Twine &Msg)
Base class for the full range of assembler expressions which are needed for parsing.
@ Constant
Constant expressions.
@ SymbolRef
References to labels and assigned expressions.
@ Target
Target specific expression.
@ Binary
Binary expressions.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
void setReg(MCRegister Reg)
Set the register number.
MCRegister getReg() const
Returns the register number.
const MCExpr * getExpr() const
uint64_t getDFPImm() const
uint16_t getEncodingValue(MCRegister Reg) const
Returns the encoding for Reg.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
unsigned getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch target operand.
unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget21OpValue - Return binary encoding of the branch target operand.
uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getMachineOpValue - Return binary encoding of operand.
unsigned getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Subtract Offset then encode as a N-bit unsigned integer.
unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValueMMR6 - Return binary encoding of the branch target operand.
unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValue - Return binary encoding of the branch target operand.
unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
Return binary encoding of memory related operand.
unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget26OpValue - Return binary encoding of the branch target operand.
unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget26OpValueMM - Return binary encoding of the branch target operand.
unsigned getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValue1SImm16 - Return binary encoding of the branch target operand.
unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getJumpOffset16OpValue - Return binary encoding of the jump target operand.
unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 10-bit branch target operand.
unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getJumpTargetOpValue - Return binary encoding of the jump target operand.
unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTargetOpValue - Return binary encoding of the microMIPS branch target operand.
unsigned getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void encodeInstruction(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
encodeInstruction - Emit the instruction.
unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget21OpValueMM - Return binary encoding of the branch target operand for microMIPS.
unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch target operand.
unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
void EmitByte(unsigned char C, raw_ostream &OS) const
unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
const MCExpr * getSubExpr() const
Get the child of this expression.
MipsExprKind getKind() const
Get the kind of this expression.
bool isGpOff(MipsExprKind &Kind) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
@ fixup_MICROMIPS_TLS_TPREL_LO16
@ fixup_MICROMIPS_GOT_PAGE
@ fixup_MICROMIPS_TLS_TPREL_HI16
@ fixup_MICROMIPS_PC21_S1
@ fixup_MICROMIPS_GPOFF_LO
@ fixup_MICROMIPS_PC19_S2
@ fixup_MICROMIPS_TLS_LDM
@ fixup_MICROMIPS_GOT_OFST
@ fixup_MICROMIPS_TLS_DTPREL_HI16
@ fixup_MICROMIPS_PC10_S1
@ fixup_MICROMIPS_HIGHEST
@ fixup_MICROMIPS_GOT_DISP
@ fixup_MICROMIPS_PC18_S3
@ fixup_MICROMIPS_PC26_S1
@ fixup_MICROMIPS_GOTTPREL
@ fixup_MICROMIPS_TLS_DTPREL_LO16
@ fixup_MICROMIPS_GPOFF_HI
This is an optimization pass for GlobalISel generic memory operations.
MCCodeEmitter * createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, MCContext &Ctx)
MCCodeEmitter * createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, MCContext &Ctx)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Description of the encoding of one expression Op.