LLVM 20.0.0git
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#include "Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h"
Additional Inherited Members | |
Protected Member Functions inherited from llvm::MCCodeEmitter | |
MCCodeEmitter () | |
Definition at line 30 of file MipsMCCodeEmitter.h.
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inline |
Definition at line 39 of file MipsMCCodeEmitter.h.
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delete |
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overridedefault |
void MipsMCCodeEmitter::EmitByte | ( | unsigned char | C, |
raw_ostream & | OS | ||
) | const |
Definition at line 127 of file MipsMCCodeEmitter.cpp.
References llvm::CallingConv::C, and OS.
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overridevirtual |
encodeInstruction - Emit the instruction.
Size the instruction with Desc.getSize().
Implements llvm::MCCodeEmitter.
Definition at line 133 of file MipsMCCodeEmitter.cpp.
References llvm::big, Endian, llvm::MCInstrInfo::get(), getBinaryCodeForInstr(), getMovePRegPairOpValue(), llvm::MCInst::getOpcode(), llvm::little, llvm_unreachable, LowerLargeShift(), MI, N, llvm::MCInst::setOpcode(), and Size.
uint64_t llvm::MipsMCCodeEmitter::getBinaryCodeForInstr | ( | const MCInst & | MI, |
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Referenced by encodeInstruction().
unsigned MipsMCCodeEmitter::getBranchTarget21OpValue | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getBranchTarget21OpValue - Return binary encoding of the branch target operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 378 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCConstantExpr::create(), llvm::MCFixup::create(), llvm::MCBinaryExpr::createAdd(), llvm::Mips::fixup_MIPS_PC21_S2, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getBranchTarget21OpValueMM | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getBranchTarget21OpValueMM - Return binary encoding of the branch target operand for microMIPS.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 400 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCConstantExpr::create(), llvm::MCFixup::create(), llvm::MCBinaryExpr::createAdd(), llvm::Mips::fixup_MICROMIPS_PC21_S1, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getBranchTarget26OpValue | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getBranchTarget26OpValue - Return binary encoding of the branch target operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 422 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCConstantExpr::create(), llvm::MCFixup::create(), llvm::MCBinaryExpr::createAdd(), llvm::Mips::fixup_MIPS_PC26_S2, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getBranchTarget26OpValueMM | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getBranchTarget26OpValueMM - Return binary encoding of the branch target operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 444 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCConstantExpr::create(), llvm::MCFixup::create(), llvm::MCBinaryExpr::createAdd(), llvm::Mips::fixup_MICROMIPS_PC26_S1, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getBranchTarget7OpValueMM | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch target operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 314 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCFixup::create(), llvm::Mips::fixup_MICROMIPS_PC7_S1, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getBranchTargetOpValue | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getBranchTargetOpValue - Return binary encoding of the branch target operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 224 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCConstantExpr::create(), llvm::MCFixup::create(), llvm::MCBinaryExpr::createAdd(), llvm::Mips::fixup_Mips_PC16, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getBranchTargetOpValue1SImm16 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getBranchTargetOpValue1SImm16 - Return binary encoding of the branch target operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 246 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCConstantExpr::create(), llvm::MCFixup::create(), llvm::MCBinaryExpr::createAdd(), llvm::Mips::fixup_Mips_PC16, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getBranchTargetOpValueLsl2MMR6 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch target operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 291 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCConstantExpr::create(), llvm::MCFixup::create(), llvm::MCBinaryExpr::createAdd(), llvm::Mips::fixup_Mips_PC16, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getBranchTargetOpValueMM | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getBranchTargetOpValue - Return binary encoding of the microMIPS branch target operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 356 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCFixup::create(), llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getBranchTargetOpValueMMPC10 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS 10-bit branch target operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 335 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCFixup::create(), llvm::Mips::fixup_MICROMIPS_PC10_S1, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getBranchTargetOpValueMMR6 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getBranchTargetOpValueMMR6 - Return binary encoding of the branch target operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 268 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCConstantExpr::create(), llvm::MCFixup::create(), llvm::MCBinaryExpr::createAdd(), llvm::Mips::fixup_Mips_PC16, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getExprOpValue | ( | const MCExpr * | Expr, |
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 578 of file MipsMCCodeEmitter.cpp.
References llvm::MCExpr::Binary, llvm::MCExpr::Constant, llvm::MCFixup::create(), llvm::Mips::fixup_MICROMIPS_CALL16, llvm::Mips::fixup_MICROMIPS_GOT16, llvm::Mips::fixup_MICROMIPS_GOT_DISP, llvm::Mips::fixup_MICROMIPS_GOT_OFST, llvm::Mips::fixup_MICROMIPS_GOT_PAGE, llvm::Mips::fixup_MICROMIPS_GOTTPREL, llvm::Mips::fixup_MICROMIPS_GPOFF_HI, llvm::Mips::fixup_MICROMIPS_GPOFF_LO, llvm::Mips::fixup_MICROMIPS_HI16, llvm::Mips::fixup_MICROMIPS_HIGHER, llvm::Mips::fixup_MICROMIPS_HIGHEST, llvm::Mips::fixup_MICROMIPS_LO16, llvm::Mips::fixup_MICROMIPS_SUB, llvm::Mips::fixup_MICROMIPS_TLS_DTPREL_HI16, llvm::Mips::fixup_MICROMIPS_TLS_DTPREL_LO16, llvm::Mips::fixup_MICROMIPS_TLS_GD, llvm::Mips::fixup_MICROMIPS_TLS_LDM, llvm::Mips::fixup_MICROMIPS_TLS_TPREL_HI16, llvm::Mips::fixup_MICROMIPS_TLS_TPREL_LO16, llvm::Mips::fixup_Mips_CALL16, llvm::Mips::fixup_Mips_CALL_HI16, llvm::Mips::fixup_Mips_CALL_LO16, llvm::Mips::fixup_Mips_DTPREL_HI, llvm::Mips::fixup_Mips_DTPREL_LO, llvm::Mips::fixup_Mips_GOT, llvm::Mips::fixup_Mips_GOT_DISP, llvm::Mips::fixup_Mips_GOT_HI16, llvm::Mips::fixup_Mips_GOT_LO16, llvm::Mips::fixup_Mips_GOT_OFST, llvm::Mips::fixup_Mips_GOT_PAGE, llvm::Mips::fixup_Mips_GOTTPREL, llvm::Mips::fixup_Mips_GPOFF_HI, llvm::Mips::fixup_Mips_GPOFF_LO, llvm::Mips::fixup_Mips_GPREL16, llvm::Mips::fixup_Mips_HI16, llvm::Mips::fixup_Mips_HIGHER, llvm::Mips::fixup_Mips_HIGHEST, llvm::Mips::fixup_Mips_LO16, llvm::Mips::fixup_MIPS_PCHI16, llvm::Mips::fixup_MIPS_PCLO16, llvm::Mips::fixup_Mips_SUB, llvm::Mips::fixup_Mips_TLSGD, llvm::Mips::fixup_Mips_TLSLDM, llvm::Mips::fixup_Mips_TPREL_HI, llvm::Mips::fixup_Mips_TPREL_LO, getExprOpValue(), llvm::MCExpr::getKind(), llvm::MipsMCExpr::getKind(), llvm::MCExpr::getLoc(), llvm::MipsMCExpr::getSubExpr(), llvm::MipsMCExpr::isGpOff(), llvm_unreachable, llvm::MipsMCExpr::MEK_CALL_HI16, llvm::MipsMCExpr::MEK_CALL_LO16, llvm::MipsMCExpr::MEK_DTPREL, llvm::MipsMCExpr::MEK_DTPREL_HI, llvm::MipsMCExpr::MEK_DTPREL_LO, llvm::MipsMCExpr::MEK_GOT, llvm::MipsMCExpr::MEK_GOT_CALL, llvm::MipsMCExpr::MEK_GOT_DISP, llvm::MipsMCExpr::MEK_GOT_HI16, llvm::MipsMCExpr::MEK_GOT_LO16, llvm::MipsMCExpr::MEK_GOT_OFST, llvm::MipsMCExpr::MEK_GOT_PAGE, llvm::MipsMCExpr::MEK_GOTTPREL, llvm::MipsMCExpr::MEK_GPREL, llvm::MipsMCExpr::MEK_HI, llvm::MipsMCExpr::MEK_HIGHER, llvm::MipsMCExpr::MEK_HIGHEST, llvm::MipsMCExpr::MEK_LO, llvm::MipsMCExpr::MEK_NEG, llvm::MipsMCExpr::MEK_None, llvm::MipsMCExpr::MEK_PCREL_HI16, llvm::MipsMCExpr::MEK_PCREL_LO16, llvm::MipsMCExpr::MEK_Special, llvm::MipsMCExpr::MEK_TLSGD, llvm::MipsMCExpr::MEK_TLSLDM, llvm::MipsMCExpr::MEK_TPREL_HI, llvm::MipsMCExpr::MEK_TPREL_LO, llvm::MCContext::reportError(), llvm::MCExpr::SymbolRef, and llvm::MCExpr::Target.
Referenced by getExprOpValue(), and getMachineOpValue().
unsigned MipsMCCodeEmitter::getJumpOffset16OpValue | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getJumpOffset16OpValue - Return binary encoding of the jump target operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 466 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCFixup::create(), llvm::Mips::fixup_MICROMIPS_LO16, llvm::Mips::fixup_Mips_LO16, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getJumpTargetOpValue | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getJumpTargetOpValue - Return binary encoding of the jump target operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 487 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCFixup::create(), llvm::Mips::fixup_Mips_26, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getJumpTargetOpValueMM | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 504 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCFixup::create(), llvm::Mips::fixup_MICROMIPS_26_S1, llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getMachineOpValue | ( | const MCInst & | MI, |
const MCOperand & | MO, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
getMachineOpValue - Return binary encoding of operand.
If the machine operand requires relocation, record the relocation and return zero.
Definition at line 722 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCOperand::getDFPImm(), llvm::MCRegisterInfo::getEncodingValue(), llvm::MCOperand::getExpr(), getExprOpValue(), llvm::MCOperand::getImm(), llvm::MCOperand::getReg(), llvm::MCContext::getRegisterInfo(), llvm::MCOperand::isDFPImm(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and llvm::MCOperand::isReg().
Referenced by getMemEncoding(), getMemEncodingMMGPImm7Lsl2(), getMemEncodingMMImm11(), getMemEncodingMMImm12(), getMemEncodingMMImm16(), getMemEncodingMMImm4(), getMemEncodingMMImm4Lsl1(), getMemEncodingMMImm4Lsl2(), getMemEncodingMMImm4sp(), getMemEncodingMMImm9(), getMemEncodingMMSPImm5Lsl2(), getSimm18Lsl3Encoding(), getSimm19Lsl2Encoding(), getSizeInsEncoding(), getUImm5Lsl2Encoding(), and getUImmWithOffsetEncoding().
unsigned MipsMCCodeEmitter::getMemEncoding | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Return binary encoding of memory related operand.
If the offset operand requires relocation, record the relocation.
Definition at line 743 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), and MI.
unsigned MipsMCCodeEmitter::getMemEncodingMMGPImm7Lsl2 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 815 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), and MI.
unsigned MipsMCCodeEmitter::getMemEncodingMMImm11 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 844 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), and MI.
unsigned MipsMCCodeEmitter::getMemEncodingMMImm12 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 857 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), and MI.
unsigned MipsMCCodeEmitter::getMemEncodingMMImm16 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 881 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), and MI.
unsigned MipsMCCodeEmitter::getMemEncodingMMImm4 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 758 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), and MI.
unsigned MipsMCCodeEmitter::getMemEncodingMMImm4Lsl1 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 772 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), and MI.
unsigned MipsMCCodeEmitter::getMemEncodingMMImm4Lsl2 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 786 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), and MI.
unsigned MipsMCCodeEmitter::getMemEncodingMMImm4sp | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 894 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), and MI.
unsigned MipsMCCodeEmitter::getMemEncodingMMImm9 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 830 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), and MI.
unsigned MipsMCCodeEmitter::getMemEncodingMMSPImm5Lsl2 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 800 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), and MI.
unsigned MipsMCCodeEmitter::getMovePRegPairOpValue | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 1054 of file MipsMCCodeEmitter.cpp.
References MI.
Referenced by encodeInstruction().
unsigned MipsMCCodeEmitter::getMovePRegSingleOpValue | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 1088 of file MipsMCCodeEmitter.cpp.
References assert(), llvm_unreachable, and MI.
unsigned llvm::MipsMCCodeEmitter::getMSAMemEncoding | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
unsigned MipsMCCodeEmitter::getRegisterListOpValue | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 1027 of file MipsMCCodeEmitter.cpp.
References llvm::MCRegisterInfo::getEncodingValue(), llvm::MCContext::getRegisterInfo(), I, and MI.
unsigned MipsMCCodeEmitter::getRegisterListOpValue16 | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 1047 of file MipsMCCodeEmitter.cpp.
References MI.
unsigned MipsMCCodeEmitter::getSimm18Lsl3Encoding | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 968 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCFixup::create(), llvm::Mips::fixup_MICROMIPS_PC18_S3, llvm::Mips::fixup_MIPS_PC18_S3, llvm::MCOperand::getExpr(), getMachineOpValue(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getSimm19Lsl2Encoding | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 946 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCFixup::create(), llvm::Mips::fixup_MICROMIPS_PC19_S2, llvm::Mips::fixup_MIPS_PC19_S2, llvm::MCOperand::getExpr(), getMachineOpValue(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getSimm23Lsl2Encoding | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 1111 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCOperand::getImm(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getSImm3Lsa2Value | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 539 of file MipsMCCodeEmitter.cpp.
References llvm::MCOperand::getImm(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getSImm9AddiuspValue | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 565 of file MipsMCCodeEmitter.cpp.
References llvm::MCOperand::getImm(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getSizeInsEncoding | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 923 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), MI, and Size.
unsigned MipsMCCodeEmitter::getUImm3Mod8Encoding | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 990 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCOperand::getImm(), and MI.
unsigned MipsMCCodeEmitter::getUImm4AndValue | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 999 of file MipsMCCodeEmitter.cpp.
References assert(), llvm::MCOperand::getImm(), llvm_unreachable, and MI.
unsigned MipsMCCodeEmitter::getUImm5Lsl2Encoding | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 521 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), llvm::MCOperand::isExpr(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getUImm6Lsl2Encoding | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Definition at line 552 of file MipsMCCodeEmitter.cpp.
References llvm::MCOperand::getImm(), llvm::MCOperand::isImm(), and MI.
unsigned MipsMCCodeEmitter::getUImmWithOffsetEncoding | ( | const MCInst & | MI, |
unsigned | OpNo, | ||
SmallVectorImpl< MCFixup > & | Fixups, | ||
const MCSubtargetInfo & | STI | ||
) | const |
Subtract Offset then encode as a N-bit unsigned integer.
Definition at line 936 of file MipsMCCodeEmitter.cpp.
References assert(), getMachineOpValue(), MI, and llvm::Offset.
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delete |