LLVM 22.0.0git
RISCVDisassembler.cpp
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1//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISCVDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/RISCVBaseInfo.h"
14#include "MCTargetDesc/RISCVMCTargetDesc.h"
15#include "TargetInfo/RISCVTargetInfo.h"
16#include "llvm/MC/MCContext.h"
17#include "llvm/MC/MCDecoder.h"
18#include "llvm/MC/MCDecoderOps.h"
19#include "llvm/MC/MCDisassembler/MCDisassembler.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/Compiler.h"
26#include "llvm/Support/Endian.h"
27
28using namespace llvm;
29using namespace llvm::MCD;
30
31#define DEBUG_TYPE "riscv-disassembler"
32
33typedef MCDisassembler::DecodeStatus DecodeStatus;
34
35namespace {
36class RISCVDisassembler : public MCDisassembler {
37 std::unique_ptr<MCInstrInfo const> const MCII;
38
39public:
40 RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
41 MCInstrInfo const *MCII)
42 : MCDisassembler(STI, Ctx), MCII(MCII) {}
43
44 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
45 ArrayRef<uint8_t> Bytes, uint64_t Address,
46 raw_ostream &CStream) const override;
47
48private:
49 DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
50 ArrayRef<uint8_t> Bytes, uint64_t Address,
51 raw_ostream &CStream) const;
52
53 DecodeStatus getInstruction32(MCInst &Instr, uint64_t &Size,
54 ArrayRef<uint8_t> Bytes, uint64_t Address,
55 raw_ostream &CStream) const;
56 DecodeStatus getInstruction16(MCInst &Instr, uint64_t &Size,
57 ArrayRef<uint8_t> Bytes, uint64_t Address,
58 raw_ostream &CStream) const;
59};
60} // end anonymous namespace
61
62static MCDisassembler *createRISCVDisassembler(const Target &T,
63 const MCSubtargetInfo &STI,
64 MCContext &Ctx) {
65 return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
66}
67
68extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
80
81static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
82 uint64_t Address,
83 const MCDisassembler *Decoder) {
84 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
85
86 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
87 return MCDisassembler::Fail;
88
89 MCRegister Reg = RISCV::X0 + RegNo;
90 Inst.addOperand(MCOperand::createReg(Reg));
91 return MCDisassembler::Success;
92}
93
94static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint32_t RegNo,
95 uint64_t Address,
96 const MCDisassembler *Decoder) {
97 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
98
99 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
100 return MCDisassembler::Fail;
101
102 MCRegister Reg = RISCV::X0_H + RegNo;
103 Inst.addOperand(MCOperand::createReg(Reg));
104 return MCDisassembler::Success;
105}
106
107static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint32_t RegNo,
108 uint64_t Address,
109 const MCDisassembler *Decoder) {
110 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
111
112 if (RegNo >= 32 || (IsRVE && RegNo >= 16))
113 return MCDisassembler::Fail;
114
115 MCRegister Reg = RISCV::X0_W + RegNo;
116 Inst.addOperand(MCOperand::createReg(Reg));
117 return MCDisassembler::Success;
118}
119
120static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
121 uint64_t Address,
122 const MCDisassembler *Decoder) {
123 MCRegister Reg = RISCV::X0 + RegNo;
124 if (Reg != RISCV::X1 && Reg != RISCV::X5)
125 return MCDisassembler::Fail;
126
127 Inst.addOperand(MCOperand::createReg(Reg));
128 return MCDisassembler::Success;
129}
130
131static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
132 uint64_t Address,
133 const MCDisassembler *Decoder) {
134 if (RegNo >= 32)
135 return MCDisassembler::Fail;
136
137 MCRegister Reg = RISCV::F0_H + RegNo;
138 Inst.addOperand(MCOperand::createReg(Reg));
139 return MCDisassembler::Success;
140}
141
142static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo,
143 uint64_t Address,
144 const MCDisassembler *Decoder) {
145 if (RegNo >= 32)
146 return MCDisassembler::Fail;
147
148 MCRegister Reg = RISCV::F0_F + RegNo;
149 Inst.addOperand(MCOperand::createReg(Reg));
150 return MCDisassembler::Success;
151}
152
153static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo,
154 uint64_t Address,
155 const MCDisassembler *Decoder) {
156 if (RegNo >= 8) {
157 return MCDisassembler::Fail;
158 }
159 MCRegister Reg = RISCV::F8_F + RegNo;
160 Inst.addOperand(MCOperand::createReg(Reg));
161 return MCDisassembler::Success;
162}
163
164static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo,
165 uint64_t Address,
166 const MCDisassembler *Decoder) {
167 if (RegNo >= 32)
168 return MCDisassembler::Fail;
169
170 MCRegister Reg = RISCV::F0_D + RegNo;
171 Inst.addOperand(MCOperand::createReg(Reg));
172 return MCDisassembler::Success;
173}
174
175static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo,
176 uint64_t Address,
177 const MCDisassembler *Decoder) {
178 if (RegNo >= 8) {
179 return MCDisassembler::Fail;
180 }
181 MCRegister Reg = RISCV::F8_D + RegNo;
182 Inst.addOperand(MCOperand::createReg(Reg));
183 return MCDisassembler::Success;
184}
185
186static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo,
187 uint64_t Address,
188 const MCDisassembler *Decoder) {
189 if (RegNo >= 32)
190 return MCDisassembler::Fail;
191
192 MCRegister Reg = RISCV::F0_Q + RegNo;
193 Inst.addOperand(MCOperand::createReg(Reg));
194 return MCDisassembler::Success;
195}
196
197static DecodeStatus DecodeSPRegisterClass(MCInst &Inst,
198 const MCDisassembler *Decoder) {
199 Inst.addOperand(MCOperand::createReg(RISCV::X2));
200 return MCDisassembler::Success;
201}
202
203static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
204 uint64_t Address,
205 const MCDisassembler *Decoder) {
206 if (RegNo == 0)
207 return MCDisassembler::Fail;
208
209 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
210}
211
212static DecodeStatus DecodeGPRNoX2RegisterClass(MCInst &Inst, uint64_t RegNo,
213 uint32_t Address,
214 const MCDisassembler *Decoder) {
215 if (RegNo == 2)
216 return MCDisassembler::Fail;
217
218 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
219}
220
221static DecodeStatus DecodeGPRNoX31RegisterClass(MCInst &Inst, uint32_t RegNo,
222 uint64_t Address,
223 const MCDisassembler *Decoder) {
224 if (RegNo == 31) {
225 return MCDisassembler::Fail;
226 }
227
228 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
229}
230
231static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
232 uint64_t Address,
233 const MCDisassembler *Decoder) {
234 if (RegNo >= 8)
235 return MCDisassembler::Fail;
236
237 MCRegister Reg = RISCV::X8 + RegNo;
238 Inst.addOperand(MCOperand::createReg(Reg));
239 return MCDisassembler::Success;
240}
241
242static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
243 uint64_t Address,
244 const MCDisassembler *Decoder) {
245 if (RegNo >= 32 || RegNo % 2)
246 return MCDisassembler::Fail;
247
248 const RISCVDisassembler *Dis =
249 static_cast<const RISCVDisassembler *>(Decoder);
250 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
251 MCRegister Reg = RI->getMatchingSuperReg(
252 RISCV::X0 + RegNo, RISCV::sub_gpr_even,
253 &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
254 Inst.addOperand(MCOperand::createReg(Reg));
255 return MCDisassembler::Success;
256}
257
258static DecodeStatus DecodeGPRPairCRegisterClass(MCInst &Inst, uint32_t RegNo,
259 uint64_t Address,
260 const MCDisassembler *Decoder) {
261 if (RegNo >= 8 || RegNo % 2)
262 return MCDisassembler::Fail;
263
264 const RISCVDisassembler *Dis =
265 static_cast<const RISCVDisassembler *>(Decoder);
266 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
267 MCRegister Reg = RI->getMatchingSuperReg(
268 RISCV::X8 + RegNo, RISCV::sub_gpr_even,
269 &RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID]);
270 Inst.addOperand(MCOperand::createReg(Reg));
271 return MCDisassembler::Success;
272}
273
274static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo,
275 uint64_t Address,
276 const void *Decoder) {
277 if (RegNo >= 8)
278 return MCDisassembler::Fail;
279
280 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
281 Inst.addOperand(MCOperand::createReg(Reg));
282 return MCDisassembler::Success;
283}
284
285static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
286 uint64_t Address,
287 const MCDisassembler *Decoder) {
288 if (RegNo >= 32)
289 return MCDisassembler::Fail;
290
291 MCRegister Reg = RISCV::V0 + RegNo;
292 Inst.addOperand(MCOperand::createReg(Reg));
293 return MCDisassembler::Success;
294}
295
296static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
297 uint64_t Address,
298 const MCDisassembler *Decoder) {
299 if (RegNo >= 32 || RegNo % 2)
300 return MCDisassembler::Fail;
301
302 const RISCVDisassembler *Dis =
303 static_cast<const RISCVDisassembler *>(Decoder);
304 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
305 MCRegister Reg =
306 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
307 &RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
308
309 Inst.addOperand(MCOperand::createReg(Reg));
310 return MCDisassembler::Success;
311}
312
313static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
314 uint64_t Address,
315 const MCDisassembler *Decoder) {
316 if (RegNo >= 32 || RegNo % 4)
317 return MCDisassembler::Fail;
318
319 const RISCVDisassembler *Dis =
320 static_cast<const RISCVDisassembler *>(Decoder);
321 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
322 MCRegister Reg =
323 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
324 &RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
325
326 Inst.addOperand(MCOperand::createReg(Reg));
327 return MCDisassembler::Success;
328}
329
330static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
331 uint64_t Address,
332 const MCDisassembler *Decoder) {
333 if (RegNo >= 32 || RegNo % 8)
334 return MCDisassembler::Fail;
335
336 const RISCVDisassembler *Dis =
337 static_cast<const RISCVDisassembler *>(Decoder);
338 const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
339 MCRegister Reg =
340 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
341 &RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
342
343 Inst.addOperand(MCOperand::createReg(Reg));
344 return MCDisassembler::Success;
345}
346
347static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo,
348 uint64_t Address,
349 const MCDisassembler *Decoder) {
350 if (RegNo)
351 return MCDisassembler::Fail;
352
353 Inst.addOperand(MCOperand::createReg(RISCV::V0));
354 return MCDisassembler::Success;
355}
356
357static DecodeStatus DecodeTRRegisterClass(MCInst &Inst, uint32_t RegNo,
358 uint64_t Address,
359 const MCDisassembler *Decoder) {
360 if (RegNo > 15)
361 return MCDisassembler::Fail;
362
363 MCRegister Reg = RISCV::T0 + RegNo;
364 Inst.addOperand(MCOperand::createReg(Reg));
365 return MCDisassembler::Success;
366}
367
368static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
369 uint64_t Address,
370 const MCDisassembler *Decoder) {
371 if (RegNo > 15 || RegNo % 2)
372 return MCDisassembler::Fail;
373
374 MCRegister Reg = RISCV::T0 + RegNo;
375 Inst.addOperand(MCOperand::createReg(Reg));
376 return MCDisassembler::Success;
377}
378
379static DecodeStatus DecodeTRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
380 uint64_t Address,
381 const MCDisassembler *Decoder) {
382 if (RegNo > 15 || RegNo % 4)
383 return MCDisassembler::Fail;
384
385 MCRegister Reg = RISCV::T0 + RegNo;
386 Inst.addOperand(MCOperand::createReg(Reg));
387 return MCDisassembler::Success;
388}
389
390static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo,
391 uint64_t Address,
392 const MCDisassembler *Decoder) {
393 if (RegNo >= 2)
394 return MCDisassembler::Fail;
395
396 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
397
398 Inst.addOperand(MCOperand::createReg(Reg));
399 return MCDisassembler::Success;
400}
401
402template <unsigned N>
403static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
404 int64_t Address,
405 const MCDisassembler *Decoder) {
406 assert(isUInt<N>(Imm) && "Invalid immediate");
407 Inst.addOperand(MCOperand::createImm(Imm));
408 return MCDisassembler::Success;
409}
410
411template <unsigned Width, unsigned LowerBound>
412static DecodeStatus decodeUImmOperandGE(MCInst &Inst, uint32_t Imm,
413 int64_t Address,
414 const MCDisassembler *Decoder) {
415 assert(isUInt<Width>(Imm) && "Invalid immediate");
416
417 if (Imm < LowerBound)
418 return MCDisassembler::Fail;
419
420 Inst.addOperand(MCOperand::createImm(Imm));
421 return MCDisassembler::Success;
422}
423
424template <unsigned Width, unsigned LowerBound>
425static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm,
426 int64_t Address,
427 const MCDisassembler *Decoder) {
428 assert(isUInt<Width>(Imm) && "Invalid immediate");
429
430 if ((Imm + 1) < LowerBound)
431 return MCDisassembler::Fail;
432
433 Inst.addOperand(MCOperand::createImm(Imm + 1));
434 return MCDisassembler::Success;
435}
436
437static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm,
438 int64_t Address,
439 const MCDisassembler *Decoder) {
440 assert(isUInt<3>(Imm) && "Invalid Slist immediate");
441 const uint8_t Slist[] = {0, 1, 2, 4, 8, 16, 15, 31};
442 Inst.addOperand(MCOperand::createImm(Slist[Imm]));
443 return MCDisassembler::Success;
444}
445
446static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
447 int64_t Address,
448 const MCDisassembler *Decoder) {
449 assert(isUInt<6>(Imm) && "Invalid immediate");
450
451 if (!Decoder->getSubtargetInfo().hasFeature(RISCV::Feature64Bit) &&
452 !isUInt<5>(Imm))
453 return MCDisassembler::Fail;
454
455 Inst.addOperand(MCOperand::createImm(Imm));
456 return MCDisassembler::Success;
457}
458
459template <unsigned N>
460static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
461 int64_t Address,
462 const MCDisassembler *Decoder) {
463 if (Imm == 0)
464 return MCDisassembler::Fail;
465 return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
466}
467
468static DecodeStatus
469decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address,
470 const MCDisassembler *Decoder) {
471 if (Imm == 0)
472 return MCDisassembler::Fail;
473 return decodeUImmLog2XLenOperand(Inst, Imm, Address, Decoder);
474}
475
476template <unsigned N>
477static DecodeStatus decodeUImmPlus1Operand(MCInst &Inst, uint32_t Imm,
478 int64_t Address,
479 const MCDisassembler *Decoder) {
480 assert(isUInt<N>(Imm) && "Invalid immediate");
481 Inst.addOperand(MCOperand::createImm(Imm + 1));
482 return MCDisassembler::Success;
483}
484
485template <unsigned N>
486static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
487 int64_t Address,
488 const MCDisassembler *Decoder) {
489 assert(isUInt<N>(Imm) && "Invalid immediate");
490 // Sign-extend the number in the bottom N bits of Imm
491 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
492 return MCDisassembler::Success;
493}
494
495template <unsigned N>
496static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
497 int64_t Address,
498 const MCDisassembler *Decoder) {
499 if (Imm == 0)
500 return MCDisassembler::Fail;
501 return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
502}
503
504template <unsigned T, unsigned N>
505static DecodeStatus decodeSImmOperandAndLslN(MCInst &Inst, uint32_t Imm,
506 int64_t Address,
507 const MCDisassembler *Decoder) {
508 assert(isUInt<T - N + 1>(Imm) && "Invalid immediate");
509 // Sign-extend the number in the bottom T bits of Imm after accounting for
510 // the fact that the T bit immediate is stored in T-N bits (the LSB is
511 // always zero)
512 Inst.addOperand(MCOperand::createImm(SignExtend64<T>(Imm << N)));
513 return MCDisassembler::Success;
514}
515
516static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm,
517 int64_t Address,
518 const MCDisassembler *Decoder) {
519 assert(isUInt<6>(Imm) && "Invalid immediate");
520 if (Imm == 0)
521 return MCDisassembler::Fail;
522 Imm = SignExtend64<6>(Imm) & 0xfffff;
523 Inst.addOperand(MCOperand::createImm(Imm));
524 return MCDisassembler::Success;
525}
526
527static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
528 const MCDisassembler *Decoder) {
529 assert(isUInt<3>(Imm) && "Invalid immediate");
530 if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
531 return MCDisassembler::Fail;
532
533 Inst.addOperand(MCOperand::createImm(Imm));
534 return MCDisassembler::Success;
535}
536
537static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
538 const MCDisassembler *Decoder) {
539 assert(isUInt<3>(Imm) && "Invalid immediate");
540 if (Imm != RISCVFPRndMode::RTZ)
541 return MCDisassembler::Fail;
542
543 Inst.addOperand(MCOperand::createImm(Imm));
544 return MCDisassembler::Success;
545}
546
547static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
548 uint64_t Address,
549 const MCDisassembler *Decoder) {
550 bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
551 if (Imm < RISCVZC::RA || (IsRVE && Imm >= RISCVZC::RA_S0_S2))
552 return MCDisassembler::Fail;
553 Inst.addOperand(MCOperand::createImm(Imm));
554 return MCDisassembler::Success;
555}
556
557static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
558 uint64_t Address,
559 const MCDisassembler *Decoder) {
560 if (Imm < RISCVZC::RA_S0)
561 return MCDisassembler::Fail;
562 return decodeZcmpRlist(Inst, Imm, Address, Decoder);
563}
564
565static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint16_t Insn,
566 uint64_t Address,
567 const MCDisassembler *Decoder) {
568 uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5);
569 [[maybe_unused]] DecodeStatus Result =
570 DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
571 assert(Result == MCDisassembler::Success && "Invalid register");
572 return MCDisassembler::Success;
573}
574
575static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
576 uint64_t Address,
577 const MCDisassembler *Decoder) {
578 DecodeStatus S = MCDisassembler::Success;
579 uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5);
580 uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5);
581 uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5);
582 uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2);
583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder)))
584 return MCDisassembler::Fail;
585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder)))
586 return MCDisassembler::Fail;
587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder)))
588 return MCDisassembler::Fail;
589 [[maybe_unused]] DecodeStatus Result =
590 decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
591 assert(Result == MCDisassembler::Success && "Invalid immediate");
592
593 // Disassemble the final operand which is implicit.
594 unsigned Opcode = Inst.getOpcode();
595 bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
596 Opcode == RISCV::TH_SWD);
597 if (IsWordOp)
598 Inst.addOperand(MCOperand::createImm(3));
599 else
600 Inst.addOperand(MCOperand::createImm(4));
601
602 return S;
603}
604
605#include "RISCVGenDisassemblerTables.inc"
606
607namespace {
608
609struct DecoderListEntry {
610 const uint8_t *Table;
611 FeatureBitset ContainedFeatures;
612 const char *Desc;
613
614 bool haveContainedFeatures(const FeatureBitset &ActiveFeatures) const {
615 return ContainedFeatures.none() ||
616 (ContainedFeatures & ActiveFeatures).any();
617 }
618};
619
620} // end anonymous namespace
621
622static constexpr FeatureBitset XCVFeatureGroup = {
623 RISCV::FeatureVendorXCVbitmanip, RISCV::FeatureVendorXCVelw,
624 RISCV::FeatureVendorXCVmac, RISCV::FeatureVendorXCVmem,
625 RISCV::FeatureVendorXCValu, RISCV::FeatureVendorXCVsimd,
626 RISCV::FeatureVendorXCVbi};
627
628static constexpr FeatureBitset XRivosFeatureGroup = {
629 RISCV::FeatureVendorXRivosVisni,
630 RISCV::FeatureVendorXRivosVizip,
631};
632
633static constexpr FeatureBitset XqciFeatureGroup = {
634 RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
635 RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
636 RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
637 RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
638 RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqciio,
639 RISCV::FeatureVendorXqcilb, RISCV::FeatureVendorXqcili,
640 RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
641 RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisim,
642 RISCV::FeatureVendorXqcisls, RISCV::FeatureVendorXqcisync,
643};
644
645static constexpr FeatureBitset XSfVectorGroup = {
646 RISCV::FeatureVendorXSfvcp, RISCV::FeatureVendorXSfvqmaccdod,
647 RISCV::FeatureVendorXSfvqmaccqoq, RISCV::FeatureVendorXSfvfwmaccqqq,
648 RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase};
649static constexpr FeatureBitset XSfSystemGroup = {
650 RISCV::FeatureVendorXSiFivecdiscarddlone,
651 RISCV::FeatureVendorXSiFivecflushdlone,
652};
653
654static constexpr FeatureBitset XMIPSGroup = {
655 RISCV::FeatureVendorXMIPSLSP,
656 RISCV::FeatureVendorXMIPSCMov,
657 RISCV::FeatureVendorXMIPSCBOP,
658 RISCV::FeatureVendorXMIPSEXECTL,
659};
660
661static constexpr FeatureBitset XTHeadGroup = {
662 RISCV::FeatureVendorXTHeadBa, RISCV::FeatureVendorXTHeadBb,
663 RISCV::FeatureVendorXTHeadBs, RISCV::FeatureVendorXTHeadCondMov,
664 RISCV::FeatureVendorXTHeadCmo, RISCV::FeatureVendorXTHeadFMemIdx,
665 RISCV::FeatureVendorXTHeadMac, RISCV::FeatureVendorXTHeadMemIdx,
666 RISCV::FeatureVendorXTHeadMemPair, RISCV::FeatureVendorXTHeadSync,
667 RISCV::FeatureVendorXTHeadVdot};
668
669static constexpr FeatureBitset XAndesGroup = {
670 RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt,
671 RISCV::FeatureVendorXAndesVBFHCvt,
672 RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,
673 RISCV::FeatureVendorXAndesVDot};
674
675static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot};
676
677static constexpr DecoderListEntry DecoderList32[]{
678 // Vendor Extensions
679 {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
680 {DecoderTableXRivos32, XRivosFeatureGroup, "Rivos"},
681 {DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
682 {DecoderTableXVentana32,
683 {RISCV::FeatureVendorXVentanaCondOps},
684 "XVentanaCondOps"},
685 {DecoderTableXTHead32, XTHeadGroup, "T-Head extensions"},
686 {DecoderTableXSfvector32, XSfVectorGroup, "SiFive vector extensions"},
687 {DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},
688 {DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive sf.cease"},
689 {DecoderTableXMIPS32, XMIPSGroup, "Mips extensions"},
690 {DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
691 {DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
692 // Standard Extensions
693 {DecoderTable32, {}, "standard 32-bit instructions"},
694 {DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
695 {DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
696 {DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
697};
698
699namespace {
700// Define bitwidths for various types used to instantiate the decoder.
701template <> constexpr uint32_t InsnBitWidth<uint16_t> = 16;
702template <> constexpr uint32_t InsnBitWidth<uint32_t> = 32;
703// Use uint64_t to represent 48 bit instructions.
704template <> constexpr uint32_t InsnBitWidth<uint64_t> = 48;
705} // namespace
706
707DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
708 ArrayRef<uint8_t> Bytes,
709 uint64_t Address,
710 raw_ostream &CS) const {
711 if (Bytes.size() < 4) {
712 Size = 0;
713 return MCDisassembler::Fail;
714 }
715 Size = 4;
716
717 uint32_t Insn = support::endian::read32le(Bytes.data());
718
719 for (const DecoderListEntry &Entry : DecoderList32) {
720 if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
721 continue;
722
723 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
724 DecodeStatus Result =
725 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
726 if (Result == MCDisassembler::Fail)
727 continue;
728
729 return Result;
730 }
731
732 return MCDisassembler::Fail;
733}
734
735static constexpr DecoderListEntry DecoderList16[]{
736 // Vendor Extensions
737 {DecoderTableXqci16, XqciFeatureGroup, "Qualcomm uC 16-bit"},
738 {DecoderTableXqccmp16,
739 {RISCV::FeatureVendorXqccmp},
740 "Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"},
741 {DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"},
742 // Standard Extensions
743 // DecoderTableZicfiss16 must be checked before DecoderTable16.
744 {DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},
745 {DecoderTable16, {}, "standard 16-bit instructions"},
746 {DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
747 // Zc* instructions incompatible with Zcf or Zcd
748 {DecoderTableZcOverlap16,
749 {},
750 "ZcOverlap (16-bit Instructions overlapping with Zcf/Zcd)"},
751};
752
753DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
754 ArrayRef<uint8_t> Bytes,
755 uint64_t Address,
756 raw_ostream &CS) const {
757 if (Bytes.size() < 2) {
758 Size = 0;
759 return MCDisassembler::Fail;
760 }
761 Size = 2;
762
763 uint16_t Insn = support::endian::read16le(Bytes.data());
764
765 for (const DecoderListEntry &Entry : DecoderList16) {
766 if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
767 continue;
768
769 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
770 DecodeStatus Result =
771 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
772 if (Result != MCDisassembler::Fail)
773 return Result;
774 }
775
776 return MCDisassembler::Fail;
777}
778
779static constexpr DecoderListEntry DecoderList48[]{
780 {DecoderTableXqci48, XqciFeatureGroup, "Qualcomm uC 48bit"},
781};
782
783DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
784 ArrayRef<uint8_t> Bytes,
785 uint64_t Address,
786 raw_ostream &CS) const {
787 if (Bytes.size() < 6) {
788 Size = 0;
789 return MCDisassembler::Fail;
790 }
791 Size = 6;
792
793 uint64_t Insn = 0;
794 for (size_t i = Size; i-- != 0;)
795 Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
796
797 for (const DecoderListEntry &Entry : DecoderList48) {
798 if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
799 continue;
800
801 LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
802 DecodeStatus Result =
803 decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
804 if (Result == MCDisassembler::Fail)
805 continue;
806
807 return Result;
808 }
809
810 return MCDisassembler::Fail;
811}
812
813DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
814 ArrayRef<uint8_t> Bytes,
815 uint64_t Address,
816 raw_ostream &CS) const {
817 CommentStream = &CS;
818 // It's a 16 bit instruction if bit 0 and 1 are not 0b11.
819 if ((Bytes[0] & 0b11) != 0b11)
820 return getInstruction16(MI, Size, Bytes, Address, CS);
821
822 // It's a 32 bit instruction if bit 1:0 are 0b11(checked above) and bits 4:2
823 // are not 0b111.
824 if ((Bytes[0] & 0b1'1100) != 0b1'1100)
825 return getInstruction32(MI, Size, Bytes, Address, CS);
826
827 // 48-bit instructions are encoded as 0bxx011111.
828 if ((Bytes[0] & 0b11'1111) == 0b01'1111) {
829 return getInstruction48(MI, Size, Bytes, Address, CS);
830 }
831
832 // 64-bit instructions are encoded as 0x0111111.
833 if ((Bytes[0] & 0b111'1111) == 0b011'1111) {
834 Size = Bytes.size() >= 8 ? 8 : 0;
835 return MCDisassembler::Fail;
836 }
837
838 // Remaining cases need to check a second byte.
839 if (Bytes.size() < 2) {
840 Size = 0;
841 return MCDisassembler::Fail;
842 }
843
844 // 80-bit through 176-bit instructions are encoded as 0bxnnnxxxx_x1111111.
845 // Where the number of bits is (80 + (nnn * 16)) for nnn != 0b111.
846 unsigned nnn = (Bytes[1] >> 4) & 0b111;
847 if (nnn != 0b111) {
848 Size = 10 + (nnn * 2);
849 if (Bytes.size() < Size)
850 Size = 0;
851 return MCDisassembler::Fail;
852 }
853
854 // Remaining encodings are reserved for > 176-bit instructions.
855 Size = 0;
856 return MCDisassembler::Fail;
857}
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition AArch64Disassembler.cpp:36
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
LLVM_ABI
#define LLVM_ABI
Definition Compiler.h:213
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
Check
#define Check(C,...)
Definition GenericConvergenceVerifierImpl.h:34
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
Reg
Register Reg
Definition MachineSink.cpp:2117
T
#define T
Definition Mips16ISelLowering.cpp:353
XqciFeatureGroup
static constexpr FeatureBitset XqciFeatureGroup
Definition RISCVDisassembler.cpp:633
decodeUImmSlistOperand
static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:437
XSMTGroup
static constexpr FeatureBitset XSMTGroup
Definition RISCVDisassembler.cpp:675
decodeUImmLog2XLenOperand
static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:446
XCVFeatureGroup
static constexpr FeatureBitset XCVFeatureGroup
Definition RISCVDisassembler.cpp:622
DecoderList48
static constexpr DecoderListEntry DecoderList48[]
Definition RISCVDisassembler.cpp:779
decodeSImmOperand
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:486
DecoderList16
static constexpr DecoderListEntry DecoderList16[]
Definition RISCVDisassembler.cpp:735
DecodeGPRX1X5RegisterClass
static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:120
DecodeGPRNoX31RegisterClass
static DecodeStatus DecodeGPRNoX31RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:221
DecodeGPRCRegisterClass
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:231
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:164
decodeUImmLog2XLenNonZeroOperand
static DecodeStatus decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:469
decodeCSSPushPopchk
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint16_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:565
decodeRTZArg
static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:537
createRISCVDisassembler
static MCDisassembler * createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition RISCVDisassembler.cpp:62
DecodeGPRF16RegisterClass
static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:94
DecodeTRM2RegisterClass
static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:368
DecodeFPR128RegisterClass
static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:186
decodeSImmOperandAndLslN
static DecodeStatus decodeSImmOperandAndLslN(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:505
XSfVectorGroup
static constexpr FeatureBitset XSfVectorGroup
Definition RISCVDisassembler.cpp:645
DecoderList32
static constexpr DecoderListEntry DecoderList32[]
Definition RISCVDisassembler.cpp:677
decodeXqccmpRlistS0
static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:557
DecodeFPR32CRegisterClass
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:153
decodeXTHeadMemPair
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:575
decodeUImmPlus1Operand
static DecodeStatus decodeUImmPlus1Operand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:477
decodeCLUIImmOperand
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:516
decodeZcmpRlist
static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:547
decodeUImmOperand
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:403
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:142
DecodeVRM8RegisterClass
static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:330
DecodeVRM4RegisterClass
static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:313
DecodeGPRNoX2RegisterClass
static DecodeStatus DecodeGPRNoX2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:212
DecodeVRRegisterClass
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:285
DecodeVRM2RegisterClass
static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:296
DecodeGPRPairRegisterClass
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:242
DecodeSPRegisterClass
static DecodeStatus DecodeSPRegisterClass(MCInst &Inst, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:197
XMIPSGroup
static constexpr FeatureBitset XMIPSGroup
Definition RISCVDisassembler.cpp:654
decodeSImmNonZeroOperand
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:496
DecodeVMV0RegisterClass
static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:347
DecodeTRRegisterClass
static DecodeStatus DecodeTRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:357
DecodeFPR64CRegisterClass
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:175
DecodeGPRF32RegisterClass
static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:107
XAndesGroup
static constexpr FeatureBitset XAndesGroup
Definition RISCVDisassembler.cpp:669
DecodeTRM4RegisterClass
static DecodeStatus DecodeTRM4RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:379
DecodeGPRNoX0RegisterClass
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:203
decodeFRMArg
static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:527
DecodeSR07RegisterClass
static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const void *Decoder)
Definition RISCVDisassembler.cpp:274
XTHeadGroup
static constexpr FeatureBitset XTHeadGroup
Definition RISCVDisassembler.cpp:661
XRivosFeatureGroup
static constexpr FeatureBitset XRivosFeatureGroup
Definition RISCVDisassembler.cpp:628
decodeUImmPlus1OperandGE
static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:425
LLVMInitializeRISCVDisassembler
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler()
Definition RISCVDisassembler.cpp:69
DecodeFPR16RegisterClass
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:131
DecodeGPRRegisterClass
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:81
decodeVMaskReg
static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:390
decodeUImmNonZeroOperand
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:460
XSfSystemGroup
static constexpr FeatureBitset XSfSystemGroup
Definition RISCVDisassembler.cpp:649
decodeUImmOperandGE
static DecodeStatus decodeUImmOperandGE(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:412
DecodeGPRPairCRegisterClass
static DecodeStatus DecodeGPRPairCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition RISCVDisassembler.cpp:258
LLVM_DEBUG
#define LLVM_DEBUG(...)
Definition Debug.h:119
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition ArrayRef.h:147
llvm::ArrayRef::data
const T * data() const
Definition ArrayRef.h:144
llvm::FeatureBitset
Container class for subtarget features.
Definition SubtargetFeature.h:42
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition MCDisassembler.h:85
llvm::MCDisassembler::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Definition MCDisassembler.h:230
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition MCDisassembler.h:109
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition MCInst.h:202
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition MCInst.h:215
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition MCRegisterInfo.h:150
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition MCRegisterInfo.cpp:108
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:77
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition MCSubtargetInfo.h:122
llvm::Target
Target - Wrapper for Target specific information.
Definition TargetRegistry.h:146
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint16_t
uint32_t
uint64_t
uint8_t
llvm::BitmaskEnumDetail::any
constexpr bool any(E Val)
Definition BitmaskEnum.h:151
llvm::COFF::Entry
@ Entry
Definition COFF.h:862
llvm::MCD::fieldFromInstruction
std::enable_if_t< std::is_integral_v< IntType >, IntType > fieldFromInstruction(const IntType &Insn, unsigned StartBit, unsigned NumBits)
Definition MCDecoder.h:37
llvm::RISCVFPRndMode::isValidRoundingMode
static bool isValidRoundingMode(unsigned Mode)
Definition RISCVBaseInfo.h:447
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
Definition MicrosoftDemangle.h:132
llvm::support::endian::read16le
uint16_t read16le(const void *P)
Definition Endian.h:426
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition Endian.h:429
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::getTheRISCV32Target
Target & getTheRISCV32Target()
Definition RISCVTargetInfo.cpp:14
llvm::getTheRISCV64beTarget
Target & getTheRISCV64beTarget()
Definition RISCVTargetInfo.cpp:29
llvm::dbgs
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:207
llvm::isUInt
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:198
llvm::getTheRISCV64Target
Target & getTheRISCV64Target()
Definition RISCVTargetInfo.cpp:19
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:577
llvm::getTheRISCV32beTarget
Target & getTheRISCV32beTarget()
Definition RISCVTargetInfo.cpp:24
N
#define N
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition TargetRegistry.h:934
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