RISCVTargetMachine.cpp File Reference

#include "RISCVTargetMachine.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVTargetObjectFile.h"
#include "RISCVTargetTransformInfo.h"
#include "TargetInfo/RISCVTargetInfo.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/MIRParser/MIParser.h"
#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Passes/PassBuilder.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/IPO.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Vectorize/LoopIdiomVectorize.h"
#include <optional>

Go to the source code of this file.

Functions
LLVM_EXTERNAL_VISIBILITY void	LLVMInitializeRISCVTarget ()
static StringRef	computeDataLayout (const Triple &TT, const TargetOptions &Options)
static Reloc::Model	getEffectiveRelocModel (const Triple &TT, std::optional< Reloc::Model > RM)

Variables
static cl::opt< bool >	EnableRedundantCopyElimination ("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< cl::boolOrDefault >	EnableGlobalMerge ("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
static cl::opt< bool >	EnableMachineCombiner ("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< unsigned >	RVVVectorBitsMaxOpt ("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< int >	RVVVectorBitsMinOpt ("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
static cl::opt< bool >	EnableRISCVCopyPropagation ("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)
static cl::opt< bool >	EnableRISCVDeadRegisterElimination ("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0"), cl::init(true))
static cl::opt< bool >	EnableSinkFold ("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
static cl::opt< bool >	EnableLoopDataPrefetch ("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
static cl::opt< bool >	EnableMISchedLoadClustering ("riscv-misched-load-clustering", cl::Hidden, cl::desc("Enable load clustering in the machine scheduler"), cl::init(false))
static cl::opt< bool >	EnableVSETVLIAfterRVVRegAlloc ("riscv-vsetvl-after-rvv-regalloc", cl::Hidden, cl::desc("Insert vsetvls after vector register allocation"), cl::init(true))

Function Documentation

computeDataLayout()

static StringRef computeDataLayout ( const Triple &  TT, const TargetOptions &  Options  )

static

Definition at line 133 of file RISCVTargetMachine.cpp.

References assert(), and Options.

getEffectiveRelocModel()

static Reloc::Model getEffectiveRelocModel ( const Triple &  TT, std::optional< Reloc::Model >  RM  )

static

Definition at line 150 of file RISCVTargetMachine.cpp.

References llvm::Reloc::Static.

LLVMInitializeRISCVTarget()

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget

(

)

Definition at line 106 of file RISCVTargetMachine.cpp.

References llvm::PassRegistry::getPassRegistry(), llvm::getTheRISCV32Target(), llvm::getTheRISCV64Target(), llvm::initializeGlobalISel(), llvm::initializeKCFIPass(), llvm::initializeRISCVCodeGenPreparePass(), llvm::initializeRISCVDAGToDAGISelLegacyPass(), llvm::initializeRISCVDeadRegisterDefinitionsPass(), llvm::initializeRISCVExpandPseudoPass(), llvm::initializeRISCVGatherScatterLoweringPass(), llvm::initializeRISCVInsertReadWriteCSRPass(), llvm::initializeRISCVInsertVSETVLIPass(), llvm::initializeRISCVInsertWriteVXRMPass(), llvm::initializeRISCVMakeCompressibleOptPass(), llvm::initializeRISCVMergeBaseOffsetOptPass(), llvm::initializeRISCVMoveMergePass(), llvm::initializeRISCVO0PreLegalizerCombinerPass(), llvm::initializeRISCVOptWInstrsPass(), llvm::initializeRISCVPostLegalizerCombinerPass(), llvm::initializeRISCVPostRAExpandPseudoPass(), llvm::initializeRISCVPreLegalizerCombinerPass(), llvm::initializeRISCVPreRAExpandPseudoPass(), llvm::initializeRISCVPushPopOptPass(), llvm::initializeRISCVVectorPeepholePass(), X, and Y.

Variable Documentation

EnableGlobalMerge

cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass")) ( "riscv-enable-global-merge"  , cl::Hidden  , cl::desc("Enable the global merge pass")    )

static

EnableLoopDataPrefetch

cl::opt< bool > EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true)) ( "riscv-enable-loop-data-prefetch"  , cl::Hidden  , cl::desc("Enable the loop data prefetch pass")  , cl::init(true)    )

static

EnableMachineCombiner

cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden) ( "riscv-enable-machine-combiner"  , cl::desc("Enable the machine combiner pass")  , cl::init(true)  , cl::Hidden    )

static

EnableMISchedLoadClustering

cl::opt< bool > EnableMISchedLoadClustering("riscv-misched-load-clustering", cl::Hidden, cl::desc("Enable load clustering in the machine scheduler"), cl::init(false)) ( "riscv-misched-load-clustering"  , cl::Hidden  , cl::desc("Enable load clustering in the machine scheduler")  , cl::init(false)    )

static

EnableRedundantCopyElimination

cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden) ( "riscv-enable-copyelim"  , cl::desc("Enable the redundant copy elimination pass")  , cl::init(true)  , cl::Hidden    )

static

EnableRISCVCopyPropagation

cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden) ( "riscv-enable-copy-propagation"  , cl::desc("Enable the copy propagation with RISC-V copy instr")  , cl::init(true)  , cl::Hidden    )

static

EnableRISCVDeadRegisterElimination

cl::opt< bool > EnableRISCVDeadRegisterElimination("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0"), cl::init(true)) ( "riscv-enable-dead-defs"  , cl::Hidden  , cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0")  , cl::init(true)    )

static

EnableSinkFold

cl::opt< bool > EnableSinkFold("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden) ( "riscv-enable-sink-fold"  , cl::desc("Enable sinking and folding of instruction copies")  , cl::init(true)  , cl::Hidden    )

static

EnableVSETVLIAfterRVVRegAlloc

cl::opt< bool > EnableVSETVLIAfterRVVRegAlloc("riscv-vsetvl-after-rvv-regalloc", cl::Hidden, cl::desc("Insert vsetvls after vector register allocation"), cl::init(true)) ( "riscv-vsetvl-after-rvv-regalloc"  , cl::Hidden  , cl::desc("Insert vsetvls after vector register allocation")  , cl::init(true)    )

static

RVVVectorBitsMaxOpt

cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden) ( "riscv-v-vector-bits-max"  , cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed.")  , cl::init(0)  , cl::Hidden    )

static

Referenced by llvm::RISCVTargetMachine::getSubtargetImpl().

RVVVectorBitsMinOpt

cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden) ( "riscv-v-vector-bits-min"  , cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors.")  , cl::init(-1)  , cl::Hidden    )

static

Referenced by llvm::RISCVTargetMachine::getSubtargetImpl().