LLVM 20.0.0git
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#include "RISCVTargetMachine.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVTargetObjectFile.h"
#include "RISCVTargetTransformInfo.h"
#include "TargetInfo/RISCVTargetInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/MIRParser/MIParser.h"
#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Passes/PassBuilder.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/IPO.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Vectorize/LoopIdiomVectorize.h"
#include <optional>
Go to the source code of this file.
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LLVM_EXTERNAL_VISIBILITY void | LLVMInitializeRISCVTarget () |
static StringRef | computeDataLayout (const Triple &TT, const TargetOptions &Options) |
static Reloc::Model | getEffectiveRelocModel (const Triple &TT, std::optional< Reloc::Model > RM) |
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static cl::opt< bool > | EnableRedundantCopyElimination ("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden) |
static cl::opt< cl::boolOrDefault > | EnableGlobalMerge ("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass")) |
static cl::opt< bool > | EnableMachineCombiner ("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden) |
static cl::opt< unsigned > | RVVVectorBitsMaxOpt ("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden) |
static cl::opt< int > | RVVVectorBitsMinOpt ("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden) |
static cl::opt< bool > | EnableRISCVCopyPropagation ("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden) |
static cl::opt< bool > | EnableRISCVDeadRegisterElimination ("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0"), cl::init(true)) |
static cl::opt< bool > | EnableSinkFold ("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden) |
static cl::opt< bool > | EnableLoopDataPrefetch ("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true)) |
static cl::opt< bool > | EnableMISchedLoadStoreClustering ("riscv-misched-load-store-clustering", cl::Hidden, cl::desc("Enable load and store clustering in the machine scheduler"), cl::init(true)) |
static cl::opt< bool > | EnablePostMISchedLoadStoreClustering ("riscv-postmisched-load-store-clustering", cl::Hidden, cl::desc("Enable PostRA load and store clustering in the machine scheduler"), cl::init(true)) |
static cl::opt< bool > | EnableVLOptimizer ("riscv-enable-vl-optimizer", cl::desc("Enable the RISC-V VL Optimizer pass"), cl::init(true), cl::Hidden) |
static cl::opt< bool > | DisableVectorMaskMutation ("riscv-disable-vector-mask-mutation", cl::desc("Disable the vector mask scheduling mutation"), cl::init(false), cl::Hidden) |
static cl::opt< bool > | EnableMachinePipeliner ("riscv-enable-pipeliner", cl::desc("Enable Machine Pipeliner for RISC-V"), cl::init(false), cl::Hidden) |
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Definition at line 148 of file RISCVTargetMachine.cpp.
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Definition at line 165 of file RISCVTargetMachine.cpp.
References llvm::Reloc::Static.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget | ( | ) |
Definition at line 120 of file RISCVTargetMachine.cpp.
References llvm::PassRegistry::getPassRegistry(), llvm::getTheRISCV32Target(), llvm::getTheRISCV64Target(), llvm::initializeGlobalISel(), llvm::initializeKCFIPass(), llvm::initializeRISCVCodeGenPreparePass(), llvm::initializeRISCVDAGToDAGISelLegacyPass(), llvm::initializeRISCVDeadRegisterDefinitionsPass(), llvm::initializeRISCVExpandPseudoPass(), llvm::initializeRISCVGatherScatterLoweringPass(), llvm::initializeRISCVInsertReadWriteCSRPass(), llvm::initializeRISCVInsertVSETVLIPass(), llvm::initializeRISCVInsertWriteVXRMPass(), llvm::initializeRISCVMakeCompressibleOptPass(), llvm::initializeRISCVMergeBaseOffsetOptPass(), llvm::initializeRISCVMoveMergePass(), llvm::initializeRISCVO0PreLegalizerCombinerPass(), llvm::initializeRISCVOptWInstrsPass(), llvm::initializeRISCVPostLegalizerCombinerPass(), llvm::initializeRISCVPostRAExpandPseudoPass(), llvm::initializeRISCVPreLegalizerCombinerPass(), llvm::initializeRISCVPreRAExpandPseudoPass(), llvm::initializeRISCVPushPopOptPass(), llvm::initializeRISCVVectorPeepholePass(), llvm::initializeRISCVVLOptimizerPass(), X, and Y.
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Referenced by llvm::RISCVTargetMachine::getSubtargetImpl().
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Referenced by llvm::RISCVTargetMachine::getSubtargetImpl().