LLVM 22.0.0git
Functions | Variables
RISCVTargetMachine.cpp File Reference
#include "RISCVTargetMachine.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVTargetObjectFile.h"
#include "RISCVTargetTransformInfo.h"
#include "TargetInfo/RISCVTargetInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
#include "llvm/CodeGen/MIRParser/MIParser.h"
#include "llvm/CodeGen/MIRYamlMapping.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Passes/PassBuilder.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/IPO.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Vectorize/LoopIdiomVectorize.h"
#include <optional>

Go to the source code of this file.

Functions

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget ()
 
static std::string computeDataLayout (const Triple &TT, const TargetOptions &Opts)
 
static Reloc::Model getEffectiveRelocModel (const Triple &TT, std::optional< Reloc::Model > RM)
 

Variables

static cl::opt< boolEnableRedundantCopyElimination ("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
 
static cl::opt< cl::boolOrDefaultEnableGlobalMerge ("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
 
static cl::opt< boolEnableMachineCombiner ("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
 
static cl::opt< unsignedRVVVectorBitsMaxOpt ("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
 
static cl::opt< int > RVVVectorBitsMinOpt ("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
 
static cl::opt< boolEnableRISCVCopyPropagation ("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)
 
static cl::opt< boolEnableRISCVDeadRegisterElimination ("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitions and replaces stores to" " them with stores to x0"), cl::init(true))
 
static cl::opt< boolEnableSinkFold ("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
 
static cl::opt< boolEnableLoopDataPrefetch ("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
 
static cl::opt< boolDisableVectorMaskMutation ("riscv-disable-vector-mask-mutation", cl::desc("Disable the vector mask scheduling mutation"), cl::init(false), cl::Hidden)
 
static cl::opt< boolEnableMachinePipeliner ("riscv-enable-pipeliner", cl::desc("Enable Machine Pipeliner for RISC-V"), cl::init(false), cl::Hidden)
 

Function Documentation

◆ computeDataLayout()

static std::string computeDataLayout ( const Triple TT,
const TargetOptions Opts 
)
static

◆ getEffectiveRelocModel()

static Reloc::Model getEffectiveRelocModel ( const Triple TT,
std::optional< Reloc::Model RM 
)
static

Definition at line 177 of file RISCVTargetMachine.cpp.

References llvm::Reloc::Static.

◆ LLVMInitializeRISCVTarget()

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget ( )

Definition at line 106 of file RISCVTargetMachine.cpp.

References A, B, llvm::PassRegistry::getPassRegistry(), llvm::getTheRISCV32beTarget(), llvm::getTheRISCV32Target(), llvm::getTheRISCV64beTarget(), llvm::getTheRISCV64Target(), llvm::initializeGlobalISel(), llvm::initializeKCFIPass(), llvm::initializeRISCVAsmPrinterPass(), llvm::initializeRISCVCodeGenPreparePass(), llvm::initializeRISCVDAGToDAGISelLegacyPass(), llvm::initializeRISCVDeadRegisterDefinitionsPass(), llvm::initializeRISCVExpandAtomicPseudoPass(), llvm::initializeRISCVExpandPseudoPass(), llvm::initializeRISCVFoldMemOffsetPass(), llvm::initializeRISCVGatherScatterLoweringPass(), llvm::initializeRISCVIndirectBranchTrackingPass(), llvm::initializeRISCVInsertReadWriteCSRPass(), llvm::initializeRISCVInsertVSETVLIPass(), llvm::initializeRISCVInsertWriteVXRMPass(), llvm::initializeRISCVLateBranchOptPass(), llvm::initializeRISCVLoadStoreOptPass(), llvm::initializeRISCVMakeCompressibleOptPass(), llvm::initializeRISCVMergeBaseOffsetOptPass(), llvm::initializeRISCVMoveMergePass(), llvm::initializeRISCVO0PreLegalizerCombinerPass(), llvm::initializeRISCVOptWInstrsPass(), llvm::initializeRISCVPostLegalizerCombinerPass(), llvm::initializeRISCVPostRAExpandPseudoPass(), llvm::initializeRISCVPreLegalizerCombinerPass(), llvm::initializeRISCVPreRAExpandPseudoPass(), llvm::initializeRISCVPushPopOptPass(), llvm::initializeRISCVRedundantCopyEliminationPass(), llvm::initializeRISCVVectorPeepholePass(), llvm::initializeRISCVVLOptimizerPass(), llvm::initializeRISCVVMV0EliminationPass(), X, and Y.

Variable Documentation

◆ DisableVectorMaskMutation

cl::opt< bool > DisableVectorMaskMutation("riscv-disable-vector-mask-mutation", cl::desc("Disable the vector mask scheduling mutation"), cl::init(false), cl::Hidden) ( "riscv-disable-vector-mask-mutation"  ,
cl::desc("Disable the vector mask scheduling mutation")  ,
cl::init(false)  ,
cl::Hidden   
)
static

◆ EnableGlobalMerge

cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass")) ( "riscv-enable-global-merge"  ,
cl::Hidden  ,
cl::desc("Enable the global merge pass")   
)
static

◆ EnableLoopDataPrefetch

cl::opt< bool > EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true)) ( "riscv-enable-loop-data-prefetch"  ,
cl::Hidden  ,
cl::desc("Enable the loop data prefetch pass")  ,
cl::init(true)   
)
static

◆ EnableMachineCombiner

cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden) ( "riscv-enable-machine-combiner"  ,
cl::desc("Enable the machine combiner pass")  ,
cl::init(true)  ,
cl::Hidden   
)
static

◆ EnableMachinePipeliner

cl::opt< bool > EnableMachinePipeliner("riscv-enable-pipeliner", cl::desc("Enable Machine Pipeliner for RISC-V"), cl::init(false), cl::Hidden) ( "riscv-enable-pipeliner"  ,
cl::desc("Enable Machine Pipeliner for RISC-V")  ,
cl::init(false)  ,
cl::Hidden   
)
static

◆ EnableRedundantCopyElimination

cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden) ( "riscv-enable-copyelim"  ,
cl::desc("Enable the redundant copy elimination pass")  ,
cl::init(true)  ,
cl::Hidden   
)
static

◆ EnableRISCVCopyPropagation

cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden) ( "riscv-enable-copy-propagation"  ,
cl::desc("Enable the copy propagation with RISC-V copy instr")  ,
cl::init(true)  ,
cl::Hidden   
)
static

◆ EnableRISCVDeadRegisterElimination

cl::opt< bool > EnableRISCVDeadRegisterElimination("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitions and replaces stores to" " them with stores to x0"), cl::init(true)) ( "riscv-enable-dead-defs"  ,
cl::Hidden  ,
cl::desc("Enable the pass that removes dead" " definitions and replaces stores to" " them with stores to x0")  ,
cl::init(true)   
)
static

◆ EnableSinkFold

cl::opt< bool > EnableSinkFold("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden) ( "riscv-enable-sink-fold"  ,
cl::desc("Enable sinking and folding of instruction copies")  ,
cl::init(true)  ,
cl::Hidden   
)
static

◆ RVVVectorBitsMaxOpt

cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden) ( "riscv-v-vector-bits-max"  ,
cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed.")  ,
cl::init(0)  ,
cl::Hidden   
)
static

◆ RVVVectorBitsMinOpt

cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden) ( "riscv-v-vector-bits-min"  ,
cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors.")  ,
cl::init(-1)  ,
cl::Hidden   
)
static