RISCVVectorPeephole.cpp File Reference

#include "RISCV.h"
#include "RISCVISelDAGToDAG.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "riscv-vector-peephole"
#define	CASE_WHOLE_REGISTER_LMUL_SEW(lmul, sew)
#define	CASE_WHOLE_REGISTER_LMUL(lmul)
#define	CASE_VMERGE_TO_VMV(lmul)

Functions
	INITIALIZE_PASS (RISCVVectorPeephole, DEBUG_TYPE, "RISC-V Fold Masks", false, false) std
	Check if an operand is an immediate or a materialized ADDI $x0, imm.
static bool	isSafeToMove (const MachineInstr &From, const MachineInstr &To)
	Check if it's safe to move From down to To, checking that no physical registers are clobbered.
static unsigned	getSEWLMULRatio (const MachineInstr &MI)

Macro Definition Documentation

CASE_VMERGE_TO_VMV

#define CASE_VMERGE_TO_VMV

(

lmul

)

Value:

  case RISCV::PseudoVMERGE_VVM_##lmul:                                         \
    NewOpc = RISCV::PseudoVMV_V_V_##lmul;                                      \
    break;

CASE_WHOLE_REGISTER_LMUL

#define CASE_WHOLE_REGISTER_LMUL

(

lmul

)

Value:

  CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 8)                                        \
  CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 16)                                       \
  CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 32)                                       \
  CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 64)

CASE_WHOLE_REGISTER_LMUL_SEW

#define CASE_WHOLE_REGISTER_LMUL_SEW	(		lmul,
			sew
	)

Value:

  case RISCV::PseudoVLE##sew##_V_M##lmul:                                      \
    NewOpc = RISCV::VL##lmul##RE##sew##_V;                                     \
    break;                                                                     \
  case RISCV::PseudoVSE##sew##_V_M##lmul:                                      \
    NewOpc = RISCV::VS##lmul##R_V;                                             \
    break;

DEBUG_TYPE

#define DEBUG_TYPE   "riscv-vector-peephole"

Definition at line 40 of file RISCVVectorPeephole.cpp.

Function Documentation

getSEWLMULRatio()

static unsigned getSEWLMULRatio ( const MachineInstr &  MI )

static

Definition at line 365 of file RISCVVectorPeephole.cpp.

References llvm::RISCVII::getLMul(), llvm::RISCVVType::getSEWLMULRatio(), llvm::RISCVII::getSEWOpNum(), and MI.

INITIALIZE_PASS()

INITIALIZE_PASS	(	RISCVVectorPeephole	,
		DEBUG_TYPE	,
		"RISC-V Fold Masks"	,
		false	,
		false
	)

Check if an operand is an immediate or a materialized ADDI $x0, imm.

Convert unit strided unmasked loads and stores to whole-register equivalents to avoid the dependency on $vl and $vtype.

x = PseudoVLE8_V_M1 passthru, ptr, vlmax, policy PseudoVSE8_V_M1 v, ptr, vlmax

->

x = VL1RE8_V ptr VS1R_V v, ptr Given two VL operands, returns the one known to be the smallest or nullptr if unknown.

Definition at line 81 of file RISCVVectorPeephole.cpp.

References MRI.

isSafeToMove()

static bool isSafeToMove ( const MachineInstr &  From, const MachineInstr &  To  )

static

Check if it's safe to move From down to To, checking that no physical registers are clobbered.

Definition at line 346 of file RISCVVectorPeephole.cpp.

References assert(), From, llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getParent(), II, and llvm::SmallVectorTemplateBase< T, bool >::push_back().