LLVM 20.0.0git
Macros | Functions
RISCVVectorPeephole.cpp File Reference
#include "RISCV.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "riscv-vector-peephole"
 
#define CASE_WHOLE_REGISTER_LMUL_SEW(lmul, sew)
 
#define CASE_WHOLE_REGISTER_LMUL(lmul)
 
#define CASE_VMERGE_TO_VMV(lmul)
 

Functions

 INITIALIZE_PASS (RISCVVectorPeephole, DEBUG_TYPE, "RISC-V Fold Masks", false, false) bool RISCVVectorPeephole
 Given User that has an input operand with EEW=SEW, which uses the dest operand of Src with an unknown EEW, return true if their EEWs match.
 
static bool isSafeToMove (const MachineInstr &From, const MachineInstr &To)
 Check if it's safe to move From down to To, checking that no physical registers are clobbered.
 
static bool dominates (MachineBasicBlock::const_iterator A, MachineBasicBlock::const_iterator B)
 Given A and B are in the same MBB, returns true if A comes before B.
 

Macro Definition Documentation

◆ CASE_VMERGE_TO_VMV

#define CASE_VMERGE_TO_VMV (   lmul)
Value:
case RISCV::PseudoVMERGE_VVM_##lmul: \
return RISCV::PseudoVMV_V_V_##lmul;

◆ CASE_WHOLE_REGISTER_LMUL

#define CASE_WHOLE_REGISTER_LMUL (   lmul)
Value:
CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 16) \
CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 32) \
CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 64)
#define CASE_WHOLE_REGISTER_LMUL_SEW(lmul, sew)

◆ CASE_WHOLE_REGISTER_LMUL_SEW

#define CASE_WHOLE_REGISTER_LMUL_SEW (   lmul,
  sew 
)
Value:
case RISCV::PseudoVLE##sew##_V_M##lmul: \
NewOpc = RISCV::VL##lmul##RE##sew##_V; \
break; \
case RISCV::PseudoVSE##sew##_V_M##lmul: \
NewOpc = RISCV::VS##lmul##R_V; \
break;

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscv-vector-peephole"

Definition at line 39 of file RISCVVectorPeephole.cpp.

Function Documentation

◆ dominates()

Given A and B are in the same MBB, returns true if A comes before B.

Definition at line 513 of file RISCVVectorPeephole.cpp.

References A, assert(), B, llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), I, and MBB.

◆ INITIALIZE_PASS()

INITIALIZE_PASS ( RISCVVectorPeephole  ,
DEBUG_TYPE  ,
"RISC-V Fold Masks"  ,
false  ,
false   
)

Given User that has an input operand with EEW=SEW, which uses the dest operand of Src with an unknown EEW, return true if their EEWs match.

Convert unit strided unmasked loads and stores to whole-register equivalents to avoid the dependency on $vl and $vtype.

x = PseudoVLE8_V_M1 passthru, ptr, vlmax, policy PseudoVSE8_V_M1 v, ptr, vlmax

->

x = VL1RE8_V ptr VS1R_V v, ptr

Definition at line 85 of file RISCVVectorPeephole.cpp.

References llvm::RISCV::getDestLog2EEW(), llvm::User::getOperand(), llvm::RISCV::getRVVMCOpcode(), llvm::RISCVII::getSEWOpNum(), and TII.

◆ isSafeToMove()

static bool isSafeToMove ( const MachineInstr From,
const MachineInstr To 
)
static

Check if it's safe to move From down to To, checking that no physical registers are clobbered.

Definition at line 493 of file RISCVVectorPeephole.cpp.

References assert(), From, llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getParent(), II, and llvm::SmallVectorTemplateBase< T, bool >::push_back().