22#define DEBUG_TYPE "machine-scheduler"
26void SystemZPostRASchedStrategy::SUSet::
29 for (
auto &SU : *
this) {
51 PredMBB = (Pred ==
MBB ? nullptr : Pred);
55 &&
"Loop MBB should not consider predecessor outside of loop.");
60void SystemZPostRASchedStrategy::
64 ((LastEmittedMI !=
nullptr && LastEmittedMI->getParent() == MBB) ?
65 std::next(LastEmittedMI) : MBB->
begin());
67 for (;
I != NextBegin; ++
I) {
68 if (
I->isPosition() ||
I->isDebugInstr())
80 assert ((SchedStates.find(NextMBB) == SchedStates.end()) &&
81 "Entering MBB twice?");
97 if (SinglePredMBB ==
nullptr ||
98 SchedStates.find(SinglePredMBB) == SchedStates.end())
104 HazardRec->
copyState(SchedStates[SinglePredMBB]);
111 bool TakenBranch = (
MI.isBranch() &&
132 (
C->MF->getSubtarget().getInstrInfo())),
133 MBB(nullptr), HazardRec(nullptr) {
140 for (
auto I : SchedStates) {
148 unsigned NumRegionInstrs) {
150 if (Begin->isTerminator())
162 if (Available.empty())
166 if (Available.size() == 1) {
169 return *Available.begin();
173 LLVM_DEBUG(
dbgs() <<
"** Available: "; Available.dump(*HazardRec););
176 for (
auto *SU : Available) {
179 Candidate c(SU, *HazardRec);
182 if (Best.SU ==
nullptr || c < Best) {
188 dbgs() <<
" Height:" << c.SU->getHeight();
dbgs() <<
"\n";);
192 if (!SU->isScheduleHigh && Best.noCost())
196 assert (Best.SU !=
nullptr);
200SystemZPostRASchedStrategy::Candidate::
213bool SystemZPostRASchedStrategy::Candidate::
214operator<(
const Candidate &other) {
217 if (GroupingCost < other.GroupingCost)
219 if (GroupingCost > other.GroupingCost)
223 if (ResourcesCost < other.ResourcesCost)
225 if (ResourcesCost > other.ResourcesCost)
229 if (SU->getHeight() > other.SU->getHeight())
231 if (SU->getHeight() < other.SU->getHeight())
235 if (SU->NodeNum < other.SU->NodeNum)
243 if (Available.size() == 1)
dbgs() <<
"(only one) ";
244 Candidate c(SU, *HazardRec); c.dumpCosts();
dbgs() <<
"\n";);
255 bool AffectsGrouping = (SC->isValid() && (SC->BeginGroup || SC->EndGroup));
259 Available.insert(SU);
const HexagonInstrInfo * TII
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static MachineBasicBlock * getSingleSchedPred(MachineBasicBlock *MBB, const MachineLoop *Loop)
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
BlockT * getHeader() const
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
unsigned pred_size() const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
pred_iterator pred_begin()
iterator_range< pred_iterator > predecessors()
Representation of each machine instruction.
Scheduling unit. This is a node in the scheduling DAG.
unsigned NodeNum
Entry # of node in the node vector.
bool isUnbuffered
Uses an unbuffered resource.
bool isScheduleHigh
True if preferable to schedule high.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
SystemZHazardRecognizer maintains the state for one MBB during scheduling.
int groupingCost(SUnit *SU) const
Return the cost of decoder grouping for SU.
void emitInstruction(MachineInstr *MI, bool TakenBranch=false)
Wrap a non-scheduled instruction in an SU and emit it.
const MCSchedClassDesc * getSchedClass(SUnit *SU) const
Resolves and cache a resolved scheduling class for an SUnit.
void copyState(SystemZHazardRecognizer *Incoming)
Copy counters from end of single predecessor.
void dumpSU(SUnit *SU, raw_ostream &OS) const
MachineBasicBlock::iterator getLastEmittedMI()
int resourcesCost(SUnit *SU)
Return the cost of SU in regards to processor resources usage.
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
MachineBasicBlock * getMBBTarget()
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
SUnit * pickNode(bool &IsTopNode) override
Pick the next node to schedule, or return NULL.
void leaveMBB() override
Tell the strategy that current MBB is done.
void initPolicy(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs) override
Called for a region before scheduling.
void schedNode(SUnit *SU, bool IsTopNode) override
ScheduleDAGMI has scheduled an instruction - tell HazardRec about it.
void initialize(ScheduleDAGMI *dag) override
Initialize the strategy after building the DAG for a new region.
void enterMBB(MachineBasicBlock *NextMBB) override
Tell the strategy that MBB is about to be processed.
virtual ~SystemZPostRASchedStrategy()
SystemZPostRASchedStrategy(const MachineSchedContext *C)
void releaseTopNode(SUnit *SU) override
SU has had all predecessor dependencies resolved.
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
TargetSubtargetInfo - Generic base class for all target subtargets.
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Summarize the scheduling resources required for an instruction of a particular scheduling class.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...