LLVM 20.0.0git
XtensaInstrInfo.h
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1//===-- XtensaInstrInfo.h - Xtensa Instruction Information ------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
6// See https://llvm.org/LICENSE.txt for license information.
7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8//
9//===----------------------------------------------------------------------===//
10//
11// This file contains the Xtensa implementation of the TargetInstrInfo class.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H
16#define LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H
17
18#include "Xtensa.h"
19#include "XtensaRegisterInfo.h"
22
23#define GET_INSTRINFO_HEADER
24
25#include "XtensaGenInstrInfo.inc"
26
27namespace llvm {
28
29class XtensaTargetMachine;
30class XtensaSubtarget;
32 const XtensaRegisterInfo RI;
33 const XtensaSubtarget &STI;
34
35public:
37
38 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
40
41 // Return the XtensaRegisterInfo, which this class owns.
42 const XtensaRegisterInfo &getRegisterInfo() const { return RI; }
43
45 int &FrameIndex) const override;
46
48 int &FrameIndex) const override;
49
51 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
52 bool KillSrc) const override;
53
56 bool isKill, int FrameIndex,
57 const TargetRegisterClass *RC,
59 Register VReg) const override;
60
63 int FrameIdx, const TargetRegisterClass *RC,
65 Register VReg) const override;
66
67 // Get the load and store opcodes for a given register class and offset.
68 void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode,
69 unsigned &StoreOpcode, int64_t offset) const;
70
71 // Emit code before MBBI in MI to move immediate value Value into
72 // physical register Reg.
74 unsigned *Reg, int64_t Value) const;
75
76 const XtensaSubtarget &getSubtarget() const { return STI; }
77};
78} // end namespace llvm
79
80#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H */
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
A debug info location.
Definition: DebugLoc.h:33
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition: Value.h:74
const XtensaSubtarget & getSubtarget() const
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned *Reg, int64_t Value) const
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
const XtensaRegisterInfo & getRegisterInfo() const
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
Adjust SP by Amount bytes.
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode, int64_t offset) const
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18