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| | ARMInstrInfo (const ARMSubtarget &STI) |
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| MCInst | getNop () const override |
| | Return the noop instruction to use for a noop.
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| unsigned | getUnindexedOpcode (unsigned Opc) const override |
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| const ARMRegisterInfo & | getRegisterInfo () const override |
| | getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
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| bool | hasNOP () const |
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| virtual unsigned | getUnindexedOpcode (unsigned Opc) const =0 |
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| MachineInstr * | convertToThreeAddress (MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override |
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| virtual const ARMBaseRegisterInfo & | getRegisterInfo () const =0 |
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| const ARMSubtarget & | getSubtarget () const |
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| ScheduleHazardRecognizer * | CreateTargetHazardRecognizer (const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override |
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| ScheduleHazardRecognizer * | CreateTargetMIHazardRecognizer (const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override |
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| ScheduleHazardRecognizer * | CreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override |
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| bool | analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override |
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| unsigned | removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override |
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| unsigned | insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override |
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| bool | reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override |
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| bool | isPredicated (const MachineInstr &MI) const override |
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| std::string | createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override |
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| ARMCC::CondCodes | getPredicate (const MachineInstr &MI) const |
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| bool | PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override |
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| bool | SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override |
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| bool | ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override |
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| bool | isPredicable (const MachineInstr &MI) const override |
| | isPredicable - Return true if the specified instruction can be predicated.
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| unsigned | getInstSizeInBytes (const MachineInstr &MI) const override |
| | GetInstSize - Returns the size of the specified MachineInstr.
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| Register | isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override |
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| Register | isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override |
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| Register | isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override |
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| Register | isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override |
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| void | copyToCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const |
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| void | copyFromCPSR (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const |
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| void | copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override |
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| void | storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override |
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| void | loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override |
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| bool | expandPostRAPseudo (MachineInstr &MI) const override |
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| bool | shouldSink (const MachineInstr &MI) const override |
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| void | reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override |
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| MachineInstr & | duplicate (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override |
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| const MachineInstrBuilder & | AddDReg (MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const |
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| bool | produceSameValue (const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override |
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| bool | areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override |
| | areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
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| bool | shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override |
| | shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.
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| bool | isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override |
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| bool | isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override |
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| bool | isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, BranchProbability Probability) const override |
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| bool | isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override |
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| unsigned | extraSizeToPredicateInstructions (const MachineFunction &MF, unsigned NumInsts) const override |
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| unsigned | predictBranchSizeForIfCvt (MachineInstr &MI) const override |
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| bool | isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override |
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| bool | analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override |
| | analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
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| bool | optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override |
| | optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.
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| bool | analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override |
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| MachineInstr * | optimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override |
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| bool | foldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override |
| | foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.
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| unsigned | getNumMicroOps (const InstrItineraryData *ItinData, const MachineInstr &MI) const override |
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| std::optional< unsigned > | getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override |
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| std::optional< unsigned > | getOperandLatency (const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override |
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| std::pair< uint16_t, uint16_t > | getExecutionDomain (const MachineInstr &MI) const override |
| | VFP/NEON execution domains.
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| void | setExecutionDomain (MachineInstr &MI, unsigned Domain) const override |
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| unsigned | getPartialRegUpdateClearance (const MachineInstr &, unsigned, const TargetRegisterInfo *) const override |
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| void | breakPartialRegDependency (MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override |
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| unsigned | getNumLDMAddresses (const MachineInstr &MI) const |
| | Get the number of addresses by LDM or VLDM or zero for unknown.
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| std::pair< unsigned, unsigned > | decomposeMachineOperandsTargetFlags (unsigned TF) const override |
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| ArrayRef< std::pair< unsigned, const char * > > | getSerializableDirectMachineOperandTargetFlags () const override |
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| ArrayRef< std::pair< unsigned, const char * > > | getSerializableBitmaskMachineOperandTargetFlags () const override |
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| bool | isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override |
| | ARM supports the MachineOutliner.
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| std::optional< std::unique_ptr< outliner::OutlinedFunction > > | getOutliningCandidateInfo (const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override |
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| void | mergeOutliningCandidateAttributes (Function &F, std::vector< outliner::Candidate > &Candidates) const override |
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| outliner::InstrType | getOutliningTypeImpl (const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const override |
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| bool | isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override |
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| void | buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override |
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| MachineBasicBlock::iterator | insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override |
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| bool | shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override |
| | Enable outlining by default at -Oz.
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| bool | isUnspillableTerminatorImpl (const MachineInstr *MI) const override |
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| std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > | analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override |
| | Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
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| bool | isFpMLxInstruction (unsigned Opcode) const |
| | isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
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| bool | isFpMLxInstruction (unsigned Opcode, unsigned &MulOpc, unsigned &AddSubOpc, bool &NegAcc, bool &HasLane) const |
| | isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to.
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| bool | canCauseFpMLxStall (unsigned Opcode) const |
| | canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.
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| bool | isSwiftFastImmShift (const MachineInstr *MI) const |
| | Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
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| unsigned | getFramePred (const MachineInstr &MI) const |
| | Returns predicate register associated with the given frame instruction.
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| std::optional< RegImmPair > | isAddImmediate (const MachineInstr &MI, Register Reg) const override |
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Static Public Member Functions inherited from llvm::ARMBaseInstrInfo