19auto GenericConvergenceVerifier<MachineSSAContext>::getConvOp(
21 switch (
MI.getOpcode()) {
24 case TargetOpcode::CONVERGENCECTRL_ENTRY:
26 case TargetOpcode::CONVERGENCECTRL_ANCHOR:
28 case TargetOpcode::CONVERGENCECTRL_LOOP:
37 "Convergence control tokens are defined explicitly.",
38 {Context.print(&MI)});
42 "Convergence control tokens must have unique definitions.",
43 {Context.print(&MI)});
48GenericConvergenceVerifier<MachineSSAContext>::findAndCheckConvergenceTokenUsed(
54 if (!MO.isReg() || !MO.isUse())
63 if (getConvOp(*Def) == CONV_NONE)
68 "Convergence control tokens can only be used by convergent operations.",
69 {Context.print(OpReg), Context.print(&MI)});
72 "An operation can use at most one convergence control token.",
73 {Context.print(OpReg), Context.print(&
MI)});
79 Tokens[&
MI] = TokenDef;
85bool GenericConvergenceVerifier<MachineSSAContext>::isInsideConvergentFunction(
93bool GenericConvergenceVerifier<MachineSSAContext>::isConvergent(
95 return MI.isConvergent();
unsigned const MachineRegisterInfo * MRI
A verifier for the static rules of convergence control tokens that works with both LLVM IR and MIR.
#define CheckOrNull(C,...)
This file declares the MIR specialization of the GenericConvergenceVerifier template.
This file declares a specialization of the GenericSSAContext<X> template class for Machine IR.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
NodeAddr< DefNode * > Def
This is an optimization pass for GlobalISel generic memory operations.
GenericSSAContext< MachineFunction > MachineSSAContext