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32 #define DEBUG_TYPE "mccodeemitter"
34 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted.");
35 STATISTIC(MCNumFixups,
"Number of MC fixups created.");
51 WebAssemblyMCCodeEmitter(
const MCInstrInfo &MCII) : MCII(MCII) {}
56 return new WebAssemblyMCCodeEmitter(MCII);
59 void WebAssemblyMCCodeEmitter::encodeInstruction(
65 if (Binary < (1 << 8)) {
66 OS << uint8_t(Binary);
67 }
else if (Binary < (1 << 16)) {
68 OS << uint8_t(Binary >> 8);
70 }
else if (Binary < (1 << 24)) {
71 OS << uint8_t(Binary >> 16);
80 if (
MI.getOpcode() == WebAssembly::BR_TABLE_I32_S ||
81 MI.getOpcode() == WebAssembly::BR_TABLE_I64_S)
83 if (
MI.getOpcode() == WebAssembly::BR_TABLE_I32 ||
84 MI.getOpcode() == WebAssembly::BR_TABLE_I64)
88 for (
unsigned I = 0,
E =
MI.getNumOperands();
I <
E; ++
I) {
93 }
else if (MO.
isImm()) {
97 <<
int(
Info.OperandType) <<
"\n");
98 switch (
Info.OperandType) {
139 size_t PaddedSize = 5;
140 switch (
Info.OperandType) {
176 #include "WebAssemblyGenMCCodeEmitter.inc"
uint64_t tell() const
tell - Return the current offset with the file.
This is an optimization pass for GlobalISel generic memory operations.
static Lanai::Fixups FixupKind(const MCExpr *Expr)
@ OPERAND_TABLE
32-bit unsigned table number.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
@ OPERAND_VEC_I32IMM
32-bit vector lane immediate
@ OPERAND_OFFSET32
32-bit unsigned memory offsets.
@ OPERAND_GLOBAL
Global index.
uint32_t getSFPImm() const
@ OPERAND_SIGNATURE
signature immediate for block/loop.
Instances of this class represent a single low-level machine instruction.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
This holds information about one operand of a machine instruction, indicating the register class for ...
@ OPERAND_VEC_I64IMM
64-bit vector lane immediate
unsigned encodeSLEB128(int64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a SLEB128 value to an output stream.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MCCodeEmitter * createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII)
Describe properties that are true of each instruction in the target description file.
STATISTIC(NumFunctions, "Total number of functions")
This class implements an extremely fast bulk output stream that can only output to a stream.
Analysis containing CSE Info
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
const MCOperandInfo * OpInfo
@ OPERAND_FUNCTION32
32-bit unsigned function indices.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ OPERAND_TYPEINDEX
type signature immediate for call_indirect.
Interface to description of machine instruction set.
@ OPERAND_VEC_I16IMM
16-bit vector lane immediate
MCCodeEmitter - Generic instruction encoding interface.
const MCExpr * getExpr() const
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ OPERAND_OFFSET64
64-bit unsigned memory offsets.
uint64_t getDFPImm() const
@ OPERAND_I64IMM
64-bit integer immediates.
unsigned encodeULEB128(uint64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a ULEB128 value to an output stream.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Instances of this class represent operands of the MCInst class.
@ OPERAND_VEC_I8IMM
8-bit vector lane immediate
Generic base class for all target subtargets.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
@ OPERAND_I32IMM
32-bit integer immediates.