LLVM 20.0.0git
WebAssemblyMCCodeEmitter.cpp
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1//=- WebAssemblyMCCodeEmitter.cpp - Convert WebAssembly code to machine code -//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements the WebAssemblyMCCodeEmitter class.
11///
12//===----------------------------------------------------------------------===//
13
16#include "llvm/ADT/Statistic.h"
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCFixup.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
23#include "llvm/MC/MCSymbol.h"
24#include "llvm/Support/Debug.h"
26#include "llvm/Support/LEB128.h"
27#include "llvm/Support/SMLoc.h"
29
30using namespace llvm;
31
32#define DEBUG_TYPE "mccodeemitter"
33
34STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
35STATISTIC(MCNumFixups, "Number of MC fixups created.");
36
37namespace {
38class WebAssemblyMCCodeEmitter final : public MCCodeEmitter {
39 const MCInstrInfo &MCII;
40 MCContext &Ctx;
41 // Implementation generated by tablegen.
42 uint64_t getBinaryCodeForInstr(const MCInst &MI,
44 const MCSubtargetInfo &STI) const;
45
48 const MCSubtargetInfo &STI) const override;
49
50public:
51 WebAssemblyMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
52 : MCII(MCII), Ctx{Ctx} {}
53};
54} // end anonymous namespace
55
57 MCContext &Ctx) {
58 return new WebAssemblyMCCodeEmitter(MCII, Ctx);
59}
60
61void WebAssemblyMCCodeEmitter::encodeInstruction(
63 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
65 uint64_t Start = OS.tell();
66
67 uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
68 if (Binary < (1 << 8)) {
69 OS << uint8_t(Binary);
70 } else if (Binary < (1 << 16)) {
71 OS << uint8_t(Binary >> 8);
72 encodeULEB128(uint8_t(Binary), OS);
73 } else if (Binary < (1 << 24)) {
74 OS << uint8_t(Binary >> 16);
75 encodeULEB128(uint16_t(Binary), OS);
76 } else {
77 llvm_unreachable("Very large (prefix + 3 byte) opcodes not supported");
78 }
79
80 // For br_table instructions, encode the size of the table. In the MCInst,
81 // there's an index operand (if not a stack instruction), one operand for
82 // each table entry, and the default operand.
83 unsigned Opcode = MI.getOpcode();
84 if (Opcode == WebAssembly::BR_TABLE_I32_S ||
85 Opcode == WebAssembly::BR_TABLE_I64_S)
86 encodeULEB128(MI.getNumOperands() - 1, OS);
87 if (Opcode == WebAssembly::BR_TABLE_I32 ||
88 Opcode == WebAssembly::BR_TABLE_I64)
89 encodeULEB128(MI.getNumOperands() - 2, OS);
90
91 const MCInstrDesc &Desc = MCII.get(Opcode);
92 for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
93 const MCOperand &MO = MI.getOperand(I);
94 if (MO.isReg()) {
95 /* nothing to encode */
96
97 } else if (MO.isImm()) {
98 if (I < Desc.getNumOperands()) {
99 const MCOperandInfo &Info = Desc.operands()[I];
100 LLVM_DEBUG(dbgs() << "Encoding immediate: type="
101 << int(Info.OperandType) << "\n");
102 switch (Info.OperandType) {
104 encodeSLEB128(int32_t(MO.getImm()), OS);
105 break;
108 break;
110 encodeSLEB128(int64_t(MO.getImm()), OS);
111 break;
114 support::endian::write<uint8_t>(OS, MO.getImm(),
116 break;
118 support::endian::write<uint16_t>(OS, MO.getImm(),
120 break;
122 support::endian::write<uint32_t>(OS, MO.getImm(),
124 break;
126 support::endian::write<uint64_t>(OS, MO.getImm(),
128 break;
130 Ctx.reportError(
131 SMLoc(),
132 Twine("Wasm globals should only be accessed symbolically!"));
133 break;
134 default:
136 }
137 } else {
138 // Variadic immediate operands are br_table's destination operands or
139 // try_table's operands (# of catch clauses, catch sub-opcodes, or catch
140 // clause destinations)
142 Opcode == WebAssembly::TRY_TABLE_S);
144 }
145
146 } else if (MO.isSFPImm()) {
147 uint32_t F = MO.getSFPImm();
148 support::endian::write<uint32_t>(OS, F, llvm::endianness::little);
149 } else if (MO.isDFPImm()) {
150 uint64_t D = MO.getDFPImm();
151 support::endian::write<uint64_t>(OS, D, llvm::endianness::little);
152 } else if (MO.isExpr()) {
154 size_t PaddedSize = 5;
155 if (I < Desc.getNumOperands()) {
156 const MCOperandInfo &Info = Desc.operands()[I];
157 switch (Info.OperandType) {
160 break;
163 PaddedSize = 10;
164 break;
173 break;
176 PaddedSize = 10;
177 break;
178 default:
179 llvm_unreachable("unexpected symbolic operand kind");
180 }
181 } else {
182 // Variadic expr operands are try_table's catch/catch_ref clauses' tags.
183 assert(Opcode == WebAssembly::TRY_TABLE_S);
185 }
186 Fixups.push_back(MCFixup::create(OS.tell() - Start, MO.getExpr(),
187 FixupKind, MI.getLoc()));
188 ++MCNumFixups;
189 encodeULEB128(0, OS, PaddedSize);
190 } else {
191 llvm_unreachable("unexpected operand kind");
192 }
193 }
194
195 ++MCNumEmitted; // Keep track of the # of mi's emitted.
196}
197
198#include "WebAssemblyGenMCCodeEmitter.inc"
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_DEBUG(...)
Definition: Debug.h:106
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:166
This file provides WebAssembly-specific target descriptions.
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
Context object for machine code objects.
Definition: MCContext.h:83
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:37
bool isSFPImm() const
Definition: MCInst.h:64
int64_t getImm() const
Definition: MCInst.h:81
bool isImm() const
Definition: MCInst.h:63
bool isReg() const
Definition: MCInst.h:62
bool isDFPImm() const
Definition: MCInst.h:65
const MCExpr * getExpr() const
Definition: MCInst.h:115
uint32_t getSFPImm() const
Definition: MCInst.h:91
uint64_t getDFPImm() const
Definition: MCInst.h:101
bool isExpr() const
Definition: MCInst.h:66
Generic base class for all target subtargets.
Represents a location in source code.
Definition: SMLoc.h:23
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
uint64_t tell() const
tell - Return the current offset with the file.
Definition: raw_ostream.h:147
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:691
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isBrTable(unsigned Opc)
@ OPERAND_GLOBAL
Global index.
@ OPERAND_OFFSET64
64-bit unsigned memory offsets.
@ OPERAND_I32IMM
32-bit integer immediates.
@ OPERAND_TABLE
32-bit unsigned table number.
@ OPERAND_VEC_I64IMM
64-bit vector lane immediate
@ OPERAND_VEC_I16IMM
16-bit vector lane immediate
@ OPERAND_TYPEINDEX
type signature immediate for call_indirect.
@ OPERAND_FUNCTION32
32-bit unsigned function indices.
@ OPERAND_VEC_I32IMM
32-bit vector lane immediate
@ OPERAND_VEC_I8IMM
8-bit vector lane immediate
@ OPERAND_SIGNATURE
signature immediate for block/loop.
@ OPERAND_I64IMM
64-bit integer immediates.
@ OPERAND_OFFSET32
32-bit unsigned memory offsets.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCCodeEmitter * createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
unsigned encodeSLEB128(int64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a SLEB128 value to an output stream.
Definition: LEB128.h:23
unsigned encodeULEB128(uint64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a ULEB128 value to an output stream.
Definition: LEB128.h:80
Description of the encoding of one expression Op.