LLVM  9.0.0svn
SystemZTargetMachine.cpp
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1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZTargetMachine.h"
11 #include "SystemZ.h"
14 #include "llvm/ADT/Optional.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
19 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/Support/CodeGen.h"
26 #include "llvm/Transforms/Scalar.h"
27 #include <string>
28 
29 using namespace llvm;
30 
31 extern "C" void LLVMInitializeSystemZTarget() {
32  // Register the target.
34 }
35 
36 // Determine whether we use the vector ABI.
37 static bool UsesVectorABI(StringRef CPU, StringRef FS) {
38  // We use the vector ABI whenever the vector facility is avaiable.
39  // This is the case by default if CPU is z13 or later, and can be
40  // overridden via "[+-]vector" feature string elements.
41  bool VectorABI = true;
42  if (CPU.empty() || CPU == "generic" ||
43  CPU == "z10" || CPU == "z196" || CPU == "zEC12")
44  VectorABI = false;
45 
47  FS.split(Features, ',', -1, false /* KeepEmpty */);
48  for (auto &Feature : Features) {
49  if (Feature == "vector" || Feature == "+vector")
50  VectorABI = true;
51  if (Feature == "-vector")
52  VectorABI = false;
53  }
54 
55  return VectorABI;
56 }
57 
58 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
59  StringRef FS) {
60  bool VectorABI = UsesVectorABI(CPU, FS);
61  std::string Ret;
62 
63  // Big endian.
64  Ret += "E";
65 
66  // Data mangling.
68 
69  // Make sure that global data has at least 16 bits of alignment by
70  // default, so that we can refer to it using LARL. We don't have any
71  // special requirements for stack variables though.
72  Ret += "-i1:8:16-i8:8:16";
73 
74  // 64-bit integers are naturally aligned.
75  Ret += "-i64:64";
76 
77  // 128-bit floats are aligned only to 64 bits.
78  Ret += "-f128:64";
79 
80  // When using the vector ABI, 128-bit vectors are also aligned to 64 bits.
81  if (VectorABI)
82  Ret += "-v128:64";
83 
84  // We prefer 16 bits of aligned for all globals; see above.
85  Ret += "-a:8:16";
86 
87  // Integer registers are 32 or 64 bits.
88  Ret += "-n32:64";
89 
90  return Ret;
91 }
92 
94  // Static code is suitable for use in a dynamic executable; there is no
95  // separate DynamicNoPIC model.
96  if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
97  return Reloc::Static;
98  return *RM;
99 }
100 
101 // For SystemZ we define the models as follows:
102 //
103 // Small: BRASL can call any function and will use a stub if necessary.
104 // Locally-binding symbols will always be in range of LARL.
105 //
106 // Medium: BRASL can call any function and will use a stub if necessary.
107 // GOT slots and locally-defined text will always be in range
108 // of LARL, but other symbols might not be.
109 //
110 // Large: Equivalent to Medium for now.
111 //
112 // Kernel: Equivalent to Medium for now.
113 //
114 // This means that any PIC module smaller than 4GB meets the
115 // requirements of Small, so Small seems like the best default there.
116 //
117 // All symbols bind locally in a non-PIC module, so the choice is less
118 // obvious. There are two cases:
119 //
120 // - When creating an executable, PLTs and copy relocations allow
121 // us to treat external symbols as part of the executable.
122 // Any executable smaller than 4GB meets the requirements of Small,
123 // so that seems like the best default.
124 //
125 // - When creating JIT code, stubs will be in range of BRASL if the
126 // image is less than 4GB in size. GOT entries will likewise be
127 // in range of LARL. However, the JIT environment has no equivalent
128 // of copy relocs, so locally-binding data symbols might not be in
129 // the range of LARL. We need the Medium model in that case.
130 static CodeModel::Model
132  bool JIT) {
133  if (CM) {
134  if (*CM == CodeModel::Tiny)
135  report_fatal_error("Target does not support the tiny CodeModel");
136  if (*CM == CodeModel::Kernel)
137  report_fatal_error("Target does not support the kernel CodeModel");
138  return *CM;
139  }
140  if (JIT)
142  return CodeModel::Small;
143 }
144 
146  StringRef CPU, StringRef FS,
147  const TargetOptions &Options,
150  CodeGenOpt::Level OL, bool JIT)
152  T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
155  OL),
157  Subtarget(TT, CPU, FS, *this) {
158  initAsmInfo();
159 }
160 
162 
163 namespace {
164 
165 /// SystemZ Code Generator Pass Configuration Options.
166 class SystemZPassConfig : public TargetPassConfig {
167 public:
168  SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM)
169  : TargetPassConfig(TM, PM) {}
170 
171  SystemZTargetMachine &getSystemZTargetMachine() const {
172  return getTM<SystemZTargetMachine>();
173  }
174 
176  createPostMachineScheduler(MachineSchedContext *C) const override {
177  return new ScheduleDAGMI(C,
178  llvm::make_unique<SystemZPostRASchedStrategy>(C),
179  /*RemoveKillFlags=*/true);
180  }
181 
182  void addIRPasses() override;
183  bool addInstSelector() override;
184  bool addILPOpts() override;
185  void addPreSched2() override;
186  void addPreEmitPass() override;
187 };
188 
189 } // end anonymous namespace
190 
191 void SystemZPassConfig::addIRPasses() {
192  if (getOptLevel() != CodeGenOpt::None) {
193  addPass(createSystemZTDCPass());
194  addPass(createLoopDataPrefetchPass());
195  }
196 
198 }
199 
200 bool SystemZPassConfig::addInstSelector() {
201  addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
202 
203  if (getOptLevel() != CodeGenOpt::None)
204  addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
205 
206  return false;
207 }
208 
209 bool SystemZPassConfig::addILPOpts() {
210  addPass(&EarlyIfConverterID);
211  return true;
212 }
213 
214 void SystemZPassConfig::addPreSched2() {
215  addPass(createSystemZExpandPseudoPass(getSystemZTargetMachine()));
216 
217  if (getOptLevel() != CodeGenOpt::None)
218  addPass(&IfConverterID);
219 }
220 
221 void SystemZPassConfig::addPreEmitPass() {
222  // Do instruction shortening before compare elimination because some
223  // vector instructions will be shortened into opcodes that compare
224  // elimination recognizes.
225  if (getOptLevel() != CodeGenOpt::None)
226  addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
227 
228  // We eliminate comparisons here rather than earlier because some
229  // transformations can change the set of available CC values and we
230  // generally want those transformations to have priority. This is
231  // especially true in the commonest case where the result of the comparison
232  // is used by a single in-range branch instruction, since we will then
233  // be able to fuse the compare and the branch instead.
234  //
235  // For example, two-address NILF can sometimes be converted into
236  // three-address RISBLG. NILF produces a CC value that indicates whether
237  // the low word is zero, but RISBLG does not modify CC at all. On the
238  // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
239  // The CC value produced by NILL isn't useful for our purposes, but the
240  // value produced by RISBG can be used for any comparison with zero
241  // (not just equality). So there are some transformations that lose
242  // CC values (while still being worthwhile) and others that happen to make
243  // the CC result more useful than it was originally.
244  //
245  // Another reason is that we only want to use BRANCH ON COUNT in cases
246  // where we know that the count register is not going to be spilled.
247  //
248  // Doing it so late makes it more likely that a register will be reused
249  // between the comparison and the branch, but it isn't clear whether
250  // preventing that would be a win or not.
251  if (getOptLevel() != CodeGenOpt::None)
252  addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
253  addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
254 
255  // Do final scheduling after all other optimizations, to get an
256  // optimal input for the decoder (branch relaxation must happen
257  // after block placement).
258  if (getOptLevel() != CodeGenOpt::None)
259  addPass(&PostMachineSchedulerID);
260 }
261 
263  return new SystemZPassConfig(*this, PM);
264 }
265 
268  return TargetTransformInfo(SystemZTTIImpl(this, F));
269 }
uint64_t CallInst * C
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
F(f)
std::enable_if<!std::is_array< T >::value, std::unique_ptr< T > >::type make_unique(Args &&... args)
Constructs a new T() with the given args and returns a unique_ptr<T> which owns the object...
Definition: STLExtras.h:1393
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:156
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createSystemZTDCPass()
FunctionPass * createSystemZISelDag(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
static std::string computeDataLayout(const Triple &TT, StringRef CPU, StringRef FS)
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Target-Independent Code Generator Pass Configuration Options.
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
FunctionPass * createSystemZShortenInstPass(SystemZTargetMachine &TM)
static CodeModel::Model getEffectiveSystemZCodeModel(Optional< CodeModel::Model > CM, Reloc::Model RM, bool JIT)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
static bool UsesVectorABI(StringRef CPU, StringRef FS)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
FunctionPass * createSystemZExpandPseudoPass(SystemZTargetMachine &TM)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
FunctionPass * createSystemZLongBranchPass(SystemZTargetMachine &TM)
void LLVMInitializeSystemZTarget()
Target - Wrapper for Target specific information.
Target & getTheSystemZTarget()
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:259
FunctionPass * createSystemZLDCleanupPass(SystemZTargetMachine &TM)
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
FunctionPass * createSystemZElimComparePass(SystemZTargetMachine &TM)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
This pass exposes codegen information to IR-level passes.