LLVM  6.0.0svn
Macros | Functions | Variables
TwoAddressInstructionPass.cpp File Reference
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Pass.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include <cassert>
#include <iterator>
#include <utility>
Include dependency graph for TwoAddressInstructionPass.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "twoaddressinstruction"
 

Functions

 STATISTIC (NumTwoAddressInstrs, "Number of two-address instructions")
 
 STATISTIC (NumCommuted, "Number of instructions commuted to coalesce")
 
 STATISTIC (NumAggrCommuted, "Number of instructions aggressively commuted")
 
 STATISTIC (NumConvertedTo3Addr, "Number of instructions promoted to 3-address")
 
 STATISTIC (Num3AddrSunk, "Number of 3-address instructions sunk")
 
 STATISTIC (NumReSchedUps, "Number of instructions re-scheduled up")
 
 STATISTIC (NumReSchedDowns, "Number of instructions re-scheduled down")
 
 INITIALIZE_PASS_BEGIN (TwoAddressInstructionPass, DEBUG_TYPE, "Two-Address instruction pass", false, false) INITIALIZE_PASS_END(TwoAddressInstructionPass
 
Two Address instruction static false bool isPlainlyKilled (MachineInstr *MI, unsigned Reg, LiveIntervals *LIS)
 Test if the given register value, which is used by the given instruction, is killed by the given instruction. More...
 
static MachineInstrgetSingleDef (unsigned Reg, MachineBasicBlock *BB, const MachineRegisterInfo *MRI)
 Return the MachineInstr* if it is the single def of the Reg in current BB. More...
 
static bool isCopyToReg (MachineInstr &MI, const TargetInstrInfo *TII, unsigned &SrcReg, unsigned &DstReg, bool &IsSrcPhys, bool &IsDstPhys)
 Return true if the specified MI is a copy instruction or an extract_subreg instruction. More...
 
static bool isKilled (MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives)
 Test if the given register value, which is used by the given instruction, is killed by the given instruction. More...
 
static bool isTwoAddrUse (MachineInstr &MI, unsigned Reg, unsigned &DstReg)
 Return true if the specified MI uses the specified register as a two-address use. More...
 
static MachineInstrfindOnlyInterestingUse (unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys)
 Given a register, if has a single in-basic block use, return the use instruction if it's a copy or a two-address use. More...
 
static unsigned getMappedReg (unsigned Reg, DenseMap< unsigned, unsigned > &RegMap)
 Return the physical register the specified virtual register might be mapped to. More...
 
static bool regsAreCompatible (unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI)
 Return true if the two registers are equal or aliased. More...
 
static bool regOverlapsSet (const SmallVectorImpl< unsigned > &Set, unsigned Reg, const TargetRegisterInfo *TRI)
 

Variables

static cl::opt< boolEnableRescheduling ("twoaddr-reschedule", cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden)
 
static cl::opt< unsignedMaxDataFlowEdge ("dataflow-edge-limit", cl::Hidden, cl::init(3), cl::desc("Maximum number of dataflow edges to traverse when evaluating " "the benefit of commuting operands"))
 
 DEBUG_TYPE
 
Two Address instruction pass
 
Two Address instruction false
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "twoaddressinstruction"

Definition at line 68 of file TwoAddressInstructionPass.cpp.

Function Documentation

◆ findOnlyInterestingUse()

static MachineInstr* findOnlyInterestingUse ( unsigned  Reg,
MachineBasicBlock MBB,
MachineRegisterInfo MRI,
const TargetInstrInfo TII,
bool IsCopy,
unsigned DstReg,
bool IsDstPhys 
)
static

Given a register, if has a single in-basic block use, return the use instruction if it's a copy or a two-address use.

Definition at line 521 of file TwoAddressInstructionPass.cpp.

References llvm::MachineInstr::getParent(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), isCopyToReg(), llvm::TargetRegisterInfo::isPhysicalRegister(), isTwoAddrUse(), llvm::MachineRegisterInfo::use_instr_nodbg_begin(), and UseMI.

Referenced by regOverlapsSet().

◆ getMappedReg()

static unsigned getMappedReg ( unsigned  Reg,
DenseMap< unsigned, unsigned > &  RegMap 
)
static

◆ getSingleDef()

static MachineInstr* getSingleDef ( unsigned  Reg,
MachineBasicBlock BB,
const MachineRegisterInfo MRI 
)
static

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( TwoAddressInstructionPass  ,
DEBUG_TYPE  ,
"Two-Address instruction pass ,
false  ,
false   
)

◆ isCopyToReg()

static bool isCopyToReg ( MachineInstr MI,
const TargetInstrInfo TII,
unsigned SrcReg,
unsigned DstReg,
bool IsSrcPhys,
bool IsDstPhys 
)
static

Return true if the specified MI is a copy instruction or an extract_subreg instruction.

It also returns the source and destination registers and whether they are physical registers by reference.

Definition at line 408 of file TwoAddressInstructionPass.cpp.

References llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::isCopy(), llvm::MachineInstr::isInsertSubreg(), llvm::TargetRegisterInfo::isPhysicalRegister(), and llvm::MachineInstr::isSubregToReg().

Referenced by findOnlyInterestingUse(), isKilled(), and regOverlapsSet().

◆ isKilled()

static bool isKilled ( MachineInstr MI,
unsigned  Reg,
const MachineRegisterInfo MRI,
const TargetInstrInfo TII,
LiveIntervals LIS,
bool  allowFalsePositives 
)
static

Test if the given register value, which is used by the given instruction, is killed by the given instruction.

This looks through coalescable copies to see if the original value is potentially not killed.

For example, in this code:

reg1034 = copy reg1024 reg1035 = copy killed reg1025 reg1036 = add killed reg1034, killed reg1035

reg1034 is not considered to be killed, since it is copied from a register which is not killed. Treating it as not killed lets the normal heuristics commute the (two-address) add, which lets coalescing eliminate the extra copy.

If allowFalsePositives is true then likely kills are treated as kills even if it can't be proven that they are kills.

Definition at line 471 of file TwoAddressInstructionPass.cpp.

References llvm::MachineRegisterInfo::def_begin(), llvm::MachineRegisterInfo::def_end(), DefMI, llvm::MachineOperand::getParent(), llvm::MachineRegisterInfo::hasOneUse(), isCopyToReg(), llvm::TargetRegisterInfo::isPhysicalRegister(), isPlainlyKilled(), and MI.

Referenced by regOverlapsSet().

◆ isPlainlyKilled()

static bool isPlainlyKilled ( MachineInstr MI,
unsigned  Reg,
LiveIntervals LIS 
)
static

◆ isTwoAddrUse()

static bool isTwoAddrUse ( MachineInstr MI,
unsigned  Reg,
unsigned DstReg 
)
static

Return true if the specified MI uses the specified register as a two-address use.

If so, return the destination register by reference.

Definition at line 504 of file TwoAddressInstructionPass.cpp.

References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isRegTiedToDefOperand(), and llvm::MachineOperand::isUse().

Referenced by findOnlyInterestingUse(), and regOverlapsSet().

◆ regOverlapsSet()

static bool regOverlapsSet ( const SmallVectorImpl< unsigned > &  Set,
unsigned  Reg,
const TargetRegisterInfo TRI 
)
static

Definition at line 572 of file TwoAddressInstructionPass.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::LiveRange::addSegment(), llvm::LiveVariables::addVirtualRegisterDead(), llvm::LiveVariables::addVirtualRegisterKilled(), assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::MachineBasicBlock::begin(), llvm::LiveRange::begin(), llvm::MachineFunction::begin(), llvm::BuildMI(), llvm::SmallPtrSetImplBase::clear(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::clear(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::clear(), llvm::TargetInstrInfo::commuteInstruction(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetInstrInfo::convertToThreeAddress(), llvm::SmallSet< T, N, C >::count(), llvm::SmallPtrSetImpl< PtrType >::count(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::dbgs(), DEBUG, llvm::MachineRegisterInfo::def_instructions(), llvm::RegState::Define, DefMI, llvm::SmallVectorBase::empty(), EnableRescheduling, llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::WebAssembly::End, llvm::MachineBasicBlock::end(), llvm::LiveRange::end(), llvm::MachineFunction::end(), llvm::SmallSet< T, N, C >::erase(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::erase(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::erase(), llvm::MachineBasicBlock::erase(), llvm::MachineInstr::eraseFromParent(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::LiveRange::find(), llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::LiveVariables::VarInfo::findKill(), findOnlyInterestingUse(), llvm::MachineInstr::findRegisterUseOperand(), llvm::MCInstrInfo::get(), llvm::TargetRegisterInfo::getAllocatableClass(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::TargetSubtargetInfo::getInstrItineraryData(), llvm::TargetInstrInfo::getInstrLatency(), llvm::LiveIntervals::getInstructionFromIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::ilist_node_impl< OptionsT >::getIterator(), getMappedReg(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::TargetRegisterInfo::getMatchingSuperRegClass(), llvm::LiveIntervals::getMBBEndIdx(), llvm::MachineFunction::getName(), llvm::LiveRange::getNextValue(), llvm::MCInstrDesc::getNumDefs(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::TargetInstrInfo::getOpcodeAfterMemoryUnfold(), llvm::MachineInstr::getOperand(), llvm::TargetMachine::getOptLevel(), llvm::MachineInstr::getParent(), llvm::SlotIndex::getPrevSlot(), llvm::MachineOperand::getReg(), llvm::TargetInstrInfo::getRegClass(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::SlotIndex::getRegSlot(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::LiveVariables::getVarInfo(), llvm::LiveIntervals::getVNInfoAllocator(), llvm::LiveIntervals::handleMove(), llvm::MachineInstr::hasUnmodeledSideEffects(), I, llvm::SmallSet< T, N, C >::insert(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::MachineBasicBlock::insert(), llvm::LiveIntervals::InsertMachineInstrInMaps(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isCall(), llvm::MachineInstr::isCommutable(), llvm::MachineInstr::isConvertibleTo3Addr(), llvm::MachineInstr::isCopy(), llvm::MachineInstr::isCopyLike(), isCopyToReg(), llvm::MachineOperand::isEarlyClobber(), llvm::MachineOperand::isKill(), isKilled(), llvm::TargetRegisterInfo::isPhysicalRegister(), isPlainlyKilled(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isRegTiedToDefOperand(), llvm::MachineInstr::isSafeToMove(), llvm::MachineInstr::isTerminator(), isTwoAddrUse(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineRegisterInfo::leaveSSA(), llvm_unreachable, llvm::make_range(), MaxDataFlowEdge, llvm::MachineInstr::mayLoad(), MI, llvm::CodeGenOpt::None, llvm::MachineInstr::operands(), llvm::SmallVectorTemplateBase< T, isPodLike >::pop_back(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), regsAreCompatible(), llvm::TargetRegisterInfo::regsOverlap(), llvm::LiveVariables::VarInfo::removeKill(), llvm::MachineInstr::RemoveOperand(), llvm::LiveRange::removeSegment(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveIntervals::repairIntervalsInRange(), llvm::LiveVariables::replaceKillInstruction(), llvm::LiveIntervals::ReplaceMachineInstrInMaps(), second, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::MachineBasicBlock::splice(), llvm::SystemZISD::TM, llvm::TargetInstrInfo::unfoldMemoryOperand(), UseMI, and llvm::MachineFunction::verify().

◆ regsAreCompatible()

static bool regsAreCompatible ( unsigned  RegA,
unsigned  RegB,
const TargetRegisterInfo TRI 
)
static

Return true if the two registers are equal or aliased.

Definition at line 563 of file TwoAddressInstructionPass.cpp.

References llvm::TargetRegisterInfo::regsOverlap().

Referenced by regOverlapsSet().

◆ STATISTIC() [1/7]

STATISTIC ( NumTwoAddressInstrs  ,
"Number of two-address instructions  
)

◆ STATISTIC() [2/7]

STATISTIC ( NumCommuted  ,
"Number of instructions commuted to coalesce"   
)

◆ STATISTIC() [3/7]

STATISTIC ( NumAggrCommuted  ,
"Number of instructions aggressively commuted"   
)

◆ STATISTIC() [4/7]

STATISTIC ( NumConvertedTo3Addr  ,
"Number of instructions promoted to 3-address"   
)

◆ STATISTIC() [5/7]

STATISTIC ( Num3AddrSunk  ,
"Number of 3-address instructions sunk"   
)

◆ STATISTIC() [6/7]

STATISTIC ( NumReSchedUps  ,
"Number of instructions re-scheduled up"   
)

◆ STATISTIC() [7/7]

STATISTIC ( NumReSchedDowns  ,
"Number of instructions re-scheduled down"   
)

Variable Documentation

◆ DEBUG_TYPE

DEBUG_TYPE

Definition at line 208 of file TwoAddressInstructionPass.cpp.

◆ EnableRescheduling

cl::opt<bool> EnableRescheduling("twoaddr-reschedule", cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden)
static

Referenced by regOverlapsSet().

◆ false

Two Address instruction false

Definition at line 208 of file TwoAddressInstructionPass.cpp.

◆ MaxDataFlowEdge

cl::opt<unsigned> MaxDataFlowEdge("dataflow-edge-limit", cl::Hidden, cl::init(3), cl::desc("Maximum number of dataflow edges to traverse when evaluating " "the benefit of commuting operands"))
static

Referenced by regOverlapsSet().

◆ pass

Two Address instruction pass

Definition at line 208 of file TwoAddressInstructionPass.cpp.