LLVM 20.0.0git
Macros | Functions | Variables
RISCVTargetTransformInfo.cpp File Reference
#include "RISCVTargetTransformInfo.h"
#include "MCTargetDesc/RISCVMatInt.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/CodeGen/CostTable.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/PatternMatch.h"
#include <cmath>
#include <optional>
#include "llvm/IR/VPIntrinsics.def"

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "riscvtti"
 
#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD)
 

Functions

static InstructionCost getIntImmCostImpl (const DataLayout &DL, const RISCVSubtarget *ST, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, bool FreeZeroes)
 
static bool canUseShiftPair (Instruction *Inst, const APInt &Imm)
 
static bool isRepeatedConcatMask (ArrayRef< int > Mask, int &SubVectorSize)
 
static VectorTypegetVRGatherIndexType (MVT DataVT, const RISCVSubtarget &ST, LLVMContext &C)
 
static unsigned isM1OrSmaller (MVT VT)
 
static unsigned getISDForVPIntrinsicID (Intrinsic::ID ID)
 

Variables

static cl::opt< unsignedRVVRegisterWidthLMUL ("riscv-v-register-bit-width-lmul", cl::desc("The LMUL to use for getRegisterBitWidth queries. Affects LMUL used " "by autovectorized code. Fractional LMULs are not supported."), cl::init(2), cl::Hidden)
 
static cl::opt< unsignedSLPMaxVF ("riscv-v-slp-max-vf", cl::desc("Overrides result used for getMaximumVF query which is used " "exclusively by SLP vectorizer."), cl::Hidden)
 
static const CostTblEntry VectorIntrinsicCostTable []
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscvtti"

Definition at line 23 of file RISCVTargetTransformInfo.cpp.

◆ HELPER_MAP_VPID_TO_VPSD

#define HELPER_MAP_VPID_TO_VPSD (   VPID,
  VPSD 
)
Value:
case Intrinsic::VPID: \
return ISD::VPSD;

Function Documentation

◆ canUseShiftPair()

static bool canUseShiftPair ( Instruction Inst,
const APInt Imm 
)
static

◆ getIntImmCostImpl()

static InstructionCost getIntImmCostImpl ( const DataLayout DL,
const RISCVSubtarget ST,
const APInt Imm,
Type Ty,
TTI::TargetCostKind  CostKind,
bool  FreeZeroes 
)
static

◆ getISDForVPIntrinsicID()

static unsigned getISDForVPIntrinsicID ( Intrinsic::ID  ID)
static

◆ getVRGatherIndexType()

static VectorType * getVRGatherIndexType ( MVT  DataVT,
const RISCVSubtarget ST,
LLVMContext C 
)
static

◆ isM1OrSmaller()

static unsigned isM1OrSmaller ( MVT  VT)
static

◆ isRepeatedConcatMask()

static bool isRepeatedConcatMask ( ArrayRef< int >  Mask,
int &  SubVectorSize 
)
static

Definition at line 346 of file RISCVTargetTransformInfo.cpp.

References I, llvm::isPowerOf2_32(), and Size.

Referenced by llvm::RISCVTTIImpl::getShuffleCost().

Variable Documentation

◆ RVVRegisterWidthLMUL

cl::opt< unsigned > RVVRegisterWidthLMUL("riscv-v-register-bit-width-lmul", cl::desc( "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used " "by autovectorized code. Fractional LMULs are not supported."), cl::init(2), cl::Hidden) ( "riscv-v-register-bit-width-lmul"  ,
cl::desc( "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used " "by autovectorized code. Fractional LMULs are not supported.")  ,
cl::init(2)  ,
cl::Hidden   
)
static

◆ SLPMaxVF

cl::opt< unsigned > SLPMaxVF("riscv-v-slp-max-vf", cl::desc( "Overrides result used for getMaximumVF query which is used " "exclusively by SLP vectorizer."), cl::Hidden) ( "riscv-v-slp-max-vf"  ,
cl::desc( "Overrides result used for getMaximumVF query which is used " "exclusively by SLP vectorizer.")  ,
cl::Hidden   
)
static

◆ VectorIntrinsicCostTable

const CostTblEntry VectorIntrinsicCostTable[]
static