LLVM  10.0.0svn
DwarfExpression.cpp
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1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains support for writing dwarf debug info into asm files.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "DwarfExpression.h"
14 #include "DwarfCompileUnit.h"
15 #include "llvm/ADT/APInt.h"
18 #include "llvm/CodeGen/Register.h"
22 #include <algorithm>
23 #include <cassert>
24 #include <cstdint>
25 
26 using namespace llvm;
27 
29  if (Value < 32)
30  emitOp(dwarf::DW_OP_lit0 + Value);
31  else if (Value == std::numeric_limits<uint64_t>::max()) {
32  // Only do this for 64-bit values as the DWARF expression stack uses
33  // target-address-size values.
34  emitOp(dwarf::DW_OP_lit0);
35  emitOp(dwarf::DW_OP_not);
36  } else {
37  emitOp(dwarf::DW_OP_constu);
38  emitUnsigned(Value);
39  }
40 }
41 
42 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
43  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
45  "location description already locked down");
47  if (DwarfReg < 32) {
48  emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
49  } else {
50  emitOp(dwarf::DW_OP_regx, Comment);
51  emitUnsigned(DwarfReg);
52  }
53 }
54 
55 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
56  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
57  assert(!isRegisterLocation() && "location description already locked down");
58  if (DwarfReg < 32) {
59  emitOp(dwarf::DW_OP_breg0 + DwarfReg);
60  } else {
61  emitOp(dwarf::DW_OP_bregx);
62  emitUnsigned(DwarfReg);
63  }
64  emitSigned(Offset);
65 }
66 
68  emitOp(dwarf::DW_OP_fbreg);
69  emitSigned(Offset);
70 }
71 
72 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
73  if (!SizeInBits)
74  return;
75 
76  const unsigned SizeOfByte = 8;
77  if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
78  emitOp(dwarf::DW_OP_bit_piece);
79  emitUnsigned(SizeInBits);
80  emitUnsigned(OffsetInBits);
81  } else {
82  emitOp(dwarf::DW_OP_piece);
83  unsigned ByteSize = SizeInBits / SizeOfByte;
84  emitUnsigned(ByteSize);
85  }
86  this->OffsetInBits += SizeInBits;
87 }
88 
89 void DwarfExpression::addShr(unsigned ShiftBy) {
90  emitConstu(ShiftBy);
91  emitOp(dwarf::DW_OP_shr);
92 }
93 
94 void DwarfExpression::addAnd(unsigned Mask) {
95  emitConstu(Mask);
96  emitOp(dwarf::DW_OP_and);
97 }
98 
100  unsigned MachineReg, unsigned MaxSize) {
101  if (!llvm::Register::isPhysicalRegister(MachineReg)) {
102  if (isFrameRegister(TRI, MachineReg)) {
103  DwarfRegs.push_back({-1, 0, nullptr});
104  return true;
105  }
106  return false;
107  }
108 
109  int Reg = TRI.getDwarfRegNum(MachineReg, false);
110 
111  // If this is a valid register number, emit it.
112  if (Reg >= 0) {
113  DwarfRegs.push_back({Reg, 0, nullptr});
114  return true;
115  }
116 
117  // Walk up the super-register chain until we find a valid number.
118  // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
119  for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
120  Reg = TRI.getDwarfRegNum(*SR, false);
121  if (Reg >= 0) {
122  unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
123  unsigned Size = TRI.getSubRegIdxSize(Idx);
124  unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
125  DwarfRegs.push_back({Reg, 0, "super-register"});
126  // Use a DW_OP_bit_piece to describe the sub-register.
127  setSubRegisterPiece(Size, RegOffset);
128  return true;
129  }
130  }
131 
132  // Otherwise, attempt to find a covering set of sub-register numbers.
133  // For example, Q0 on ARM is a composition of D0+D1.
134  unsigned CurPos = 0;
135  // The size of the register in bits.
136  const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
137  unsigned RegSize = TRI.getRegSizeInBits(*RC);
138  // Keep track of the bits in the register we already emitted, so we
139  // can avoid emitting redundant aliasing subregs. Because this is
140  // just doing a greedy scan of all subregisters, it is possible that
141  // this doesn't find a combination of subregisters that fully cover
142  // the register (even though one may exist).
143  SmallBitVector Coverage(RegSize, false);
144  for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
145  unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
146  unsigned Size = TRI.getSubRegIdxSize(Idx);
147  unsigned Offset = TRI.getSubRegIdxOffset(Idx);
148  Reg = TRI.getDwarfRegNum(*SR, false);
149  if (Reg < 0)
150  continue;
151 
152  // Intersection between the bits we already emitted and the bits
153  // covered by this subregister.
154  SmallBitVector CurSubReg(RegSize, false);
155  CurSubReg.set(Offset, Offset + Size);
156 
157  // If this sub-register has a DWARF number and we haven't covered
158  // its range, emit a DWARF piece for it.
159  if (CurSubReg.test(Coverage)) {
160  // Emit a piece for any gap in the coverage.
161  if (Offset > CurPos)
162  DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
163  DwarfRegs.push_back(
164  {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
165  if (Offset >= MaxSize)
166  break;
167 
168  // Mark it as emitted.
169  Coverage.set(Offset, Offset + Size);
170  CurPos = Offset + Size;
171  }
172  }
173  // Failed to find any DWARF encoding.
174  if (CurPos == 0)
175  return false;
176  // Found a partial or complete DWARF encoding.
177  if (CurPos < RegSize)
178  DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
179  return true;
180 }
181 
183  if (DwarfVersion >= 4)
184  emitOp(dwarf::DW_OP_stack_value);
185 }
186 
190  emitOp(dwarf::DW_OP_consts);
191  emitSigned(Value);
192 }
193 
197  emitConstu(Value);
198 }
199 
203 
204  unsigned Size = Value.getBitWidth();
205  const uint64_t *Data = Value.getRawData();
206 
207  // Chop it up into 64-bit pieces, because that's the maximum that
208  // addUnsignedConstant takes.
209  unsigned Offset = 0;
210  while (Offset < Size) {
211  addUnsignedConstant(*Data++);
212  if (Offset == 0 && Size <= 64)
213  break;
214  addStackValue();
215  addOpPiece(std::min(Size - Offset, 64u), Offset);
216  Offset += 64;
217  }
218 }
219 
221  DIExpressionCursor &ExprCursor,
222  unsigned MachineReg,
223  unsigned FragmentOffsetInBits) {
224  auto Fragment = ExprCursor.getFragmentInfo();
225  if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
227  return false;
228  }
229 
230  bool HasComplexExpression = false;
231  auto Op = ExprCursor.peek();
232  if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
233  HasComplexExpression = true;
234 
235  // If the register can only be described by a complex expression (i.e.,
236  // multiple subregisters) it doesn't safely compose with another complex
237  // expression. For example, it is not possible to apply a DW_OP_deref
238  // operation to multiple DW_OP_pieces.
239  if (HasComplexExpression && DwarfRegs.size() > 1) {
240  DwarfRegs.clear();
242  return false;
243  }
244 
245  // Handle simple register locations. If we are supposed to emit
246  // a call site parameter expression and if that expression is just a register
247  // location, emit it with addBReg and offset 0, because we should emit a DWARF
248  // expression representing a value, rather than a location.
249  if (!isMemoryLocation() && !HasComplexExpression &&
250  (!isParameterValue() || isEntryValue())) {
251  for (auto &Reg : DwarfRegs) {
252  if (Reg.DwarfRegNo >= 0)
253  addReg(Reg.DwarfRegNo, Reg.Comment);
254  addOpPiece(Reg.Size);
255  }
256 
257  if (isEntryValue())
259 
260  if (isEntryValue() && !isParameterValue() && DwarfVersion >= 4)
261  emitOp(dwarf::DW_OP_stack_value);
262 
263  DwarfRegs.clear();
264  return true;
265  }
266 
267  // Don't emit locations that cannot be expressed without DW_OP_stack_value.
268  if (DwarfVersion < 4)
269  if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
270  return Op.getOp() == dwarf::DW_OP_stack_value;
271  })) {
272  DwarfRegs.clear();
274  return false;
275  }
276 
277  assert(DwarfRegs.size() == 1);
278  auto Reg = DwarfRegs[0];
279  bool FBReg = isFrameRegister(TRI, MachineReg);
280  int SignedOffset = 0;
281  assert(Reg.Size == 0 && "subregister has same size as superregister");
282 
283  // Pattern-match combinations for which more efficient representations exist.
284  // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
285  if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
286  uint64_t Offset = Op->getArg(0);
287  uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
288  if (Offset <= IntMax) {
289  SignedOffset = Offset;
290  ExprCursor.take();
291  }
292  }
293 
294  // [Reg, DW_OP_constu, Offset, DW_OP_plus] --> [DW_OP_breg, Offset]
295  // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
296  // If Reg is a subregister we need to mask it out before subtracting.
297  if (Op && Op->getOp() == dwarf::DW_OP_constu) {
298  uint64_t Offset = Op->getArg(0);
299  uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
300  auto N = ExprCursor.peekNext();
301  if (N && N->getOp() == dwarf::DW_OP_plus && Offset <= IntMax) {
302  SignedOffset = Offset;
303  ExprCursor.consume(2);
304  } else if (N && N->getOp() == dwarf::DW_OP_minus &&
305  !SubRegisterSizeInBits && Offset <= IntMax + 1) {
306  SignedOffset = -static_cast<int64_t>(Offset);
307  ExprCursor.consume(2);
308  }
309  }
310 
311  if (FBReg)
312  addFBReg(SignedOffset);
313  else
314  addBReg(Reg.DwarfRegNo, SignedOffset);
315  DwarfRegs.clear();
316  return true;
317 }
318 
320  DIExpressionCursor &ExprCursor) {
321  auto Op = ExprCursor.take();
322  (void)Op;
323  assert(Op && Op->getOp() == dwarf::DW_OP_LLVM_entry_value);
325  "We don't support entry values of memory locations yet");
326  assert(!IsEmittingEntryValue && "Already emitting entry value?");
327  assert(Op->getArg(0) == 1 &&
328  "Can currently only emit entry values covering a single operation");
329 
330  emitOp(CU.getDwarf5OrGNULocationAtom(dwarf::DW_OP_entry_value));
331  IsEmittingEntryValue = true;
333 }
334 
336  assert(IsEmittingEntryValue && "Entry value not open?");
338 
339  // Emit the entry value's size operand.
340  unsigned Size = getTemporaryBufferSize();
341  emitUnsigned(Size);
342 
343  // Emit the entry value's DWARF block operand.
345 
346  IsEmittingEntryValue = false;
347 }
348 
349 /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
350 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
351  while (ExprCursor) {
352  auto Op = ExprCursor.take();
353  switch (Op->getOp()) {
354  case dwarf::DW_OP_deref:
356  break;
357  default:
358  return false;
359  }
360  }
361  return true;
362 }
363 
365  unsigned FragmentOffsetInBits) {
366  // If we need to mask out a subregister, do it now, unless the next
367  // operation would emit an OpPiece anyway.
368  auto N = ExprCursor.peek();
369  if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
370  maskSubRegister();
371 
373 
374  while (ExprCursor) {
375  auto Op = ExprCursor.take();
376  uint64_t OpNum = Op->getOp();
377 
378  if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
379  emitOp(OpNum);
380  continue;
381  } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
382  addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
383  continue;
384  }
385 
386  switch (OpNum) {
388  unsigned SizeInBits = Op->getArg(1);
389  unsigned FragmentOffset = Op->getArg(0);
390  // The fragment offset must have already been adjusted by emitting an
391  // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
392  // location.
393  assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
394 
395  // If addMachineReg already emitted DW_OP_piece operations to represent
396  // a super-register by splicing together sub-registers, subtract the size
397  // of the pieces that was already emitted.
398  SizeInBits -= OffsetInBits - FragmentOffset;
399 
400  // If addMachineReg requested a DW_OP_bit_piece to stencil out a
401  // sub-register that is smaller than the current fragment's size, use it.
403  SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
404 
405  // Emit a DW_OP_stack_value for implicit location descriptions.
406  if (isImplicitLocation())
407  addStackValue();
408 
409  // Emit the DW_OP_piece.
410  addOpPiece(SizeInBits, SubRegisterOffsetInBits);
411  setSubRegisterPiece(0, 0);
412  // Reset the location description kind.
414  return;
415  }
416  case dwarf::DW_OP_plus_uconst:
418  emitOp(dwarf::DW_OP_plus_uconst);
419  emitUnsigned(Op->getArg(0));
420  break;
421  case dwarf::DW_OP_plus:
422  case dwarf::DW_OP_minus:
423  case dwarf::DW_OP_mul:
424  case dwarf::DW_OP_div:
425  case dwarf::DW_OP_mod:
426  case dwarf::DW_OP_or:
427  case dwarf::DW_OP_and:
428  case dwarf::DW_OP_xor:
429  case dwarf::DW_OP_shl:
430  case dwarf::DW_OP_shr:
431  case dwarf::DW_OP_shra:
432  case dwarf::DW_OP_lit0:
433  case dwarf::DW_OP_not:
434  case dwarf::DW_OP_dup:
435  emitOp(OpNum);
436  break;
437  case dwarf::DW_OP_deref:
439  // For more detailed explanation see llvm.org/PR43343.
440  assert(!isParameterValue() && "Parameter entry values should not be "
441  "dereferenced due to safety reasons.");
442  if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
443  // Turning this into a memory location description makes the deref
444  // implicit.
446  else
447  emitOp(dwarf::DW_OP_deref);
448  break;
449  case dwarf::DW_OP_constu:
451  emitConstu(Op->getArg(0));
452  break;
454  unsigned BitSize = Op->getArg(0);
455  dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
456  if (DwarfVersion >= 5) {
457  emitOp(dwarf::DW_OP_convert);
458  // Reuse the base_type if we already have one in this CU otherwise we
459  // create a new one.
460  unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
461  for (; I != E; ++I)
462  if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
463  CU.ExprRefedBaseTypes[I].Encoding == Encoding)
464  break;
465 
466  if (I == E)
467  CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
468 
469  // If targeting a location-list; simply emit the index into the raw
470  // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
471  // fitted with means to extract it later.
472  // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
473  // (containing the index and a resolve mechanism during emit) into the
474  // DIE value list.
475  emitBaseTypeRef(I);
476  } else {
477  if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
478  if (Encoding == dwarf::DW_ATE_signed)
479  emitLegacySExt(PrevConvertOp->getArg(0));
480  else if (Encoding == dwarf::DW_ATE_unsigned)
481  emitLegacyZExt(PrevConvertOp->getArg(0));
482  PrevConvertOp = None;
483  } else {
484  PrevConvertOp = Op;
485  }
486  }
487  break;
488  }
489  case dwarf::DW_OP_stack_value:
491  break;
492  case dwarf::DW_OP_swap:
494  emitOp(dwarf::DW_OP_swap);
495  break;
496  case dwarf::DW_OP_xderef:
498  emitOp(dwarf::DW_OP_xderef);
499  break;
500  case dwarf::DW_OP_deref_size:
501  emitOp(dwarf::DW_OP_deref_size);
502  emitData1(Op->getArg(0));
503  break;
505  TagOffset = Op->getArg(0);
506  break;
507  case dwarf::DW_OP_regx:
508  emitOp(dwarf::DW_OP_regx);
509  emitUnsigned(Op->getArg(0));
510  break;
511  case dwarf::DW_OP_bregx:
512  emitOp(dwarf::DW_OP_bregx);
513  emitUnsigned(Op->getArg(0));
514  emitSigned(Op->getArg(1));
515  break;
516  default:
517  llvm_unreachable("unhandled opcode found in expression");
518  }
519  }
520 
522  // Turn this into an implicit location description.
523  addStackValue();
524 }
525 
526 /// add masking operations to stencil out a subregister.
528  assert(SubRegisterSizeInBits && "no subregister was registered");
529  if (SubRegisterOffsetInBits > 0)
531  uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
532  addAnd(Mask);
533 }
534 
536  assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
537  // Emit any outstanding DW_OP_piece operations to mask out subregisters.
538  if (SubRegisterSizeInBits == 0)
539  return;
540  // Don't emit a DW_OP_piece for a subregister at offset 0.
541  if (SubRegisterOffsetInBits == 0)
542  return;
544 }
545 
547  if (!Expr || !Expr->isFragment())
548  return;
549 
550  uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
551  assert(FragmentOffset >= OffsetInBits &&
552  "overlapping or duplicate fragments");
553  if (FragmentOffset > OffsetInBits)
554  addOpPiece(FragmentOffset - OffsetInBits);
555  OffsetInBits = FragmentOffset;
556 }
557 
558 void DwarfExpression::emitLegacySExt(unsigned FromBits) {
559  // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
560  emitOp(dwarf::DW_OP_dup);
561  emitOp(dwarf::DW_OP_constu);
562  emitUnsigned(FromBits - 1);
563  emitOp(dwarf::DW_OP_shr);
564  emitOp(dwarf::DW_OP_lit0);
565  emitOp(dwarf::DW_OP_not);
566  emitOp(dwarf::DW_OP_mul);
567  emitOp(dwarf::DW_OP_constu);
568  emitUnsigned(FromBits);
569  emitOp(dwarf::DW_OP_shl);
570  emitOp(dwarf::DW_OP_or);
571 }
572 
573 void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
574  // (X & (1 << FromBits - 1))
575  emitOp(dwarf::DW_OP_constu);
576  emitUnsigned((1ULL << FromBits) - 1);
577  emitOp(dwarf::DW_OP_and);
578 }
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
void addShr(unsigned ShiftBy)
Emit a shift-right dwarf operation.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void addUnsignedConstant(uint64_t Value)
Emit an unsigned constant.
void emitConstu(uint64_t Value)
Emit a normalized unsigned constant.
bool IsEmittingEntryValue
Whether we are currently emitting an entry value operation.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
unsigned Reg
void beginEntryValueExpression(DIExpressionCursor &ExprCursor)
Begin emission of an entry value dwarf operation.
Only used in LLVM metadata.
Definition: Dwarf.h:121
unsigned const TargetRegisterInfo * TRI
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1517
bool test(unsigned Idx) const
virtual void enableTemporaryBuffer()=0
Start emitting data to the temporary buffer.
virtual void emitData1(uint8_t Value)=0
MCSuperRegIterator enumerates all super-registers of Reg.
void addBReg(int DwarfReg, int Offset)
Emit a DW_OP_breg operation.
void addFBReg(int Offset)
Emit DW_OP_fbreg <Offset>.
Only used in LLVM metadata.
Definition: Dwarf.h:120
Holds a DIExpression and keeps track of how many operands have been consumed so far.
virtual void commitTemporaryBuffer()=0
Commit the data stored in the temporary buffer to the main output.
This file implements a class to represent arbitrary precision integral constant values and operations...
void addReg(int DwarfReg, const char *Comment=nullptr)
Emit a DW_OP_reg operation.
void setSubRegisterPiece(unsigned SizeInBits, unsigned OffsetInBits)
Push a DW_OP_piece / DW_OP_bit_piece for emitting later, if one is needed to represent a subregister...
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
Optional< DIExpression::ExprOperand > peek() const
Return the current operation.
bool isImplicitLocation() const
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
static Optional< FragmentInfo > getFragmentInfo(expr_op_iterator Start, expr_op_iterator End)
Retrieve the details of this fragment expression.
void emitLegacyZExt(unsigned FromBits)
void maskSubRegister()
Add masking operations to stencil out a subregister.
uint64_t getArg(unsigned I) const
Get an argument to the operand.
Optional< DIExpression::ExprOperand > peekNext() const
Return the next operation.
virtual void emitUnsigned(uint64_t Value)=0
Emit a raw unsigned value.
Optional< DIExpression::ExprOperand > take()
Consume one operation.
uint64_t getOp() const
Get the operand code.
virtual void emitOp(uint8_t Op, const char *Comment=nullptr)=0
Output a dwarf operand and an optional assembler comment.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Only used in LLVM metadata.
Definition: Dwarf.h:122
A lightweight wrapper around an expression operand.
uint64_t OffsetInBits
Current Fragment Offset in Bits.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1172
Only used in LLVM metadata.
Definition: Dwarf.h:123
virtual void emitSigned(int64_t Value)=0
Emit a raw signed value.
virtual unsigned getTemporaryBufferSize()=0
Return the emitted size, in number of bytes, for the data stored in the temporary buffer...
bool isMemoryLocation() const
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SmallBitVector & set()
void addExpression(DIExpressionCursor &&Expr, unsigned FragmentOffsetInBits=0)
Emit all remaining operations in the DIExpressionCursor.
bool addMachineReg(const TargetRegisterInfo &TRI, unsigned MachineReg, unsigned MaxSize=~1U)
Emit a partial DWARF register operation.
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:390
bool isUnknownLocation() const
void addStackValue()
Emit a DW_OP_stack_value, if supported.
virtual void disableTemporaryBuffer()=0
Disable emission to the temporary buffer.
DWARF expression.
This file contains constants used for implementing Dwarf debug support.
Class for arbitrary precision integers.
Definition: APInt.h:69
void addAnd(unsigned Mask)
Emit a bitwise and dwarf operation.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Optional< DIExpression::FragmentInfo > getFragmentInfo() const
Retrieve the fragment information, if any.
Optional< uint8_t > TagOffset
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:674
unsigned SubRegisterSizeInBits
Sometimes we need to add a DW_OP_bit_piece to describe a subregister.
void consume(unsigned N)
Consume N operations.
virtual void emitBaseTypeRef(uint64_t Idx)=0
void finalize()
This needs to be called last to commit any pending changes.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
uint32_t Size
Definition: Profile.cpp:46
void emitLegacySExt(unsigned FromBits)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
void addFragmentOffset(const DIExpression *Expr)
If applicable, emit an empty DW_OP_piece / DW_OP_bit_piece to advance to the fragment described by Ex...
void finalizeEntryValue()
Finalize an entry value by emitting its size operand, and committing the DWARF block which has been e...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:74
void addOpPiece(unsigned SizeInBits, unsigned OffsetInBits=0)
Emit a DW_OP_piece or DW_OP_bit_piece operation for a variable fragment.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
void addSignedConstant(int64_t Value)
Emit a signed constant.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
SmallVector< Register, 2 > DwarfRegs
The register location, if any.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
bool isFragment() const
Return whether this is a piece of an aggregate variable.
bool isRegisterLocation() const
bool addMachineRegExpression(const TargetRegisterInfo &TRI, DIExpressionCursor &Expr, unsigned MachineReg, unsigned FragmentOffsetInBits=0)
Emit a machine register location.
virtual bool isFrameRegister(const TargetRegisterInfo &TRI, unsigned MachineReg)=0
Return whether the given machine register is the frame register in the current function.