LLVM  10.0.0svn
DwarfExpression.cpp
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1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains support for writing dwarf debug info into asm files.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "DwarfExpression.h"
14 #include "DwarfCompileUnit.h"
15 #include "llvm/ADT/APInt.h"
18 #include "llvm/CodeGen/Register.h"
22 #include <algorithm>
23 #include <cassert>
24 #include <cstdint>
25 
26 using namespace llvm;
27 
29  if (Value < 32)
30  emitOp(dwarf::DW_OP_lit0 + Value);
31  else if (Value == std::numeric_limits<uint64_t>::max()) {
32  // Only do this for 64-bit values as the DWARF expression stack uses
33  // target-address-size values.
34  emitOp(dwarf::DW_OP_lit0);
35  emitOp(dwarf::DW_OP_not);
36  } else {
37  emitOp(dwarf::DW_OP_constu);
38  emitUnsigned(Value);
39  }
40 }
41 
42 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
43  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
45  "location description already locked down");
47  if (DwarfReg < 32) {
48  emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
49  } else {
50  emitOp(dwarf::DW_OP_regx, Comment);
51  emitUnsigned(DwarfReg);
52  }
53 }
54 
55 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
56  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
57  assert(!isRegisterLocation() && "location description already locked down");
58  if (DwarfReg < 32) {
59  emitOp(dwarf::DW_OP_breg0 + DwarfReg);
60  } else {
61  emitOp(dwarf::DW_OP_bregx);
62  emitUnsigned(DwarfReg);
63  }
64  emitSigned(Offset);
65 }
66 
68  emitOp(dwarf::DW_OP_fbreg);
69  emitSigned(Offset);
70 }
71 
72 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
73  if (!SizeInBits)
74  return;
75 
76  const unsigned SizeOfByte = 8;
77  if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
78  emitOp(dwarf::DW_OP_bit_piece);
79  emitUnsigned(SizeInBits);
80  emitUnsigned(OffsetInBits);
81  } else {
82  emitOp(dwarf::DW_OP_piece);
83  unsigned ByteSize = SizeInBits / SizeOfByte;
84  emitUnsigned(ByteSize);
85  }
86  this->OffsetInBits += SizeInBits;
87 }
88 
89 void DwarfExpression::addShr(unsigned ShiftBy) {
90  emitConstu(ShiftBy);
91  emitOp(dwarf::DW_OP_shr);
92 }
93 
94 void DwarfExpression::addAnd(unsigned Mask) {
95  emitConstu(Mask);
96  emitOp(dwarf::DW_OP_and);
97 }
98 
100  unsigned MachineReg, unsigned MaxSize) {
101  if (!llvm::Register::isPhysicalRegister(MachineReg)) {
102  if (isFrameRegister(TRI, MachineReg)) {
103  DwarfRegs.push_back({-1, 0, nullptr});
104  return true;
105  }
106  return false;
107  }
108 
109  int Reg = TRI.getDwarfRegNum(MachineReg, false);
110 
111  // If this is a valid register number, emit it.
112  if (Reg >= 0) {
113  DwarfRegs.push_back({Reg, 0, nullptr});
114  return true;
115  }
116 
117  // Walk up the super-register chain until we find a valid number.
118  // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
119  for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
120  Reg = TRI.getDwarfRegNum(*SR, false);
121  if (Reg >= 0) {
122  unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
123  unsigned Size = TRI.getSubRegIdxSize(Idx);
124  unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
125  DwarfRegs.push_back({Reg, 0, "super-register"});
126  // Use a DW_OP_bit_piece to describe the sub-register.
127  setSubRegisterPiece(Size, RegOffset);
128  return true;
129  }
130  }
131 
132  // Otherwise, attempt to find a covering set of sub-register numbers.
133  // For example, Q0 on ARM is a composition of D0+D1.
134  unsigned CurPos = 0;
135  // The size of the register in bits.
136  const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
137  unsigned RegSize = TRI.getRegSizeInBits(*RC);
138  // Keep track of the bits in the register we already emitted, so we
139  // can avoid emitting redundant aliasing subregs. Because this is
140  // just doing a greedy scan of all subregisters, it is possible that
141  // this doesn't find a combination of subregisters that fully cover
142  // the register (even though one may exist).
143  SmallBitVector Coverage(RegSize, false);
144  for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
145  unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
146  unsigned Size = TRI.getSubRegIdxSize(Idx);
147  unsigned Offset = TRI.getSubRegIdxOffset(Idx);
148  Reg = TRI.getDwarfRegNum(*SR, false);
149  if (Reg < 0)
150  continue;
151 
152  // Intersection between the bits we already emitted and the bits
153  // covered by this subregister.
154  SmallBitVector CurSubReg(RegSize, false);
155  CurSubReg.set(Offset, Offset + Size);
156 
157  // If this sub-register has a DWARF number and we haven't covered
158  // its range, emit a DWARF piece for it.
159  if (CurSubReg.test(Coverage)) {
160  // Emit a piece for any gap in the coverage.
161  if (Offset > CurPos)
162  DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
163  DwarfRegs.push_back(
164  {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
165  if (Offset >= MaxSize)
166  break;
167 
168  // Mark it as emitted.
169  Coverage.set(Offset, Offset + Size);
170  CurPos = Offset + Size;
171  }
172  }
173  // Failed to find any DWARF encoding.
174  if (CurPos == 0)
175  return false;
176  // Found a partial or complete DWARF encoding.
177  if (CurPos < RegSize)
178  DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
179  return true;
180 }
181 
183  if (DwarfVersion >= 4)
184  emitOp(dwarf::DW_OP_stack_value);
185 }
186 
190  emitOp(dwarf::DW_OP_consts);
191  emitSigned(Value);
192 }
193 
197  emitConstu(Value);
198 }
199 
203 
204  unsigned Size = Value.getBitWidth();
205  const uint64_t *Data = Value.getRawData();
206 
207  // Chop it up into 64-bit pieces, because that's the maximum that
208  // addUnsignedConstant takes.
209  unsigned Offset = 0;
210  while (Offset < Size) {
211  addUnsignedConstant(*Data++);
212  if (Offset == 0 && Size <= 64)
213  break;
214  addStackValue();
215  addOpPiece(std::min(Size - Offset, 64u), Offset);
216  Offset += 64;
217  }
218 }
219 
221  DIExpressionCursor &ExprCursor,
222  unsigned MachineReg,
223  unsigned FragmentOffsetInBits) {
224  auto Fragment = ExprCursor.getFragmentInfo();
225  if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
227  return false;
228  }
229 
230  bool HasComplexExpression = false;
231  auto Op = ExprCursor.peek();
232  if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
233  HasComplexExpression = true;
234 
235  // If the register can only be described by a complex expression (i.e.,
236  // multiple subregisters) it doesn't safely compose with another complex
237  // expression. For example, it is not possible to apply a DW_OP_deref
238  // operation to multiple DW_OP_pieces.
239  if (HasComplexExpression && DwarfRegs.size() > 1) {
240  DwarfRegs.clear();
242  return false;
243  }
244 
245  // Handle simple register locations. If we are supposed to emit
246  // a call site parameter expression and if that expression is just a register
247  // location, emit it with addBReg and offset 0, because we should emit a DWARF
248  // expression representing a value, rather than a location.
249  if (!isMemoryLocation() && !HasComplexExpression && (!isParameterValue() ||
250  isEntryValue())) {
251  for (auto &Reg : DwarfRegs) {
252  if (Reg.DwarfRegNo >= 0)
253  addReg(Reg.DwarfRegNo, Reg.Comment);
254  addOpPiece(Reg.Size);
255  }
256 
257  if (isEntryValue() && !isParameterValue() && DwarfVersion >= 4)
258  emitOp(dwarf::DW_OP_stack_value);
259 
260  DwarfRegs.clear();
261  return true;
262  }
263 
264  // Don't emit locations that cannot be expressed without DW_OP_stack_value.
265  if (DwarfVersion < 4)
266  if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
267  return Op.getOp() == dwarf::DW_OP_stack_value;
268  })) {
269  DwarfRegs.clear();
271  return false;
272  }
273 
274  assert(DwarfRegs.size() == 1);
275  auto Reg = DwarfRegs[0];
276  bool FBReg = isFrameRegister(TRI, MachineReg);
277  int SignedOffset = 0;
278  assert(Reg.Size == 0 && "subregister has same size as superregister");
279 
280  // Pattern-match combinations for which more efficient representations exist.
281  // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
282  if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
283  SignedOffset = Op->getArg(0);
284  ExprCursor.take();
285  }
286 
287  // [Reg, DW_OP_constu, Offset, DW_OP_plus] --> [DW_OP_breg, Offset]
288  // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
289  // If Reg is a subregister we need to mask it out before subtracting.
290  if (Op && Op->getOp() == dwarf::DW_OP_constu) {
291  auto N = ExprCursor.peekNext();
292  if (N && (N->getOp() == dwarf::DW_OP_plus ||
293  (N->getOp() == dwarf::DW_OP_minus && !SubRegisterSizeInBits))) {
294  int Offset = Op->getArg(0);
295  SignedOffset = (N->getOp() == dwarf::DW_OP_minus) ? -Offset : Offset;
296  ExprCursor.consume(2);
297  }
298  }
299 
300  if (FBReg)
301  addFBReg(SignedOffset);
302  else
303  addBReg(Reg.DwarfRegNo, SignedOffset);
304  DwarfRegs.clear();
305  return true;
306 }
307 
309  auto Op = ExprCursor.take();
310  assert(Op && Op->getOp() == dwarf::DW_OP_entry_value);
312  "We don't support entry values of memory locations yet");
313 
314  if (DwarfVersion >= 5)
315  emitOp(dwarf::DW_OP_entry_value);
316  else
317  emitOp(dwarf::DW_OP_GNU_entry_value);
318  emitUnsigned(Op->getArg(0));
319 }
320 
321 /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
322 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
323  while (ExprCursor) {
324  auto Op = ExprCursor.take();
325  switch (Op->getOp()) {
326  case dwarf::DW_OP_deref:
328  break;
329  default:
330  return false;
331  }
332  }
333  return true;
334 }
335 
337  unsigned FragmentOffsetInBits) {
338  // If we need to mask out a subregister, do it now, unless the next
339  // operation would emit an OpPiece anyway.
340  auto N = ExprCursor.peek();
341  if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
342  maskSubRegister();
343 
345 
346  while (ExprCursor) {
347  auto Op = ExprCursor.take();
348  uint64_t OpNum = Op->getOp();
349 
350  if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
351  emitOp(OpNum);
352  continue;
353  } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
354  addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
355  continue;
356  }
357 
358  switch (OpNum) {
360  unsigned SizeInBits = Op->getArg(1);
361  unsigned FragmentOffset = Op->getArg(0);
362  // The fragment offset must have already been adjusted by emitting an
363  // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
364  // location.
365  assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
366 
367  // If addMachineReg already emitted DW_OP_piece operations to represent
368  // a super-register by splicing together sub-registers, subtract the size
369  // of the pieces that was already emitted.
370  SizeInBits -= OffsetInBits - FragmentOffset;
371 
372  // If addMachineReg requested a DW_OP_bit_piece to stencil out a
373  // sub-register that is smaller than the current fragment's size, use it.
375  SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
376 
377  // Emit a DW_OP_stack_value for implicit location descriptions.
378  if (isImplicitLocation())
379  addStackValue();
380 
381  // Emit the DW_OP_piece.
382  addOpPiece(SizeInBits, SubRegisterOffsetInBits);
383  setSubRegisterPiece(0, 0);
384  // Reset the location description kind.
386  return;
387  }
388  case dwarf::DW_OP_plus_uconst:
390  emitOp(dwarf::DW_OP_plus_uconst);
391  emitUnsigned(Op->getArg(0));
392  break;
393  case dwarf::DW_OP_plus:
394  case dwarf::DW_OP_minus:
395  case dwarf::DW_OP_mul:
396  case dwarf::DW_OP_div:
397  case dwarf::DW_OP_mod:
398  case dwarf::DW_OP_or:
399  case dwarf::DW_OP_and:
400  case dwarf::DW_OP_xor:
401  case dwarf::DW_OP_shl:
402  case dwarf::DW_OP_shr:
403  case dwarf::DW_OP_shra:
404  case dwarf::DW_OP_lit0:
405  case dwarf::DW_OP_not:
406  case dwarf::DW_OP_dup:
407  emitOp(OpNum);
408  break;
409  case dwarf::DW_OP_deref:
411  if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
412  // Turning this into a memory location description makes the deref
413  // implicit.
415  else
416  emitOp(dwarf::DW_OP_deref);
417  break;
418  case dwarf::DW_OP_constu:
420  emitConstu(Op->getArg(0));
421  break;
423  unsigned BitSize = Op->getArg(0);
424  dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
425  if (DwarfVersion >= 5) {
426  emitOp(dwarf::DW_OP_convert);
427  // Reuse the base_type if we already have one in this CU otherwise we
428  // create a new one.
429  unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
430  for (; I != E; ++I)
431  if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
432  CU.ExprRefedBaseTypes[I].Encoding == Encoding)
433  break;
434 
435  if (I == E)
436  CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
437 
438  // If targeting a location-list; simply emit the index into the raw
439  // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
440  // fitted with means to extract it later.
441  // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
442  // (containing the index and a resolve mechanism during emit) into the
443  // DIE value list.
444  emitBaseTypeRef(I);
445  } else {
446  if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
447  if (Encoding == dwarf::DW_ATE_signed)
448  emitLegacySExt(PrevConvertOp->getArg(0));
449  else if (Encoding == dwarf::DW_ATE_unsigned)
450  emitLegacyZExt(PrevConvertOp->getArg(0));
451  PrevConvertOp = None;
452  } else {
453  PrevConvertOp = Op;
454  }
455  }
456  break;
457  }
458  case dwarf::DW_OP_stack_value:
460  break;
461  case dwarf::DW_OP_swap:
463  emitOp(dwarf::DW_OP_swap);
464  break;
465  case dwarf::DW_OP_xderef:
467  emitOp(dwarf::DW_OP_xderef);
468  break;
469  case dwarf::DW_OP_deref_size:
470  emitOp(dwarf::DW_OP_deref_size);
471  emitData1(Op->getArg(0));
472  break;
474  TagOffset = Op->getArg(0);
475  break;
476  case dwarf::DW_OP_regx:
477  emitOp(dwarf::DW_OP_regx);
478  emitUnsigned(Op->getArg(0));
479  break;
480  case dwarf::DW_OP_bregx:
481  emitOp(dwarf::DW_OP_bregx);
482  emitUnsigned(Op->getArg(0));
483  emitSigned(Op->getArg(1));
484  break;
485  default:
486  llvm_unreachable("unhandled opcode found in expression");
487  }
488  }
489 
491  // Turn this into an implicit location description.
492  addStackValue();
493 }
494 
495 /// add masking operations to stencil out a subregister.
497  assert(SubRegisterSizeInBits && "no subregister was registered");
498  if (SubRegisterOffsetInBits > 0)
500  uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
501  addAnd(Mask);
502 }
503 
505  assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
506  // Emit any outstanding DW_OP_piece operations to mask out subregisters.
507  if (SubRegisterSizeInBits == 0)
508  return;
509  // Don't emit a DW_OP_piece for a subregister at offset 0.
510  if (SubRegisterOffsetInBits == 0)
511  return;
513 }
514 
516  if (!Expr || !Expr->isFragment())
517  return;
518 
519  uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
520  assert(FragmentOffset >= OffsetInBits &&
521  "overlapping or duplicate fragments");
522  if (FragmentOffset > OffsetInBits)
523  addOpPiece(FragmentOffset - OffsetInBits);
524  OffsetInBits = FragmentOffset;
525 }
526 
527 void DwarfExpression::emitLegacySExt(unsigned FromBits) {
528  // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
529  emitOp(dwarf::DW_OP_dup);
530  emitOp(dwarf::DW_OP_constu);
531  emitUnsigned(FromBits - 1);
532  emitOp(dwarf::DW_OP_shr);
533  emitOp(dwarf::DW_OP_lit0);
534  emitOp(dwarf::DW_OP_not);
535  emitOp(dwarf::DW_OP_mul);
536  emitOp(dwarf::DW_OP_constu);
537  emitUnsigned(FromBits);
538  emitOp(dwarf::DW_OP_shl);
539  emitOp(dwarf::DW_OP_or);
540 }
541 
542 void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
543  // (X & (1 << FromBits - 1))
544  emitOp(dwarf::DW_OP_constu);
545  emitUnsigned((1ULL << FromBits) - 1);
546  emitOp(dwarf::DW_OP_and);
547 }
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
void addShr(unsigned ShiftBy)
Emit a shift-right dwarf operation.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void addUnsignedConstant(uint64_t Value)
Emit an unsigned constant.
void emitConstu(uint64_t Value)
Emit a normalized unsigned constant.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
unsigned Reg
Only used in LLVM metadata.
Definition: Dwarf.h:121
unsigned const TargetRegisterInfo * TRI
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1515
bool test(unsigned Idx) const
virtual void emitData1(uint8_t Value)=0
MCSuperRegIterator enumerates all super-registers of Reg.
void addBReg(int DwarfReg, int Offset)
Emit a DW_OP_breg operation.
void addFBReg(int Offset)
Emit DW_OP_fbreg <Offset>.
Only used in LLVM metadata.
Definition: Dwarf.h:120
Holds a DIExpression and keeps track of how many operands have been consumed so far.
This file implements a class to represent arbitrary precision integral constant values and operations...
void addReg(int DwarfReg, const char *Comment=nullptr)
Emit a DW_OP_reg operation.
void setSubRegisterPiece(unsigned SizeInBits, unsigned OffsetInBits)
Push a DW_OP_piece / DW_OP_bit_piece for emitting later, if one is needed to represent a subregister...
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
Optional< DIExpression::ExprOperand > peek() const
Return the current operation.
bool isImplicitLocation() const
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
static Optional< FragmentInfo > getFragmentInfo(expr_op_iterator Start, expr_op_iterator End)
Retrieve the details of this fragment expression.
void emitLegacyZExt(unsigned FromBits)
void maskSubRegister()
Add masking operations to stencil out a subregister.
uint64_t getArg(unsigned I) const
Get an argument to the operand.
Optional< DIExpression::ExprOperand > peekNext() const
Return the next operation.
virtual void emitUnsigned(uint64_t Value)=0
Emit a raw unsigned value.
Optional< DIExpression::ExprOperand > take()
Consume one operation.
uint64_t getOp() const
Get the operand code.
virtual void emitOp(uint8_t Op, const char *Comment=nullptr)=0
Output a dwarf operand and an optional assembler comment.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Only used in LLVM metadata.
Definition: Dwarf.h:122
A lightweight wrapper around an expression operand.
uint64_t OffsetInBits
Current Fragment Offset in Bits.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1184
void addEntryValueExpression(DIExpressionCursor &ExprCursor)
Emit entry value dwarf operation.
virtual void emitSigned(int64_t Value)=0
Emit a raw signed value.
bool isMemoryLocation() const
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SmallBitVector & set()
void addExpression(DIExpressionCursor &&Expr, unsigned FragmentOffsetInBits=0)
Emit all remaining operations in the DIExpressionCursor.
bool addMachineReg(const TargetRegisterInfo &TRI, unsigned MachineReg, unsigned MaxSize=~1U)
Emit a partial DWARF register operation.
bool isUnknownLocation() const
void addStackValue()
Emit a DW_OP_stack_value, if supported.
DWARF expression.
This file contains constants used for implementing Dwarf debug support.
Class for arbitrary precision integers.
Definition: APInt.h:69
void addAnd(unsigned Mask)
Emit a bitwise and dwarf operation.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Optional< DIExpression::FragmentInfo > getFragmentInfo() const
Retrieve the fragment information, if any.
Optional< uint8_t > TagOffset
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:674
unsigned SubRegisterSizeInBits
Sometimes we need to add a DW_OP_bit_piece to describe a subregister.
void consume(unsigned N)
Consume N operations.
virtual void emitBaseTypeRef(uint64_t Idx)=0
void finalize()
This needs to be called last to commit any pending changes.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
uint32_t Size
Definition: Profile.cpp:46
void emitLegacySExt(unsigned FromBits)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
void addFragmentOffset(const DIExpression *Expr)
If applicable, emit an empty DW_OP_piece / DW_OP_bit_piece to advance to the fragment described by Ex...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
void addOpPiece(unsigned SizeInBits, unsigned OffsetInBits=0)
Emit a DW_OP_piece or DW_OP_bit_piece operation for a variable fragment.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
void addSignedConstant(int64_t Value)
Emit a signed constant.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
SmallVector< Register, 2 > DwarfRegs
The register location, if any.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
bool isFragment() const
Return whether this is a piece of an aggregate variable.
bool isRegisterLocation() const
bool addMachineRegExpression(const TargetRegisterInfo &TRI, DIExpressionCursor &Expr, unsigned MachineReg, unsigned FragmentOffsetInBits=0)
Emit a machine register location.
virtual bool isFrameRegister(const TargetRegisterInfo &TRI, unsigned MachineReg)=0
Return whether the given machine register is the frame register in the current function.