LLVM  12.0.0git
DwarfExpression.cpp
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1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains support for writing dwarf debug info into asm files.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "DwarfExpression.h"
14 #include "DwarfCompileUnit.h"
15 #include "llvm/ADT/APInt.h"
18 #include "llvm/CodeGen/Register.h"
22 #include <algorithm>
23 #include <cassert>
24 #include <cstdint>
25 
26 using namespace llvm;
27 
29  if (Value < 32)
30  emitOp(dwarf::DW_OP_lit0 + Value);
31  else if (Value == std::numeric_limits<uint64_t>::max()) {
32  // Only do this for 64-bit values as the DWARF expression stack uses
33  // target-address-size values.
34  emitOp(dwarf::DW_OP_lit0);
35  emitOp(dwarf::DW_OP_not);
36  } else {
37  emitOp(dwarf::DW_OP_constu);
38  emitUnsigned(Value);
39  }
40 }
41 
42 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
43  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
45  "location description already locked down");
47  if (DwarfReg < 32) {
48  emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
49  } else {
50  emitOp(dwarf::DW_OP_regx, Comment);
51  emitUnsigned(DwarfReg);
52  }
53 }
54 
55 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
56  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
57  assert(!isRegisterLocation() && "location description already locked down");
58  if (DwarfReg < 32) {
59  emitOp(dwarf::DW_OP_breg0 + DwarfReg);
60  } else {
61  emitOp(dwarf::DW_OP_bregx);
62  emitUnsigned(DwarfReg);
63  }
64  emitSigned(Offset);
65 }
66 
68  emitOp(dwarf::DW_OP_fbreg);
69  emitSigned(Offset);
70 }
71 
72 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
73  if (!SizeInBits)
74  return;
75 
76  const unsigned SizeOfByte = 8;
77  if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
78  emitOp(dwarf::DW_OP_bit_piece);
79  emitUnsigned(SizeInBits);
80  emitUnsigned(OffsetInBits);
81  } else {
82  emitOp(dwarf::DW_OP_piece);
83  unsigned ByteSize = SizeInBits / SizeOfByte;
84  emitUnsigned(ByteSize);
85  }
86  this->OffsetInBits += SizeInBits;
87 }
88 
89 void DwarfExpression::addShr(unsigned ShiftBy) {
90  emitConstu(ShiftBy);
91  emitOp(dwarf::DW_OP_shr);
92 }
93 
94 void DwarfExpression::addAnd(unsigned Mask) {
95  emitConstu(Mask);
96  emitOp(dwarf::DW_OP_and);
97 }
98 
100  unsigned MachineReg, unsigned MaxSize) {
101  if (!llvm::Register::isPhysicalRegister(MachineReg)) {
102  if (isFrameRegister(TRI, MachineReg)) {
103  DwarfRegs.push_back(Register::createRegister(-1, nullptr));
104  return true;
105  }
106  return false;
107  }
108 
109  int Reg = TRI.getDwarfRegNum(MachineReg, false);
110 
111  // If this is a valid register number, emit it.
112  if (Reg >= 0) {
113  DwarfRegs.push_back(Register::createRegister(Reg, nullptr));
114  return true;
115  }
116 
117  // Walk up the super-register chain until we find a valid number.
118  // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
119  for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
120  Reg = TRI.getDwarfRegNum(*SR, false);
121  if (Reg >= 0) {
122  unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
123  unsigned Size = TRI.getSubRegIdxSize(Idx);
124  unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
125  DwarfRegs.push_back(Register::createRegister(Reg, "super-register"));
126  // Use a DW_OP_bit_piece to describe the sub-register.
127  setSubRegisterPiece(Size, RegOffset);
128  return true;
129  }
130  }
131 
132  // Otherwise, attempt to find a covering set of sub-register numbers.
133  // For example, Q0 on ARM is a composition of D0+D1.
134  unsigned CurPos = 0;
135  // The size of the register in bits.
136  const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
137  unsigned RegSize = TRI.getRegSizeInBits(*RC);
138  // Keep track of the bits in the register we already emitted, so we
139  // can avoid emitting redundant aliasing subregs. Because this is
140  // just doing a greedy scan of all subregisters, it is possible that
141  // this doesn't find a combination of subregisters that fully cover
142  // the register (even though one may exist).
143  SmallBitVector Coverage(RegSize, false);
144  for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
145  unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
146  unsigned Size = TRI.getSubRegIdxSize(Idx);
147  unsigned Offset = TRI.getSubRegIdxOffset(Idx);
148  Reg = TRI.getDwarfRegNum(*SR, false);
149  if (Reg < 0)
150  continue;
151 
152  // Used to build the intersection between the bits we already
153  // emitted and the bits covered by this subregister.
154  SmallBitVector CurSubReg(RegSize, false);
155  CurSubReg.set(Offset, Offset + Size);
156 
157  // If this sub-register has a DWARF number and we haven't covered
158  // its range, and its range covers the value, emit a DWARF piece for it.
159  if (Offset < MaxSize && CurSubReg.test(Coverage)) {
160  // Emit a piece for any gap in the coverage.
161  if (Offset > CurPos)
163  -1, Offset - CurPos, "no DWARF register encoding"));
164  if (Offset == 0 && Size >= MaxSize)
165  DwarfRegs.push_back(Register::createRegister(Reg, "sub-register"));
166  else
168  Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"));
169  }
170  // Mark it as emitted.
171  Coverage.set(Offset, Offset + Size);
172  CurPos = Offset + Size;
173  }
174  // Failed to find any DWARF encoding.
175  if (CurPos == 0)
176  return false;
177  // Found a partial or complete DWARF encoding.
178  if (CurPos < RegSize)
180  -1, RegSize - CurPos, "no DWARF register encoding"));
181  return true;
182 }
183 
185  if (DwarfVersion >= 4)
186  emitOp(dwarf::DW_OP_stack_value);
187 }
188 
192  emitOp(dwarf::DW_OP_consts);
193  emitSigned(Value);
194 }
195 
199  emitConstu(Value);
200 }
201 
205 
206  unsigned Size = Value.getBitWidth();
207  const uint64_t *Data = Value.getRawData();
208 
209  // Chop it up into 64-bit pieces, because that's the maximum that
210  // addUnsignedConstant takes.
211  unsigned Offset = 0;
212  while (Offset < Size) {
213  addUnsignedConstant(*Data++);
214  if (Offset == 0 && Size <= 64)
215  break;
216  addStackValue();
217  addOpPiece(std::min(Size - Offset, 64u), Offset);
218  Offset += 64;
219  }
220 }
221 
223  DIExpressionCursor &ExprCursor,
224  unsigned MachineReg,
225  unsigned FragmentOffsetInBits) {
226  auto Fragment = ExprCursor.getFragmentInfo();
227  if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
229  return false;
230  }
231 
232  bool HasComplexExpression = false;
233  auto Op = ExprCursor.peek();
234  if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
235  HasComplexExpression = true;
236 
237  // If the register can only be described by a complex expression (i.e.,
238  // multiple subregisters) it doesn't safely compose with another complex
239  // expression. For example, it is not possible to apply a DW_OP_deref
240  // operation to multiple DW_OP_pieces, since composite location descriptions
241  // do not push anything on the DWARF stack.
242  //
243  // DW_OP_entry_value operations can only hold a DWARF expression or a
244  // register location description, so we can't emit a single entry value
245  // covering a composite location description. In the future we may want to
246  // emit entry value operations for each register location in the composite
247  // location, but until that is supported do not emit anything.
248  if ((HasComplexExpression || IsEmittingEntryValue) && DwarfRegs.size() > 1) {
251  DwarfRegs.clear();
253  return false;
254  }
255 
256  // Handle simple register locations. If we are supposed to emit
257  // a call site parameter expression and if that expression is just a register
258  // location, emit it with addBReg and offset 0, because we should emit a DWARF
259  // expression representing a value, rather than a location.
260  if (!isMemoryLocation() && !HasComplexExpression &&
261  (!isParameterValue() || isEntryValue())) {
262  for (auto &Reg : DwarfRegs) {
263  if (Reg.DwarfRegNo >= 0)
264  addReg(Reg.DwarfRegNo, Reg.Comment);
265  addOpPiece(Reg.SubRegSize);
266  }
267 
268  if (isEntryValue())
270 
271  if (isEntryValue() && !isIndirect() && !isParameterValue() &&
272  DwarfVersion >= 4)
273  emitOp(dwarf::DW_OP_stack_value);
274 
275  DwarfRegs.clear();
276  return true;
277  }
278 
279  // Don't emit locations that cannot be expressed without DW_OP_stack_value.
280  if (DwarfVersion < 4)
281  if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
282  return Op.getOp() == dwarf::DW_OP_stack_value;
283  })) {
284  DwarfRegs.clear();
286  return false;
287  }
288 
289  assert(DwarfRegs.size() == 1);
290  auto Reg = DwarfRegs[0];
291  bool FBReg = isFrameRegister(TRI, MachineReg);
292  int SignedOffset = 0;
293  assert(!Reg.isSubRegister() && "full register expected");
294 
295  // Pattern-match combinations for which more efficient representations exist.
296  // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
297  if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
298  uint64_t Offset = Op->getArg(0);
299  uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
300  if (Offset <= IntMax) {
301  SignedOffset = Offset;
302  ExprCursor.take();
303  }
304  }
305 
306  // [Reg, DW_OP_constu, Offset, DW_OP_plus] --> [DW_OP_breg, Offset]
307  // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
308  // If Reg is a subregister we need to mask it out before subtracting.
309  if (Op && Op->getOp() == dwarf::DW_OP_constu) {
310  uint64_t Offset = Op->getArg(0);
311  uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
312  auto N = ExprCursor.peekNext();
313  if (N && N->getOp() == dwarf::DW_OP_plus && Offset <= IntMax) {
314  SignedOffset = Offset;
315  ExprCursor.consume(2);
316  } else if (N && N->getOp() == dwarf::DW_OP_minus &&
317  !SubRegisterSizeInBits && Offset <= IntMax + 1) {
318  SignedOffset = -static_cast<int64_t>(Offset);
319  ExprCursor.consume(2);
320  }
321  }
322 
323  if (FBReg)
324  addFBReg(SignedOffset);
325  else
326  addBReg(Reg.DwarfRegNo, SignedOffset);
327  DwarfRegs.clear();
328  return true;
329 }
330 
333  if (Loc.isIndirect())
335 }
336 
338  const DIExpression *DIExpr) {
339  if (Loc.isIndirect())
340  // Do not treat entry value descriptions of indirect parameters as memory
341  // locations. This allows DwarfExpression::addReg() to add DW_OP_regN to an
342  // entry value description.
343  if (!DIExpr->isEntryValue())
345 
346  if (DIExpr->isEntryValue())
347  setEntryValueFlags(Loc);
348 }
349 
351  DIExpressionCursor &ExprCursor) {
352  auto Op = ExprCursor.take();
353  (void)Op;
354  assert(Op && Op->getOp() == dwarf::DW_OP_LLVM_entry_value);
356  "We don't support entry values of memory locations yet");
357  assert(!IsEmittingEntryValue && "Already emitting entry value?");
358  assert(Op->getArg(0) == 1 &&
359  "Can currently only emit entry values covering a single operation");
360 
361  IsEmittingEntryValue = true;
363 }
364 
366  assert(IsEmittingEntryValue && "Entry value not open?");
368 
369  emitOp(CU.getDwarf5OrGNULocationAtom(dwarf::DW_OP_entry_value));
370 
371  // Emit the entry value's size operand.
372  unsigned Size = getTemporaryBufferSize();
373  emitUnsigned(Size);
374 
375  // Emit the entry value's DWARF block operand.
377 
378  IsEmittingEntryValue = false;
379 }
380 
382  assert(IsEmittingEntryValue && "Entry value not open?");
384 
385  // The temporary buffer can't be emptied, so for now just assert that nothing
386  // has been emitted to it.
388  "Began emitting entry value block before cancelling entry value");
389 
390  IsEmittingEntryValue = false;
391 }
392 
393 unsigned DwarfExpression::getOrCreateBaseType(unsigned BitSize,
394  dwarf::TypeKind Encoding) {
395  // Reuse the base_type if we already have one in this CU otherwise we
396  // create a new one.
397  unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
398  for (; I != E; ++I)
399  if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
400  CU.ExprRefedBaseTypes[I].Encoding == Encoding)
401  break;
402 
403  if (I == E)
404  CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
405  return I;
406 }
407 
408 /// Assuming a well-formed expression, match "DW_OP_deref*
409 /// DW_OP_LLVM_fragment?".
410 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
411  while (ExprCursor) {
412  auto Op = ExprCursor.take();
413  switch (Op->getOp()) {
414  case dwarf::DW_OP_deref:
416  break;
417  default:
418  return false;
419  }
420  }
421  return true;
422 }
423 
425  unsigned FragmentOffsetInBits) {
426  // Entry values can currently only cover the initial register location,
427  // and not any other parts of the following DWARF expression.
428  assert(!IsEmittingEntryValue && "Can't emit entry value around expression");
429 
430  // If we need to mask out a subregister, do it now, unless the next
431  // operation would emit an OpPiece anyway.
432  auto N = ExprCursor.peek();
433  if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
434  maskSubRegister();
435 
437 
438  while (ExprCursor) {
439  auto Op = ExprCursor.take();
440  uint64_t OpNum = Op->getOp();
441 
442  if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
443  emitOp(OpNum);
444  continue;
445  } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
446  addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
447  continue;
448  }
449 
450  switch (OpNum) {
452  unsigned SizeInBits = Op->getArg(1);
453  unsigned FragmentOffset = Op->getArg(0);
454  // The fragment offset must have already been adjusted by emitting an
455  // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
456  // location.
457  assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
458  assert(SizeInBits >= OffsetInBits - FragmentOffset && "size underflow");
459 
460  // If addMachineReg already emitted DW_OP_piece operations to represent
461  // a super-register by splicing together sub-registers, subtract the size
462  // of the pieces that was already emitted.
463  SizeInBits -= OffsetInBits - FragmentOffset;
464 
465  // If addMachineReg requested a DW_OP_bit_piece to stencil out a
466  // sub-register that is smaller than the current fragment's size, use it.
468  SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
469 
470  // Emit a DW_OP_stack_value for implicit location descriptions.
471  if (isImplicitLocation())
472  addStackValue();
473 
474  // Emit the DW_OP_piece.
475  addOpPiece(SizeInBits, SubRegisterOffsetInBits);
476  setSubRegisterPiece(0, 0);
477  // Reset the location description kind.
479  return;
480  }
481  case dwarf::DW_OP_plus_uconst:
483  emitOp(dwarf::DW_OP_plus_uconst);
484  emitUnsigned(Op->getArg(0));
485  break;
486  case dwarf::DW_OP_plus:
487  case dwarf::DW_OP_minus:
488  case dwarf::DW_OP_mul:
489  case dwarf::DW_OP_div:
490  case dwarf::DW_OP_mod:
491  case dwarf::DW_OP_or:
492  case dwarf::DW_OP_and:
493  case dwarf::DW_OP_xor:
494  case dwarf::DW_OP_shl:
495  case dwarf::DW_OP_shr:
496  case dwarf::DW_OP_shra:
497  case dwarf::DW_OP_lit0:
498  case dwarf::DW_OP_not:
499  case dwarf::DW_OP_dup:
500  case dwarf::DW_OP_push_object_address:
501  emitOp(OpNum);
502  break;
503  case dwarf::DW_OP_deref:
505  if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
506  // Turning this into a memory location description makes the deref
507  // implicit.
509  else
510  emitOp(dwarf::DW_OP_deref);
511  break;
512  case dwarf::DW_OP_constu:
514  emitConstu(Op->getArg(0));
515  break;
517  unsigned BitSize = Op->getArg(0);
518  dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
519  if (DwarfVersion >= 5) {
520  emitOp(dwarf::DW_OP_convert);
521  // If targeting a location-list; simply emit the index into the raw
522  // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
523  // fitted with means to extract it later.
524  // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
525  // (containing the index and a resolve mechanism during emit) into the
526  // DIE value list.
527  emitBaseTypeRef(getOrCreateBaseType(BitSize, Encoding));
528  } else {
529  if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
530  if (Encoding == dwarf::DW_ATE_signed)
531  emitLegacySExt(PrevConvertOp->getArg(0));
532  else if (Encoding == dwarf::DW_ATE_unsigned)
533  emitLegacyZExt(PrevConvertOp->getArg(0));
534  PrevConvertOp = None;
535  } else {
536  PrevConvertOp = Op;
537  }
538  }
539  break;
540  }
541  case dwarf::DW_OP_stack_value:
543  break;
544  case dwarf::DW_OP_swap:
546  emitOp(dwarf::DW_OP_swap);
547  break;
548  case dwarf::DW_OP_xderef:
550  emitOp(dwarf::DW_OP_xderef);
551  break;
552  case dwarf::DW_OP_deref_size:
553  emitOp(dwarf::DW_OP_deref_size);
554  emitData1(Op->getArg(0));
555  break;
557  TagOffset = Op->getArg(0);
558  break;
559  case dwarf::DW_OP_regx:
560  emitOp(dwarf::DW_OP_regx);
561  emitUnsigned(Op->getArg(0));
562  break;
563  case dwarf::DW_OP_bregx:
564  emitOp(dwarf::DW_OP_bregx);
565  emitUnsigned(Op->getArg(0));
566  emitSigned(Op->getArg(1));
567  break;
568  default:
569  llvm_unreachable("unhandled opcode found in expression");
570  }
571  }
572 
574  // Turn this into an implicit location description.
575  addStackValue();
576 }
577 
578 /// add masking operations to stencil out a subregister.
580  assert(SubRegisterSizeInBits && "no subregister was registered");
581  if (SubRegisterOffsetInBits > 0)
583  uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
584  addAnd(Mask);
585 }
586 
588  assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
589  // Emit any outstanding DW_OP_piece operations to mask out subregisters.
590  if (SubRegisterSizeInBits == 0)
591  return;
592  // Don't emit a DW_OP_piece for a subregister at offset 0.
593  if (SubRegisterOffsetInBits == 0)
594  return;
596 }
597 
599  if (!Expr || !Expr->isFragment())
600  return;
601 
602  uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
603  assert(FragmentOffset >= OffsetInBits &&
604  "overlapping or duplicate fragments");
605  if (FragmentOffset > OffsetInBits)
606  addOpPiece(FragmentOffset - OffsetInBits);
607  OffsetInBits = FragmentOffset;
608 }
609 
610 void DwarfExpression::emitLegacySExt(unsigned FromBits) {
611  // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
612  emitOp(dwarf::DW_OP_dup);
613  emitOp(dwarf::DW_OP_constu);
614  emitUnsigned(FromBits - 1);
615  emitOp(dwarf::DW_OP_shr);
616  emitOp(dwarf::DW_OP_lit0);
617  emitOp(dwarf::DW_OP_not);
618  emitOp(dwarf::DW_OP_mul);
619  emitOp(dwarf::DW_OP_constu);
620  emitUnsigned(FromBits);
621  emitOp(dwarf::DW_OP_shl);
622  emitOp(dwarf::DW_OP_or);
623 }
624 
625 void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
626  // (X & (1 << FromBits - 1))
627  emitOp(dwarf::DW_OP_constu);
628  emitUnsigned((1ULL << FromBits) - 1);
629  emitOp(dwarf::DW_OP_and);
630 }
631 
635  emitOp(dwarf::DW_OP_WASM_location);
636  emitUnsigned(Index);
637  emitUnsigned(Offset);
638 }
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
This is a &#39;bitvector&#39; (really, a variable-sized bit array), optimized for the case when the array is ...
void addShr(unsigned ShiftBy)
Emit a shift-right dwarf operation.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void addUnsignedConstant(uint64_t Value)
Emit an unsigned constant.
void emitConstu(uint64_t Value)
Emit a normalized unsigned constant.
bool IsEmittingEntryValue
Whether we are currently emitting an entry value operation.
void setMemoryLocationKind()
Lock this down to become a memory location description.
void cancelEntryValue()
Cancel the emission of an entry value.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
unsigned Reg
void beginEntryValueExpression(DIExpressionCursor &ExprCursor)
Begin emission of an entry value dwarf operation.
Only used in LLVM metadata.
Definition: Dwarf.h:122
unsigned const TargetRegisterInfo * TRI
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1569
bool test(unsigned Idx) const
virtual void enableTemporaryBuffer()=0
Start emitting data to the temporary buffer.
virtual void emitData1(uint8_t Value)=0
MCSuperRegIterator enumerates all super-registers of Reg.
void addBReg(int DwarfReg, int Offset)
Emit a DW_OP_breg operation.
void addFBReg(int Offset)
Emit DW_OP_fbreg <Offset>.
Only used in LLVM metadata.
Definition: Dwarf.h:121
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
Holds a DIExpression and keeps track of how many operands have been consumed so far.
virtual void commitTemporaryBuffer()=0
Commit the data stored in the temporary buffer to the main output.
This file implements a class to represent arbitrary precision integral constant values and operations...
void addReg(int DwarfReg, const char *Comment=nullptr)
Emit a DW_OP_reg operation.
void setSubRegisterPiece(unsigned SizeInBits, unsigned OffsetInBits)
Push a DW_OP_piece / DW_OP_bit_piece for emitting later, if one is needed to represent a subregister...
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
Optional< DIExpression::ExprOperand > peek() const
Return the current operation.
bool isImplicitLocation() const
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
static Optional< FragmentInfo > getFragmentInfo(expr_op_iterator Start, expr_op_iterator End)
Retrieve the details of this fragment expression.
void emitLegacyZExt(unsigned FromBits)
void maskSubRegister()
Add masking operations to stencil out a subregister.
uint64_t getArg(unsigned I) const
Get an argument to the operand.
Optional< DIExpression::ExprOperand > peekNext() const
Return the next operation.
virtual void emitUnsigned(uint64_t Value)=0
Emit a raw unsigned value.
Optional< DIExpression::ExprOperand > take()
Consume one operation.
uint64_t getOp() const
Get the operand code.
virtual void emitOp(uint8_t Op, const char *Comment=nullptr)=0
Output a dwarf operand and an optional assembler comment.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Only used in LLVM metadata.
Definition: Dwarf.h:123
A lightweight wrapper around an expression operand.
uint64_t OffsetInBits
Current Fragment Offset in Bits.
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:305
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1498
Only used in LLVM metadata.
Definition: Dwarf.h:124
virtual void emitSigned(int64_t Value)=0
Emit a raw signed value.
virtual unsigned getTemporaryBufferSize()=0
Return the emitted size, in number of bytes, for the data stored in the temporary buffer...
bool isMemoryLocation() const
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SmallBitVector & set()
void addExpression(DIExpressionCursor &&Expr, unsigned FragmentOffsetInBits=0)
Emit all remaining operations in the DIExpressionCursor.
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool addMachineReg(const TargetRegisterInfo &TRI, unsigned MachineReg, unsigned MaxSize=~1U)
Emit a partial DWARF register operation.
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
static Register createRegister(int RegNo, const char *Comment)
Create a full register, no extra DW_OP_piece operators necessary.
bool isUnknownLocation() const
void addStackValue()
Emit a DW_OP_stack_value, if supported.
virtual void disableTemporaryBuffer()=0
Disable emission to the temporary buffer.
void addWasmLocation(unsigned Index, uint64_t Offset)
Emit location information expressed via WebAssembly location + offset The Index is an identifier for ...
DWARF expression.
This file contains constants used for implementing Dwarf debug support.
Class for arbitrary precision integers.
Definition: APInt.h:69
void addAnd(unsigned Mask)
Emit a bitwise and dwarf operation.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Optional< DIExpression::FragmentInfo > getFragmentInfo() const
Retrieve the fragment information, if any.
Optional< uint8_t > TagOffset
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:693
unsigned SubRegisterSizeInBits
Sometimes we need to add a DW_OP_bit_piece to describe a subregister.
void consume(unsigned N)
Consume N operations.
virtual void emitBaseTypeRef(uint64_t Idx)=0
void finalize()
This needs to be called last to commit any pending changes.
#define I(x, y, z)
Definition: MD5.cpp:59
#define N
uint32_t Size
Definition: Profile.cpp:46
void emitLegacySExt(unsigned FromBits)
void addFragmentOffset(const DIExpression *Expr)
If applicable, emit an empty DW_OP_piece / DW_OP_bit_piece to advance to the fragment described by Ex...
void finalizeEntryValue()
Finalize an entry value by emitting its size operand, and committing the DWARF block which has been e...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:74
void addOpPiece(unsigned SizeInBits, unsigned OffsetInBits=0)
Emit a DW_OP_piece or DW_OP_bit_piece operation for a variable fragment.
unsigned getOrCreateBaseType(unsigned BitSize, dwarf::TypeKind Encoding)
Return the index of a base type with the given properties and create one if necessary.
void setLocation(const MachineLocation &Loc, const DIExpression *DIExpr)
Set the location (Loc) and DIExpression (DIExpr) to describe.
void addSignedConstant(int64_t Value)
Emit a signed constant.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
SmallVector< Register, 2 > DwarfRegs
The register location, if any.
static Register createSubRegister(int RegNo, unsigned SizeInBits, const char *Comment)
Create a subregister that needs a DW_OP_piece operator with SizeInBits.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
void setEntryValueFlags(const MachineLocation &Loc)
Lock this down to become an entry value location.
bool isFragment() const
Return whether this is a piece of an aggregate variable.
bool isRegisterLocation() const
bool addMachineRegExpression(const TargetRegisterInfo &TRI, DIExpressionCursor &Expr, unsigned MachineReg, unsigned FragmentOffsetInBits=0)
Emit a machine register location.
virtual bool isFrameRegister(const TargetRegisterInfo &TRI, unsigned MachineReg)=0
Return whether the given machine register is the frame register in the current function.