LLVM API Documentation

X86MCInstLower.cpp
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00001 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains code to lower X86 MachineInstrs to their corresponding
00011 // MCInst records.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "X86AsmPrinter.h"
00016 #include "X86RegisterInfo.h"
00017 #include "InstPrinter/X86ATTInstPrinter.h"
00018 #include "MCTargetDesc/X86BaseInfo.h"
00019 #include "Utils/X86ShuffleDecode.h"
00020 #include "llvm/ADT/SmallString.h"
00021 #include "llvm/CodeGen/MachineFunction.h"
00022 #include "llvm/CodeGen/MachineConstantPool.h"
00023 #include "llvm/CodeGen/MachineOperand.h"
00024 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00025 #include "llvm/CodeGen/StackMaps.h"
00026 #include "llvm/IR/DataLayout.h"
00027 #include "llvm/IR/GlobalValue.h"
00028 #include "llvm/IR/Mangler.h"
00029 #include "llvm/MC/MCAsmInfo.h"
00030 #include "llvm/MC/MCCodeEmitter.h"
00031 #include "llvm/MC/MCContext.h"
00032 #include "llvm/MC/MCExpr.h"
00033 #include "llvm/MC/MCInst.h"
00034 #include "llvm/MC/MCInstBuilder.h"
00035 #include "llvm/MC/MCStreamer.h"
00036 #include "llvm/MC/MCSymbol.h"
00037 #include "llvm/Support/TargetRegistry.h"
00038 using namespace llvm;
00039 
00040 namespace {
00041 
00042 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
00043 class X86MCInstLower {
00044   MCContext &Ctx;
00045   const MachineFunction &MF;
00046   const TargetMachine &TM;
00047   const MCAsmInfo &MAI;
00048   X86AsmPrinter &AsmPrinter;
00049 public:
00050   X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
00051 
00052   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
00053 
00054   MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
00055   MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
00056 
00057 private:
00058   MachineModuleInfoMachO &getMachOMMI() const;
00059   Mangler *getMang() const {
00060     return AsmPrinter.Mang;
00061   }
00062 };
00063 
00064 } // end anonymous namespace
00065 
00066 // Emit a minimal sequence of nops spanning NumBytes bytes.
00067 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
00068                      const MCSubtargetInfo &STI);
00069 
00070 namespace llvm {
00071    X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
00072      : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
00073 
00074   X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
00075 
00076   void
00077   X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &MF) {
00078     CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
00079         *TM.getSubtargetImpl()->getInstrInfo(),
00080         *TM.getSubtargetImpl()->getRegisterInfo(), *TM.getSubtargetImpl(),
00081         MF.getContext()));
00082   }
00083 
00084   void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
00085                                                    const MCSubtargetInfo &STI) {
00086     if (InShadow) {
00087       SmallString<256> Code;
00088       SmallVector<MCFixup, 4> Fixups;
00089       raw_svector_ostream VecOS(Code);
00090       CodeEmitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
00091       VecOS.flush();
00092       CurrentShadowSize += Code.size();
00093       if (CurrentShadowSize >= RequiredShadowSize)
00094         InShadow = false; // The shadow is big enough. Stop counting.
00095     }
00096   }
00097 
00098   void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
00099     MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
00100     if (InShadow && CurrentShadowSize < RequiredShadowSize) {
00101       InShadow = false;
00102       EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
00103                TM.getSubtarget<X86Subtarget>().is64Bit(), STI);
00104     }
00105   }
00106 
00107   void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
00108     OutStreamer.EmitInstruction(Inst, getSubtargetInfo());
00109     SMShadowTracker.count(Inst, getSubtargetInfo());
00110   }
00111 } // end llvm namespace
00112 
00113 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
00114                                X86AsmPrinter &asmprinter)
00115 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()),
00116   MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
00117 
00118 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
00119   return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
00120 }
00121 
00122 
00123 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
00124 /// operand to an MCSymbol.
00125 MCSymbol *X86MCInstLower::
00126 GetSymbolFromOperand(const MachineOperand &MO) const {
00127   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
00128   assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
00129 
00130   SmallString<128> Name;
00131   StringRef Suffix;
00132 
00133   switch (MO.getTargetFlags()) {
00134   case X86II::MO_DLLIMPORT:
00135     // Handle dllimport linkage.
00136     Name += "__imp_";
00137     break;
00138   case X86II::MO_DARWIN_STUB:
00139     Suffix = "$stub";
00140     break;
00141   case X86II::MO_DARWIN_NONLAZY:
00142   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
00143   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
00144     Suffix = "$non_lazy_ptr";
00145     break;
00146   }
00147 
00148   if (!Suffix.empty())
00149     Name += DL->getPrivateGlobalPrefix();
00150 
00151   unsigned PrefixLen = Name.size();
00152 
00153   if (MO.isGlobal()) {
00154     const GlobalValue *GV = MO.getGlobal();
00155     AsmPrinter.getNameWithPrefix(Name, GV);
00156   } else if (MO.isSymbol()) {
00157     getMang()->getNameWithPrefix(Name, MO.getSymbolName());
00158   } else if (MO.isMBB()) {
00159     Name += MO.getMBB()->getSymbol()->getName();
00160   }
00161   unsigned OrigLen = Name.size() - PrefixLen;
00162 
00163   Name += Suffix;
00164   MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
00165 
00166   StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
00167 
00168   // If the target flags on the operand changes the name of the symbol, do that
00169   // before we return the symbol.
00170   switch (MO.getTargetFlags()) {
00171   default: break;
00172   case X86II::MO_DARWIN_NONLAZY:
00173   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
00174     MachineModuleInfoImpl::StubValueTy &StubSym =
00175       getMachOMMI().getGVStubEntry(Sym);
00176     if (!StubSym.getPointer()) {
00177       assert(MO.isGlobal() && "Extern symbol not handled yet");
00178       StubSym =
00179         MachineModuleInfoImpl::
00180         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
00181                     !MO.getGlobal()->hasInternalLinkage());
00182     }
00183     break;
00184   }
00185   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
00186     MachineModuleInfoImpl::StubValueTy &StubSym =
00187       getMachOMMI().getHiddenGVStubEntry(Sym);
00188     if (!StubSym.getPointer()) {
00189       assert(MO.isGlobal() && "Extern symbol not handled yet");
00190       StubSym =
00191         MachineModuleInfoImpl::
00192         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
00193                     !MO.getGlobal()->hasInternalLinkage());
00194     }
00195     break;
00196   }
00197   case X86II::MO_DARWIN_STUB: {
00198     MachineModuleInfoImpl::StubValueTy &StubSym =
00199       getMachOMMI().getFnStubEntry(Sym);
00200     if (StubSym.getPointer())
00201       return Sym;
00202 
00203     if (MO.isGlobal()) {
00204       StubSym =
00205         MachineModuleInfoImpl::
00206         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
00207                     !MO.getGlobal()->hasInternalLinkage());
00208     } else {
00209       StubSym =
00210         MachineModuleInfoImpl::
00211         StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false);
00212     }
00213     break;
00214   }
00215   }
00216 
00217   return Sym;
00218 }
00219 
00220 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
00221                                              MCSymbol *Sym) const {
00222   // FIXME: We would like an efficient form for this, so we don't have to do a
00223   // lot of extra uniquing.
00224   const MCExpr *Expr = nullptr;
00225   MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
00226 
00227   switch (MO.getTargetFlags()) {
00228   default: llvm_unreachable("Unknown target flag on GV operand");
00229   case X86II::MO_NO_FLAG:    // No flag.
00230   // These affect the name of the symbol, not any suffix.
00231   case X86II::MO_DARWIN_NONLAZY:
00232   case X86II::MO_DLLIMPORT:
00233   case X86II::MO_DARWIN_STUB:
00234     break;
00235 
00236   case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
00237   case X86II::MO_TLVP_PIC_BASE:
00238     Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
00239     // Subtract the pic base.
00240     Expr = MCBinaryExpr::CreateSub(Expr,
00241                                   MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
00242                                                            Ctx),
00243                                    Ctx);
00244     break;
00245   case X86II::MO_SECREL:    RefKind = MCSymbolRefExpr::VK_SECREL; break;
00246   case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
00247   case X86II::MO_TLSLD:     RefKind = MCSymbolRefExpr::VK_TLSLD; break;
00248   case X86II::MO_TLSLDM:    RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
00249   case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
00250   case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
00251   case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
00252   case X86II::MO_DTPOFF:    RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
00253   case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
00254   case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
00255   case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
00256   case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
00257   case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
00258   case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
00259   case X86II::MO_PIC_BASE_OFFSET:
00260   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
00261   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
00262     Expr = MCSymbolRefExpr::Create(Sym, Ctx);
00263     // Subtract the pic base.
00264     Expr = MCBinaryExpr::CreateSub(Expr,
00265                             MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
00266                                    Ctx);
00267     if (MO.isJTI() && MAI.hasSetDirective()) {
00268       // If .set directive is supported, use it to reduce the number of
00269       // relocations the assembler will generate for differences between
00270       // local labels. This is only safe when the symbols are in the same
00271       // section so we are restricting it to jumptable references.
00272       MCSymbol *Label = Ctx.CreateTempSymbol();
00273       AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
00274       Expr = MCSymbolRefExpr::Create(Label, Ctx);
00275     }
00276     break;
00277   }
00278 
00279   if (!Expr)
00280     Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
00281 
00282   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
00283     Expr = MCBinaryExpr::CreateAdd(Expr,
00284                                    MCConstantExpr::Create(MO.getOffset(), Ctx),
00285                                    Ctx);
00286   return MCOperand::CreateExpr(Expr);
00287 }
00288 
00289 
00290 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
00291 /// a short fixed-register form.
00292 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
00293   unsigned ImmOp = Inst.getNumOperands() - 1;
00294   assert(Inst.getOperand(0).isReg() &&
00295          (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
00296          ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
00297            Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
00298           Inst.getNumOperands() == 2) && "Unexpected instruction!");
00299 
00300   // Check whether the destination register can be fixed.
00301   unsigned Reg = Inst.getOperand(0).getReg();
00302   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
00303     return;
00304 
00305   // If so, rewrite the instruction.
00306   MCOperand Saved = Inst.getOperand(ImmOp);
00307   Inst = MCInst();
00308   Inst.setOpcode(Opcode);
00309   Inst.addOperand(Saved);
00310 }
00311 
00312 /// \brief If a movsx instruction has a shorter encoding for the used register
00313 /// simplify the instruction to use it instead.
00314 static void SimplifyMOVSX(MCInst &Inst) {
00315   unsigned NewOpcode = 0;
00316   unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
00317   switch (Inst.getOpcode()) {
00318   default:
00319     llvm_unreachable("Unexpected instruction!");
00320   case X86::MOVSX16rr8:  // movsbw %al, %ax   --> cbtw
00321     if (Op0 == X86::AX && Op1 == X86::AL)
00322       NewOpcode = X86::CBW;
00323     break;
00324   case X86::MOVSX32rr16: // movswl %ax, %eax  --> cwtl
00325     if (Op0 == X86::EAX && Op1 == X86::AX)
00326       NewOpcode = X86::CWDE;
00327     break;
00328   case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
00329     if (Op0 == X86::RAX && Op1 == X86::EAX)
00330       NewOpcode = X86::CDQE;
00331     break;
00332   }
00333 
00334   if (NewOpcode != 0) {
00335     Inst = MCInst();
00336     Inst.setOpcode(NewOpcode);
00337   }
00338 }
00339 
00340 /// \brief Simplify things like MOV32rm to MOV32o32a.
00341 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
00342                                   unsigned Opcode) {
00343   // Don't make these simplifications in 64-bit mode; other assemblers don't
00344   // perform them because they make the code larger.
00345   if (Printer.getSubtarget().is64Bit())
00346     return;
00347 
00348   bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
00349   unsigned AddrBase = IsStore;
00350   unsigned RegOp = IsStore ? 0 : 5;
00351   unsigned AddrOp = AddrBase + 3;
00352   assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
00353          Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
00354          Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
00355          Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
00356          Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
00357          (Inst.getOperand(AddrOp).isExpr() ||
00358           Inst.getOperand(AddrOp).isImm()) &&
00359          "Unexpected instruction!");
00360 
00361   // Check whether the destination register can be fixed.
00362   unsigned Reg = Inst.getOperand(RegOp).getReg();
00363   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
00364     return;
00365 
00366   // Check whether this is an absolute address.
00367   // FIXME: We know TLVP symbol refs aren't, but there should be a better way
00368   // to do this here.
00369   bool Absolute = true;
00370   if (Inst.getOperand(AddrOp).isExpr()) {
00371     const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
00372     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
00373       if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
00374         Absolute = false;
00375   }
00376 
00377   if (Absolute &&
00378       (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
00379        Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
00380        Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
00381     return;
00382 
00383   // If so, rewrite the instruction.
00384   MCOperand Saved = Inst.getOperand(AddrOp);
00385   MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
00386   Inst = MCInst();
00387   Inst.setOpcode(Opcode);
00388   Inst.addOperand(Saved);
00389   Inst.addOperand(Seg);
00390 }
00391 
00392 static unsigned getRetOpcode(const X86Subtarget &Subtarget)
00393 {
00394   return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
00395 }
00396 
00397 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
00398   OutMI.setOpcode(MI->getOpcode());
00399 
00400   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
00401     const MachineOperand &MO = MI->getOperand(i);
00402 
00403     MCOperand MCOp;
00404     switch (MO.getType()) {
00405     default:
00406       MI->dump();
00407       llvm_unreachable("unknown operand type");
00408     case MachineOperand::MO_Register:
00409       // Ignore all implicit register operands.
00410       if (MO.isImplicit()) continue;
00411       MCOp = MCOperand::CreateReg(MO.getReg());
00412       break;
00413     case MachineOperand::MO_Immediate:
00414       MCOp = MCOperand::CreateImm(MO.getImm());
00415       break;
00416     case MachineOperand::MO_MachineBasicBlock:
00417     case MachineOperand::MO_GlobalAddress:
00418     case MachineOperand::MO_ExternalSymbol:
00419       MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
00420       break;
00421     case MachineOperand::MO_JumpTableIndex:
00422       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
00423       break;
00424     case MachineOperand::MO_ConstantPoolIndex:
00425       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
00426       break;
00427     case MachineOperand::MO_BlockAddress:
00428       MCOp = LowerSymbolOperand(MO,
00429                      AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
00430       break;
00431     case MachineOperand::MO_RegisterMask:
00432       // Ignore call clobbers.
00433       continue;
00434     }
00435 
00436     OutMI.addOperand(MCOp);
00437   }
00438 
00439   // Handle a few special cases to eliminate operand modifiers.
00440 ReSimplify:
00441   switch (OutMI.getOpcode()) {
00442   case X86::LEA64_32r:
00443   case X86::LEA64r:
00444   case X86::LEA16r:
00445   case X86::LEA32r:
00446     // LEA should have a segment register, but it must be empty.
00447     assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
00448            "Unexpected # of LEA operands");
00449     assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
00450            "LEA has segment specified!");
00451     break;
00452 
00453   case X86::MOV32ri64:
00454     OutMI.setOpcode(X86::MOV32ri);
00455     break;
00456 
00457   // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
00458   // if one of the registers is extended, but other isn't.
00459   case X86::VMOVAPDrr:
00460   case X86::VMOVAPDYrr:
00461   case X86::VMOVAPSrr:
00462   case X86::VMOVAPSYrr:
00463   case X86::VMOVDQArr:
00464   case X86::VMOVDQAYrr:
00465   case X86::VMOVDQUrr:
00466   case X86::VMOVDQUYrr:
00467   case X86::VMOVUPDrr:
00468   case X86::VMOVUPDYrr:
00469   case X86::VMOVUPSrr:
00470   case X86::VMOVUPSYrr: {
00471     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
00472         X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
00473       unsigned NewOpc;
00474       switch (OutMI.getOpcode()) {
00475       default: llvm_unreachable("Invalid opcode");
00476       case X86::VMOVAPDrr:  NewOpc = X86::VMOVAPDrr_REV;  break;
00477       case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
00478       case X86::VMOVAPSrr:  NewOpc = X86::VMOVAPSrr_REV;  break;
00479       case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
00480       case X86::VMOVDQArr:  NewOpc = X86::VMOVDQArr_REV;  break;
00481       case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
00482       case X86::VMOVDQUrr:  NewOpc = X86::VMOVDQUrr_REV;  break;
00483       case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
00484       case X86::VMOVUPDrr:  NewOpc = X86::VMOVUPDrr_REV;  break;
00485       case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
00486       case X86::VMOVUPSrr:  NewOpc = X86::VMOVUPSrr_REV;  break;
00487       case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
00488       }
00489       OutMI.setOpcode(NewOpc);
00490     }
00491     break;
00492   }
00493   case X86::VMOVSDrr:
00494   case X86::VMOVSSrr: {
00495     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
00496         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
00497       unsigned NewOpc;
00498       switch (OutMI.getOpcode()) {
00499       default: llvm_unreachable("Invalid opcode");
00500       case X86::VMOVSDrr:   NewOpc = X86::VMOVSDrr_REV;   break;
00501       case X86::VMOVSSrr:   NewOpc = X86::VMOVSSrr_REV;   break;
00502       }
00503       OutMI.setOpcode(NewOpc);
00504     }
00505     break;
00506   }
00507 
00508   // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
00509   // inputs modeled as normal uses instead of implicit uses.  As such, truncate
00510   // off all but the first operand (the callee).  FIXME: Change isel.
00511   case X86::TAILJMPr64:
00512   case X86::CALL64r:
00513   case X86::CALL64pcrel32: {
00514     unsigned Opcode = OutMI.getOpcode();
00515     MCOperand Saved = OutMI.getOperand(0);
00516     OutMI = MCInst();
00517     OutMI.setOpcode(Opcode);
00518     OutMI.addOperand(Saved);
00519     break;
00520   }
00521 
00522   case X86::EH_RETURN:
00523   case X86::EH_RETURN64: {
00524     OutMI = MCInst();
00525     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
00526     break;
00527   }
00528 
00529   // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
00530   case X86::TAILJMPr:
00531   case X86::TAILJMPd:
00532   case X86::TAILJMPd64: {
00533     unsigned Opcode;
00534     switch (OutMI.getOpcode()) {
00535     default: llvm_unreachable("Invalid opcode");
00536     case X86::TAILJMPr: Opcode = X86::JMP32r; break;
00537     case X86::TAILJMPd:
00538     case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
00539     }
00540 
00541     MCOperand Saved = OutMI.getOperand(0);
00542     OutMI = MCInst();
00543     OutMI.setOpcode(Opcode);
00544     OutMI.addOperand(Saved);
00545     break;
00546   }
00547 
00548   // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
00549   // this with an ugly goto in case the resultant OR uses EAX and needs the
00550   // short form.
00551   case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
00552   case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
00553   case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
00554   case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
00555   case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
00556   case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
00557   case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
00558   case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
00559   case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
00560 
00561   // The assembler backend wants to see branches in their small form and relax
00562   // them to their large form.  The JIT can only handle the large form because
00563   // it does not do relaxation.  For now, translate the large form to the
00564   // small one here.
00565   case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
00566   case X86::JO_4:  OutMI.setOpcode(X86::JO_1); break;
00567   case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
00568   case X86::JB_4:  OutMI.setOpcode(X86::JB_1); break;
00569   case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
00570   case X86::JE_4:  OutMI.setOpcode(X86::JE_1); break;
00571   case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
00572   case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
00573   case X86::JA_4:  OutMI.setOpcode(X86::JA_1); break;
00574   case X86::JS_4:  OutMI.setOpcode(X86::JS_1); break;
00575   case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
00576   case X86::JP_4:  OutMI.setOpcode(X86::JP_1); break;
00577   case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
00578   case X86::JL_4:  OutMI.setOpcode(X86::JL_1); break;
00579   case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
00580   case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
00581   case X86::JG_4:  OutMI.setOpcode(X86::JG_1); break;
00582 
00583   // Atomic load and store require a separate pseudo-inst because Acquire
00584   // implies mayStore and Release implies mayLoad; fix these to regular MOV
00585   // instructions here
00586   case X86::ACQUIRE_MOV8rm:  OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
00587   case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
00588   case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
00589   case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
00590   case X86::RELEASE_MOV8mr:  OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
00591   case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
00592   case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
00593   case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
00594 
00595   // We don't currently select the correct instruction form for instructions
00596   // which have a short %eax, etc. form. Handle this by custom lowering, for
00597   // now.
00598   //
00599   // Note, we are currently not handling the following instructions:
00600   // MOV64ao8, MOV64o8a
00601   // XCHG16ar, XCHG32ar, XCHG64ar
00602   case X86::MOV8mr_NOREX:
00603   case X86::MOV8mr:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
00604   case X86::MOV8rm_NOREX:
00605   case X86::MOV8rm:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
00606   case X86::MOV16mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
00607   case X86::MOV16rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
00608   case X86::MOV32mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
00609   case X86::MOV32rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
00610 
00611   case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
00612   case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
00613   case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
00614   case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
00615   case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
00616   case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
00617   case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
00618   case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
00619   case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
00620   case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
00621   case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
00622   case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
00623   case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
00624   case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
00625   case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
00626   case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
00627   case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
00628   case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
00629   case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
00630   case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
00631   case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
00632   case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
00633   case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
00634   case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
00635   case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
00636   case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
00637   case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
00638   case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
00639   case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
00640   case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
00641   case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
00642   case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
00643   case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
00644   case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
00645   case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
00646   case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
00647 
00648   // Try to shrink some forms of movsx.
00649   case X86::MOVSX16rr8:
00650   case X86::MOVSX32rr16:
00651   case X86::MOVSX64rr32:
00652     SimplifyMOVSX(OutMI);
00653     break;
00654   }
00655 }
00656 
00657 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
00658                                  const MachineInstr &MI) {
00659 
00660   bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
00661                   MI.getOpcode() == X86::TLS_base_addr64;
00662 
00663   bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
00664 
00665   MCContext &context = OutStreamer.getContext();
00666 
00667   if (needsPadding)
00668     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
00669 
00670   MCSymbolRefExpr::VariantKind SRVK;
00671   switch (MI.getOpcode()) {
00672     case X86::TLS_addr32:
00673     case X86::TLS_addr64:
00674       SRVK = MCSymbolRefExpr::VK_TLSGD;
00675       break;
00676     case X86::TLS_base_addr32:
00677       SRVK = MCSymbolRefExpr::VK_TLSLDM;
00678       break;
00679     case X86::TLS_base_addr64:
00680       SRVK = MCSymbolRefExpr::VK_TLSLD;
00681       break;
00682     default:
00683       llvm_unreachable("unexpected opcode");
00684   }
00685 
00686   MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
00687   const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
00688 
00689   MCInst LEA;
00690   if (is64Bits) {
00691     LEA.setOpcode(X86::LEA64r);
00692     LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
00693     LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
00694     LEA.addOperand(MCOperand::CreateImm(1));        // scale
00695     LEA.addOperand(MCOperand::CreateReg(0));        // index
00696     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
00697     LEA.addOperand(MCOperand::CreateReg(0));        // seg
00698   } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
00699     LEA.setOpcode(X86::LEA32r);
00700     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
00701     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
00702     LEA.addOperand(MCOperand::CreateImm(1));        // scale
00703     LEA.addOperand(MCOperand::CreateReg(0));        // index
00704     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
00705     LEA.addOperand(MCOperand::CreateReg(0));        // seg
00706   } else {
00707     LEA.setOpcode(X86::LEA32r);
00708     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
00709     LEA.addOperand(MCOperand::CreateReg(0));        // base
00710     LEA.addOperand(MCOperand::CreateImm(1));        // scale
00711     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
00712     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
00713     LEA.addOperand(MCOperand::CreateReg(0));        // seg
00714   }
00715   EmitAndCountInstruction(LEA);
00716 
00717   if (needsPadding) {
00718     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
00719     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
00720     EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
00721   }
00722 
00723   StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
00724   MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
00725   const MCSymbolRefExpr *tlsRef =
00726     MCSymbolRefExpr::Create(tlsGetAddr,
00727                             MCSymbolRefExpr::VK_PLT,
00728                             context);
00729 
00730   EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
00731                                                  : X86::CALLpcrel32)
00732                             .addExpr(tlsRef));
00733 }
00734 
00735 /// \brief Emit the optimal amount of multi-byte nops on X86.
00736 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
00737   // This works only for 64bit. For 32bit we have to do additional checking if
00738   // the CPU supports multi-byte nops.
00739   assert(Is64Bit && "EmitNops only supports X86-64");
00740   while (NumBytes) {
00741     unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
00742     Opc = IndexReg = Displacement = SegmentReg = 0;
00743     BaseReg = X86::RAX; ScaleVal = 1;
00744     switch (NumBytes) {
00745     case  0: llvm_unreachable("Zero nops?"); break;
00746     case  1: NumBytes -=  1; Opc = X86::NOOP; break;
00747     case  2: NumBytes -=  2; Opc = X86::XCHG16ar; break;
00748     case  3: NumBytes -=  3; Opc = X86::NOOPL; break;
00749     case  4: NumBytes -=  4; Opc = X86::NOOPL; Displacement = 8; break;
00750     case  5: NumBytes -=  5; Opc = X86::NOOPL; Displacement = 8;
00751              IndexReg = X86::RAX; break;
00752     case  6: NumBytes -=  6; Opc = X86::NOOPW; Displacement = 8;
00753              IndexReg = X86::RAX; break;
00754     case  7: NumBytes -=  7; Opc = X86::NOOPL; Displacement = 512; break;
00755     case  8: NumBytes -=  8; Opc = X86::NOOPL; Displacement = 512;
00756              IndexReg = X86::RAX; break;
00757     case  9: NumBytes -=  9; Opc = X86::NOOPW; Displacement = 512;
00758              IndexReg = X86::RAX; break;
00759     default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
00760              IndexReg = X86::RAX; SegmentReg = X86::CS; break;
00761     }
00762 
00763     unsigned NumPrefixes = std::min(NumBytes, 5U);
00764     NumBytes -= NumPrefixes;
00765     for (unsigned i = 0; i != NumPrefixes; ++i)
00766       OS.EmitBytes("\x66");
00767 
00768     switch (Opc) {
00769     default: llvm_unreachable("Unexpected opcode"); break;
00770     case X86::NOOP:
00771       OS.EmitInstruction(MCInstBuilder(Opc), STI);
00772       break;
00773     case X86::XCHG16ar:
00774       OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
00775       break;
00776     case X86::NOOPL:
00777     case X86::NOOPW:
00778       OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
00779                          .addImm(ScaleVal).addReg(IndexReg)
00780                          .addImm(Displacement).addReg(SegmentReg), STI);
00781       break;
00782     }
00783   } // while (NumBytes)
00784 }
00785 
00786 // Lower a stackmap of the form:
00787 // <id>, <shadowBytes>, ...
00788 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
00789   SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
00790   SM.recordStackMap(MI);
00791   unsigned NumShadowBytes = MI.getOperand(1).getImm();
00792   SMShadowTracker.reset(NumShadowBytes);
00793 }
00794 
00795 // Lower a patchpoint of the form:
00796 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
00797 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI) {
00798   assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
00799 
00800   SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
00801 
00802   SM.recordPatchPoint(MI);
00803 
00804   PatchPointOpers opers(&MI);
00805   unsigned ScratchIdx = opers.getNextScratchIdx();
00806   unsigned EncodedBytes = 0;
00807   int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
00808   if (CallTarget) {
00809     // Emit MOV to materialize the target address and the CALL to target.
00810     // This is encoded with 12-13 bytes, depending on which register is used.
00811     unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
00812     if (X86II::isX86_64ExtendedReg(ScratchReg))
00813       EncodedBytes = 13;
00814     else
00815       EncodedBytes = 12;
00816     EmitAndCountInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)
00817                                                        .addImm(CallTarget));
00818     EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
00819   }
00820   // Emit padding.
00821   unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
00822   assert(NumBytes >= EncodedBytes &&
00823          "Patchpoint can't request size less than the length of a call.");
00824 
00825   EmitNops(OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
00826            getSubtargetInfo());
00827 }
00828 
00829 // Returns instruction preceding MBBI in MachineFunction.
00830 // If MBBI is the first instruction of the first basic block, returns null.
00831 static MachineBasicBlock::const_iterator
00832 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
00833   const MachineBasicBlock *MBB = MBBI->getParent();
00834   while (MBBI == MBB->begin()) {
00835     if (MBB == MBB->getParent()->begin())
00836       return nullptr;
00837     MBB = MBB->getPrevNode();
00838     MBBI = MBB->end();
00839   }
00840   return --MBBI;
00841 }
00842 
00843 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
00844   X86MCInstLower MCInstLowering(*MF, *this);
00845   const X86RegisterInfo *RI = static_cast<const X86RegisterInfo *>(
00846       TM.getSubtargetImpl()->getRegisterInfo());
00847 
00848   switch (MI->getOpcode()) {
00849   case TargetOpcode::DBG_VALUE:
00850     llvm_unreachable("Should be handled target independently");
00851 
00852   // Emit nothing here but a comment if we can.
00853   case X86::Int_MemBarrier:
00854     OutStreamer.emitRawComment("MEMBARRIER");
00855     return;
00856 
00857 
00858   case X86::EH_RETURN:
00859   case X86::EH_RETURN64: {
00860     // Lower these as normal, but add some comments.
00861     unsigned Reg = MI->getOperand(0).getReg();
00862     OutStreamer.AddComment(StringRef("eh_return, addr: %") +
00863                            X86ATTInstPrinter::getRegisterName(Reg));
00864     break;
00865   }
00866   case X86::TAILJMPr:
00867   case X86::TAILJMPd:
00868   case X86::TAILJMPd64:
00869     // Lower these as normal, but add some comments.
00870     OutStreamer.AddComment("TAILCALL");
00871     break;
00872 
00873   case X86::TLS_addr32:
00874   case X86::TLS_addr64:
00875   case X86::TLS_base_addr32:
00876   case X86::TLS_base_addr64:
00877     return LowerTlsAddr(MCInstLowering, *MI);
00878 
00879   case X86::MOVPC32r: {
00880     // This is a pseudo op for a two instruction sequence with a label, which
00881     // looks like:
00882     //     call "L1$pb"
00883     // "L1$pb":
00884     //     popl %esi
00885 
00886     // Emit the call.
00887     MCSymbol *PICBase = MF->getPICBaseSymbol();
00888     // FIXME: We would like an efficient form for this, so we don't have to do a
00889     // lot of extra uniquing.
00890     EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
00891       .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
00892 
00893     // Emit the label.
00894     OutStreamer.EmitLabel(PICBase);
00895 
00896     // popl $reg
00897     EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
00898                             .addReg(MI->getOperand(0).getReg()));
00899     return;
00900   }
00901 
00902   case X86::ADD32ri: {
00903     // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
00904     if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
00905       break;
00906 
00907     // Okay, we have something like:
00908     //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
00909 
00910     // For this, we want to print something like:
00911     //   MYGLOBAL + (. - PICBASE)
00912     // However, we can't generate a ".", so just emit a new label here and refer
00913     // to it.
00914     MCSymbol *DotSym = OutContext.CreateTempSymbol();
00915     OutStreamer.EmitLabel(DotSym);
00916 
00917     // Now that we have emitted the label, lower the complex operand expression.
00918     MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
00919 
00920     const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
00921     const MCExpr *PICBase =
00922       MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
00923     DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
00924 
00925     DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
00926                                       DotExpr, OutContext);
00927 
00928     EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
00929       .addReg(MI->getOperand(0).getReg())
00930       .addReg(MI->getOperand(1).getReg())
00931       .addExpr(DotExpr));
00932     return;
00933   }
00934 
00935   case TargetOpcode::STACKMAP:
00936     return LowerSTACKMAP(*MI);
00937 
00938   case TargetOpcode::PATCHPOINT:
00939     return LowerPATCHPOINT(*MI);
00940 
00941   case X86::MORESTACK_RET:
00942     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
00943     return;
00944 
00945   case X86::MORESTACK_RET_RESTORE_R10:
00946     // Return, then restore R10.
00947     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
00948     EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
00949                             .addReg(X86::R10)
00950                             .addReg(X86::RAX));
00951     return;
00952 
00953   case X86::SEH_PushReg:
00954     OutStreamer.EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
00955     return;
00956 
00957   case X86::SEH_SaveReg:
00958     OutStreamer.EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
00959                                   MI->getOperand(1).getImm());
00960     return;
00961 
00962   case X86::SEH_SaveXMM:
00963     OutStreamer.EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
00964                                   MI->getOperand(1).getImm());
00965     return;
00966 
00967   case X86::SEH_StackAlloc:
00968     OutStreamer.EmitWinCFIAllocStack(MI->getOperand(0).getImm());
00969     return;
00970 
00971   case X86::SEH_SetFrame:
00972     OutStreamer.EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
00973                                    MI->getOperand(1).getImm());
00974     return;
00975 
00976   case X86::SEH_PushFrame:
00977     OutStreamer.EmitWinCFIPushFrame(MI->getOperand(0).getImm());
00978     return;
00979 
00980   case X86::SEH_EndPrologue:
00981     OutStreamer.EmitWinCFIEndProlog();
00982     return;
00983 
00984   case X86::SEH_Epilogue: {
00985     MachineBasicBlock::const_iterator MBBI(MI);
00986     // Check if preceded by a call and emit nop if so.
00987     for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
00988       // Conservatively assume that pseudo instructions don't emit code and keep
00989       // looking for a call. We may emit an unnecessary nop in some cases.
00990       if (!MBBI->isPseudo()) {
00991         if (MBBI->isCall())
00992           EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
00993         break;
00994       }
00995     }
00996     return;
00997   }
00998 
00999   case X86::PSHUFBrm:
01000   case X86::VPSHUFBrm:
01001     // Lower PSHUFB normally but add a comment if we can find a constant
01002     // shuffle mask. We won't be able to do this at the MC layer because the
01003     // mask isn't an immediate.
01004     std::string Comment;
01005     raw_string_ostream CS(Comment);
01006     SmallVector<int, 16> Mask;
01007 
01008     assert(MI->getNumOperands() >= 6 &&
01009            "Wrong number of operands for PSHUFBrm or VPSHUFBrm");
01010     const MachineOperand &DstOp = MI->getOperand(0);
01011     const MachineOperand &SrcOp = MI->getOperand(1);
01012     const MachineOperand &MaskOp = MI->getOperand(5);
01013 
01014     // Compute the name for a register. This is really goofy because we have
01015     // multiple instruction printers that could (in theory) use different
01016     // names. Fortunately most people use the ATT style (outside of Windows)
01017     // and they actually agree on register naming here. Ultimately, this is
01018     // a comment, and so its OK if it isn't perfect.
01019     auto GetRegisterName = [](unsigned RegNum) -> StringRef {
01020       return X86ATTInstPrinter::getRegisterName(RegNum);
01021     };
01022 
01023     StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
01024     StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
01025     CS << DstName << " = ";
01026 
01027     if (MaskOp.isCPI()) {
01028       ArrayRef<MachineConstantPoolEntry> Constants =
01029           MI->getParent()->getParent()->getConstantPool()->getConstants();
01030       const MachineConstantPoolEntry &MaskConstantEntry =
01031           Constants[MaskOp.getIndex()];
01032       Type *MaskTy = MaskConstantEntry.getType();
01033       (void)MaskTy;
01034       if (!MaskConstantEntry.isMachineConstantPoolEntry())
01035         if (auto *C = dyn_cast<ConstantDataSequential>(
01036                 MaskConstantEntry.Val.ConstVal)) {
01037           assert(MaskTy == C->getType() &&
01038                  "Expected a constant of the same type!");
01039 
01040           DecodePSHUFBMask(C, Mask);
01041           assert(Mask.size() == MaskTy->getVectorNumElements() &&
01042                  "Shuffle mask has a different size than its type!");
01043         }
01044     }
01045 
01046     if (!Mask.empty()) {
01047       bool NeedComma = false;
01048       bool InSrc = false;
01049       for (int M : Mask) {
01050         // Wrap up any prior entry...
01051         if (M == SM_SentinelZero && InSrc) {
01052           InSrc = false;
01053           CS << "]";
01054         }
01055         if (NeedComma)
01056           CS << ",";
01057         else
01058           NeedComma = true;
01059 
01060         // Print this shuffle...
01061         if (M == SM_SentinelZero) {
01062           CS << "zero";
01063         } else {
01064           if (!InSrc) {
01065             InSrc = true;
01066             CS << SrcName << "[";
01067           }
01068           CS << M;
01069         }
01070       }
01071       if (InSrc)
01072         CS << "]";
01073 
01074       OutStreamer.AddComment(CS.str());
01075     }
01076     break;
01077   }
01078 
01079   MCInst TmpInst;
01080   MCInstLowering.Lower(MI, TmpInst);
01081   EmitAndCountInstruction(TmpInst);
01082 }