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X86MCInstLower.cpp
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00001 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains code to lower X86 MachineInstrs to their corresponding
00011 // MCInst records.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "X86AsmPrinter.h"
00016 #include "InstPrinter/X86ATTInstPrinter.h"
00017 #include "MCTargetDesc/X86BaseInfo.h"
00018 #include "llvm/ADT/SmallString.h"
00019 #include "llvm/CodeGen/MachineFunction.h"
00020 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00021 #include "llvm/CodeGen/StackMaps.h"
00022 #include "llvm/IR/DataLayout.h"
00023 #include "llvm/IR/GlobalValue.h"
00024 #include "llvm/IR/Mangler.h"
00025 #include "llvm/MC/MCAsmInfo.h"
00026 #include "llvm/MC/MCContext.h"
00027 #include "llvm/MC/MCExpr.h"
00028 #include "llvm/MC/MCInst.h"
00029 #include "llvm/MC/MCInstBuilder.h"
00030 #include "llvm/MC/MCStreamer.h"
00031 #include "llvm/MC/MCSymbol.h"
00032 using namespace llvm;
00033 
00034 namespace {
00035 
00036 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
00037 class X86MCInstLower {
00038   MCContext &Ctx;
00039   const MachineFunction &MF;
00040   const TargetMachine &TM;
00041   const MCAsmInfo &MAI;
00042   X86AsmPrinter &AsmPrinter;
00043 public:
00044   X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
00045 
00046   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
00047 
00048   MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
00049   MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
00050 
00051 private:
00052   MachineModuleInfoMachO &getMachOMMI() const;
00053   Mangler *getMang() const {
00054     return AsmPrinter.Mang;
00055   }
00056 };
00057 
00058 } // end anonymous namespace
00059 
00060 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
00061                                X86AsmPrinter &asmprinter)
00062 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()),
00063   MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
00064 
00065 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
00066   return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
00067 }
00068 
00069 
00070 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
00071 /// operand to an MCSymbol.
00072 MCSymbol *X86MCInstLower::
00073 GetSymbolFromOperand(const MachineOperand &MO) const {
00074   const DataLayout *DL = TM.getDataLayout();
00075   assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
00076 
00077   SmallString<128> Name;
00078   StringRef Suffix;
00079 
00080   switch (MO.getTargetFlags()) {
00081   case X86II::MO_DLLIMPORT:
00082     // Handle dllimport linkage.
00083     Name += "__imp_";
00084     break;
00085   case X86II::MO_DARWIN_STUB:
00086     Suffix = "$stub";
00087     break;
00088   case X86II::MO_DARWIN_NONLAZY:
00089   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
00090   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
00091     Suffix = "$non_lazy_ptr";
00092     break;
00093   }
00094 
00095   if (!Suffix.empty())
00096     Name += DL->getPrivateGlobalPrefix();
00097 
00098   unsigned PrefixLen = Name.size();
00099 
00100   if (MO.isGlobal()) {
00101     const GlobalValue *GV = MO.getGlobal();
00102     AsmPrinter.getNameWithPrefix(Name, GV);
00103   } else if (MO.isSymbol()) {
00104     getMang()->getNameWithPrefix(Name, MO.getSymbolName());
00105   } else if (MO.isMBB()) {
00106     Name += MO.getMBB()->getSymbol()->getName();
00107   }
00108   unsigned OrigLen = Name.size() - PrefixLen;
00109 
00110   Name += Suffix;
00111   MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
00112 
00113   StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
00114 
00115   // If the target flags on the operand changes the name of the symbol, do that
00116   // before we return the symbol.
00117   switch (MO.getTargetFlags()) {
00118   default: break;
00119   case X86II::MO_DARWIN_NONLAZY:
00120   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
00121     MachineModuleInfoImpl::StubValueTy &StubSym =
00122       getMachOMMI().getGVStubEntry(Sym);
00123     if (StubSym.getPointer() == 0) {
00124       assert(MO.isGlobal() && "Extern symbol not handled yet");
00125       StubSym =
00126         MachineModuleInfoImpl::
00127         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
00128                     !MO.getGlobal()->hasInternalLinkage());
00129     }
00130     break;
00131   }
00132   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
00133     MachineModuleInfoImpl::StubValueTy &StubSym =
00134       getMachOMMI().getHiddenGVStubEntry(Sym);
00135     if (StubSym.getPointer() == 0) {
00136       assert(MO.isGlobal() && "Extern symbol not handled yet");
00137       StubSym =
00138         MachineModuleInfoImpl::
00139         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
00140                     !MO.getGlobal()->hasInternalLinkage());
00141     }
00142     break;
00143   }
00144   case X86II::MO_DARWIN_STUB: {
00145     MachineModuleInfoImpl::StubValueTy &StubSym =
00146       getMachOMMI().getFnStubEntry(Sym);
00147     if (StubSym.getPointer())
00148       return Sym;
00149 
00150     if (MO.isGlobal()) {
00151       StubSym =
00152         MachineModuleInfoImpl::
00153         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
00154                     !MO.getGlobal()->hasInternalLinkage());
00155     } else {
00156       StubSym =
00157         MachineModuleInfoImpl::
00158         StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false);
00159     }
00160     break;
00161   }
00162   }
00163 
00164   return Sym;
00165 }
00166 
00167 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
00168                                              MCSymbol *Sym) const {
00169   // FIXME: We would like an efficient form for this, so we don't have to do a
00170   // lot of extra uniquing.
00171   const MCExpr *Expr = 0;
00172   MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
00173 
00174   switch (MO.getTargetFlags()) {
00175   default: llvm_unreachable("Unknown target flag on GV operand");
00176   case X86II::MO_NO_FLAG:    // No flag.
00177   // These affect the name of the symbol, not any suffix.
00178   case X86II::MO_DARWIN_NONLAZY:
00179   case X86II::MO_DLLIMPORT:
00180   case X86II::MO_DARWIN_STUB:
00181     break;
00182 
00183   case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
00184   case X86II::MO_TLVP_PIC_BASE:
00185     Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
00186     // Subtract the pic base.
00187     Expr = MCBinaryExpr::CreateSub(Expr,
00188                                   MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
00189                                                            Ctx),
00190                                    Ctx);
00191     break;
00192   case X86II::MO_SECREL:    RefKind = MCSymbolRefExpr::VK_SECREL; break;
00193   case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
00194   case X86II::MO_TLSLD:     RefKind = MCSymbolRefExpr::VK_TLSLD; break;
00195   case X86II::MO_TLSLDM:    RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
00196   case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
00197   case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
00198   case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
00199   case X86II::MO_DTPOFF:    RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
00200   case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
00201   case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
00202   case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
00203   case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
00204   case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
00205   case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
00206   case X86II::MO_PIC_BASE_OFFSET:
00207   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
00208   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
00209     Expr = MCSymbolRefExpr::Create(Sym, Ctx);
00210     // Subtract the pic base.
00211     Expr = MCBinaryExpr::CreateSub(Expr,
00212                             MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
00213                                    Ctx);
00214     if (MO.isJTI() && MAI.hasSetDirective()) {
00215       // If .set directive is supported, use it to reduce the number of
00216       // relocations the assembler will generate for differences between
00217       // local labels. This is only safe when the symbols are in the same
00218       // section so we are restricting it to jumptable references.
00219       MCSymbol *Label = Ctx.CreateTempSymbol();
00220       AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
00221       Expr = MCSymbolRefExpr::Create(Label, Ctx);
00222     }
00223     break;
00224   }
00225 
00226   if (Expr == 0)
00227     Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
00228 
00229   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
00230     Expr = MCBinaryExpr::CreateAdd(Expr,
00231                                    MCConstantExpr::Create(MO.getOffset(), Ctx),
00232                                    Ctx);
00233   return MCOperand::CreateExpr(Expr);
00234 }
00235 
00236 
00237 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
00238 /// a short fixed-register form.
00239 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
00240   unsigned ImmOp = Inst.getNumOperands() - 1;
00241   assert(Inst.getOperand(0).isReg() &&
00242          (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
00243          ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
00244            Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
00245           Inst.getNumOperands() == 2) && "Unexpected instruction!");
00246 
00247   // Check whether the destination register can be fixed.
00248   unsigned Reg = Inst.getOperand(0).getReg();
00249   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
00250     return;
00251 
00252   // If so, rewrite the instruction.
00253   MCOperand Saved = Inst.getOperand(ImmOp);
00254   Inst = MCInst();
00255   Inst.setOpcode(Opcode);
00256   Inst.addOperand(Saved);
00257 }
00258 
00259 /// \brief If a movsx instruction has a shorter encoding for the used register
00260 /// simplify the instruction to use it instead.
00261 static void SimplifyMOVSX(MCInst &Inst) {
00262   unsigned NewOpcode = 0;
00263   unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
00264   switch (Inst.getOpcode()) {
00265   default:
00266     llvm_unreachable("Unexpected instruction!");
00267   case X86::MOVSX16rr8:  // movsbw %al, %ax   --> cbtw
00268     if (Op0 == X86::AX && Op1 == X86::AL)
00269       NewOpcode = X86::CBW;
00270     break;
00271   case X86::MOVSX32rr16: // movswl %ax, %eax  --> cwtl
00272     if (Op0 == X86::EAX && Op1 == X86::AX)
00273       NewOpcode = X86::CWDE;
00274     break;
00275   case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
00276     if (Op0 == X86::RAX && Op1 == X86::EAX)
00277       NewOpcode = X86::CDQE;
00278     break;
00279   }
00280 
00281   if (NewOpcode != 0) {
00282     Inst = MCInst();
00283     Inst.setOpcode(NewOpcode);
00284   }
00285 }
00286 
00287 /// \brief Simplify things like MOV32rm to MOV32o32a.
00288 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
00289                                   unsigned Opcode) {
00290   // Don't make these simplifications in 64-bit mode; other assemblers don't
00291   // perform them because they make the code larger.
00292   if (Printer.getSubtarget().is64Bit())
00293     return;
00294 
00295   bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
00296   unsigned AddrBase = IsStore;
00297   unsigned RegOp = IsStore ? 0 : 5;
00298   unsigned AddrOp = AddrBase + 3;
00299   assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
00300          Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
00301          Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
00302          Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
00303          Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
00304          (Inst.getOperand(AddrOp).isExpr() ||
00305           Inst.getOperand(AddrOp).isImm()) &&
00306          "Unexpected instruction!");
00307 
00308   // Check whether the destination register can be fixed.
00309   unsigned Reg = Inst.getOperand(RegOp).getReg();
00310   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
00311     return;
00312 
00313   // Check whether this is an absolute address.
00314   // FIXME: We know TLVP symbol refs aren't, but there should be a better way
00315   // to do this here.
00316   bool Absolute = true;
00317   if (Inst.getOperand(AddrOp).isExpr()) {
00318     const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
00319     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
00320       if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
00321         Absolute = false;
00322   }
00323 
00324   if (Absolute &&
00325       (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
00326        Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
00327        Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
00328     return;
00329 
00330   // If so, rewrite the instruction.
00331   MCOperand Saved = Inst.getOperand(AddrOp);
00332   MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
00333   Inst = MCInst();
00334   Inst.setOpcode(Opcode);
00335   Inst.addOperand(Saved);
00336   Inst.addOperand(Seg);
00337 }
00338 
00339 static unsigned getRetOpcode(const X86Subtarget &Subtarget)
00340 {
00341   return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
00342 }
00343 
00344 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
00345   OutMI.setOpcode(MI->getOpcode());
00346 
00347   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
00348     const MachineOperand &MO = MI->getOperand(i);
00349 
00350     MCOperand MCOp;
00351     switch (MO.getType()) {
00352     default:
00353       MI->dump();
00354       llvm_unreachable("unknown operand type");
00355     case MachineOperand::MO_Register:
00356       // Ignore all implicit register operands.
00357       if (MO.isImplicit()) continue;
00358       MCOp = MCOperand::CreateReg(MO.getReg());
00359       break;
00360     case MachineOperand::MO_Immediate:
00361       MCOp = MCOperand::CreateImm(MO.getImm());
00362       break;
00363     case MachineOperand::MO_MachineBasicBlock:
00364     case MachineOperand::MO_GlobalAddress:
00365     case MachineOperand::MO_ExternalSymbol:
00366       MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
00367       break;
00368     case MachineOperand::MO_JumpTableIndex:
00369       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
00370       break;
00371     case MachineOperand::MO_ConstantPoolIndex:
00372       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
00373       break;
00374     case MachineOperand::MO_BlockAddress:
00375       MCOp = LowerSymbolOperand(MO,
00376                      AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
00377       break;
00378     case MachineOperand::MO_RegisterMask:
00379       // Ignore call clobbers.
00380       continue;
00381     }
00382 
00383     OutMI.addOperand(MCOp);
00384   }
00385 
00386   // Handle a few special cases to eliminate operand modifiers.
00387 ReSimplify:
00388   switch (OutMI.getOpcode()) {
00389   case X86::LEA64_32r:
00390   case X86::LEA64r:
00391   case X86::LEA16r:
00392   case X86::LEA32r:
00393     // LEA should have a segment register, but it must be empty.
00394     assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
00395            "Unexpected # of LEA operands");
00396     assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
00397            "LEA has segment specified!");
00398     break;
00399 
00400   case X86::MOV32ri64:
00401     OutMI.setOpcode(X86::MOV32ri);
00402     break;
00403 
00404   // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
00405   // if one of the registers is extended, but other isn't.
00406   case X86::VMOVAPDrr:
00407   case X86::VMOVAPDYrr:
00408   case X86::VMOVAPSrr:
00409   case X86::VMOVAPSYrr:
00410   case X86::VMOVDQArr:
00411   case X86::VMOVDQAYrr:
00412   case X86::VMOVDQUrr:
00413   case X86::VMOVDQUYrr:
00414   case X86::VMOVUPDrr:
00415   case X86::VMOVUPDYrr:
00416   case X86::VMOVUPSrr:
00417   case X86::VMOVUPSYrr: {
00418     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
00419         X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
00420       unsigned NewOpc;
00421       switch (OutMI.getOpcode()) {
00422       default: llvm_unreachable("Invalid opcode");
00423       case X86::VMOVAPDrr:  NewOpc = X86::VMOVAPDrr_REV;  break;
00424       case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
00425       case X86::VMOVAPSrr:  NewOpc = X86::VMOVAPSrr_REV;  break;
00426       case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
00427       case X86::VMOVDQArr:  NewOpc = X86::VMOVDQArr_REV;  break;
00428       case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
00429       case X86::VMOVDQUrr:  NewOpc = X86::VMOVDQUrr_REV;  break;
00430       case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
00431       case X86::VMOVUPDrr:  NewOpc = X86::VMOVUPDrr_REV;  break;
00432       case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
00433       case X86::VMOVUPSrr:  NewOpc = X86::VMOVUPSrr_REV;  break;
00434       case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
00435       }
00436       OutMI.setOpcode(NewOpc);
00437     }
00438     break;
00439   }
00440   case X86::VMOVSDrr:
00441   case X86::VMOVSSrr: {
00442     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
00443         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
00444       unsigned NewOpc;
00445       switch (OutMI.getOpcode()) {
00446       default: llvm_unreachable("Invalid opcode");
00447       case X86::VMOVSDrr:   NewOpc = X86::VMOVSDrr_REV;   break;
00448       case X86::VMOVSSrr:   NewOpc = X86::VMOVSSrr_REV;   break;
00449       }
00450       OutMI.setOpcode(NewOpc);
00451     }
00452     break;
00453   }
00454 
00455   // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
00456   // inputs modeled as normal uses instead of implicit uses.  As such, truncate
00457   // off all but the first operand (the callee).  FIXME: Change isel.
00458   case X86::TAILJMPr64:
00459   case X86::CALL64r:
00460   case X86::CALL64pcrel32: {
00461     unsigned Opcode = OutMI.getOpcode();
00462     MCOperand Saved = OutMI.getOperand(0);
00463     OutMI = MCInst();
00464     OutMI.setOpcode(Opcode);
00465     OutMI.addOperand(Saved);
00466     break;
00467   }
00468 
00469   case X86::EH_RETURN:
00470   case X86::EH_RETURN64: {
00471     OutMI = MCInst();
00472     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
00473     break;
00474   }
00475 
00476   // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
00477   case X86::TAILJMPr:
00478   case X86::TAILJMPd:
00479   case X86::TAILJMPd64: {
00480     unsigned Opcode;
00481     switch (OutMI.getOpcode()) {
00482     default: llvm_unreachable("Invalid opcode");
00483     case X86::TAILJMPr: Opcode = X86::JMP32r; break;
00484     case X86::TAILJMPd:
00485     case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
00486     }
00487 
00488     MCOperand Saved = OutMI.getOperand(0);
00489     OutMI = MCInst();
00490     OutMI.setOpcode(Opcode);
00491     OutMI.addOperand(Saved);
00492     break;
00493   }
00494 
00495   // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
00496   // this with an ugly goto in case the resultant OR uses EAX and needs the
00497   // short form.
00498   case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
00499   case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
00500   case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
00501   case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
00502   case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
00503   case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
00504   case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
00505   case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
00506   case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
00507 
00508   // The assembler backend wants to see branches in their small form and relax
00509   // them to their large form.  The JIT can only handle the large form because
00510   // it does not do relaxation.  For now, translate the large form to the
00511   // small one here.
00512   case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
00513   case X86::JO_4:  OutMI.setOpcode(X86::JO_1); break;
00514   case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
00515   case X86::JB_4:  OutMI.setOpcode(X86::JB_1); break;
00516   case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
00517   case X86::JE_4:  OutMI.setOpcode(X86::JE_1); break;
00518   case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
00519   case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
00520   case X86::JA_4:  OutMI.setOpcode(X86::JA_1); break;
00521   case X86::JS_4:  OutMI.setOpcode(X86::JS_1); break;
00522   case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
00523   case X86::JP_4:  OutMI.setOpcode(X86::JP_1); break;
00524   case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
00525   case X86::JL_4:  OutMI.setOpcode(X86::JL_1); break;
00526   case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
00527   case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
00528   case X86::JG_4:  OutMI.setOpcode(X86::JG_1); break;
00529 
00530   // Atomic load and store require a separate pseudo-inst because Acquire
00531   // implies mayStore and Release implies mayLoad; fix these to regular MOV
00532   // instructions here
00533   case X86::ACQUIRE_MOV8rm:  OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
00534   case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
00535   case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
00536   case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
00537   case X86::RELEASE_MOV8mr:  OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
00538   case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
00539   case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
00540   case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
00541 
00542   // We don't currently select the correct instruction form for instructions
00543   // which have a short %eax, etc. form. Handle this by custom lowering, for
00544   // now.
00545   //
00546   // Note, we are currently not handling the following instructions:
00547   // MOV64ao8, MOV64o8a
00548   // XCHG16ar, XCHG32ar, XCHG64ar
00549   case X86::MOV8mr_NOREX:
00550   case X86::MOV8mr:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
00551   case X86::MOV8rm_NOREX:
00552   case X86::MOV8rm:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
00553   case X86::MOV16mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
00554   case X86::MOV16rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
00555   case X86::MOV32mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
00556   case X86::MOV32rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
00557 
00558   case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
00559   case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
00560   case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
00561   case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
00562   case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
00563   case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
00564   case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
00565   case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
00566   case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
00567   case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
00568   case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
00569   case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
00570   case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
00571   case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
00572   case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
00573   case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
00574   case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
00575   case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
00576   case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
00577   case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
00578   case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
00579   case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
00580   case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
00581   case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
00582   case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
00583   case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
00584   case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
00585   case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
00586   case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
00587   case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
00588   case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
00589   case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
00590   case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
00591   case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
00592   case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
00593   case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
00594 
00595   // Try to shrink some forms of movsx.
00596   case X86::MOVSX16rr8:
00597   case X86::MOVSX32rr16:
00598   case X86::MOVSX64rr32:
00599     SimplifyMOVSX(OutMI);
00600     break;
00601   }
00602 }
00603 
00604 static void LowerTlsAddr(MCStreamer &OutStreamer,
00605                          X86MCInstLower &MCInstLowering,
00606                          const MachineInstr &MI,
00607                          const MCSubtargetInfo& STI) {
00608 
00609   bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
00610                   MI.getOpcode() == X86::TLS_base_addr64;
00611 
00612   bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
00613 
00614   MCContext &context = OutStreamer.getContext();
00615 
00616   if (needsPadding)
00617     OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI);
00618 
00619   MCSymbolRefExpr::VariantKind SRVK;
00620   switch (MI.getOpcode()) {
00621     case X86::TLS_addr32:
00622     case X86::TLS_addr64:
00623       SRVK = MCSymbolRefExpr::VK_TLSGD;
00624       break;
00625     case X86::TLS_base_addr32:
00626       SRVK = MCSymbolRefExpr::VK_TLSLDM;
00627       break;
00628     case X86::TLS_base_addr64:
00629       SRVK = MCSymbolRefExpr::VK_TLSLD;
00630       break;
00631     default:
00632       llvm_unreachable("unexpected opcode");
00633   }
00634 
00635   MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
00636   const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
00637 
00638   MCInst LEA;
00639   if (is64Bits) {
00640     LEA.setOpcode(X86::LEA64r);
00641     LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
00642     LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
00643     LEA.addOperand(MCOperand::CreateImm(1));        // scale
00644     LEA.addOperand(MCOperand::CreateReg(0));        // index
00645     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
00646     LEA.addOperand(MCOperand::CreateReg(0));        // seg
00647   } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
00648     LEA.setOpcode(X86::LEA32r);
00649     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
00650     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
00651     LEA.addOperand(MCOperand::CreateImm(1));        // scale
00652     LEA.addOperand(MCOperand::CreateReg(0));        // index
00653     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
00654     LEA.addOperand(MCOperand::CreateReg(0));        // seg
00655   } else {
00656     LEA.setOpcode(X86::LEA32r);
00657     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
00658     LEA.addOperand(MCOperand::CreateReg(0));        // base
00659     LEA.addOperand(MCOperand::CreateImm(1));        // scale
00660     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
00661     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
00662     LEA.addOperand(MCOperand::CreateReg(0));        // seg
00663   }
00664   OutStreamer.EmitInstruction(LEA, STI);
00665 
00666   if (needsPadding) {
00667     OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI);
00668     OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI);
00669     OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX), STI);
00670   }
00671 
00672   StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
00673   MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
00674   const MCSymbolRefExpr *tlsRef =
00675     MCSymbolRefExpr::Create(tlsGetAddr,
00676                             MCSymbolRefExpr::VK_PLT,
00677                             context);
00678 
00679   OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
00680                                                      : X86::CALLpcrel32)
00681     .addExpr(tlsRef), STI);
00682 }
00683 
00684 /// \brief Emit the optimal amount of multi-byte nops on X86.
00685 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
00686   // This works only for 64bit. For 32bit we have to do additional checking if
00687   // the CPU supports multi-byte nops.
00688   assert(Is64Bit && "EmitNops only supports X86-64");
00689   while (NumBytes) {
00690     unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
00691     Opc = IndexReg = Displacement = SegmentReg = 0;
00692     BaseReg = X86::RAX; ScaleVal = 1;
00693     switch (NumBytes) {
00694     case  0: llvm_unreachable("Zero nops?"); break;
00695     case  1: NumBytes -=  1; Opc = X86::NOOP; break;
00696     case  2: NumBytes -=  2; Opc = X86::XCHG16ar; break;
00697     case  3: NumBytes -=  3; Opc = X86::NOOPL; break;
00698     case  4: NumBytes -=  4; Opc = X86::NOOPL; Displacement = 8; break;
00699     case  5: NumBytes -=  5; Opc = X86::NOOPL; Displacement = 8;
00700              IndexReg = X86::RAX; break;
00701     case  6: NumBytes -=  6; Opc = X86::NOOPW; Displacement = 8;
00702              IndexReg = X86::RAX; break;
00703     case  7: NumBytes -=  7; Opc = X86::NOOPL; Displacement = 512; break;
00704     case  8: NumBytes -=  8; Opc = X86::NOOPL; Displacement = 512;
00705              IndexReg = X86::RAX; break;
00706     case  9: NumBytes -=  9; Opc = X86::NOOPW; Displacement = 512;
00707              IndexReg = X86::RAX; break;
00708     default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
00709              IndexReg = X86::RAX; SegmentReg = X86::CS; break;
00710     }
00711 
00712     unsigned NumPrefixes = std::min(NumBytes, 5U);
00713     NumBytes -= NumPrefixes;
00714     for (unsigned i = 0; i != NumPrefixes; ++i)
00715       OS.EmitBytes("\x66");
00716 
00717     switch (Opc) {
00718     default: llvm_unreachable("Unexpected opcode"); break;
00719     case X86::NOOP:
00720       OS.EmitInstruction(MCInstBuilder(Opc), STI);
00721       break;
00722     case X86::XCHG16ar:
00723       OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
00724       break;
00725     case X86::NOOPL:
00726     case X86::NOOPW:
00727       OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg).addImm(ScaleVal)
00728                                            .addReg(IndexReg)
00729                                            .addImm(Displacement)
00730                                            .addReg(SegmentReg), STI);
00731       break;
00732     }
00733   } // while (NumBytes)
00734 }
00735 
00736 // Lower a stackmap of the form:
00737 // <id>, <shadowBytes>, ...
00738 static void LowerSTACKMAP(MCStreamer &OS, StackMaps &SM,
00739                           const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) {
00740   unsigned NumBytes = MI.getOperand(1).getImm();
00741   SM.recordStackMap(MI);
00742   // Emit padding.
00743   // FIXME: These nops ensure that the stackmap's shadow is covered by
00744   // instructions from the same basic block, but the nops should not be
00745   // necessary if instructions from the same block follow the stackmap.
00746   EmitNops(OS, NumBytes, Is64Bit, STI);
00747 }
00748 
00749 // Lower a patchpoint of the form:
00750 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
00751 static void LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM,
00752                             const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) {
00753   assert(Is64Bit && "Patchpoint currently only supports X86-64");
00754   SM.recordPatchPoint(MI);
00755 
00756   PatchPointOpers opers(&MI);
00757   unsigned ScratchIdx = opers.getNextScratchIdx();
00758   unsigned EncodedBytes = 0;
00759   int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
00760   if (CallTarget) {
00761     // Emit MOV to materialize the target address and the CALL to target.
00762     // This is encoded with 12-13 bytes, depending on which register is used.
00763     unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
00764     if (X86II::isX86_64ExtendedReg(ScratchReg))
00765       EncodedBytes = 13;
00766     else
00767       EncodedBytes = 12;
00768     OS.EmitInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)
00769                                                   .addImm(CallTarget), STI);
00770     OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg), STI);
00771   }
00772   // Emit padding.
00773   unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
00774   assert(NumBytes >= EncodedBytes &&
00775          "Patchpoint can't request size less than the length of a call.");
00776 
00777   EmitNops(OS, NumBytes - EncodedBytes, Is64Bit, STI);
00778 }
00779 
00780 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
00781   X86MCInstLower MCInstLowering(*MF, *this);
00782   switch (MI->getOpcode()) {
00783   case TargetOpcode::DBG_VALUE:
00784     llvm_unreachable("Should be handled target independently");
00785 
00786   // Emit nothing here but a comment if we can.
00787   case X86::Int_MemBarrier:
00788     OutStreamer.emitRawComment("MEMBARRIER");
00789     return;
00790 
00791 
00792   case X86::EH_RETURN:
00793   case X86::EH_RETURN64: {
00794     // Lower these as normal, but add some comments.
00795     unsigned Reg = MI->getOperand(0).getReg();
00796     OutStreamer.AddComment(StringRef("eh_return, addr: %") +
00797                            X86ATTInstPrinter::getRegisterName(Reg));
00798     break;
00799   }
00800   case X86::TAILJMPr:
00801   case X86::TAILJMPd:
00802   case X86::TAILJMPd64:
00803     // Lower these as normal, but add some comments.
00804     OutStreamer.AddComment("TAILCALL");
00805     break;
00806 
00807   case X86::TLS_addr32:
00808   case X86::TLS_addr64:
00809   case X86::TLS_base_addr32:
00810   case X86::TLS_base_addr64:
00811     return LowerTlsAddr(OutStreamer, MCInstLowering, *MI, getSubtargetInfo());
00812 
00813   case X86::MOVPC32r: {
00814     // This is a pseudo op for a two instruction sequence with a label, which
00815     // looks like:
00816     //     call "L1$pb"
00817     // "L1$pb":
00818     //     popl %esi
00819 
00820     // Emit the call.
00821     MCSymbol *PICBase = MF->getPICBaseSymbol();
00822     // FIXME: We would like an efficient form for this, so we don't have to do a
00823     // lot of extra uniquing.
00824     EmitToStreamer(OutStreamer, MCInstBuilder(X86::CALLpcrel32)
00825       .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
00826 
00827     // Emit the label.
00828     OutStreamer.EmitLabel(PICBase);
00829 
00830     // popl $reg
00831     EmitToStreamer(OutStreamer, MCInstBuilder(X86::POP32r)
00832       .addReg(MI->getOperand(0).getReg()));
00833     return;
00834   }
00835 
00836   case X86::ADD32ri: {
00837     // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
00838     if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
00839       break;
00840 
00841     // Okay, we have something like:
00842     //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
00843 
00844     // For this, we want to print something like:
00845     //   MYGLOBAL + (. - PICBASE)
00846     // However, we can't generate a ".", so just emit a new label here and refer
00847     // to it.
00848     MCSymbol *DotSym = OutContext.CreateTempSymbol();
00849     OutStreamer.EmitLabel(DotSym);
00850 
00851     // Now that we have emitted the label, lower the complex operand expression.
00852     MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
00853 
00854     const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
00855     const MCExpr *PICBase =
00856       MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
00857     DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
00858 
00859     DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
00860                                       DotExpr, OutContext);
00861 
00862     EmitToStreamer(OutStreamer, MCInstBuilder(X86::ADD32ri)
00863       .addReg(MI->getOperand(0).getReg())
00864       .addReg(MI->getOperand(1).getReg())
00865       .addExpr(DotExpr));
00866     return;
00867   }
00868 
00869   case TargetOpcode::STACKMAP:
00870     return LowerSTACKMAP(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo());
00871 
00872   case TargetOpcode::PATCHPOINT:
00873     return LowerPATCHPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo());
00874 
00875   case X86::MORESTACK_RET:
00876     EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget)));
00877     return;
00878 
00879   case X86::MORESTACK_RET_RESTORE_R10:
00880     // Return, then restore R10.
00881     EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget)));
00882     EmitToStreamer(OutStreamer, MCInstBuilder(X86::MOV64rr)
00883       .addReg(X86::R10)
00884       .addReg(X86::RAX));
00885     return;
00886   }
00887 
00888   MCInst TmpInst;
00889   MCInstLowering.Lower(MI, TmpInst);
00890   EmitToStreamer(OutStreamer, TmpInst);
00891 }