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X86MCInstLower.cpp
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00001 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains code to lower X86 MachineInstrs to their corresponding
00011 // MCInst records.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "X86AsmPrinter.h"
00016 #include "X86RegisterInfo.h"
00017 #include "InstPrinter/X86ATTInstPrinter.h"
00018 #include "MCTargetDesc/X86BaseInfo.h"
00019 #include "llvm/ADT/SmallString.h"
00020 #include "llvm/CodeGen/MachineFunction.h"
00021 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00022 #include "llvm/CodeGen/StackMaps.h"
00023 #include "llvm/IR/DataLayout.h"
00024 #include "llvm/IR/GlobalValue.h"
00025 #include "llvm/IR/Mangler.h"
00026 #include "llvm/MC/MCAsmInfo.h"
00027 #include "llvm/MC/MCContext.h"
00028 #include "llvm/MC/MCExpr.h"
00029 #include "llvm/MC/MCInst.h"
00030 #include "llvm/MC/MCInstBuilder.h"
00031 #include "llvm/MC/MCStreamer.h"
00032 #include "llvm/MC/MCSymbol.h"
00033 using namespace llvm;
00034 
00035 namespace {
00036 
00037 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
00038 class X86MCInstLower {
00039   MCContext &Ctx;
00040   const MachineFunction &MF;
00041   const TargetMachine &TM;
00042   const MCAsmInfo &MAI;
00043   X86AsmPrinter &AsmPrinter;
00044 public:
00045   X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
00046 
00047   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
00048 
00049   MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
00050   MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
00051 
00052 private:
00053   MachineModuleInfoMachO &getMachOMMI() const;
00054   Mangler *getMang() const {
00055     return AsmPrinter.Mang;
00056   }
00057 };
00058 
00059 } // end anonymous namespace
00060 
00061 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
00062                                X86AsmPrinter &asmprinter)
00063 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()),
00064   MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
00065 
00066 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
00067   return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
00068 }
00069 
00070 
00071 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
00072 /// operand to an MCSymbol.
00073 MCSymbol *X86MCInstLower::
00074 GetSymbolFromOperand(const MachineOperand &MO) const {
00075   const DataLayout *DL = TM.getDataLayout();
00076   assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
00077 
00078   SmallString<128> Name;
00079   StringRef Suffix;
00080 
00081   switch (MO.getTargetFlags()) {
00082   case X86II::MO_DLLIMPORT:
00083     // Handle dllimport linkage.
00084     Name += "__imp_";
00085     break;
00086   case X86II::MO_DARWIN_STUB:
00087     Suffix = "$stub";
00088     break;
00089   case X86II::MO_DARWIN_NONLAZY:
00090   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
00091   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
00092     Suffix = "$non_lazy_ptr";
00093     break;
00094   }
00095 
00096   if (!Suffix.empty())
00097     Name += DL->getPrivateGlobalPrefix();
00098 
00099   unsigned PrefixLen = Name.size();
00100 
00101   if (MO.isGlobal()) {
00102     const GlobalValue *GV = MO.getGlobal();
00103     AsmPrinter.getNameWithPrefix(Name, GV);
00104   } else if (MO.isSymbol()) {
00105     getMang()->getNameWithPrefix(Name, MO.getSymbolName());
00106   } else if (MO.isMBB()) {
00107     Name += MO.getMBB()->getSymbol()->getName();
00108   }
00109   unsigned OrigLen = Name.size() - PrefixLen;
00110 
00111   Name += Suffix;
00112   MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
00113 
00114   StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
00115 
00116   // If the target flags on the operand changes the name of the symbol, do that
00117   // before we return the symbol.
00118   switch (MO.getTargetFlags()) {
00119   default: break;
00120   case X86II::MO_DARWIN_NONLAZY:
00121   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
00122     MachineModuleInfoImpl::StubValueTy &StubSym =
00123       getMachOMMI().getGVStubEntry(Sym);
00124     if (!StubSym.getPointer()) {
00125       assert(MO.isGlobal() && "Extern symbol not handled yet");
00126       StubSym =
00127         MachineModuleInfoImpl::
00128         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
00129                     !MO.getGlobal()->hasInternalLinkage());
00130     }
00131     break;
00132   }
00133   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
00134     MachineModuleInfoImpl::StubValueTy &StubSym =
00135       getMachOMMI().getHiddenGVStubEntry(Sym);
00136     if (!StubSym.getPointer()) {
00137       assert(MO.isGlobal() && "Extern symbol not handled yet");
00138       StubSym =
00139         MachineModuleInfoImpl::
00140         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
00141                     !MO.getGlobal()->hasInternalLinkage());
00142     }
00143     break;
00144   }
00145   case X86II::MO_DARWIN_STUB: {
00146     MachineModuleInfoImpl::StubValueTy &StubSym =
00147       getMachOMMI().getFnStubEntry(Sym);
00148     if (StubSym.getPointer())
00149       return Sym;
00150 
00151     if (MO.isGlobal()) {
00152       StubSym =
00153         MachineModuleInfoImpl::
00154         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
00155                     !MO.getGlobal()->hasInternalLinkage());
00156     } else {
00157       StubSym =
00158         MachineModuleInfoImpl::
00159         StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false);
00160     }
00161     break;
00162   }
00163   }
00164 
00165   return Sym;
00166 }
00167 
00168 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
00169                                              MCSymbol *Sym) const {
00170   // FIXME: We would like an efficient form for this, so we don't have to do a
00171   // lot of extra uniquing.
00172   const MCExpr *Expr = nullptr;
00173   MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
00174 
00175   switch (MO.getTargetFlags()) {
00176   default: llvm_unreachable("Unknown target flag on GV operand");
00177   case X86II::MO_NO_FLAG:    // No flag.
00178   // These affect the name of the symbol, not any suffix.
00179   case X86II::MO_DARWIN_NONLAZY:
00180   case X86II::MO_DLLIMPORT:
00181   case X86II::MO_DARWIN_STUB:
00182     break;
00183 
00184   case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
00185   case X86II::MO_TLVP_PIC_BASE:
00186     Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
00187     // Subtract the pic base.
00188     Expr = MCBinaryExpr::CreateSub(Expr,
00189                                   MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
00190                                                            Ctx),
00191                                    Ctx);
00192     break;
00193   case X86II::MO_SECREL:    RefKind = MCSymbolRefExpr::VK_SECREL; break;
00194   case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
00195   case X86II::MO_TLSLD:     RefKind = MCSymbolRefExpr::VK_TLSLD; break;
00196   case X86II::MO_TLSLDM:    RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
00197   case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
00198   case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
00199   case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
00200   case X86II::MO_DTPOFF:    RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
00201   case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
00202   case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
00203   case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
00204   case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
00205   case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
00206   case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
00207   case X86II::MO_PIC_BASE_OFFSET:
00208   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
00209   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
00210     Expr = MCSymbolRefExpr::Create(Sym, Ctx);
00211     // Subtract the pic base.
00212     Expr = MCBinaryExpr::CreateSub(Expr,
00213                             MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
00214                                    Ctx);
00215     if (MO.isJTI() && MAI.hasSetDirective()) {
00216       // If .set directive is supported, use it to reduce the number of
00217       // relocations the assembler will generate for differences between
00218       // local labels. This is only safe when the symbols are in the same
00219       // section so we are restricting it to jumptable references.
00220       MCSymbol *Label = Ctx.CreateTempSymbol();
00221       AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
00222       Expr = MCSymbolRefExpr::Create(Label, Ctx);
00223     }
00224     break;
00225   }
00226 
00227   if (!Expr)
00228     Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
00229 
00230   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
00231     Expr = MCBinaryExpr::CreateAdd(Expr,
00232                                    MCConstantExpr::Create(MO.getOffset(), Ctx),
00233                                    Ctx);
00234   return MCOperand::CreateExpr(Expr);
00235 }
00236 
00237 
00238 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
00239 /// a short fixed-register form.
00240 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
00241   unsigned ImmOp = Inst.getNumOperands() - 1;
00242   assert(Inst.getOperand(0).isReg() &&
00243          (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
00244          ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
00245            Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
00246           Inst.getNumOperands() == 2) && "Unexpected instruction!");
00247 
00248   // Check whether the destination register can be fixed.
00249   unsigned Reg = Inst.getOperand(0).getReg();
00250   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
00251     return;
00252 
00253   // If so, rewrite the instruction.
00254   MCOperand Saved = Inst.getOperand(ImmOp);
00255   Inst = MCInst();
00256   Inst.setOpcode(Opcode);
00257   Inst.addOperand(Saved);
00258 }
00259 
00260 /// \brief If a movsx instruction has a shorter encoding for the used register
00261 /// simplify the instruction to use it instead.
00262 static void SimplifyMOVSX(MCInst &Inst) {
00263   unsigned NewOpcode = 0;
00264   unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
00265   switch (Inst.getOpcode()) {
00266   default:
00267     llvm_unreachable("Unexpected instruction!");
00268   case X86::MOVSX16rr8:  // movsbw %al, %ax   --> cbtw
00269     if (Op0 == X86::AX && Op1 == X86::AL)
00270       NewOpcode = X86::CBW;
00271     break;
00272   case X86::MOVSX32rr16: // movswl %ax, %eax  --> cwtl
00273     if (Op0 == X86::EAX && Op1 == X86::AX)
00274       NewOpcode = X86::CWDE;
00275     break;
00276   case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
00277     if (Op0 == X86::RAX && Op1 == X86::EAX)
00278       NewOpcode = X86::CDQE;
00279     break;
00280   }
00281 
00282   if (NewOpcode != 0) {
00283     Inst = MCInst();
00284     Inst.setOpcode(NewOpcode);
00285   }
00286 }
00287 
00288 /// \brief Simplify things like MOV32rm to MOV32o32a.
00289 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
00290                                   unsigned Opcode) {
00291   // Don't make these simplifications in 64-bit mode; other assemblers don't
00292   // perform them because they make the code larger.
00293   if (Printer.getSubtarget().is64Bit())
00294     return;
00295 
00296   bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
00297   unsigned AddrBase = IsStore;
00298   unsigned RegOp = IsStore ? 0 : 5;
00299   unsigned AddrOp = AddrBase + 3;
00300   assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
00301          Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
00302          Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
00303          Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
00304          Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
00305          (Inst.getOperand(AddrOp).isExpr() ||
00306           Inst.getOperand(AddrOp).isImm()) &&
00307          "Unexpected instruction!");
00308 
00309   // Check whether the destination register can be fixed.
00310   unsigned Reg = Inst.getOperand(RegOp).getReg();
00311   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
00312     return;
00313 
00314   // Check whether this is an absolute address.
00315   // FIXME: We know TLVP symbol refs aren't, but there should be a better way
00316   // to do this here.
00317   bool Absolute = true;
00318   if (Inst.getOperand(AddrOp).isExpr()) {
00319     const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
00320     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
00321       if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
00322         Absolute = false;
00323   }
00324 
00325   if (Absolute &&
00326       (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
00327        Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
00328        Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
00329     return;
00330 
00331   // If so, rewrite the instruction.
00332   MCOperand Saved = Inst.getOperand(AddrOp);
00333   MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
00334   Inst = MCInst();
00335   Inst.setOpcode(Opcode);
00336   Inst.addOperand(Saved);
00337   Inst.addOperand(Seg);
00338 }
00339 
00340 static unsigned getRetOpcode(const X86Subtarget &Subtarget)
00341 {
00342   return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
00343 }
00344 
00345 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
00346   OutMI.setOpcode(MI->getOpcode());
00347 
00348   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
00349     const MachineOperand &MO = MI->getOperand(i);
00350 
00351     MCOperand MCOp;
00352     switch (MO.getType()) {
00353     default:
00354       MI->dump();
00355       llvm_unreachable("unknown operand type");
00356     case MachineOperand::MO_Register:
00357       // Ignore all implicit register operands.
00358       if (MO.isImplicit()) continue;
00359       MCOp = MCOperand::CreateReg(MO.getReg());
00360       break;
00361     case MachineOperand::MO_Immediate:
00362       MCOp = MCOperand::CreateImm(MO.getImm());
00363       break;
00364     case MachineOperand::MO_MachineBasicBlock:
00365     case MachineOperand::MO_GlobalAddress:
00366     case MachineOperand::MO_ExternalSymbol:
00367       MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
00368       break;
00369     case MachineOperand::MO_JumpTableIndex:
00370       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
00371       break;
00372     case MachineOperand::MO_ConstantPoolIndex:
00373       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
00374       break;
00375     case MachineOperand::MO_BlockAddress:
00376       MCOp = LowerSymbolOperand(MO,
00377                      AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
00378       break;
00379     case MachineOperand::MO_RegisterMask:
00380       // Ignore call clobbers.
00381       continue;
00382     }
00383 
00384     OutMI.addOperand(MCOp);
00385   }
00386 
00387   // Handle a few special cases to eliminate operand modifiers.
00388 ReSimplify:
00389   switch (OutMI.getOpcode()) {
00390   case X86::LEA64_32r:
00391   case X86::LEA64r:
00392   case X86::LEA16r:
00393   case X86::LEA32r:
00394     // LEA should have a segment register, but it must be empty.
00395     assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
00396            "Unexpected # of LEA operands");
00397     assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
00398            "LEA has segment specified!");
00399     break;
00400 
00401   case X86::MOV32ri64:
00402     OutMI.setOpcode(X86::MOV32ri);
00403     break;
00404 
00405   // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
00406   // if one of the registers is extended, but other isn't.
00407   case X86::VMOVAPDrr:
00408   case X86::VMOVAPDYrr:
00409   case X86::VMOVAPSrr:
00410   case X86::VMOVAPSYrr:
00411   case X86::VMOVDQArr:
00412   case X86::VMOVDQAYrr:
00413   case X86::VMOVDQUrr:
00414   case X86::VMOVDQUYrr:
00415   case X86::VMOVUPDrr:
00416   case X86::VMOVUPDYrr:
00417   case X86::VMOVUPSrr:
00418   case X86::VMOVUPSYrr: {
00419     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
00420         X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
00421       unsigned NewOpc;
00422       switch (OutMI.getOpcode()) {
00423       default: llvm_unreachable("Invalid opcode");
00424       case X86::VMOVAPDrr:  NewOpc = X86::VMOVAPDrr_REV;  break;
00425       case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
00426       case X86::VMOVAPSrr:  NewOpc = X86::VMOVAPSrr_REV;  break;
00427       case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
00428       case X86::VMOVDQArr:  NewOpc = X86::VMOVDQArr_REV;  break;
00429       case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
00430       case X86::VMOVDQUrr:  NewOpc = X86::VMOVDQUrr_REV;  break;
00431       case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
00432       case X86::VMOVUPDrr:  NewOpc = X86::VMOVUPDrr_REV;  break;
00433       case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
00434       case X86::VMOVUPSrr:  NewOpc = X86::VMOVUPSrr_REV;  break;
00435       case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
00436       }
00437       OutMI.setOpcode(NewOpc);
00438     }
00439     break;
00440   }
00441   case X86::VMOVSDrr:
00442   case X86::VMOVSSrr: {
00443     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
00444         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
00445       unsigned NewOpc;
00446       switch (OutMI.getOpcode()) {
00447       default: llvm_unreachable("Invalid opcode");
00448       case X86::VMOVSDrr:   NewOpc = X86::VMOVSDrr_REV;   break;
00449       case X86::VMOVSSrr:   NewOpc = X86::VMOVSSrr_REV;   break;
00450       }
00451       OutMI.setOpcode(NewOpc);
00452     }
00453     break;
00454   }
00455 
00456   // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
00457   // inputs modeled as normal uses instead of implicit uses.  As such, truncate
00458   // off all but the first operand (the callee).  FIXME: Change isel.
00459   case X86::TAILJMPr64:
00460   case X86::CALL64r:
00461   case X86::CALL64pcrel32: {
00462     unsigned Opcode = OutMI.getOpcode();
00463     MCOperand Saved = OutMI.getOperand(0);
00464     OutMI = MCInst();
00465     OutMI.setOpcode(Opcode);
00466     OutMI.addOperand(Saved);
00467     break;
00468   }
00469 
00470   case X86::EH_RETURN:
00471   case X86::EH_RETURN64: {
00472     OutMI = MCInst();
00473     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
00474     break;
00475   }
00476 
00477   // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
00478   case X86::TAILJMPr:
00479   case X86::TAILJMPd:
00480   case X86::TAILJMPd64: {
00481     unsigned Opcode;
00482     switch (OutMI.getOpcode()) {
00483     default: llvm_unreachable("Invalid opcode");
00484     case X86::TAILJMPr: Opcode = X86::JMP32r; break;
00485     case X86::TAILJMPd:
00486     case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
00487     }
00488 
00489     MCOperand Saved = OutMI.getOperand(0);
00490     OutMI = MCInst();
00491     OutMI.setOpcode(Opcode);
00492     OutMI.addOperand(Saved);
00493     break;
00494   }
00495 
00496   // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
00497   // this with an ugly goto in case the resultant OR uses EAX and needs the
00498   // short form.
00499   case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
00500   case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
00501   case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
00502   case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
00503   case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
00504   case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
00505   case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
00506   case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
00507   case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
00508 
00509   // The assembler backend wants to see branches in their small form and relax
00510   // them to their large form.  The JIT can only handle the large form because
00511   // it does not do relaxation.  For now, translate the large form to the
00512   // small one here.
00513   case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
00514   case X86::JO_4:  OutMI.setOpcode(X86::JO_1); break;
00515   case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
00516   case X86::JB_4:  OutMI.setOpcode(X86::JB_1); break;
00517   case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
00518   case X86::JE_4:  OutMI.setOpcode(X86::JE_1); break;
00519   case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
00520   case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
00521   case X86::JA_4:  OutMI.setOpcode(X86::JA_1); break;
00522   case X86::JS_4:  OutMI.setOpcode(X86::JS_1); break;
00523   case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
00524   case X86::JP_4:  OutMI.setOpcode(X86::JP_1); break;
00525   case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
00526   case X86::JL_4:  OutMI.setOpcode(X86::JL_1); break;
00527   case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
00528   case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
00529   case X86::JG_4:  OutMI.setOpcode(X86::JG_1); break;
00530 
00531   // Atomic load and store require a separate pseudo-inst because Acquire
00532   // implies mayStore and Release implies mayLoad; fix these to regular MOV
00533   // instructions here
00534   case X86::ACQUIRE_MOV8rm:  OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
00535   case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
00536   case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
00537   case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
00538   case X86::RELEASE_MOV8mr:  OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
00539   case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
00540   case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
00541   case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
00542 
00543   // We don't currently select the correct instruction form for instructions
00544   // which have a short %eax, etc. form. Handle this by custom lowering, for
00545   // now.
00546   //
00547   // Note, we are currently not handling the following instructions:
00548   // MOV64ao8, MOV64o8a
00549   // XCHG16ar, XCHG32ar, XCHG64ar
00550   case X86::MOV8mr_NOREX:
00551   case X86::MOV8mr:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
00552   case X86::MOV8rm_NOREX:
00553   case X86::MOV8rm:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
00554   case X86::MOV16mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
00555   case X86::MOV16rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
00556   case X86::MOV32mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
00557   case X86::MOV32rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
00558 
00559   case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
00560   case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
00561   case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
00562   case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
00563   case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
00564   case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
00565   case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
00566   case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
00567   case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
00568   case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
00569   case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
00570   case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
00571   case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
00572   case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
00573   case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
00574   case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
00575   case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
00576   case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
00577   case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
00578   case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
00579   case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
00580   case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
00581   case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
00582   case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
00583   case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
00584   case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
00585   case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
00586   case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
00587   case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
00588   case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
00589   case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
00590   case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
00591   case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
00592   case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
00593   case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
00594   case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
00595 
00596   // Try to shrink some forms of movsx.
00597   case X86::MOVSX16rr8:
00598   case X86::MOVSX32rr16:
00599   case X86::MOVSX64rr32:
00600     SimplifyMOVSX(OutMI);
00601     break;
00602   }
00603 }
00604 
00605 static void LowerTlsAddr(MCStreamer &OutStreamer,
00606                          X86MCInstLower &MCInstLowering,
00607                          const MachineInstr &MI,
00608                          const MCSubtargetInfo& STI) {
00609 
00610   bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
00611                   MI.getOpcode() == X86::TLS_base_addr64;
00612 
00613   bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
00614 
00615   MCContext &context = OutStreamer.getContext();
00616 
00617   if (needsPadding)
00618     OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI);
00619 
00620   MCSymbolRefExpr::VariantKind SRVK;
00621   switch (MI.getOpcode()) {
00622     case X86::TLS_addr32:
00623     case X86::TLS_addr64:
00624       SRVK = MCSymbolRefExpr::VK_TLSGD;
00625       break;
00626     case X86::TLS_base_addr32:
00627       SRVK = MCSymbolRefExpr::VK_TLSLDM;
00628       break;
00629     case X86::TLS_base_addr64:
00630       SRVK = MCSymbolRefExpr::VK_TLSLD;
00631       break;
00632     default:
00633       llvm_unreachable("unexpected opcode");
00634   }
00635 
00636   MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
00637   const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
00638 
00639   MCInst LEA;
00640   if (is64Bits) {
00641     LEA.setOpcode(X86::LEA64r);
00642     LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
00643     LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
00644     LEA.addOperand(MCOperand::CreateImm(1));        // scale
00645     LEA.addOperand(MCOperand::CreateReg(0));        // index
00646     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
00647     LEA.addOperand(MCOperand::CreateReg(0));        // seg
00648   } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
00649     LEA.setOpcode(X86::LEA32r);
00650     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
00651     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
00652     LEA.addOperand(MCOperand::CreateImm(1));        // scale
00653     LEA.addOperand(MCOperand::CreateReg(0));        // index
00654     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
00655     LEA.addOperand(MCOperand::CreateReg(0));        // seg
00656   } else {
00657     LEA.setOpcode(X86::LEA32r);
00658     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
00659     LEA.addOperand(MCOperand::CreateReg(0));        // base
00660     LEA.addOperand(MCOperand::CreateImm(1));        // scale
00661     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
00662     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
00663     LEA.addOperand(MCOperand::CreateReg(0));        // seg
00664   }
00665   OutStreamer.EmitInstruction(LEA, STI);
00666 
00667   if (needsPadding) {
00668     OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI);
00669     OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI);
00670     OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX), STI);
00671   }
00672 
00673   StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
00674   MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
00675   const MCSymbolRefExpr *tlsRef =
00676     MCSymbolRefExpr::Create(tlsGetAddr,
00677                             MCSymbolRefExpr::VK_PLT,
00678                             context);
00679 
00680   OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
00681                                                      : X86::CALLpcrel32)
00682     .addExpr(tlsRef), STI);
00683 }
00684 
00685 /// \brief Emit the optimal amount of multi-byte nops on X86.
00686 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
00687   // This works only for 64bit. For 32bit we have to do additional checking if
00688   // the CPU supports multi-byte nops.
00689   assert(Is64Bit && "EmitNops only supports X86-64");
00690   while (NumBytes) {
00691     unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
00692     Opc = IndexReg = Displacement = SegmentReg = 0;
00693     BaseReg = X86::RAX; ScaleVal = 1;
00694     switch (NumBytes) {
00695     case  0: llvm_unreachable("Zero nops?"); break;
00696     case  1: NumBytes -=  1; Opc = X86::NOOP; break;
00697     case  2: NumBytes -=  2; Opc = X86::XCHG16ar; break;
00698     case  3: NumBytes -=  3; Opc = X86::NOOPL; break;
00699     case  4: NumBytes -=  4; Opc = X86::NOOPL; Displacement = 8; break;
00700     case  5: NumBytes -=  5; Opc = X86::NOOPL; Displacement = 8;
00701              IndexReg = X86::RAX; break;
00702     case  6: NumBytes -=  6; Opc = X86::NOOPW; Displacement = 8;
00703              IndexReg = X86::RAX; break;
00704     case  7: NumBytes -=  7; Opc = X86::NOOPL; Displacement = 512; break;
00705     case  8: NumBytes -=  8; Opc = X86::NOOPL; Displacement = 512;
00706              IndexReg = X86::RAX; break;
00707     case  9: NumBytes -=  9; Opc = X86::NOOPW; Displacement = 512;
00708              IndexReg = X86::RAX; break;
00709     default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
00710              IndexReg = X86::RAX; SegmentReg = X86::CS; break;
00711     }
00712 
00713     unsigned NumPrefixes = std::min(NumBytes, 5U);
00714     NumBytes -= NumPrefixes;
00715     for (unsigned i = 0; i != NumPrefixes; ++i)
00716       OS.EmitBytes("\x66");
00717 
00718     switch (Opc) {
00719     default: llvm_unreachable("Unexpected opcode"); break;
00720     case X86::NOOP:
00721       OS.EmitInstruction(MCInstBuilder(Opc), STI);
00722       break;
00723     case X86::XCHG16ar:
00724       OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
00725       break;
00726     case X86::NOOPL:
00727     case X86::NOOPW:
00728       OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg).addImm(ScaleVal)
00729                                            .addReg(IndexReg)
00730                                            .addImm(Displacement)
00731                                            .addReg(SegmentReg), STI);
00732       break;
00733     }
00734   } // while (NumBytes)
00735 }
00736 
00737 // Lower a stackmap of the form:
00738 // <id>, <shadowBytes>, ...
00739 static void LowerSTACKMAP(MCStreamer &OS, StackMaps &SM,
00740                           const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) {
00741   unsigned NumBytes = MI.getOperand(1).getImm();
00742   SM.recordStackMap(MI);
00743   // Emit padding.
00744   // FIXME: These nops ensure that the stackmap's shadow is covered by
00745   // instructions from the same basic block, but the nops should not be
00746   // necessary if instructions from the same block follow the stackmap.
00747   EmitNops(OS, NumBytes, Is64Bit, STI);
00748 }
00749 
00750 // Lower a patchpoint of the form:
00751 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
00752 static void LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM,
00753                             const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) {
00754   assert(Is64Bit && "Patchpoint currently only supports X86-64");
00755   SM.recordPatchPoint(MI);
00756 
00757   PatchPointOpers opers(&MI);
00758   unsigned ScratchIdx = opers.getNextScratchIdx();
00759   unsigned EncodedBytes = 0;
00760   int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
00761   if (CallTarget) {
00762     // Emit MOV to materialize the target address and the CALL to target.
00763     // This is encoded with 12-13 bytes, depending on which register is used.
00764     unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
00765     if (X86II::isX86_64ExtendedReg(ScratchReg))
00766       EncodedBytes = 13;
00767     else
00768       EncodedBytes = 12;
00769     OS.EmitInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)
00770                                                   .addImm(CallTarget), STI);
00771     OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg), STI);
00772   }
00773   // Emit padding.
00774   unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
00775   assert(NumBytes >= EncodedBytes &&
00776          "Patchpoint can't request size less than the length of a call.");
00777 
00778   EmitNops(OS, NumBytes - EncodedBytes, Is64Bit, STI);
00779 }
00780 
00781 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
00782   X86MCInstLower MCInstLowering(*MF, *this);
00783   const X86RegisterInfo *RI =
00784       static_cast<const X86RegisterInfo *>(TM.getRegisterInfo());
00785 
00786   switch (MI->getOpcode()) {
00787   case TargetOpcode::DBG_VALUE:
00788     llvm_unreachable("Should be handled target independently");
00789 
00790   // Emit nothing here but a comment if we can.
00791   case X86::Int_MemBarrier:
00792     OutStreamer.emitRawComment("MEMBARRIER");
00793     return;
00794 
00795 
00796   case X86::EH_RETURN:
00797   case X86::EH_RETURN64: {
00798     // Lower these as normal, but add some comments.
00799     unsigned Reg = MI->getOperand(0).getReg();
00800     OutStreamer.AddComment(StringRef("eh_return, addr: %") +
00801                            X86ATTInstPrinter::getRegisterName(Reg));
00802     break;
00803   }
00804   case X86::TAILJMPr:
00805   case X86::TAILJMPd:
00806   case X86::TAILJMPd64:
00807     // Lower these as normal, but add some comments.
00808     OutStreamer.AddComment("TAILCALL");
00809     break;
00810 
00811   case X86::TLS_addr32:
00812   case X86::TLS_addr64:
00813   case X86::TLS_base_addr32:
00814   case X86::TLS_base_addr64:
00815     return LowerTlsAddr(OutStreamer, MCInstLowering, *MI, getSubtargetInfo());
00816 
00817   case X86::MOVPC32r: {
00818     // This is a pseudo op for a two instruction sequence with a label, which
00819     // looks like:
00820     //     call "L1$pb"
00821     // "L1$pb":
00822     //     popl %esi
00823 
00824     // Emit the call.
00825     MCSymbol *PICBase = MF->getPICBaseSymbol();
00826     // FIXME: We would like an efficient form for this, so we don't have to do a
00827     // lot of extra uniquing.
00828     EmitToStreamer(OutStreamer, MCInstBuilder(X86::CALLpcrel32)
00829       .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
00830 
00831     // Emit the label.
00832     OutStreamer.EmitLabel(PICBase);
00833 
00834     // popl $reg
00835     EmitToStreamer(OutStreamer, MCInstBuilder(X86::POP32r)
00836       .addReg(MI->getOperand(0).getReg()));
00837     return;
00838   }
00839 
00840   case X86::ADD32ri: {
00841     // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
00842     if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
00843       break;
00844 
00845     // Okay, we have something like:
00846     //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
00847 
00848     // For this, we want to print something like:
00849     //   MYGLOBAL + (. - PICBASE)
00850     // However, we can't generate a ".", so just emit a new label here and refer
00851     // to it.
00852     MCSymbol *DotSym = OutContext.CreateTempSymbol();
00853     OutStreamer.EmitLabel(DotSym);
00854 
00855     // Now that we have emitted the label, lower the complex operand expression.
00856     MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
00857 
00858     const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
00859     const MCExpr *PICBase =
00860       MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
00861     DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
00862 
00863     DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
00864                                       DotExpr, OutContext);
00865 
00866     EmitToStreamer(OutStreamer, MCInstBuilder(X86::ADD32ri)
00867       .addReg(MI->getOperand(0).getReg())
00868       .addReg(MI->getOperand(1).getReg())
00869       .addExpr(DotExpr));
00870     return;
00871   }
00872 
00873   case TargetOpcode::STACKMAP:
00874     return LowerSTACKMAP(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo());
00875 
00876   case TargetOpcode::PATCHPOINT:
00877     return LowerPATCHPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo());
00878 
00879   case X86::MORESTACK_RET:
00880     EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget)));
00881     return;
00882 
00883   case X86::MORESTACK_RET_RESTORE_R10:
00884     // Return, then restore R10.
00885     EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget)));
00886     EmitToStreamer(OutStreamer, MCInstBuilder(X86::MOV64rr)
00887       .addReg(X86::R10)
00888       .addReg(X86::RAX));
00889     return;
00890 
00891   case X86::SEH_PushReg:
00892     OutStreamer.EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
00893     return;
00894 
00895   case X86::SEH_SaveReg:
00896     OutStreamer.EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
00897                                   MI->getOperand(1).getImm());
00898     return;
00899 
00900   case X86::SEH_SaveXMM:
00901     OutStreamer.EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
00902                                   MI->getOperand(1).getImm());
00903     return;
00904 
00905   case X86::SEH_StackAlloc:
00906     OutStreamer.EmitWinCFIAllocStack(MI->getOperand(0).getImm());
00907     return;
00908 
00909   case X86::SEH_SetFrame:
00910     OutStreamer.EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
00911                                    MI->getOperand(1).getImm());
00912     return;
00913 
00914   case X86::SEH_PushFrame:
00915     OutStreamer.EmitWinCFIPushFrame(MI->getOperand(0).getImm());
00916     return;
00917 
00918   case X86::SEH_EndPrologue:
00919     OutStreamer.EmitWinCFIEndProlog();
00920     return;
00921   }
00922 
00923   MCInst TmpInst;
00924   MCInstLowering.Lower(MI, TmpInst);
00925   EmitToStreamer(OutStreamer, TmpInst);
00926 }