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X86MCInstLower.cpp
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00001 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains code to lower X86 MachineInstrs to their corresponding
00011 // MCInst records.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "X86AsmPrinter.h"
00016 #include "X86RegisterInfo.h"
00017 #include "X86ShuffleDecodeConstantPool.h"
00018 #include "InstPrinter/X86ATTInstPrinter.h"
00019 #include "MCTargetDesc/X86BaseInfo.h"
00020 #include "Utils/X86ShuffleDecode.h"
00021 #include "llvm/ADT/Optional.h"
00022 #include "llvm/ADT/SmallString.h"
00023 #include "llvm/CodeGen/MachineFunction.h"
00024 #include "llvm/CodeGen/MachineConstantPool.h"
00025 #include "llvm/CodeGen/MachineOperand.h"
00026 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00027 #include "llvm/CodeGen/StackMaps.h"
00028 #include "llvm/IR/DataLayout.h"
00029 #include "llvm/IR/GlobalValue.h"
00030 #include "llvm/IR/Mangler.h"
00031 #include "llvm/MC/MCAsmInfo.h"
00032 #include "llvm/MC/MCCodeEmitter.h"
00033 #include "llvm/MC/MCContext.h"
00034 #include "llvm/MC/MCExpr.h"
00035 #include "llvm/MC/MCFixup.h"
00036 #include "llvm/MC/MCInst.h"
00037 #include "llvm/MC/MCInstBuilder.h"
00038 #include "llvm/MC/MCStreamer.h"
00039 #include "llvm/MC/MCSymbol.h"
00040 #include "llvm/Support/TargetRegistry.h"
00041 using namespace llvm;
00042 
00043 namespace {
00044 
00045 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
00046 class X86MCInstLower {
00047   MCContext &Ctx;
00048   const MachineFunction &MF;
00049   const TargetMachine &TM;
00050   const MCAsmInfo &MAI;
00051   X86AsmPrinter &AsmPrinter;
00052 public:
00053   X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
00054 
00055   Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
00056                                           const MachineOperand &MO) const;
00057   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
00058 
00059   MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
00060   MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
00061 
00062 private:
00063   MachineModuleInfoMachO &getMachOMMI() const;
00064   Mangler *getMang() const {
00065     return AsmPrinter.Mang;
00066   }
00067 };
00068 
00069 } // end anonymous namespace
00070 
00071 // Emit a minimal sequence of nops spanning NumBytes bytes.
00072 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
00073                      const MCSubtargetInfo &STI);
00074 
00075 namespace llvm {
00076    X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
00077      : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
00078 
00079   X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
00080 
00081   void
00082   X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
00083     MF = &F;
00084     CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
00085         *MF->getSubtarget().getInstrInfo(),
00086         *MF->getSubtarget().getRegisterInfo(), MF->getContext()));
00087   }
00088 
00089   void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
00090                                                    const MCSubtargetInfo &STI) {
00091     if (InShadow) {
00092       SmallString<256> Code;
00093       SmallVector<MCFixup, 4> Fixups;
00094       raw_svector_ostream VecOS(Code);
00095       CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
00096       CurrentShadowSize += Code.size();
00097       if (CurrentShadowSize >= RequiredShadowSize)
00098         InShadow = false; // The shadow is big enough. Stop counting.
00099     }
00100   }
00101 
00102   void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
00103     MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
00104     if (InShadow && CurrentShadowSize < RequiredShadowSize) {
00105       InShadow = false;
00106       EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
00107                MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
00108     }
00109   }
00110 
00111   void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
00112     OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
00113     SMShadowTracker.count(Inst, getSubtargetInfo());
00114   }
00115 } // end llvm namespace
00116 
00117 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
00118                                X86AsmPrinter &asmprinter)
00119     : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
00120       AsmPrinter(asmprinter) {}
00121 
00122 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
00123   return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
00124 }
00125 
00126 
00127 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
00128 /// operand to an MCSymbol.
00129 MCSymbol *X86MCInstLower::
00130 GetSymbolFromOperand(const MachineOperand &MO) const {
00131   const DataLayout &DL = MF.getDataLayout();
00132   assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
00133 
00134   MCSymbol *Sym = nullptr;
00135   SmallString<128> Name;
00136   StringRef Suffix;
00137 
00138   switch (MO.getTargetFlags()) {
00139   case X86II::MO_DLLIMPORT:
00140     // Handle dllimport linkage.
00141     Name += "__imp_";
00142     break;
00143   case X86II::MO_DARWIN_STUB:
00144     Suffix = "$stub";
00145     break;
00146   case X86II::MO_DARWIN_NONLAZY:
00147   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
00148   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
00149     Suffix = "$non_lazy_ptr";
00150     break;
00151   }
00152 
00153   if (!Suffix.empty())
00154     Name += DL.getPrivateGlobalPrefix();
00155 
00156   unsigned PrefixLen = Name.size();
00157 
00158   if (MO.isGlobal()) {
00159     const GlobalValue *GV = MO.getGlobal();
00160     AsmPrinter.getNameWithPrefix(Name, GV);
00161   } else if (MO.isSymbol()) {
00162     Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
00163   } else if (MO.isMBB()) {
00164     assert(Suffix.empty());
00165     Sym = MO.getMBB()->getSymbol();
00166   }
00167   unsigned OrigLen = Name.size() - PrefixLen;
00168 
00169   Name += Suffix;
00170   if (!Sym)
00171     Sym = Ctx.getOrCreateSymbol(Name);
00172 
00173   StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
00174 
00175   // If the target flags on the operand changes the name of the symbol, do that
00176   // before we return the symbol.
00177   switch (MO.getTargetFlags()) {
00178   default: break;
00179   case X86II::MO_DARWIN_NONLAZY:
00180   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
00181     MachineModuleInfoImpl::StubValueTy &StubSym =
00182       getMachOMMI().getGVStubEntry(Sym);
00183     if (!StubSym.getPointer()) {
00184       assert(MO.isGlobal() && "Extern symbol not handled yet");
00185       StubSym =
00186         MachineModuleInfoImpl::
00187         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
00188                     !MO.getGlobal()->hasInternalLinkage());
00189     }
00190     break;
00191   }
00192   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
00193     MachineModuleInfoImpl::StubValueTy &StubSym =
00194       getMachOMMI().getHiddenGVStubEntry(Sym);
00195     if (!StubSym.getPointer()) {
00196       assert(MO.isGlobal() && "Extern symbol not handled yet");
00197       StubSym =
00198         MachineModuleInfoImpl::
00199         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
00200                     !MO.getGlobal()->hasInternalLinkage());
00201     }
00202     break;
00203   }
00204   case X86II::MO_DARWIN_STUB: {
00205     MachineModuleInfoImpl::StubValueTy &StubSym =
00206       getMachOMMI().getFnStubEntry(Sym);
00207     if (StubSym.getPointer())
00208       return Sym;
00209 
00210     if (MO.isGlobal()) {
00211       StubSym =
00212         MachineModuleInfoImpl::
00213         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
00214                     !MO.getGlobal()->hasInternalLinkage());
00215     } else {
00216       StubSym =
00217         MachineModuleInfoImpl::
00218         StubValueTy(Ctx.getOrCreateSymbol(OrigName), false);
00219     }
00220     break;
00221   }
00222   }
00223 
00224   return Sym;
00225 }
00226 
00227 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
00228                                              MCSymbol *Sym) const {
00229   // FIXME: We would like an efficient form for this, so we don't have to do a
00230   // lot of extra uniquing.
00231   const MCExpr *Expr = nullptr;
00232   MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
00233 
00234   switch (MO.getTargetFlags()) {
00235   default: llvm_unreachable("Unknown target flag on GV operand");
00236   case X86II::MO_NO_FLAG:    // No flag.
00237   // These affect the name of the symbol, not any suffix.
00238   case X86II::MO_DARWIN_NONLAZY:
00239   case X86II::MO_DLLIMPORT:
00240   case X86II::MO_DARWIN_STUB:
00241     break;
00242 
00243   case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
00244   case X86II::MO_TLVP_PIC_BASE:
00245     Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
00246     // Subtract the pic base.
00247     Expr = MCBinaryExpr::createSub(Expr,
00248                                   MCSymbolRefExpr::create(MF.getPICBaseSymbol(),
00249                                                            Ctx),
00250                                    Ctx);
00251     break;
00252   case X86II::MO_SECREL:    RefKind = MCSymbolRefExpr::VK_SECREL; break;
00253   case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
00254   case X86II::MO_TLSLD:     RefKind = MCSymbolRefExpr::VK_TLSLD; break;
00255   case X86II::MO_TLSLDM:    RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
00256   case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
00257   case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
00258   case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
00259   case X86II::MO_DTPOFF:    RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
00260   case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
00261   case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
00262   case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
00263   case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
00264   case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
00265   case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
00266   case X86II::MO_PIC_BASE_OFFSET:
00267   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
00268   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
00269     Expr = MCSymbolRefExpr::create(Sym, Ctx);
00270     // Subtract the pic base.
00271     Expr = MCBinaryExpr::createSub(Expr,
00272                             MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx),
00273                                    Ctx);
00274     if (MO.isJTI()) {
00275       assert(MAI.doesSetDirectiveSuppressesReloc());
00276       // If .set directive is supported, use it to reduce the number of
00277       // relocations the assembler will generate for differences between
00278       // local labels. This is only safe when the symbols are in the same
00279       // section so we are restricting it to jumptable references.
00280       MCSymbol *Label = Ctx.createTempSymbol();
00281       AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
00282       Expr = MCSymbolRefExpr::create(Label, Ctx);
00283     }
00284     break;
00285   }
00286 
00287   if (!Expr)
00288     Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
00289 
00290   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
00291     Expr = MCBinaryExpr::createAdd(Expr,
00292                                    MCConstantExpr::create(MO.getOffset(), Ctx),
00293                                    Ctx);
00294   return MCOperand::createExpr(Expr);
00295 }
00296 
00297 
00298 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
00299 /// a short fixed-register form.
00300 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
00301   unsigned ImmOp = Inst.getNumOperands() - 1;
00302   assert(Inst.getOperand(0).isReg() &&
00303          (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
00304          ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
00305            Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
00306           Inst.getNumOperands() == 2) && "Unexpected instruction!");
00307 
00308   // Check whether the destination register can be fixed.
00309   unsigned Reg = Inst.getOperand(0).getReg();
00310   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
00311     return;
00312 
00313   // If so, rewrite the instruction.
00314   MCOperand Saved = Inst.getOperand(ImmOp);
00315   Inst = MCInst();
00316   Inst.setOpcode(Opcode);
00317   Inst.addOperand(Saved);
00318 }
00319 
00320 /// \brief If a movsx instruction has a shorter encoding for the used register
00321 /// simplify the instruction to use it instead.
00322 static void SimplifyMOVSX(MCInst &Inst) {
00323   unsigned NewOpcode = 0;
00324   unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
00325   switch (Inst.getOpcode()) {
00326   default:
00327     llvm_unreachable("Unexpected instruction!");
00328   case X86::MOVSX16rr8:  // movsbw %al, %ax   --> cbtw
00329     if (Op0 == X86::AX && Op1 == X86::AL)
00330       NewOpcode = X86::CBW;
00331     break;
00332   case X86::MOVSX32rr16: // movswl %ax, %eax  --> cwtl
00333     if (Op0 == X86::EAX && Op1 == X86::AX)
00334       NewOpcode = X86::CWDE;
00335     break;
00336   case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
00337     if (Op0 == X86::RAX && Op1 == X86::EAX)
00338       NewOpcode = X86::CDQE;
00339     break;
00340   }
00341 
00342   if (NewOpcode != 0) {
00343     Inst = MCInst();
00344     Inst.setOpcode(NewOpcode);
00345   }
00346 }
00347 
00348 /// \brief Simplify things like MOV32rm to MOV32o32a.
00349 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
00350                                   unsigned Opcode) {
00351   // Don't make these simplifications in 64-bit mode; other assemblers don't
00352   // perform them because they make the code larger.
00353   if (Printer.getSubtarget().is64Bit())
00354     return;
00355 
00356   bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
00357   unsigned AddrBase = IsStore;
00358   unsigned RegOp = IsStore ? 0 : 5;
00359   unsigned AddrOp = AddrBase + 3;
00360   assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
00361          Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
00362          Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
00363          Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
00364          Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
00365          (Inst.getOperand(AddrOp).isExpr() ||
00366           Inst.getOperand(AddrOp).isImm()) &&
00367          "Unexpected instruction!");
00368 
00369   // Check whether the destination register can be fixed.
00370   unsigned Reg = Inst.getOperand(RegOp).getReg();
00371   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
00372     return;
00373 
00374   // Check whether this is an absolute address.
00375   // FIXME: We know TLVP symbol refs aren't, but there should be a better way
00376   // to do this here.
00377   bool Absolute = true;
00378   if (Inst.getOperand(AddrOp).isExpr()) {
00379     const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
00380     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
00381       if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
00382         Absolute = false;
00383   }
00384 
00385   if (Absolute &&
00386       (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
00387        Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
00388        Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
00389     return;
00390 
00391   // If so, rewrite the instruction.
00392   MCOperand Saved = Inst.getOperand(AddrOp);
00393   MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
00394   Inst = MCInst();
00395   Inst.setOpcode(Opcode);
00396   Inst.addOperand(Saved);
00397   Inst.addOperand(Seg);
00398 }
00399 
00400 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
00401   return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
00402 }
00403 
00404 Optional<MCOperand>
00405 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
00406                                     const MachineOperand &MO) const {
00407   switch (MO.getType()) {
00408   default:
00409     MI->dump();
00410     llvm_unreachable("unknown operand type");
00411   case MachineOperand::MO_Register:
00412     // Ignore all implicit register operands.
00413     if (MO.isImplicit())
00414       return None;
00415     return MCOperand::createReg(MO.getReg());
00416   case MachineOperand::MO_Immediate:
00417     return MCOperand::createImm(MO.getImm());
00418   case MachineOperand::MO_MachineBasicBlock:
00419   case MachineOperand::MO_GlobalAddress:
00420   case MachineOperand::MO_ExternalSymbol:
00421     return LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
00422   case MachineOperand::MO_MCSymbol:
00423     return LowerSymbolOperand(MO, MO.getMCSymbol());
00424   case MachineOperand::MO_JumpTableIndex:
00425     return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
00426   case MachineOperand::MO_ConstantPoolIndex:
00427     return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
00428   case MachineOperand::MO_BlockAddress:
00429     return LowerSymbolOperand(
00430         MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
00431   case MachineOperand::MO_RegisterMask:
00432     // Ignore call clobbers.
00433     return None;
00434   }
00435 }
00436 
00437 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
00438   OutMI.setOpcode(MI->getOpcode());
00439 
00440   for (const MachineOperand &MO : MI->operands())
00441     if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
00442       OutMI.addOperand(MaybeMCOp.getValue());
00443 
00444   // Handle a few special cases to eliminate operand modifiers.
00445 ReSimplify:
00446   switch (OutMI.getOpcode()) {
00447   case X86::LEA64_32r:
00448   case X86::LEA64r:
00449   case X86::LEA16r:
00450   case X86::LEA32r:
00451     // LEA should have a segment register, but it must be empty.
00452     assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
00453            "Unexpected # of LEA operands");
00454     assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
00455            "LEA has segment specified!");
00456     break;
00457 
00458   // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
00459   // if one of the registers is extended, but other isn't.
00460   case X86::VMOVZPQILo2PQIrr:
00461   case X86::VMOVAPDrr:
00462   case X86::VMOVAPDYrr:
00463   case X86::VMOVAPSrr:
00464   case X86::VMOVAPSYrr:
00465   case X86::VMOVDQArr:
00466   case X86::VMOVDQAYrr:
00467   case X86::VMOVDQUrr:
00468   case X86::VMOVDQUYrr:
00469   case X86::VMOVUPDrr:
00470   case X86::VMOVUPDYrr:
00471   case X86::VMOVUPSrr:
00472   case X86::VMOVUPSYrr: {
00473     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
00474         X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
00475       unsigned NewOpc;
00476       switch (OutMI.getOpcode()) {
00477       default: llvm_unreachable("Invalid opcode");
00478       case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr;   break;
00479       case X86::VMOVAPDrr:        NewOpc = X86::VMOVAPDrr_REV;  break;
00480       case X86::VMOVAPDYrr:       NewOpc = X86::VMOVAPDYrr_REV; break;
00481       case X86::VMOVAPSrr:        NewOpc = X86::VMOVAPSrr_REV;  break;
00482       case X86::VMOVAPSYrr:       NewOpc = X86::VMOVAPSYrr_REV; break;
00483       case X86::VMOVDQArr:        NewOpc = X86::VMOVDQArr_REV;  break;
00484       case X86::VMOVDQAYrr:       NewOpc = X86::VMOVDQAYrr_REV; break;
00485       case X86::VMOVDQUrr:        NewOpc = X86::VMOVDQUrr_REV;  break;
00486       case X86::VMOVDQUYrr:       NewOpc = X86::VMOVDQUYrr_REV; break;
00487       case X86::VMOVUPDrr:        NewOpc = X86::VMOVUPDrr_REV;  break;
00488       case X86::VMOVUPDYrr:       NewOpc = X86::VMOVUPDYrr_REV; break;
00489       case X86::VMOVUPSrr:        NewOpc = X86::VMOVUPSrr_REV;  break;
00490       case X86::VMOVUPSYrr:       NewOpc = X86::VMOVUPSYrr_REV; break;
00491       }
00492       OutMI.setOpcode(NewOpc);
00493     }
00494     break;
00495   }
00496   case X86::VMOVSDrr:
00497   case X86::VMOVSSrr: {
00498     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
00499         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
00500       unsigned NewOpc;
00501       switch (OutMI.getOpcode()) {
00502       default: llvm_unreachable("Invalid opcode");
00503       case X86::VMOVSDrr:   NewOpc = X86::VMOVSDrr_REV;   break;
00504       case X86::VMOVSSrr:   NewOpc = X86::VMOVSSrr_REV;   break;
00505       }
00506       OutMI.setOpcode(NewOpc);
00507     }
00508     break;
00509   }
00510 
00511   // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
00512   // inputs modeled as normal uses instead of implicit uses.  As such, truncate
00513   // off all but the first operand (the callee).  FIXME: Change isel.
00514   case X86::TAILJMPr64:
00515   case X86::TAILJMPr64_REX:
00516   case X86::CALL64r:
00517   case X86::CALL64pcrel32: {
00518     unsigned Opcode = OutMI.getOpcode();
00519     MCOperand Saved = OutMI.getOperand(0);
00520     OutMI = MCInst();
00521     OutMI.setOpcode(Opcode);
00522     OutMI.addOperand(Saved);
00523     break;
00524   }
00525 
00526   case X86::EH_RETURN:
00527   case X86::EH_RETURN64: {
00528     OutMI = MCInst();
00529     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
00530     break;
00531   }
00532 
00533   case X86::CLEANUPRET: {
00534     // Replace CATCHRET with the appropriate RET.
00535     OutMI = MCInst();
00536     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
00537     break;
00538   }
00539 
00540   case X86::CATCHRET: {
00541     // Replace CATCHRET with the appropriate RET.
00542     const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
00543     unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
00544     OutMI = MCInst();
00545     OutMI.setOpcode(getRetOpcode(Subtarget));
00546     OutMI.addOperand(MCOperand::createReg(ReturnReg));
00547     break;
00548   }
00549 
00550   // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
00551   case X86::TAILJMPr:
00552   case X86::TAILJMPd:
00553   case X86::TAILJMPd64: {
00554     unsigned Opcode;
00555     switch (OutMI.getOpcode()) {
00556     default: llvm_unreachable("Invalid opcode");
00557     case X86::TAILJMPr: Opcode = X86::JMP32r; break;
00558     case X86::TAILJMPd:
00559     case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
00560     }
00561 
00562     MCOperand Saved = OutMI.getOperand(0);
00563     OutMI = MCInst();
00564     OutMI.setOpcode(Opcode);
00565     OutMI.addOperand(Saved);
00566     break;
00567   }
00568 
00569   case X86::DEC16r:
00570   case X86::DEC32r:
00571   case X86::INC16r:
00572   case X86::INC32r:
00573     // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
00574     if (!AsmPrinter.getSubtarget().is64Bit()) {
00575       unsigned Opcode;
00576       switch (OutMI.getOpcode()) {
00577       default: llvm_unreachable("Invalid opcode");
00578       case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
00579       case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
00580       case X86::INC16r: Opcode = X86::INC16r_alt; break;
00581       case X86::INC32r: Opcode = X86::INC32r_alt; break;
00582       }
00583       OutMI.setOpcode(Opcode);
00584     }
00585     break;
00586 
00587   // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
00588   // this with an ugly goto in case the resultant OR uses EAX and needs the
00589   // short form.
00590   case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
00591   case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
00592   case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
00593   case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
00594   case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
00595   case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
00596   case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
00597   case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
00598   case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
00599 
00600   // Atomic load and store require a separate pseudo-inst because Acquire
00601   // implies mayStore and Release implies mayLoad; fix these to regular MOV
00602   // instructions here
00603   case X86::ACQUIRE_MOV8rm:    OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
00604   case X86::ACQUIRE_MOV16rm:   OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
00605   case X86::ACQUIRE_MOV32rm:   OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
00606   case X86::ACQUIRE_MOV64rm:   OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
00607   case X86::RELEASE_MOV8mr:    OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
00608   case X86::RELEASE_MOV16mr:   OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
00609   case X86::RELEASE_MOV32mr:   OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
00610   case X86::RELEASE_MOV64mr:   OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
00611   case X86::RELEASE_MOV8mi:    OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
00612   case X86::RELEASE_MOV16mi:   OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
00613   case X86::RELEASE_MOV32mi:   OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
00614   case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
00615   case X86::RELEASE_ADD8mi:    OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
00616   case X86::RELEASE_ADD8mr:    OutMI.setOpcode(X86::ADD8mr); goto ReSimplify;
00617   case X86::RELEASE_ADD32mi:   OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
00618   case X86::RELEASE_ADD32mr:   OutMI.setOpcode(X86::ADD32mr); goto ReSimplify;
00619   case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
00620   case X86::RELEASE_ADD64mr:   OutMI.setOpcode(X86::ADD64mr); goto ReSimplify;
00621   case X86::RELEASE_AND8mi:    OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
00622   case X86::RELEASE_AND8mr:    OutMI.setOpcode(X86::AND8mr); goto ReSimplify;
00623   case X86::RELEASE_AND32mi:   OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
00624   case X86::RELEASE_AND32mr:   OutMI.setOpcode(X86::AND32mr); goto ReSimplify;
00625   case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
00626   case X86::RELEASE_AND64mr:   OutMI.setOpcode(X86::AND64mr); goto ReSimplify;
00627   case X86::RELEASE_OR8mi:     OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
00628   case X86::RELEASE_OR8mr:     OutMI.setOpcode(X86::OR8mr); goto ReSimplify;
00629   case X86::RELEASE_OR32mi:    OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
00630   case X86::RELEASE_OR32mr:    OutMI.setOpcode(X86::OR32mr); goto ReSimplify;
00631   case X86::RELEASE_OR64mi32:  OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
00632   case X86::RELEASE_OR64mr:    OutMI.setOpcode(X86::OR64mr); goto ReSimplify;
00633   case X86::RELEASE_XOR8mi:    OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
00634   case X86::RELEASE_XOR8mr:    OutMI.setOpcode(X86::XOR8mr); goto ReSimplify;
00635   case X86::RELEASE_XOR32mi:   OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
00636   case X86::RELEASE_XOR32mr:   OutMI.setOpcode(X86::XOR32mr); goto ReSimplify;
00637   case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
00638   case X86::RELEASE_XOR64mr:   OutMI.setOpcode(X86::XOR64mr); goto ReSimplify;
00639   case X86::RELEASE_INC8m:     OutMI.setOpcode(X86::INC8m); goto ReSimplify;
00640   case X86::RELEASE_INC16m:    OutMI.setOpcode(X86::INC16m); goto ReSimplify;
00641   case X86::RELEASE_INC32m:    OutMI.setOpcode(X86::INC32m); goto ReSimplify;
00642   case X86::RELEASE_INC64m:    OutMI.setOpcode(X86::INC64m); goto ReSimplify;
00643   case X86::RELEASE_DEC8m:     OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
00644   case X86::RELEASE_DEC16m:    OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
00645   case X86::RELEASE_DEC32m:    OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
00646   case X86::RELEASE_DEC64m:    OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
00647 
00648   // We don't currently select the correct instruction form for instructions
00649   // which have a short %eax, etc. form. Handle this by custom lowering, for
00650   // now.
00651   //
00652   // Note, we are currently not handling the following instructions:
00653   // MOV64ao8, MOV64o8a
00654   // XCHG16ar, XCHG32ar, XCHG64ar
00655   case X86::MOV8mr_NOREX:
00656   case X86::MOV8mr:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o32a); break;
00657   case X86::MOV8rm_NOREX:
00658   case X86::MOV8rm:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao32); break;
00659   case X86::MOV16mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o32a); break;
00660   case X86::MOV16rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao32); break;
00661   case X86::MOV32mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
00662   case X86::MOV32rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
00663 
00664   case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
00665   case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
00666   case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
00667   case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
00668   case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
00669   case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
00670   case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
00671   case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
00672   case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
00673   case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
00674   case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
00675   case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
00676   case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
00677   case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
00678   case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
00679   case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
00680   case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
00681   case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
00682   case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
00683   case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
00684   case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
00685   case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
00686   case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
00687   case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
00688   case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
00689   case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
00690   case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
00691   case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
00692   case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
00693   case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
00694   case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
00695   case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
00696   case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
00697   case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
00698   case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
00699   case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
00700 
00701   // Try to shrink some forms of movsx.
00702   case X86::MOVSX16rr8:
00703   case X86::MOVSX32rr16:
00704   case X86::MOVSX64rr32:
00705     SimplifyMOVSX(OutMI);
00706     break;
00707   }
00708 }
00709 
00710 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
00711                                  const MachineInstr &MI) {
00712 
00713   bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
00714                   MI.getOpcode() == X86::TLS_base_addr64;
00715 
00716   bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
00717 
00718   MCContext &context = OutStreamer->getContext();
00719 
00720   if (needsPadding)
00721     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
00722 
00723   MCSymbolRefExpr::VariantKind SRVK;
00724   switch (MI.getOpcode()) {
00725     case X86::TLS_addr32:
00726     case X86::TLS_addr64:
00727       SRVK = MCSymbolRefExpr::VK_TLSGD;
00728       break;
00729     case X86::TLS_base_addr32:
00730       SRVK = MCSymbolRefExpr::VK_TLSLDM;
00731       break;
00732     case X86::TLS_base_addr64:
00733       SRVK = MCSymbolRefExpr::VK_TLSLD;
00734       break;
00735     default:
00736       llvm_unreachable("unexpected opcode");
00737   }
00738 
00739   MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
00740   const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
00741 
00742   MCInst LEA;
00743   if (is64Bits) {
00744     LEA.setOpcode(X86::LEA64r);
00745     LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
00746     LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
00747     LEA.addOperand(MCOperand::createImm(1));        // scale
00748     LEA.addOperand(MCOperand::createReg(0));        // index
00749     LEA.addOperand(MCOperand::createExpr(symRef));  // disp
00750     LEA.addOperand(MCOperand::createReg(0));        // seg
00751   } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
00752     LEA.setOpcode(X86::LEA32r);
00753     LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
00754     LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
00755     LEA.addOperand(MCOperand::createImm(1));        // scale
00756     LEA.addOperand(MCOperand::createReg(0));        // index
00757     LEA.addOperand(MCOperand::createExpr(symRef));  // disp
00758     LEA.addOperand(MCOperand::createReg(0));        // seg
00759   } else {
00760     LEA.setOpcode(X86::LEA32r);
00761     LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
00762     LEA.addOperand(MCOperand::createReg(0));        // base
00763     LEA.addOperand(MCOperand::createImm(1));        // scale
00764     LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
00765     LEA.addOperand(MCOperand::createExpr(symRef));  // disp
00766     LEA.addOperand(MCOperand::createReg(0));        // seg
00767   }
00768   EmitAndCountInstruction(LEA);
00769 
00770   if (needsPadding) {
00771     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
00772     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
00773     EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
00774   }
00775 
00776   StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
00777   MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
00778   const MCSymbolRefExpr *tlsRef =
00779     MCSymbolRefExpr::create(tlsGetAddr,
00780                             MCSymbolRefExpr::VK_PLT,
00781                             context);
00782 
00783   EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
00784                                                  : X86::CALLpcrel32)
00785                             .addExpr(tlsRef));
00786 }
00787 
00788 /// \brief Emit the optimal amount of multi-byte nops on X86.
00789 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
00790   // This works only for 64bit. For 32bit we have to do additional checking if
00791   // the CPU supports multi-byte nops.
00792   assert(Is64Bit && "EmitNops only supports X86-64");
00793   while (NumBytes) {
00794     unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
00795     Opc = IndexReg = Displacement = SegmentReg = 0;
00796     BaseReg = X86::RAX; ScaleVal = 1;
00797     switch (NumBytes) {
00798     case  0: llvm_unreachable("Zero nops?"); break;
00799     case  1: NumBytes -=  1; Opc = X86::NOOP; break;
00800     case  2: NumBytes -=  2; Opc = X86::XCHG16ar; break;
00801     case  3: NumBytes -=  3; Opc = X86::NOOPL; break;
00802     case  4: NumBytes -=  4; Opc = X86::NOOPL; Displacement = 8; break;
00803     case  5: NumBytes -=  5; Opc = X86::NOOPL; Displacement = 8;
00804              IndexReg = X86::RAX; break;
00805     case  6: NumBytes -=  6; Opc = X86::NOOPW; Displacement = 8;
00806              IndexReg = X86::RAX; break;
00807     case  7: NumBytes -=  7; Opc = X86::NOOPL; Displacement = 512; break;
00808     case  8: NumBytes -=  8; Opc = X86::NOOPL; Displacement = 512;
00809              IndexReg = X86::RAX; break;
00810     case  9: NumBytes -=  9; Opc = X86::NOOPW; Displacement = 512;
00811              IndexReg = X86::RAX; break;
00812     default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
00813              IndexReg = X86::RAX; SegmentReg = X86::CS; break;
00814     }
00815 
00816     unsigned NumPrefixes = std::min(NumBytes, 5U);
00817     NumBytes -= NumPrefixes;
00818     for (unsigned i = 0; i != NumPrefixes; ++i)
00819       OS.EmitBytes("\x66");
00820 
00821     switch (Opc) {
00822     default: llvm_unreachable("Unexpected opcode"); break;
00823     case X86::NOOP:
00824       OS.EmitInstruction(MCInstBuilder(Opc), STI);
00825       break;
00826     case X86::XCHG16ar:
00827       OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
00828       break;
00829     case X86::NOOPL:
00830     case X86::NOOPW:
00831       OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
00832                          .addImm(ScaleVal).addReg(IndexReg)
00833                          .addImm(Displacement).addReg(SegmentReg), STI);
00834       break;
00835     }
00836   } // while (NumBytes)
00837 }
00838 
00839 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
00840                                     X86MCInstLower &MCIL) {
00841   assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
00842 
00843   StatepointOpers SOpers(&MI);
00844   if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
00845     EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
00846              getSubtargetInfo());
00847   } else {
00848     // Lower call target and choose correct opcode
00849     const MachineOperand &CallTarget = SOpers.getCallTarget();
00850     MCOperand CallTargetMCOp;
00851     unsigned CallOpcode;
00852     switch (CallTarget.getType()) {
00853     case MachineOperand::MO_GlobalAddress:
00854     case MachineOperand::MO_ExternalSymbol:
00855       CallTargetMCOp = MCIL.LowerSymbolOperand(
00856           CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
00857       CallOpcode = X86::CALL64pcrel32;
00858       // Currently, we only support relative addressing with statepoints.
00859       // Otherwise, we'll need a scratch register to hold the target
00860       // address.  You'll fail asserts during load & relocation if this
00861       // symbol is to far away. (TODO: support non-relative addressing)
00862       break;
00863     case MachineOperand::MO_Immediate:
00864       CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
00865       CallOpcode = X86::CALL64pcrel32;
00866       // Currently, we only support relative addressing with statepoints.
00867       // Otherwise, we'll need a scratch register to hold the target
00868       // immediate.  You'll fail asserts during load & relocation if this
00869       // address is to far away. (TODO: support non-relative addressing)
00870       break;
00871     case MachineOperand::MO_Register:
00872       CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
00873       CallOpcode = X86::CALL64r;
00874       break;
00875     default:
00876       llvm_unreachable("Unsupported operand type in statepoint call target");
00877       break;
00878     }
00879 
00880     // Emit call
00881     MCInst CallInst;
00882     CallInst.setOpcode(CallOpcode);
00883     CallInst.addOperand(CallTargetMCOp);
00884     OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
00885   }
00886 
00887   // Record our statepoint node in the same section used by STACKMAP
00888   // and PATCHPOINT
00889   SM.recordStatepoint(MI);
00890 }
00891 
00892 void X86AsmPrinter::LowerFAULTING_LOAD_OP(const MachineInstr &MI,
00893                                        X86MCInstLower &MCIL) {
00894   // FAULTING_LOAD_OP <def>, <handler label>, <load opcode>, <load operands>
00895 
00896   unsigned LoadDefRegister = MI.getOperand(0).getReg();
00897   MCSymbol *HandlerLabel = MI.getOperand(1).getMCSymbol();
00898   unsigned LoadOpcode = MI.getOperand(2).getImm();
00899   unsigned LoadOperandsBeginIdx = 3;
00900 
00901   FM.recordFaultingOp(FaultMaps::FaultingLoad, HandlerLabel);
00902 
00903   MCInst LoadMI;
00904   LoadMI.setOpcode(LoadOpcode);
00905 
00906   if (LoadDefRegister != X86::NoRegister)
00907     LoadMI.addOperand(MCOperand::createReg(LoadDefRegister));
00908 
00909   for (auto I = MI.operands_begin() + LoadOperandsBeginIdx,
00910             E = MI.operands_end();
00911        I != E; ++I)
00912     if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, *I))
00913       LoadMI.addOperand(MaybeOperand.getValue());
00914 
00915   OutStreamer->EmitInstruction(LoadMI, getSubtargetInfo());
00916 }
00917 
00918 // Lower a stackmap of the form:
00919 // <id>, <shadowBytes>, ...
00920 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
00921   SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
00922   SM.recordStackMap(MI);
00923   unsigned NumShadowBytes = MI.getOperand(1).getImm();
00924   SMShadowTracker.reset(NumShadowBytes);
00925 }
00926 
00927 // Lower a patchpoint of the form:
00928 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
00929 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
00930                                     X86MCInstLower &MCIL) {
00931   assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
00932 
00933   SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
00934 
00935   SM.recordPatchPoint(MI);
00936 
00937   PatchPointOpers opers(&MI);
00938   unsigned ScratchIdx = opers.getNextScratchIdx();
00939   unsigned EncodedBytes = 0;
00940   const MachineOperand &CalleeMO =
00941     opers.getMetaOper(PatchPointOpers::TargetPos);
00942 
00943   // Check for null target. If target is non-null (i.e. is non-zero or is
00944   // symbolic) then emit a call.
00945   if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
00946     MCOperand CalleeMCOp;
00947     switch (CalleeMO.getType()) {
00948     default:
00949       /// FIXME: Add a verifier check for bad callee types.
00950       llvm_unreachable("Unrecognized callee operand type.");
00951     case MachineOperand::MO_Immediate:
00952       if (CalleeMO.getImm())
00953         CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
00954       break;
00955     case MachineOperand::MO_ExternalSymbol:
00956     case MachineOperand::MO_GlobalAddress:
00957       CalleeMCOp =
00958         MCIL.LowerSymbolOperand(CalleeMO,
00959                                 MCIL.GetSymbolFromOperand(CalleeMO));
00960       break;
00961     }
00962 
00963     // Emit MOV to materialize the target address and the CALL to target.
00964     // This is encoded with 12-13 bytes, depending on which register is used.
00965     unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
00966     if (X86II::isX86_64ExtendedReg(ScratchReg))
00967       EncodedBytes = 13;
00968     else
00969       EncodedBytes = 12;
00970 
00971     EmitAndCountInstruction(
00972         MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
00973     EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
00974   }
00975 
00976   // Emit padding.
00977   unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
00978   assert(NumBytes >= EncodedBytes &&
00979          "Patchpoint can't request size less than the length of a call.");
00980 
00981   EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
00982            getSubtargetInfo());
00983 }
00984 
00985 // Returns instruction preceding MBBI in MachineFunction.
00986 // If MBBI is the first instruction of the first basic block, returns null.
00987 static MachineBasicBlock::const_iterator
00988 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
00989   const MachineBasicBlock *MBB = MBBI->getParent();
00990   while (MBBI == MBB->begin()) {
00991     if (MBB == MBB->getParent()->begin())
00992       return nullptr;
00993     MBB = MBB->getPrevNode();
00994     MBBI = MBB->end();
00995   }
00996   return --MBBI;
00997 }
00998 
00999 static const Constant *getConstantFromPool(const MachineInstr &MI,
01000                                            const MachineOperand &Op) {
01001   if (!Op.isCPI())
01002     return nullptr;
01003 
01004   ArrayRef<MachineConstantPoolEntry> Constants =
01005       MI.getParent()->getParent()->getConstantPool()->getConstants();
01006   const MachineConstantPoolEntry &ConstantEntry =
01007       Constants[Op.getIndex()];
01008 
01009   // Bail if this is a machine constant pool entry, we won't be able to dig out
01010   // anything useful.
01011   if (ConstantEntry.isMachineConstantPoolEntry())
01012     return nullptr;
01013 
01014   auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
01015   assert((!C || ConstantEntry.getType() == C->getType()) &&
01016          "Expected a constant of the same type!");
01017   return C;
01018 }
01019 
01020 static std::string getShuffleComment(const MachineOperand &DstOp,
01021                                      const MachineOperand &SrcOp,
01022                                      ArrayRef<int> Mask) {
01023   std::string Comment;
01024 
01025   // Compute the name for a register. This is really goofy because we have
01026   // multiple instruction printers that could (in theory) use different
01027   // names. Fortunately most people use the ATT style (outside of Windows)
01028   // and they actually agree on register naming here. Ultimately, this is
01029   // a comment, and so its OK if it isn't perfect.
01030   auto GetRegisterName = [](unsigned RegNum) -> StringRef {
01031     return X86ATTInstPrinter::getRegisterName(RegNum);
01032   };
01033 
01034   StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
01035   StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
01036 
01037   raw_string_ostream CS(Comment);
01038   CS << DstName << " = ";
01039   bool NeedComma = false;
01040   bool InSrc = false;
01041   for (int M : Mask) {
01042     // Wrap up any prior entry...
01043     if (M == SM_SentinelZero && InSrc) {
01044       InSrc = false;
01045       CS << "]";
01046     }
01047     if (NeedComma)
01048       CS << ",";
01049     else
01050       NeedComma = true;
01051 
01052     // Print this shuffle...
01053     if (M == SM_SentinelZero) {
01054       CS << "zero";
01055     } else {
01056       if (!InSrc) {
01057         InSrc = true;
01058         CS << SrcName << "[";
01059       }
01060       if (M == SM_SentinelUndef)
01061         CS << "u";
01062       else
01063         CS << M;
01064     }
01065   }
01066   if (InSrc)
01067     CS << "]";
01068   CS.flush();
01069 
01070   return Comment;
01071 }
01072 
01073 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
01074   X86MCInstLower MCInstLowering(*MF, *this);
01075   const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
01076 
01077   switch (MI->getOpcode()) {
01078   case TargetOpcode::DBG_VALUE:
01079     llvm_unreachable("Should be handled target independently");
01080 
01081   // Emit nothing here but a comment if we can.
01082   case X86::Int_MemBarrier:
01083     OutStreamer->emitRawComment("MEMBARRIER");
01084     return;
01085 
01086 
01087   case X86::EH_RETURN:
01088   case X86::EH_RETURN64: {
01089     // Lower these as normal, but add some comments.
01090     unsigned Reg = MI->getOperand(0).getReg();
01091     OutStreamer->AddComment(StringRef("eh_return, addr: %") +
01092                             X86ATTInstPrinter::getRegisterName(Reg));
01093     break;
01094   }
01095   case X86::CLEANUPRET: {
01096     // Lower these as normal, but add some comments.
01097     OutStreamer->AddComment("CLEANUPRET");
01098     break;
01099   }
01100 
01101   case X86::CATCHRET: {
01102     // Lower these as normal, but add some comments.
01103     OutStreamer->AddComment("CATCHRET");
01104     break;
01105   }
01106 
01107   case X86::TAILJMPr:
01108   case X86::TAILJMPm:
01109   case X86::TAILJMPd:
01110   case X86::TAILJMPr64:
01111   case X86::TAILJMPm64:
01112   case X86::TAILJMPd64:
01113   case X86::TAILJMPr64_REX:
01114   case X86::TAILJMPm64_REX:
01115   case X86::TAILJMPd64_REX:
01116     // Lower these as normal, but add some comments.
01117     OutStreamer->AddComment("TAILCALL");
01118     break;
01119 
01120   case X86::TLS_addr32:
01121   case X86::TLS_addr64:
01122   case X86::TLS_base_addr32:
01123   case X86::TLS_base_addr64:
01124     return LowerTlsAddr(MCInstLowering, *MI);
01125 
01126   case X86::MOVPC32r: {
01127     // This is a pseudo op for a two instruction sequence with a label, which
01128     // looks like:
01129     //     call "L1$pb"
01130     // "L1$pb":
01131     //     popl %esi
01132 
01133     // Emit the call.
01134     MCSymbol *PICBase = MF->getPICBaseSymbol();
01135     // FIXME: We would like an efficient form for this, so we don't have to do a
01136     // lot of extra uniquing.
01137     EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
01138       .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
01139 
01140     const X86FrameLowering* FrameLowering =
01141         MF->getSubtarget<X86Subtarget>().getFrameLowering();
01142     bool hasFP = FrameLowering->hasFP(*MF);
01143     
01144     // TODO: This is needed only if we require precise CFA.
01145     bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
01146                                !OutStreamer->getDwarfFrameInfos().back().End;
01147 
01148     int stackGrowth = -RI->getSlotSize();
01149 
01150     if (HasActiveDwarfFrame && !hasFP) {
01151       OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth);
01152     }
01153 
01154     // Emit the label.
01155     OutStreamer->EmitLabel(PICBase);
01156 
01157     // popl $reg
01158     EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
01159                             .addReg(MI->getOperand(0).getReg()));
01160 
01161     if (HasActiveDwarfFrame && !hasFP) {
01162       OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth);
01163     }
01164     return;
01165   }
01166 
01167   case X86::ADD32ri: {
01168     // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
01169     if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
01170       break;
01171 
01172     // Okay, we have something like:
01173     //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
01174 
01175     // For this, we want to print something like:
01176     //   MYGLOBAL + (. - PICBASE)
01177     // However, we can't generate a ".", so just emit a new label here and refer
01178     // to it.
01179     MCSymbol *DotSym = OutContext.createTempSymbol();
01180     OutStreamer->EmitLabel(DotSym);
01181 
01182     // Now that we have emitted the label, lower the complex operand expression.
01183     MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
01184 
01185     const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
01186     const MCExpr *PICBase =
01187       MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext);
01188     DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
01189 
01190     DotExpr = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(OpSym,OutContext),
01191                                       DotExpr, OutContext);
01192 
01193     EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
01194       .addReg(MI->getOperand(0).getReg())
01195       .addReg(MI->getOperand(1).getReg())
01196       .addExpr(DotExpr));
01197     return;
01198   }
01199   case TargetOpcode::STATEPOINT:
01200     return LowerSTATEPOINT(*MI, MCInstLowering);
01201 
01202   case TargetOpcode::FAULTING_LOAD_OP:
01203     return LowerFAULTING_LOAD_OP(*MI, MCInstLowering);
01204 
01205   case TargetOpcode::STACKMAP:
01206     return LowerSTACKMAP(*MI);
01207 
01208   case TargetOpcode::PATCHPOINT:
01209     return LowerPATCHPOINT(*MI, MCInstLowering);
01210 
01211   case X86::MORESTACK_RET:
01212     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
01213     return;
01214 
01215   case X86::MORESTACK_RET_RESTORE_R10:
01216     // Return, then restore R10.
01217     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
01218     EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
01219                             .addReg(X86::R10)
01220                             .addReg(X86::RAX));
01221     return;
01222 
01223   case X86::SEH_PushReg:
01224     OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
01225     return;
01226 
01227   case X86::SEH_SaveReg:
01228     OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
01229                                    MI->getOperand(1).getImm());
01230     return;
01231 
01232   case X86::SEH_SaveXMM:
01233     OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
01234                                    MI->getOperand(1).getImm());
01235     return;
01236 
01237   case X86::SEH_StackAlloc:
01238     OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
01239     return;
01240 
01241   case X86::SEH_SetFrame:
01242     OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
01243                                     MI->getOperand(1).getImm());
01244     return;
01245 
01246   case X86::SEH_PushFrame:
01247     OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
01248     return;
01249 
01250   case X86::SEH_EndPrologue:
01251     OutStreamer->EmitWinCFIEndProlog();
01252     return;
01253 
01254   case X86::SEH_Epilogue: {
01255     MachineBasicBlock::const_iterator MBBI(MI);
01256     // Check if preceded by a call and emit nop if so.
01257     for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
01258       // Conservatively assume that pseudo instructions don't emit code and keep
01259       // looking for a call. We may emit an unnecessary nop in some cases.
01260       if (!MBBI->isPseudo()) {
01261         if (MBBI->isCall())
01262           EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
01263         break;
01264       }
01265     }
01266     return;
01267   }
01268 
01269   // Lower PSHUFB and VPERMILP normally but add a comment if we can find
01270   // a constant shuffle mask. We won't be able to do this at the MC layer
01271   // because the mask isn't an immediate.
01272   case X86::PSHUFBrm:
01273   case X86::VPSHUFBrm:
01274   case X86::VPSHUFBYrm:
01275   case X86::VPSHUFBZ128rm:
01276   case X86::VPSHUFBZ128rmk:
01277   case X86::VPSHUFBZ128rmkz:
01278   case X86::VPSHUFBZ256rm:
01279   case X86::VPSHUFBZ256rmk:
01280   case X86::VPSHUFBZ256rmkz:
01281   case X86::VPSHUFBZrm:
01282   case X86::VPSHUFBZrmk:
01283   case X86::VPSHUFBZrmkz: {
01284     if (!OutStreamer->isVerboseAsm())
01285       break;
01286     unsigned SrcIdx, MaskIdx;
01287     switch (MI->getOpcode()) {
01288     default: llvm_unreachable("Invalid opcode");
01289     case X86::PSHUFBrm:
01290     case X86::VPSHUFBrm:
01291     case X86::VPSHUFBYrm:
01292     case X86::VPSHUFBZ128rm:
01293     case X86::VPSHUFBZ256rm:
01294     case X86::VPSHUFBZrm:
01295       SrcIdx = 1; MaskIdx = 5; break;
01296     case X86::VPSHUFBZ128rmkz:
01297     case X86::VPSHUFBZ256rmkz:
01298     case X86::VPSHUFBZrmkz:
01299       SrcIdx = 2; MaskIdx = 6; break;
01300     case X86::VPSHUFBZ128rmk:
01301     case X86::VPSHUFBZ256rmk:
01302     case X86::VPSHUFBZrmk:
01303       SrcIdx = 3; MaskIdx = 7; break;
01304     }
01305 
01306     assert(MI->getNumOperands() >= 6 &&
01307            "We should always have at least 6 operands!");
01308     const MachineOperand &DstOp = MI->getOperand(0);
01309     const MachineOperand &SrcOp = MI->getOperand(SrcIdx);
01310     const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
01311 
01312     if (auto *C = getConstantFromPool(*MI, MaskOp)) {
01313       SmallVector<int, 16> Mask;
01314       DecodePSHUFBMask(C, Mask);
01315       if (!Mask.empty())
01316         OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
01317     }
01318     break;
01319   }
01320   case X86::VPERMILPSrm:
01321   case X86::VPERMILPDrm:
01322   case X86::VPERMILPSYrm:
01323   case X86::VPERMILPDYrm: {
01324     if (!OutStreamer->isVerboseAsm())
01325       break;
01326     assert(MI->getNumOperands() > 5 &&
01327            "We should always have at least 5 operands!");
01328     const MachineOperand &DstOp = MI->getOperand(0);
01329     const MachineOperand &SrcOp = MI->getOperand(1);
01330     const MachineOperand &MaskOp = MI->getOperand(5);
01331 
01332     unsigned ElSize;
01333     switch (MI->getOpcode()) {
01334     default: llvm_unreachable("Invalid opcode");
01335     case X86::VPERMILPSrm: case X86::VPERMILPSYrm: ElSize = 32; break;
01336     case X86::VPERMILPDrm: case X86::VPERMILPDYrm: ElSize = 64; break;
01337     }
01338 
01339     if (auto *C = getConstantFromPool(*MI, MaskOp)) {
01340       SmallVector<int, 16> Mask;
01341       DecodeVPERMILPMask(C, ElSize, Mask);
01342       if (!Mask.empty())
01343         OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
01344     }
01345     break;
01346   }
01347 
01348 #define MOV_CASE(Prefix, Suffix)        \
01349   case X86::Prefix##MOVAPD##Suffix##rm: \
01350   case X86::Prefix##MOVAPS##Suffix##rm: \
01351   case X86::Prefix##MOVUPD##Suffix##rm: \
01352   case X86::Prefix##MOVUPS##Suffix##rm: \
01353   case X86::Prefix##MOVDQA##Suffix##rm: \
01354   case X86::Prefix##MOVDQU##Suffix##rm:
01355 
01356 #define MOV_AVX512_CASE(Suffix)         \
01357   case X86::VMOVDQA64##Suffix##rm:      \
01358   case X86::VMOVDQA32##Suffix##rm:      \
01359   case X86::VMOVDQU64##Suffix##rm:      \
01360   case X86::VMOVDQU32##Suffix##rm:      \
01361   case X86::VMOVDQU16##Suffix##rm:      \
01362   case X86::VMOVDQU8##Suffix##rm:       \
01363   case X86::VMOVAPS##Suffix##rm:        \
01364   case X86::VMOVAPD##Suffix##rm:        \
01365   case X86::VMOVUPS##Suffix##rm:        \
01366   case X86::VMOVUPD##Suffix##rm:
01367 
01368 #define CASE_ALL_MOV_RM()               \
01369   MOV_CASE(, )   /* SSE */              \
01370   MOV_CASE(V, )  /* AVX-128 */          \
01371   MOV_CASE(V, Y) /* AVX-256 */          \
01372   MOV_AVX512_CASE(Z)                    \
01373   MOV_AVX512_CASE(Z256)                 \
01374   MOV_AVX512_CASE(Z128)
01375 
01376   // For loads from a constant pool to a vector register, print the constant
01377   // loaded.
01378   CASE_ALL_MOV_RM()
01379     if (!OutStreamer->isVerboseAsm())
01380       break;
01381     if (MI->getNumOperands() > 4)
01382     if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
01383       std::string Comment;
01384       raw_string_ostream CS(Comment);
01385       const MachineOperand &DstOp = MI->getOperand(0);
01386       CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
01387       if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
01388         CS << "[";
01389         for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
01390           if (i != 0)
01391             CS << ",";
01392           if (CDS->getElementType()->isIntegerTy())
01393             CS << CDS->getElementAsInteger(i);
01394           else if (CDS->getElementType()->isFloatTy())
01395             CS << CDS->getElementAsFloat(i);
01396           else if (CDS->getElementType()->isDoubleTy())
01397             CS << CDS->getElementAsDouble(i);
01398           else
01399             CS << "?";
01400         }
01401         CS << "]";
01402         OutStreamer->AddComment(CS.str());
01403       } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
01404         CS << "<";
01405         for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
01406           if (i != 0)
01407             CS << ",";
01408           Constant *COp = CV->getOperand(i);
01409           if (isa<UndefValue>(COp)) {
01410             CS << "u";
01411           } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
01412             if (CI->getBitWidth() <= 64) {
01413               CS << CI->getZExtValue();
01414             } else {
01415               // print multi-word constant as (w0,w1)
01416               auto Val = CI->getValue();
01417               CS << "(";
01418               for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
01419                 if (i > 0)
01420                   CS << ",";
01421                 CS << Val.getRawData()[i];
01422               }
01423               CS << ")";
01424             }
01425           } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
01426             SmallString<32> Str;
01427             CF->getValueAPF().toString(Str);
01428             CS << Str;
01429           } else {
01430             CS << "?";
01431           }
01432         }
01433         CS << ">";
01434         OutStreamer->AddComment(CS.str());
01435       }
01436     }
01437     break;
01438   }
01439 
01440   MCInst TmpInst;
01441   MCInstLowering.Lower(MI, TmpInst);
01442 
01443   // Stackmap shadows cannot include branch targets, so we can count the bytes
01444   // in a call towards the shadow, but must ensure that the no thread returns
01445   // in to the stackmap shadow.  The only way to achieve this is if the call
01446   // is at the end of the shadow.
01447   if (MI->isCall()) {
01448     // Count then size of the call towards the shadow
01449     SMShadowTracker.count(TmpInst, getSubtargetInfo());
01450     // Then flush the shadow so that we fill with nops before the call, not
01451     // after it.
01452     SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
01453     // Then emit the call
01454     OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
01455     return;
01456   }
01457 
01458   EmitAndCountInstruction(TmpInst);
01459 }