13#ifndef LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
14#define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
19#define GET_INSTRINFO_HEADER
20#include "ARCGenInstrInfo.inc"
28 virtual void anchor();
41 int &FrameIndex)
const override;
49 int &FrameIndex)
const override;
56 bool AllowModify)
const override;
61 int *BytesAdded =
nullptr)
const override;
64 int *BytesRemoved =
nullptr)
const override;
68 bool KillSrc)
const override;
72 bool IsKill,
int FrameIndex,
94 unsigned &OffsetPos)
const override;
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &, int *BytesAdded=nullptr) const override
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
bool isPostIncrement(const MachineInstr &MI) const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
const ARCRegisterInfo & getRegisterInfo() const
bool isPreIncrement(const MachineInstr &MI) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Return the inverse opcode of the specified Branch instruction.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Wrapper class representing physical registers. Should be passed by value.
Representation of each machine instruction.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
This is an optimization pass for GlobalISel generic memory operations.