LLVM 20.0.0git
ARCInstrInfo.h
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1//===- ARCInstrInfo.h - ARC Instruction Information -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the ARC implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
14#define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
15
16#include "ARCRegisterInfo.h"
18
19#define GET_INSTRINFO_HEADER
20#include "ARCGenInstrInfo.inc"
21
22namespace llvm {
23
24class ARCSubtarget;
25
27 const ARCRegisterInfo RI;
28 virtual void anchor();
29
30public:
32
33 const ARCRegisterInfo &getRegisterInfo() const { return RI; }
34
35 /// If the specified machine instruction is a direct
36 /// load from a stack slot, return the virtual or physical register number of
37 /// the destination along with the FrameIndex of the loaded stack slot. If
38 /// not, return 0. This predicate must return 0 if the instruction has
39 /// any side effects other than loading from the stack slot.
41 int &FrameIndex) const override;
42
43 /// If the specified machine instruction is a direct
44 /// store to a stack slot, return the virtual or physical register number of
45 /// the source reg along with the FrameIndex of the loaded stack slot. If
46 /// not, return 0. This predicate must return 0 if the instruction has
47 /// any side effects other than storing to the stack slot.
49 int &FrameIndex) const override;
50
51 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
52
56 bool AllowModify) const override;
57
60 const DebugLoc &,
61 int *BytesAdded = nullptr) const override;
62
64 int *BytesRemoved = nullptr) const override;
65
67 const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
68 bool KillSrc) const override;
69
72 bool IsKill, int FrameIndex,
73 const TargetRegisterClass *RC,
75 Register VReg) const override;
76
79 int FrameIndex, const TargetRegisterClass *RC,
81 Register VReg) const override;
82
83 bool
85
86
87 bool isPostIncrement(const MachineInstr &MI) const override;
88
89 // ARC-specific
90 bool isPreIncrement(const MachineInstr &MI) const;
91
92 virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
93 unsigned &BasePos,
94 unsigned &OffsetPos) const override;
95
96 // Emit code before MBBI to load immediate value into physical register Reg.
97 // Returns an iterator to the new instruction.
100 unsigned Reg, uint64_t Value) const;
101};
102
103} // end namespace llvm
104
105#endif // LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H
MachineBasicBlock & MBB
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &, int *BytesAdded=nullptr) const override
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
bool isPostIncrement(const MachineInstr &MI) const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
const ARCRegisterInfo & getRegisterInfo() const
Definition: ARCInstrInfo.h:33
bool isPreIncrement(const MachineInstr &MI) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Return the inverse opcode of the specified Branch instruction.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
Definition: Value.h:74
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18