LLVM 24.0.0git
AVRExpandPseudoInsts.cpp
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1//===-- AVRExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AVR.h"
16#include "AVRInstrInfo.h"
17#include "AVRMachineFunctionInfo.h"
18#include "AVRTargetMachine.h"
19#include "MCTargetDesc/AVRMCTargetDesc.h"
20
21#include "llvm/CodeGen/MachineFunctionPass.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/TargetRegisterInfo.h"
25
26using namespace llvm;
27
28#define AVR_EXPAND_PSEUDO_NAME "AVR pseudo instruction expansion pass"
29
30namespace {
31
32/// Expands "placeholder" instructions marked as pseudo into
33/// actual AVR instructions.
34class AVRExpandPseudo : public MachineFunctionPass {
35public:
36 static char ID;
37
38 AVRExpandPseudo() : MachineFunctionPass(ID) {}
39
40 bool runOnMachineFunction(MachineFunction &MF) override;
41
42 StringRef getPassName() const override { return AVR_EXPAND_PSEUDO_NAME; }
43
44private:
45 typedef MachineBasicBlock Block;
46 typedef Block::iterator BlockIt;
47
48 const AVRRegisterInfo *TRI;
49 const TargetInstrInfo *TII;
50
51 bool expandMBB(Block &MBB);
52 bool expandMI(Block &MBB, BlockIt MBBI);
53 template <unsigned OP> bool expand(Block &MBB, BlockIt MBBI);
54
55 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
56 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
57 }
58
59 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode,
60 Register DstReg) {
61 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
62 }
63
64 MachineRegisterInfo &getRegInfo(Block &MBB) {
65 return MBB.getParent()->getRegInfo();
66 }
67
68 bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
69 bool expandLogic(unsigned Op, Block &MBB, BlockIt MBBI);
70 bool expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI);
71 bool isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const;
72 bool isLogicRegOpUndef(unsigned Op, unsigned ImmVal) const;
73
74 template <typename Func> bool expandAtomic(Block &MBB, BlockIt MBBI, Func f);
75
76 template <typename Func>
77 bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI, Func f);
78
79 bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI);
80
81 /// Specific shift implementation for int8.
82 bool expandLSLB7Rd(Block &MBB, BlockIt MBBI);
83 bool expandLSRB7Rd(Block &MBB, BlockIt MBBI);
84 bool expandASRB6Rd(Block &MBB, BlockIt MBBI);
85 bool expandASRB7Rd(Block &MBB, BlockIt MBBI);
86
87 /// Specific shift implementation for int16.
88 bool expandLSLW4Rd(Block &MBB, BlockIt MBBI);
89 bool expandLSRW4Rd(Block &MBB, BlockIt MBBI);
90 bool expandASRW7Rd(Block &MBB, BlockIt MBBI);
91 bool expandLSLW8Rd(Block &MBB, BlockIt MBBI);
92 bool expandLSRW8Rd(Block &MBB, BlockIt MBBI);
93 bool expandASRW8Rd(Block &MBB, BlockIt MBBI);
94 bool expandLSLW12Rd(Block &MBB, BlockIt MBBI);
95 bool expandLSRW12Rd(Block &MBB, BlockIt MBBI);
96 bool expandASRW14Rd(Block &MBB, BlockIt MBBI);
97 bool expandASRW15Rd(Block &MBB, BlockIt MBBI);
98
99 // Common implementation of LPMWRdZ and ELPMWRdZ.
100 bool expandLPMWELPMW(Block &MBB, BlockIt MBBI, bool IsELPM);
101 // Common implementation of LPMBRdZ and ELPMBRdZ.
102 bool expandLPMBELPMB(Block &MBB, BlockIt MBBI, bool IsELPM);
103 // Common implementation of ROLBRdR1 and ROLBRdR17.
104 bool expandROLBRd(Block &MBB, BlockIt MBBI);
105};
106
107char AVRExpandPseudo::ID = 0;
108
109bool AVRExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
110 bool Modified = false;
111
112 BlockIt MBBI = MBB.begin(), E = MBB.end();
113 while (MBBI != E) {
114 BlockIt NMBBI = std::next(MBBI);
115 Modified |= expandMI(MBB, MBBI);
116 MBBI = NMBBI;
117 }
118
119 return Modified;
120}
121
122bool AVRExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
123 bool Modified = false;
124
125 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
126 TRI = STI.getRegisterInfo();
127 TII = STI.getInstrInfo();
128
129 for (Block &MBB : MF) {
130 bool ContinueExpanding = true;
131 unsigned ExpandCount = 0;
132
133 // Continue expanding the block until all pseudos are expanded.
134 do {
135 assert(ExpandCount < 10 && "pseudo expand limit reached");
136 (void)ExpandCount;
137
138 bool BlockModified = expandMBB(MBB);
139 Modified |= BlockModified;
140 ExpandCount++;
141
142 ContinueExpanding = BlockModified;
143 } while (ContinueExpanding);
144 }
145
146 return Modified;
147}
148
149bool AVRExpandPseudo::expandArith(unsigned OpLo, unsigned OpHi, Block &MBB,
150 BlockIt MBBI) {
151 MachineInstr &MI = *MBBI;
152 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
153 Register DstReg = MI.getOperand(0).getReg();
154 Register SrcReg = MI.getOperand(2).getReg();
155 bool DstIsDead = MI.getOperand(0).isDead();
156 bool DstIsKill = MI.getOperand(1).isKill();
157 bool SrcIsKill = MI.getOperand(2).isKill();
158 bool ImpIsDead = MI.getOperand(3).isDead();
159 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
160 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
161
162 buildMI(MBB, MBBI, OpLo)
163 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
164 .addReg(DstLoReg, getKillRegState(DstIsKill))
165 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
166
167 auto MIBHI =
168 buildMI(MBB, MBBI, OpHi)
169 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
170 .addReg(DstHiReg, getKillRegState(DstIsKill))
171 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
172
173 if (ImpIsDead)
174 MIBHI->getOperand(3).setIsDead();
175
176 // SREG is always implicitly killed
177 MIBHI->getOperand(4).setIsKill();
178
179 MI.eraseFromParent();
180 return true;
181}
182
183bool AVRExpandPseudo::expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
184 MachineInstr &MI = *MBBI;
185 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
186 Register DstReg = MI.getOperand(0).getReg();
187 Register SrcReg = MI.getOperand(2).getReg();
188 bool DstIsDead = MI.getOperand(0).isDead();
189 bool DstIsKill = MI.getOperand(1).isKill();
190 bool SrcIsKill = MI.getOperand(2).isKill();
191 bool ImpIsDead = MI.getOperand(3).isDead();
192 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
193 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
194
195 auto MIBLO =
196 buildMI(MBB, MBBI, Op)
197 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
198 .addReg(DstLoReg, getKillRegState(DstIsKill))
199 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
200
201 // SREG is always implicitly dead
202 MIBLO->getOperand(3).setIsDead();
203
204 auto MIBHI =
205 buildMI(MBB, MBBI, Op)
206 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
207 .addReg(DstHiReg, getKillRegState(DstIsKill))
208 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
209
210 if (ImpIsDead)
211 MIBHI->getOperand(3).setIsDead();
212
213 MI.eraseFromParent();
214 return true;
215}
216
217bool AVRExpandPseudo::isLogicImmOpRedundant(unsigned Op,
218 unsigned ImmVal) const {
219
220 // ANDI Rd, 0xff is redundant.
221 if (Op == AVR::ANDIRdK && ImmVal == 0xff)
222 return true;
223
224 // ORI Rd, 0x0 is redundant.
225 if (Op == AVR::ORIRdK && ImmVal == 0x0)
226 return true;
227
228 return false;
229}
230
231bool AVRExpandPseudo::isLogicRegOpUndef(unsigned Op, unsigned ImmVal) const {
232 // ANDI Rd, 0x00 clears all input bits.
233 if (Op == AVR::ANDIRdK && ImmVal == 0x00)
234 return true;
235
236 // ORI Rd, 0xff sets all input bits.
237 if (Op == AVR::ORIRdK && ImmVal == 0xff)
238 return true;
239
240 return false;
241}
242
243bool AVRExpandPseudo::expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI) {
244 MachineInstr &MI = *MBBI;
245 Register DstLoReg, DstHiReg;
246 Register DstReg = MI.getOperand(0).getReg();
247 bool DstIsDead = MI.getOperand(0).isDead();
248 bool SrcIsKill = MI.getOperand(1).isKill();
249 bool ImpIsDead = MI.getOperand(3).isDead();
250 unsigned Imm = MI.getOperand(2).getImm();
251 unsigned Lo8 = Imm & 0xff;
252 unsigned Hi8 = (Imm >> 8) & 0xff;
253 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
254
255 if (!isLogicImmOpRedundant(Op, Lo8)) {
256 auto MIBLO =
257 buildMI(MBB, MBBI, Op)
258 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
259 .addReg(DstLoReg, getKillRegState(SrcIsKill))
260 .addImm(Lo8);
261
262 // SREG is always implicitly dead
263 MIBLO->getOperand(3).setIsDead();
264
265 if (isLogicRegOpUndef(Op, Lo8))
266 MIBLO->getOperand(1).setIsUndef(true);
267 }
268
269 if (!isLogicImmOpRedundant(Op, Hi8)) {
270 auto MIBHI =
271 buildMI(MBB, MBBI, Op)
272 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
273 .addReg(DstHiReg, getKillRegState(SrcIsKill))
274 .addImm(Hi8);
275
276 if (ImpIsDead)
277 MIBHI->getOperand(3).setIsDead();
278
279 if (isLogicRegOpUndef(Op, Hi8))
280 MIBHI->getOperand(1).setIsUndef(true);
281 }
282
283 MI.eraseFromParent();
284 return true;
285}
286
287template <>
288bool AVRExpandPseudo::expand<AVR::ADDWRdRr>(Block &MBB, BlockIt MBBI) {
289 return expandArith(AVR::ADDRdRr, AVR::ADCRdRr, MBB, MBBI);
290}
291
292template <>
293bool AVRExpandPseudo::expand<AVR::ADCWRdRr>(Block &MBB, BlockIt MBBI) {
294 return expandArith(AVR::ADCRdRr, AVR::ADCRdRr, MBB, MBBI);
295}
296
297template <>
298bool AVRExpandPseudo::expand<AVR::ADIWRdKP>(Block &MBB, BlockIt MBBI) {
299 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
300 MachineInstr &MI = *MBBI;
301 Register DstReg = MI.getOperand(0).getReg();
302 Register SrcReg = MI.getOperand(1).getReg();
303 int64_t Imm = MI.getOperand(2).getImm();
304 unsigned Opcode;
305
306 if (SrcReg != DstReg) {
307 TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DstReg, SrcReg, false, false,
308 false);
309 }
310
311 if (isUInt<6>(Imm) && STI.hasADDSUBIW() &&
312 AVR::IWREGSRegClass.contains(DstReg)) {
313 Opcode = AVR::ADIWRdK;
314 } else {
315 Opcode = AVR::SUBIWRdK;
316 Imm = -Imm;
317 }
318
319 buildMI(MBB, MI, Opcode)
320 .addReg(DstReg, RegState::Define)
321 .addReg(DstReg, RegState::Kill)
322 .addImm(Imm)
323 .setOperandDead(3); // implicit-def $sreg
324
325 MI.eraseFromParent();
326 return true;
327}
328
329template <>
330bool AVRExpandPseudo::expand<AVR::SUBWRdRr>(Block &MBB, BlockIt MBBI) {
331 return expandArith(AVR::SUBRdRr, AVR::SBCRdRr, MBB, MBBI);
332}
333
334template <>
335bool AVRExpandPseudo::expand<AVR::SUBIWRdK>(Block &MBB, BlockIt MBBI) {
336 MachineInstr &MI = *MBBI;
337 Register DstLoReg, DstHiReg;
338 Register DstReg = MI.getOperand(0).getReg();
339 bool DstIsDead = MI.getOperand(0).isDead();
340 bool SrcIsKill = MI.getOperand(1).isKill();
341 bool ImpIsDead = MI.getOperand(3).isDead();
342 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
343
344 auto MIBLO =
345 buildMI(MBB, MBBI, AVR::SUBIRdK)
346 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
347 .addReg(DstLoReg, getKillRegState(SrcIsKill));
348
349 auto MIBHI =
350 buildMI(MBB, MBBI, AVR::SBCIRdK)
351 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
352 .addReg(DstHiReg, getKillRegState(SrcIsKill));
353
354 switch (MI.getOperand(2).getType()) {
355 case MachineOperand::MO_GlobalAddress: {
356 const GlobalValue *GV = MI.getOperand(2).getGlobal();
357 int64_t Offs = MI.getOperand(2).getOffset();
358 unsigned TF = MI.getOperand(2).getTargetFlags();
359 MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_LO);
360 MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_HI);
361 break;
362 }
363 case MachineOperand::MO_Immediate: {
364 unsigned Imm = MI.getOperand(2).getImm();
365 MIBLO.addImm(Imm & 0xff);
366 MIBHI.addImm((Imm >> 8) & 0xff);
367 break;
368 }
369 default:
370 llvm_unreachable("Unknown operand type!");
371 }
372
373 if (ImpIsDead)
374 MIBHI->getOperand(3).setIsDead();
375
376 // SREG is always implicitly killed
377 MIBHI->getOperand(4).setIsKill();
378
379 MI.eraseFromParent();
380 return true;
381}
382
383template <>
384bool AVRExpandPseudo::expand<AVR::SBCWRdRr>(Block &MBB, BlockIt MBBI) {
385 return expandArith(AVR::SBCRdRr, AVR::SBCRdRr, MBB, MBBI);
386}
387
388template <>
389bool AVRExpandPseudo::expand<AVR::SBCIWRdK>(Block &MBB, BlockIt MBBI) {
390 MachineInstr &MI = *MBBI;
391 Register DstLoReg, DstHiReg;
392 Register DstReg = MI.getOperand(0).getReg();
393 bool DstIsDead = MI.getOperand(0).isDead();
394 bool SrcIsKill = MI.getOperand(1).isKill();
395 bool ImpIsDead = MI.getOperand(3).isDead();
396 unsigned Imm = MI.getOperand(2).getImm();
397 unsigned Lo8 = Imm & 0xff;
398 unsigned Hi8 = (Imm >> 8) & 0xff;
399 unsigned OpLo = AVR::SBCIRdK;
400 unsigned OpHi = AVR::SBCIRdK;
401 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
402
403 auto MIBLO =
404 buildMI(MBB, MBBI, OpLo)
405 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
406 .addReg(DstLoReg, getKillRegState(SrcIsKill))
407 .addImm(Lo8);
408
409 // SREG is always implicitly killed
410 MIBLO->getOperand(4).setIsKill();
411
412 auto MIBHI =
413 buildMI(MBB, MBBI, OpHi)
414 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
415 .addReg(DstHiReg, getKillRegState(SrcIsKill))
416 .addImm(Hi8);
417
418 if (ImpIsDead)
419 MIBHI->getOperand(3).setIsDead();
420
421 // SREG is always implicitly killed
422 MIBHI->getOperand(4).setIsKill();
423
424 MI.eraseFromParent();
425 return true;
426}
427
428template <>
429bool AVRExpandPseudo::expand<AVR::ANDWRdRr>(Block &MBB, BlockIt MBBI) {
430 return expandLogic(AVR::ANDRdRr, MBB, MBBI);
431}
432
433template <>
434bool AVRExpandPseudo::expand<AVR::ANDIWRdK>(Block &MBB, BlockIt MBBI) {
435 return expandLogicImm(AVR::ANDIRdK, MBB, MBBI);
436}
437
438template <>
439bool AVRExpandPseudo::expand<AVR::ORWRdRr>(Block &MBB, BlockIt MBBI) {
440 return expandLogic(AVR::ORRdRr, MBB, MBBI);
441}
442
443template <>
444bool AVRExpandPseudo::expand<AVR::ORIWRdK>(Block &MBB, BlockIt MBBI) {
445 return expandLogicImm(AVR::ORIRdK, MBB, MBBI);
446}
447
448template <>
449bool AVRExpandPseudo::expand<AVR::EORWRdRr>(Block &MBB, BlockIt MBBI) {
450 return expandLogic(AVR::EORRdRr, MBB, MBBI);
451}
452
453template <>
454bool AVRExpandPseudo::expand<AVR::COMWRd>(Block &MBB, BlockIt MBBI) {
455 MachineInstr &MI = *MBBI;
456 Register DstLoReg, DstHiReg;
457 Register DstReg = MI.getOperand(0).getReg();
458 bool DstIsDead = MI.getOperand(0).isDead();
459 bool DstIsKill = MI.getOperand(1).isKill();
460 bool ImpIsDead = MI.getOperand(2).isDead();
461 unsigned OpLo = AVR::COMRd;
462 unsigned OpHi = AVR::COMRd;
463 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
464
465 auto MIBLO =
466 buildMI(MBB, MBBI, OpLo)
467 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
468 .addReg(DstLoReg, getKillRegState(DstIsKill));
469
470 // SREG is always implicitly dead
471 MIBLO->getOperand(2).setIsDead();
472
473 auto MIBHI =
474 buildMI(MBB, MBBI, OpHi)
475 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
476 .addReg(DstHiReg, getKillRegState(DstIsKill));
477
478 if (ImpIsDead)
479 MIBHI->getOperand(2).setIsDead();
480
481 MI.eraseFromParent();
482 return true;
483}
484
485template <>
486bool AVRExpandPseudo::expand<AVR::NEGWRd>(Block &MBB, BlockIt MBBI) {
487 MachineInstr &MI = *MBBI;
488 Register DstLoReg, DstHiReg;
489 Register DstReg = MI.getOperand(0).getReg();
490 Register ZeroReg = MI.getOperand(2).getReg();
491 bool DstIsDead = MI.getOperand(0).isDead();
492 bool DstIsKill = MI.getOperand(1).isKill();
493 bool ImpIsDead = MI.getOperand(2).isDead();
494 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
495
496 // Do NEG on the upper byte.
497 auto MIBHI =
498 buildMI(MBB, MBBI, AVR::NEGRd)
499 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
500 .addReg(DstHiReg, RegState::Kill);
501 // SREG is always implicitly dead
502 MIBHI->getOperand(2).setIsDead();
503
504 // Do NEG on the lower byte.
505 buildMI(MBB, MBBI, AVR::NEGRd)
506 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
507 .addReg(DstLoReg, getKillRegState(DstIsKill));
508
509 // Do an extra SBC.
510 auto MISBCI =
511 buildMI(MBB, MBBI, AVR::SBCRdRr)
512 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
513 .addReg(DstHiReg, getKillRegState(DstIsKill))
514 .addReg(ZeroReg);
515 if (ImpIsDead)
516 MISBCI->getOperand(3).setIsDead();
517 // SREG is always implicitly killed
518 MISBCI->getOperand(4).setIsKill();
519
520 MI.eraseFromParent();
521 return true;
522}
523
524template <>
525bool AVRExpandPseudo::expand<AVR::CPWRdRr>(Block &MBB, BlockIt MBBI) {
526 MachineInstr &MI = *MBBI;
527 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
528 Register DstReg = MI.getOperand(0).getReg();
529 Register SrcReg = MI.getOperand(1).getReg();
530 bool DstIsKill = MI.getOperand(0).isKill();
531 bool SrcIsKill = MI.getOperand(1).isKill();
532 bool ImpIsDead = MI.getOperand(2).isDead();
533 unsigned OpLo = AVR::CPRdRr;
534 unsigned OpHi = AVR::CPCRdRr;
535 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
536 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
537
538 // Low part
539 buildMI(MBB, MBBI, OpLo)
540 .addReg(DstLoReg, getKillRegState(DstIsKill))
541 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
542
543 auto MIBHI = buildMI(MBB, MBBI, OpHi)
544 .addReg(DstHiReg, getKillRegState(DstIsKill))
545 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
546
547 if (ImpIsDead)
548 MIBHI->getOperand(2).setIsDead();
549
550 // SREG is always implicitly killed
551 MIBHI->getOperand(3).setIsKill();
552
553 MI.eraseFromParent();
554 return true;
555}
556
557template <>
558bool AVRExpandPseudo::expand<AVR::CPCWRdRr>(Block &MBB, BlockIt MBBI) {
559 MachineInstr &MI = *MBBI;
560 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
561 Register DstReg = MI.getOperand(0).getReg();
562 Register SrcReg = MI.getOperand(1).getReg();
563 bool DstIsKill = MI.getOperand(0).isKill();
564 bool SrcIsKill = MI.getOperand(1).isKill();
565 bool ImpIsDead = MI.getOperand(2).isDead();
566 unsigned OpLo = AVR::CPCRdRr;
567 unsigned OpHi = AVR::CPCRdRr;
568 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
569 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
570
571 auto MIBLO = buildMI(MBB, MBBI, OpLo)
572 .addReg(DstLoReg, getKillRegState(DstIsKill))
573 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
574
575 // SREG is always implicitly killed
576 MIBLO->getOperand(3).setIsKill();
577
578 auto MIBHI = buildMI(MBB, MBBI, OpHi)
579 .addReg(DstHiReg, getKillRegState(DstIsKill))
580 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
581
582 if (ImpIsDead)
583 MIBHI->getOperand(2).setIsDead();
584
585 // SREG is always implicitly killed
586 MIBHI->getOperand(3).setIsKill();
587
588 MI.eraseFromParent();
589 return true;
590}
591
592template <>
593bool AVRExpandPseudo::expand<AVR::LDIWRdK>(Block &MBB, BlockIt MBBI) {
594 MachineInstr &MI = *MBBI;
595 Register DstLoReg, DstHiReg;
596 Register DstReg = MI.getOperand(0).getReg();
597 bool DstIsDead = MI.getOperand(0).isDead();
598 unsigned OpLo = AVR::LDIRdK;
599 unsigned OpHi = AVR::LDIRdK;
600 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
601
602 auto MIBLO =
603 buildMI(MBB, MBBI, OpLo)
604 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
605
606 auto MIBHI =
607 buildMI(MBB, MBBI, OpHi)
608 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
609
610 switch (MI.getOperand(1).getType()) {
611 case MachineOperand::MO_GlobalAddress: {
612 const GlobalValue *GV = MI.getOperand(1).getGlobal();
613 int64_t Offs = MI.getOperand(1).getOffset();
614 unsigned TF = MI.getOperand(1).getTargetFlags();
615
616 MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_LO);
617 MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_HI);
618 break;
619 }
620 case MachineOperand::MO_BlockAddress: {
621 const BlockAddress *BA = MI.getOperand(1).getBlockAddress();
622 unsigned TF = MI.getOperand(1).getTargetFlags();
623
624 MIBLO.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_LO));
625 MIBHI.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_HI));
626 break;
627 }
628 case MachineOperand::MO_Immediate: {
629 unsigned Imm = MI.getOperand(1).getImm();
630
631 MIBLO.addImm(Imm & 0xff);
632 MIBHI.addImm((Imm >> 8) & 0xff);
633 break;
634 }
635 default:
636 llvm_unreachable("Unknown operand type!");
637 }
638
639 MI.eraseFromParent();
640 return true;
641}
642
643template <>
644bool AVRExpandPseudo::expand<AVR::LDSWRdK>(Block &MBB, BlockIt MBBI) {
645 MachineInstr &MI = *MBBI;
646 Register DstLoReg, DstHiReg;
647 Register DstReg = MI.getOperand(0).getReg();
648 bool DstIsDead = MI.getOperand(0).isDead();
649 unsigned OpLo = AVR::LDSRdK;
650 unsigned OpHi = AVR::LDSRdK;
651 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
652
653 auto MIBLO =
654 buildMI(MBB, MBBI, OpLo)
655 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
656
657 auto MIBHI =
658 buildMI(MBB, MBBI, OpHi)
659 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
660
661 switch (MI.getOperand(1).getType()) {
662 case MachineOperand::MO_GlobalAddress: {
663 const GlobalValue *GV = MI.getOperand(1).getGlobal();
664 int64_t Offs = MI.getOperand(1).getOffset();
665 unsigned TF = MI.getOperand(1).getTargetFlags();
666
667 MIBLO.addGlobalAddress(GV, Offs, TF);
668 MIBHI.addGlobalAddress(GV, Offs + 1, TF);
669 break;
670 }
671 case MachineOperand::MO_Immediate: {
672 unsigned Imm = MI.getOperand(1).getImm();
673
674 MIBLO.addImm(Imm);
675 MIBHI.addImm(Imm + 1);
676 break;
677 }
678 default:
679 llvm_unreachable("Unknown operand type!");
680 }
681
682 MIBLO.setMemRefs(MI.memoperands());
683 MIBHI.setMemRefs(MI.memoperands());
684
685 MI.eraseFromParent();
686 return true;
687}
688
689template <>
690bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
691 MachineInstr &MI = *MBBI;
692 Register DstReg = MI.getOperand(0).getReg();
693 Register SrcReg = MI.getOperand(1).getReg();
694 bool DstIsKill = MI.getOperand(0).isKill();
695 bool SrcIsKill = MI.getOperand(1).isKill();
696 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
697
698 // DstReg has an earlyclobber so the register allocator will allocate them in
699 // separate registers.
700 assert(DstReg != SrcReg && "Dst and Src registers are the same!");
701
702 if (STI.hasTinyEncoding()) {
703 // Handle this case in the expansion of LDDWRdPtrQ because it is very
704 // similar.
705 buildMI(MBB, MBBI, AVR::LDDWRdPtrQ)
706 .addDef(DstReg, getKillRegState(DstIsKill))
707 .addReg(SrcReg, getKillRegState(SrcIsKill))
708 .addImm(0)
709 .setMemRefs(MI.memoperands());
710
711 } else {
712 Register DstLoReg, DstHiReg;
713 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
714
715 // Load low byte.
716 buildMI(MBB, MBBI, AVR::LDRdPtr)
717 .addReg(DstLoReg, RegState::Define)
718 .addReg(SrcReg)
719 .setMemRefs(MI.memoperands());
720
721 // Load high byte.
722 buildMI(MBB, MBBI, AVR::LDDRdPtrQ)
723 .addReg(DstHiReg, RegState::Define)
724 .addReg(SrcReg, getKillRegState(SrcIsKill))
725 .addImm(1)
726 .setMemRefs(MI.memoperands());
727 }
728
729 MI.eraseFromParent();
730 return true;
731}
732
733template <>
734bool AVRExpandPseudo::expand<AVR::LDWRdPtrPi>(Block &MBB, BlockIt MBBI) {
735 MachineInstr &MI = *MBBI;
736 Register DstLoReg, DstHiReg;
737 Register DstReg = MI.getOperand(0).getReg();
738 Register SrcReg = MI.getOperand(1).getReg();
739 bool DstIsDead = MI.getOperand(0).isDead();
740 bool SrcIsDead = MI.getOperand(1).isKill();
741 unsigned OpLo = AVR::LDRdPtrPi;
742 unsigned OpHi = AVR::LDRdPtrPi;
743 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
744
745 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
746
747 auto MIBLO =
748 buildMI(MBB, MBBI, OpLo)
749 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
750 .addReg(SrcReg, RegState::Define)
751 .addReg(SrcReg, RegState::Kill);
752
753 auto MIBHI =
754 buildMI(MBB, MBBI, OpHi)
755 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
756 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
757 .addReg(SrcReg, RegState::Kill);
758
759 MIBLO.setMemRefs(MI.memoperands());
760 MIBHI.setMemRefs(MI.memoperands());
761
762 MI.eraseFromParent();
763 return true;
764}
765
766template <>
767bool AVRExpandPseudo::expand<AVR::LDWRdPtrPd>(Block &MBB, BlockIt MBBI) {
768 MachineInstr &MI = *MBBI;
769 Register DstLoReg, DstHiReg;
770 Register DstReg = MI.getOperand(0).getReg();
771 Register SrcReg = MI.getOperand(1).getReg();
772 bool DstIsDead = MI.getOperand(0).isDead();
773 bool SrcIsDead = MI.getOperand(1).isKill();
774 unsigned OpLo = AVR::LDRdPtrPd;
775 unsigned OpHi = AVR::LDRdPtrPd;
776 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
777
778 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
779
780 auto MIBHI =
781 buildMI(MBB, MBBI, OpHi)
782 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
783 .addReg(SrcReg, RegState::Define)
784 .addReg(SrcReg, RegState::Kill);
785
786 auto MIBLO =
787 buildMI(MBB, MBBI, OpLo)
788 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
789 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
790 .addReg(SrcReg, RegState::Kill);
791
792 MIBLO.setMemRefs(MI.memoperands());
793 MIBHI.setMemRefs(MI.memoperands());
794
795 MI.eraseFromParent();
796 return true;
797}
798
799template <>
800bool AVRExpandPseudo::expand<AVR::LDDRdPtrQ>(Block &MBB, BlockIt MBBI) {
801 MachineInstr &MI = *MBBI;
802 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
803
804 // LDDRdPtrQ is a real instruction on ordinary AVR devices, but we treat it
805 // as a pseudo instruction on AVR tiny devices.
806 if (!STI.hasTinyEncoding())
807 return false;
808
809 Register DstReg = MI.getOperand(0).getReg();
810 bool DstIsDead = MI.getOperand(0).isDead();
811 Register SrcReg = MI.getOperand(1).getReg();
812 bool SrcIsKill = MI.getOperand(1).isKill();
813 unsigned Imm = MI.getOperand(2).getImm();
814
815 assert((Imm == 0 || SrcIsKill || !TRI->regsOverlap(DstReg, SrcReg)) &&
816 "Cannot restore a pointer that the load overwrites");
817
818 if (Imm != 0)
819 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg)
820 .addReg(SrcReg, RegState::Kill)
821 .addImm(0x10000 - Imm);
822
823 buildMI(MBB, MBBI, AVR::LDRdPtr)
824 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
825 .addReg(SrcReg, getKillRegState(SrcIsKill))
826 .setMemRefs(MI.memoperands());
827
828 if (Imm != 0 && !SrcIsKill)
829 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg)
830 .addReg(SrcReg, RegState::Kill)
831 .addImm(Imm);
832
833 MI.eraseFromParent();
834 return true;
835}
836
837template <>
838bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
839 MachineInstr &MI = *MBBI;
840 Register DstReg = MI.getOperand(0).getReg();
841 Register SrcReg = MI.getOperand(1).getReg();
842 unsigned Imm = MI.getOperand(2).getImm();
843 bool DstIsKill = MI.getOperand(0).isKill();
844 bool SrcIsKill = MI.getOperand(1).isKill();
845 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
846
847 // Since we add 1 to the Imm value for the high byte below, and 63 is the
848 // highest Imm value allowed for the instruction, 62 is the limit here.
849 assert(Imm <= 62 && "Offset is out of range");
850
851 // DstReg has an earlyclobber so the register allocator will allocate them in
852 // separate registers.
853 assert(DstReg != SrcReg && "Dst and Src registers are the same!");
854
855 if (STI.hasTinyEncoding()) {
856 // Reduced tiny cores don't support load/store with displacement. However,
857 // they do support postincrement. So we'll simply adjust the pointer before
858 // and after and use postincrement to load multiple registers.
859
860 // Add offset. The offset can be 0 when expanding this instruction from the
861 // more specific LDWRdPtr instruction.
862 if (Imm != 0) {
863 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg)
864 .addReg(SrcReg)
865 .addImm(0x10000 - Imm);
866 }
867
868 // Do a word load with postincrement. This will be lowered to a two byte
869 // load.
870 buildMI(MBB, MBBI, AVR::LDWRdPtrPi)
871 .addDef(DstReg, getKillRegState(DstIsKill))
872 .addReg(SrcReg, getKillRegState(SrcIsKill))
873 .addImm(0)
874 .setMemRefs(MI.memoperands());
875
876 // If the pointer is used after the store instruction, subtract the new
877 // offset (with 2 added after the postincrement instructions) so it is the
878 // same as before.
879 if (!SrcIsKill) {
880 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg).addReg(SrcReg).addImm(Imm + 2);
881 }
882 } else {
883 Register DstLoReg, DstHiReg;
884 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
885
886 // Load low byte.
887 buildMI(MBB, MBBI, AVR::LDDRdPtrQ)
888 .addReg(DstLoReg, RegState::Define)
889 .addReg(SrcReg)
890 .addImm(Imm)
891 .setMemRefs(MI.memoperands());
892
893 // Load high byte.
894 buildMI(MBB, MBBI, AVR::LDDRdPtrQ)
895 .addReg(DstHiReg, RegState::Define)
896 .addReg(SrcReg, getKillRegState(SrcIsKill))
897 .addImm(Imm + 1)
898 .setMemRefs(MI.memoperands());
899 }
900
901 MI.eraseFromParent();
902 return true;
903}
904
905bool AVRExpandPseudo::expandLPMWELPMW(Block &MBB, BlockIt MBBI, bool IsELPM) {
906 MachineInstr &MI = *MBBI;
907 Register DstLoReg, DstHiReg;
908 Register DstReg = MI.getOperand(0).getReg();
909 Register SrcReg = MI.getOperand(1).getReg();
910 Register SrcLoReg, SrcHiReg;
911 bool SrcIsKill = MI.getOperand(1).isKill();
912 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
913 bool IsLPMRn = IsELPM ? STI.hasELPMX() : STI.hasLPMX();
914
915 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
916 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
917
918 // Set the I/O register RAMPZ for ELPM.
919 if (IsELPM) {
920 Register Bank = MI.getOperand(2).getReg();
921 // out RAMPZ, rtmp
922 buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(Bank);
923 }
924
925 // This is enforced by the @earlyclobber constraint.
926 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
927
928 if (IsLPMRn) {
929 unsigned OpLo = IsELPM ? AVR::ELPMRdZPi : AVR::LPMRdZPi;
930 unsigned OpHi = IsELPM ? AVR::ELPMRdZ : AVR::LPMRdZ;
931 // Load low byte.
932 auto MIBLO = buildMI(MBB, MBBI, OpLo)
933 .addReg(DstLoReg, RegState::Define)
934 .addReg(SrcReg);
935 // Load high byte.
936 auto MIBHI = buildMI(MBB, MBBI, OpHi)
937 .addReg(DstHiReg, RegState::Define)
938 .addReg(SrcReg, getKillRegState(SrcIsKill));
939 MIBLO.setMemRefs(MI.memoperands());
940 MIBHI.setMemRefs(MI.memoperands());
941 } else {
942 unsigned Opc = IsELPM ? AVR::ELPM : AVR::LPM;
943 // Load low byte, and copy to the low destination register.
944 auto MIBLO = buildMI(MBB, MBBI, Opc);
945 buildMI(MBB, MBBI, AVR::MOVRdRr)
946 .addReg(DstLoReg, RegState::Define)
947 .addReg(STI.getTmpRegister(), RegState::Kill);
948 MIBLO.setMemRefs(MI.memoperands());
949 // Increase the Z register by 1.
950 if (STI.hasADDSUBIW()) {
951 // adiw r31:r30, 1
952 auto MIINC = buildMI(MBB, MBBI, AVR::ADIWRdK)
953 .addReg(SrcReg, RegState::Define)
954 .addReg(SrcReg, getKillRegState(SrcIsKill))
955 .addImm(1);
956 MIINC->getOperand(3).setIsDead();
957 } else {
958 // subi r30, 255
959 // sbci r31, 255
960 buildMI(MBB, MBBI, AVR::SUBIRdK)
961 .addReg(SrcLoReg, RegState::Define)
962 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
963 .addImm(255);
964 auto MIZHI = buildMI(MBB, MBBI, AVR::SBCIRdK)
965 .addReg(SrcHiReg, RegState::Define)
966 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
967 .addImm(255);
968 MIZHI->getOperand(3).setIsDead();
969 MIZHI->getOperand(4).setIsKill();
970 }
971 // Load high byte, and copy to the high destination register.
972 auto MIBHI = buildMI(MBB, MBBI, Opc);
973 buildMI(MBB, MBBI, AVR::MOVRdRr)
974 .addReg(DstHiReg, RegState::Define)
975 .addReg(STI.getTmpRegister(), RegState::Kill);
976 MIBHI.setMemRefs(MI.memoperands());
977 }
978
979 // Restore the Z register if it is not killed.
980 if (!SrcIsKill) {
981 if (STI.hasADDSUBIW()) {
982 // sbiw r31:r30, 1
983 auto MIDEC = buildMI(MBB, MBBI, AVR::SBIWRdK)
984 .addReg(SrcReg, RegState::Define)
985 .addReg(SrcReg, getKillRegState(SrcIsKill))
986 .addImm(1);
987 MIDEC->getOperand(3).setIsDead();
988 } else {
989 // subi r30, 1
990 // sbci r31, 0
991 buildMI(MBB, MBBI, AVR::SUBIRdK)
992 .addReg(SrcLoReg, RegState::Define)
993 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
994 .addImm(1);
995 auto MIZHI = buildMI(MBB, MBBI, AVR::SBCIRdK)
996 .addReg(SrcHiReg, RegState::Define)
997 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
998 .addImm(0);
999 MIZHI->getOperand(3).setIsDead();
1000 MIZHI->getOperand(4).setIsKill();
1001 }
1002 }
1003
1004 MI.eraseFromParent();
1005 return true;
1006}
1007
1008template <>
1009bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
1010 return expandLPMWELPMW(MBB, MBBI, false);
1011}
1012
1013template <>
1014bool AVRExpandPseudo::expand<AVR::ELPMWRdZ>(Block &MBB, BlockIt MBBI) {
1015 return expandLPMWELPMW(MBB, MBBI, true);
1016}
1017
1018bool AVRExpandPseudo::expandLPMBELPMB(Block &MBB, BlockIt MBBI, bool IsELPM) {
1019 MachineInstr &MI = *MBBI;
1020 Register DstReg = MI.getOperand(0).getReg();
1021 Register SrcReg = MI.getOperand(1).getReg();
1022 bool SrcIsKill = MI.getOperand(1).isKill();
1023 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1024 bool IsLPMRn = IsELPM ? STI.hasELPMX() : STI.hasLPMX();
1025
1026 // Set the I/O register RAMPZ for ELPM (out RAMPZ, rtmp).
1027 if (IsELPM) {
1028 Register BankReg = MI.getOperand(2).getReg();
1029 buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(BankReg);
1030 }
1031
1032 // Load byte.
1033 if (IsLPMRn) {
1034 unsigned Opc = IsELPM ? AVR::ELPMRdZ : AVR::LPMRdZ;
1035 auto MILB = buildMI(MBB, MBBI, Opc)
1036 .addReg(DstReg, RegState::Define)
1037 .addReg(SrcReg, getKillRegState(SrcIsKill));
1038 MILB.setMemRefs(MI.memoperands());
1039 } else {
1040 // For the basic ELPM/LPM instruction, its operand[0] is the implicit
1041 // 'Z' register, and its operand[1] is the implicit 'R0' register.
1042 unsigned Opc = IsELPM ? AVR::ELPM : AVR::LPM;
1043 auto MILB = buildMI(MBB, MBBI, Opc);
1044 buildMI(MBB, MBBI, AVR::MOVRdRr)
1045 .addReg(DstReg, RegState::Define)
1046 .addReg(STI.getTmpRegister(), RegState::Kill);
1047 MILB.setMemRefs(MI.memoperands());
1048 }
1049
1050 MI.eraseFromParent();
1051 return true;
1052}
1053
1054template <>
1055bool AVRExpandPseudo::expand<AVR::ELPMBRdZ>(Block &MBB, BlockIt MBBI) {
1056 return expandLPMBELPMB(MBB, MBBI, true);
1057}
1058
1059template <>
1060bool AVRExpandPseudo::expand<AVR::LPMBRdZ>(Block &MBB, BlockIt MBBI) {
1061 return expandLPMBELPMB(MBB, MBBI, false);
1062}
1063
1064template <>
1065bool AVRExpandPseudo::expand<AVR::LPMWRdZPi>(Block &MBB, BlockIt MBBI) {
1066 llvm_unreachable("16-bit LPMPi is unimplemented");
1067}
1068
1069template <>
1070bool AVRExpandPseudo::expand<AVR::ELPMBRdZPi>(Block &MBB, BlockIt MBBI) {
1071 llvm_unreachable("8-bit ELPMPi is unimplemented");
1072}
1073
1074template <>
1075bool AVRExpandPseudo::expand<AVR::ELPMWRdZPi>(Block &MBB, BlockIt MBBI) {
1076 llvm_unreachable("16-bit ELPMPi is unimplemented");
1077}
1078
1079template <typename Func>
1080bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
1081 MachineInstr &MI = *MBBI;
1082 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1083
1084 // Store the SREG.
1085 buildMI(MBB, MBBI, AVR::INRdA)
1086 .addReg(STI.getTmpRegister(), RegState::Define)
1087 .addImm(STI.getIORegSREG());
1088
1089 // Disable exceptions.
1090 buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
1091
1092 f(MI);
1093
1094 // Restore the status reg.
1095 buildMI(MBB, MBBI, AVR::OUTARr)
1096 .addImm(STI.getIORegSREG())
1097 .addReg(STI.getTmpRegister());
1098
1099 MI.eraseFromParent();
1100 return true;
1101}
1102
1103template <typename Func>
1104bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
1105 BlockIt MBBI, Func f) {
1106 return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
1107 auto Op1 = MI.getOperand(0);
1108 auto Op2 = MI.getOperand(1);
1109
1110 MachineInstr &NewInst =
1111 *buildMI(MBB, MBBI, Opcode).add(Op1).add(Op2).getInstr();
1112 f(NewInst);
1113 });
1114}
1115
1116bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
1117 BlockIt MBBI) {
1118 return expandAtomicBinaryOp(Opcode, MBB, MBBI, [](MachineInstr &MI) {});
1119}
1120
1121template <>
1122bool AVRExpandPseudo::expand<AVR::AtomicLoad8>(Block &MBB, BlockIt MBBI) {
1123 return expandAtomicBinaryOp(AVR::LDRdPtr, MBB, MBBI);
1124}
1125
1126template <>
1127bool AVRExpandPseudo::expand<AVR::AtomicLoad16>(Block &MBB, BlockIt MBBI) {
1128 return expandAtomicBinaryOp(AVR::LDWRdPtr, MBB, MBBI);
1129}
1130
1131template <>
1132bool AVRExpandPseudo::expand<AVR::AtomicStore8>(Block &MBB, BlockIt MBBI) {
1133 return expandAtomicBinaryOp(AVR::STPtrRr, MBB, MBBI);
1134}
1135
1136template <>
1137bool AVRExpandPseudo::expand<AVR::AtomicStore16>(Block &MBB, BlockIt MBBI) {
1138 return expandAtomicBinaryOp(AVR::STWPtrRr, MBB, MBBI);
1139}
1140
1141template <>
1142bool AVRExpandPseudo::expand<AVR::AtomicFence>(Block &MBB, BlockIt MBBI) {
1143 // On AVR, there is only one core and so atomic fences do nothing.
1144 MBBI->eraseFromParent();
1145 return true;
1146}
1147
1148template <>
1149bool AVRExpandPseudo::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) {
1150 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1151 MachineInstr &MI = *MBBI;
1152 Register SrcLoReg, SrcHiReg;
1153 Register SrcReg = MI.getOperand(1).getReg();
1154 bool SrcIsKill = MI.getOperand(1).isKill();
1155 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1156
1157 auto MIB0 = buildMI(MBB, MBBI, AVR::STSKRr);
1158 auto MIB1 = buildMI(MBB, MBBI, AVR::STSKRr);
1159
1160 switch (MI.getOperand(0).getType()) {
1161 case MachineOperand::MO_GlobalAddress: {
1162 const GlobalValue *GV = MI.getOperand(0).getGlobal();
1163 int64_t Offs = MI.getOperand(0).getOffset();
1164 unsigned TF = MI.getOperand(0).getTargetFlags();
1165
1166 if (STI.hasLowByteFirst()) {
1167 // Write the low byte first for XMEGA devices.
1168 MIB0.addGlobalAddress(GV, Offs, TF);
1169 MIB1.addGlobalAddress(GV, Offs + 1, TF);
1170 } else {
1171 // Write the high byte first for traditional devices.
1172 MIB0.addGlobalAddress(GV, Offs + 1, TF);
1173 MIB1.addGlobalAddress(GV, Offs, TF);
1174 }
1175
1176 break;
1177 }
1178 case MachineOperand::MO_Immediate: {
1179 unsigned Imm = MI.getOperand(0).getImm();
1180
1181 if (STI.hasLowByteFirst()) {
1182 // Write the low byte first for XMEGA devices.
1183 MIB0.addImm(Imm);
1184 MIB1.addImm(Imm + 1);
1185 } else {
1186 // Write the high byte first for traditional devices.
1187 MIB0.addImm(Imm + 1);
1188 MIB1.addImm(Imm);
1189 }
1190
1191 break;
1192 }
1193 default:
1194 llvm_unreachable("Unknown operand type!");
1195 }
1196
1197 if (STI.hasLowByteFirst()) {
1198 // Write the low byte first for XMEGA devices.
1199 MIB0.addReg(SrcLoReg, getKillRegState(SrcIsKill))
1200 .setMemRefs(MI.memoperands());
1201 MIB1.addReg(SrcHiReg, getKillRegState(SrcIsKill))
1202 .setMemRefs(MI.memoperands());
1203 } else {
1204 // Write the high byte first for traditional devices.
1205 MIB0.addReg(SrcHiReg, getKillRegState(SrcIsKill))
1206 .setMemRefs(MI.memoperands());
1207 MIB1.addReg(SrcLoReg, getKillRegState(SrcIsKill))
1208 .setMemRefs(MI.memoperands());
1209 }
1210
1211 MI.eraseFromParent();
1212 return true;
1213}
1214
1215template <>
1216bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
1217 MachineInstr &MI = *MBBI;
1218 Register DstReg = MI.getOperand(0).getReg();
1219 Register SrcReg = MI.getOperand(1).getReg();
1220 bool DstIsKill = MI.getOperand(0).isKill();
1221 bool DstIsUndef = MI.getOperand(0).isUndef();
1222 bool SrcIsKill = MI.getOperand(1).isKill();
1223 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1224
1225 if (STI.hasTinyEncoding()) {
1226 // Handle this case in the expansion of STDWPtrQRr because it is very
1227 // similar.
1228 buildMI(MBB, MBBI, AVR::STDWPtrQRr)
1229 .addReg(DstReg,
1230 getKillRegState(DstIsKill) | getUndefRegState(DstIsUndef))
1231 .addImm(0)
1232 .addReg(SrcReg, getKillRegState(SrcIsKill))
1233 .setMemRefs(MI.memoperands());
1234
1235 } else {
1236 Register SrcLoReg, SrcHiReg;
1237 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1238 if (STI.hasLowByteFirst()) {
1239 buildMI(MBB, MBBI, AVR::STPtrRr)
1240 .addReg(DstReg, getUndefRegState(DstIsUndef))
1241 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1242 .setMemRefs(MI.memoperands());
1243 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1244 .addReg(DstReg, getUndefRegState(DstIsUndef))
1245 .addImm(1)
1246 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1247 .setMemRefs(MI.memoperands());
1248 } else {
1249 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1250 .addReg(DstReg, getUndefRegState(DstIsUndef))
1251 .addImm(1)
1252 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1253 .setMemRefs(MI.memoperands());
1254 buildMI(MBB, MBBI, AVR::STPtrRr)
1255 .addReg(DstReg, getUndefRegState(DstIsUndef))
1256 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1257 .setMemRefs(MI.memoperands());
1258 }
1259 }
1260
1261 MI.eraseFromParent();
1262 return true;
1263}
1264
1265template <>
1266bool AVRExpandPseudo::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) {
1267 MachineInstr &MI = *MBBI;
1268 Register SrcLoReg, SrcHiReg;
1269 Register DstReg = MI.getOperand(0).getReg();
1270 Register SrcReg = MI.getOperand(2).getReg();
1271 unsigned Imm = MI.getOperand(3).getImm();
1272 bool DstIsDead = MI.getOperand(0).isDead();
1273 bool SrcIsKill = MI.getOperand(2).isKill();
1274 unsigned OpLo = AVR::STPtrPiRr;
1275 unsigned OpHi = AVR::STPtrPiRr;
1276 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1277
1278 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1279
1280 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1281 .addReg(DstReg, RegState::Define)
1282 .addReg(DstReg, RegState::Kill)
1283 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1284 .addImm(Imm);
1285
1286 auto MIBHI =
1287 buildMI(MBB, MBBI, OpHi)
1288 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1289 .addReg(DstReg, RegState::Kill)
1290 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1291 .addImm(Imm);
1292
1293 MIBLO.setMemRefs(MI.memoperands());
1294 MIBHI.setMemRefs(MI.memoperands());
1295
1296 MI.eraseFromParent();
1297 return true;
1298}
1299
1300template <>
1301bool AVRExpandPseudo::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) {
1302 MachineInstr &MI = *MBBI;
1303 Register SrcLoReg, SrcHiReg;
1304 Register DstReg = MI.getOperand(0).getReg();
1305 Register SrcReg = MI.getOperand(2).getReg();
1306 unsigned Imm = MI.getOperand(3).getImm();
1307 bool DstIsDead = MI.getOperand(0).isDead();
1308 bool SrcIsKill = MI.getOperand(2).isKill();
1309 unsigned OpLo = AVR::STPtrPdRr;
1310 unsigned OpHi = AVR::STPtrPdRr;
1311 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1312
1313 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1314
1315 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1316 .addReg(DstReg, RegState::Define)
1317 .addReg(DstReg, RegState::Kill)
1318 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1319 .addImm(Imm);
1320
1321 auto MIBLO =
1322 buildMI(MBB, MBBI, OpLo)
1323 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1324 .addReg(DstReg, RegState::Kill)
1325 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1326 .addImm(Imm);
1327
1328 MIBLO.setMemRefs(MI.memoperands());
1329 MIBHI.setMemRefs(MI.memoperands());
1330
1331 MI.eraseFromParent();
1332 return true;
1333}
1334
1335template <>
1336bool AVRExpandPseudo::expand<AVR::STDPtrQRr>(Block &MBB, BlockIt MBBI) {
1337 MachineInstr &MI = *MBBI;
1338 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1339
1340 // STDPtrQRr is a real instruction on ordinary AVR devices, but we treat it
1341 // as a pseudo instruction on AVR tiny devices.
1342 if (!STI.hasTinyEncoding())
1343 return false;
1344
1345 Register DstReg = MI.getOperand(0).getReg();
1346 bool DstIsKill = MI.getOperand(0).isKill();
1347 unsigned Imm = MI.getOperand(1).getImm();
1348 Register SrcReg = MI.getOperand(2).getReg();
1349 bool SrcIsKill = MI.getOperand(2).isKill();
1350
1351 assert((Imm == 0 || !TRI->regsOverlap(DstReg, SrcReg)) &&
1352 "Cannot adjust a pointer that holds the value to store");
1353
1354 if (Imm != 0)
1355 buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
1356 .addReg(DstReg, RegState::Kill)
1357 .addImm(0x10000 - Imm);
1358
1359 buildMI(MBB, MBBI, AVR::STPtrRr)
1360 .addReg(DstReg, getKillRegState(DstIsKill))
1361 .addReg(SrcReg, getKillRegState(SrcIsKill))
1362 .setMemRefs(MI.memoperands());
1363
1364 if (Imm != 0 && !DstIsKill)
1365 buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
1366 .addReg(DstReg, RegState::Kill)
1367 .addImm(Imm);
1368
1369 MI.eraseFromParent();
1370 return true;
1371}
1372
1373template <>
1374bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
1375 MachineInstr &MI = *MBBI;
1376 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1377
1378 Register DstReg = MI.getOperand(0).getReg();
1379 bool DstIsKill = MI.getOperand(0).isKill();
1380 unsigned Imm = MI.getOperand(1).getImm();
1381 Register SrcReg = MI.getOperand(2).getReg();
1382 bool SrcIsKill = MI.getOperand(2).isKill();
1383
1384 // STD's maximum displacement is 63, so larger stores have to be split into a
1385 // set of operations.
1386 // For avrtiny chips, STD is not available at all so we always have to fall
1387 // back to manual pointer adjustments.
1388 if (Imm >= 63 || STI.hasTinyEncoding()) {
1389 // Add offset. The offset can be 0 when expanding this instruction from the
1390 // more specific STWPtrRr instruction.
1391 if (Imm != 0) {
1392 buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
1393 .addReg(DstReg, RegState::Kill)
1394 .addImm(0x10000 - Imm);
1395 }
1396
1397 // Do the store. This is a word store, that will be expanded further.
1398 buildMI(MBB, MBBI, AVR::STWPtrPiRr, DstReg)
1399 .addReg(DstReg, getKillRegState(DstIsKill))
1400 .addReg(SrcReg, getKillRegState(SrcIsKill))
1401 .addImm(0)
1402 .setMemRefs(MI.memoperands());
1403
1404 // If the pointer is used after the store instruction, subtract the new
1405 // offset (with 2 added after the postincrement instructions) so it is the
1406 // same as before.
1407 if (!DstIsKill) {
1408 buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
1409 .addReg(DstReg, RegState::Kill)
1410 .addImm(Imm + 2);
1411 }
1412 } else {
1413 Register SrcLoReg, SrcHiReg;
1414 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1415
1416 if (STI.hasLowByteFirst()) {
1417 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1418 .addReg(DstReg)
1419 .addImm(Imm)
1420 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1421 .setMemRefs(MI.memoperands());
1422 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1423 .addReg(DstReg, getKillRegState(DstIsKill))
1424 .addImm(Imm + 1)
1425 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1426 .setMemRefs(MI.memoperands());
1427 } else {
1428 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1429 .addReg(DstReg)
1430 .addImm(Imm + 1)
1431 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1432 .setMemRefs(MI.memoperands());
1433 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1434 .addReg(DstReg, getKillRegState(DstIsKill))
1435 .addImm(Imm)
1436 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1437 .setMemRefs(MI.memoperands());
1438 }
1439 }
1440
1441 MI.eraseFromParent();
1442 return true;
1443}
1444
1445template <>
1446bool AVRExpandPseudo::expand<AVR::STDSPQRr>(Block &MBB, BlockIt MBBI) {
1447 MachineInstr &MI = *MBBI;
1448 const MachineFunction &MF = *MBB.getParent();
1449 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
1450
1451 assert(MI.getOperand(0).getReg() == AVR::SP &&
1452 "SP is expected as base pointer");
1453
1454 assert(STI.getFrameLowering()->hasReservedCallFrame(MF) &&
1455 "unexpected STDSPQRr pseudo instruction");
1456
1457 if (STI.hasTinyEncoding()) {
1458 // Reduced tiny cores don't support std, so emulate it with a plain store
1459 // and pointer adjustments.
1460 unsigned Imm = MI.getOperand(1).getImm();
1461 Register SrcReg = MI.getOperand(2).getReg();
1462 bool SrcIsKill = MI.getOperand(2).isKill();
1463
1464 if (Imm != 0)
1465 buildMI(MBB, MBBI, AVR::SUBIWRdK, AVR::R29R28)
1466 .addReg(AVR::R29R28, RegState::Kill)
1467 .addImm(0x10000 - Imm);
1468
1469 buildMI(MBB, MBBI, AVR::STPtrRr)
1470 .addReg(AVR::R29R28, RegState::Kill)
1471 .addReg(SrcReg, getKillRegState(SrcIsKill))
1472 .setMemRefs(MI.memoperands());
1473
1474 if (Imm != 0)
1475 buildMI(MBB, std::next(MBBI), AVR::SUBIWRdK, AVR::R29R28)
1476 .addReg(AVR::R29R28, RegState::Kill)
1477 .addImm(Imm);
1478
1479 MI.eraseFromParent();
1480 } else {
1481 MI.setDesc(TII->get(AVR::STDPtrQRr));
1482 MI.getOperand(0).setReg(AVR::R29R28);
1483 }
1484
1485 return true;
1486}
1487
1488template <>
1489bool AVRExpandPseudo::expand<AVR::STDWSPQRr>(Block &MBB, BlockIt MBBI) {
1490 MachineInstr &MI = *MBBI;
1491 const MachineFunction &MF = *MBB.getParent();
1492 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
1493
1494 assert(MI.getOperand(0).getReg() == AVR::SP &&
1495 "SP is expected as base pointer");
1496
1497 assert(STI.getFrameLowering()->hasReservedCallFrame(MF) &&
1498 "unexpected STDWSPQRr pseudo instruction");
1499 (void)STI;
1500
1501 MI.setDesc(TII->get(AVR::STDWPtrQRr));
1502 MI.getOperand(0).setReg(AVR::R29R28);
1503
1504 return true;
1505}
1506
1507template <>
1508bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {
1509 MachineInstr &MI = *MBBI;
1510 Register DstLoReg, DstHiReg;
1511 unsigned Imm = MI.getOperand(1).getImm();
1512 Register DstReg = MI.getOperand(0).getReg();
1513 bool DstIsDead = MI.getOperand(0).isDead();
1514 unsigned OpLo = AVR::INRdA;
1515 unsigned OpHi = AVR::INRdA;
1516 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1517
1518 // Since we add 1 to the Imm value for the high byte below, and 63 is the
1519 // highest Imm value allowed for the instruction, 62 is the limit here.
1520 assert(Imm <= 62 && "Address is out of range");
1521
1522 auto MIBLO =
1523 buildMI(MBB, MBBI, OpLo)
1524 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1525 .addImm(Imm);
1526
1527 auto MIBHI =
1528 buildMI(MBB, MBBI, OpHi)
1529 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1530 .addImm(Imm + 1);
1531
1532 MIBLO.setMemRefs(MI.memoperands());
1533 MIBHI.setMemRefs(MI.memoperands());
1534
1535 MI.eraseFromParent();
1536 return true;
1537}
1538
1539template <>
1540bool AVRExpandPseudo::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) {
1541 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1542 MachineInstr &MI = *MBBI;
1543 Register SrcLoReg, SrcHiReg;
1544 unsigned Imm = MI.getOperand(0).getImm();
1545 Register SrcReg = MI.getOperand(1).getReg();
1546 bool SrcIsKill = MI.getOperand(1).isKill();
1547 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1548
1549 // Since we add 1 to the Imm value for the high byte below, and 63 is the
1550 // highest Imm value allowed for the instruction, 62 is the limit here.
1551 assert(Imm <= 62 && "Address is out of range");
1552
1553 // 16 bit I/O writes need the high byte first on normal AVR devices,
1554 // and in reverse order for the XMEGA/XMEGA3/XMEGAU families.
1555 auto MIBHI = buildMI(MBB, MBBI, AVR::OUTARr)
1556 .addImm(STI.hasLowByteFirst() ? Imm : Imm + 1)
1557 .addReg(STI.hasLowByteFirst() ? SrcLoReg : SrcHiReg,
1558 getKillRegState(SrcIsKill));
1559 auto MIBLO = buildMI(MBB, MBBI, AVR::OUTARr)
1560 .addImm(STI.hasLowByteFirst() ? Imm + 1 : Imm)
1561 .addReg(STI.hasLowByteFirst() ? SrcHiReg : SrcLoReg,
1562 getKillRegState(SrcIsKill));
1563
1564 MIBLO.setMemRefs(MI.memoperands());
1565 MIBHI.setMemRefs(MI.memoperands());
1566
1567 MI.eraseFromParent();
1568 return true;
1569}
1570
1571template <>
1572bool AVRExpandPseudo::expand<AVR::PUSHWRr>(Block &MBB, BlockIt MBBI) {
1573 MachineInstr &MI = *MBBI;
1574 Register SrcLoReg, SrcHiReg;
1575 Register SrcReg = MI.getOperand(0).getReg();
1576 bool SrcIsKill = MI.getOperand(0).isKill();
1577 unsigned Flags = MI.getFlags();
1578 unsigned OpLo = AVR::PUSHRr;
1579 unsigned OpHi = AVR::PUSHRr;
1580 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1581
1582 // Low part
1583 buildMI(MBB, MBBI, OpLo)
1584 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1585 .setMIFlags(Flags);
1586
1587 // High part
1588 buildMI(MBB, MBBI, OpHi)
1589 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1590 .setMIFlags(Flags);
1591
1592 MI.eraseFromParent();
1593 return true;
1594}
1595
1596template <>
1597bool AVRExpandPseudo::expand<AVR::POPWRd>(Block &MBB, BlockIt MBBI) {
1598 MachineInstr &MI = *MBBI;
1599 Register DstLoReg, DstHiReg;
1600 Register DstReg = MI.getOperand(0).getReg();
1601 unsigned Flags = MI.getFlags();
1602 unsigned OpLo = AVR::POPRd;
1603 unsigned OpHi = AVR::POPRd;
1604 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1605
1606 buildMI(MBB, MBBI, OpHi, DstHiReg).setMIFlags(Flags); // High
1607 buildMI(MBB, MBBI, OpLo, DstLoReg).setMIFlags(Flags); // Low
1608
1609 MI.eraseFromParent();
1610 return true;
1611}
1612
1613bool AVRExpandPseudo::expandROLBRd(Block &MBB, BlockIt MBBI) {
1614 // In AVR, the rotate instructions behave quite unintuitively. They rotate
1615 // bits through the carry bit in SREG, effectively rotating over 9 bits,
1616 // instead of 8. This is useful when we are dealing with numbers over
1617 // multiple registers, but when we actually need to rotate stuff, we have
1618 // to explicitly add the carry bit.
1619
1620 MachineInstr &MI = *MBBI;
1621 unsigned OpShift, OpCarry;
1622 Register DstReg = MI.getOperand(0).getReg();
1623 Register ZeroReg = MI.getOperand(3).getReg();
1624 bool DstIsDead = MI.getOperand(0).isDead();
1625 bool DstIsKill = MI.getOperand(1).isKill();
1626 OpShift = AVR::ADDRdRr;
1627 OpCarry = AVR::ADCRdRr;
1628
1629 // add r16, r16
1630 // adc r16, r1
1631
1632 // Shift part
1633 buildMI(MBB, MBBI, OpShift)
1634 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1635 .addReg(DstReg, RegState::Kill)
1636 .addReg(DstReg, RegState::Kill);
1637
1638 // Add the carry bit
1639 auto MIB = buildMI(MBB, MBBI, OpCarry)
1640 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1641 .addReg(DstReg, getKillRegState(DstIsKill))
1642 .addReg(ZeroReg);
1643
1644 MIB->getOperand(3).setIsDead(); // SREG is always dead
1645 MIB->getOperand(4).setIsKill(); // SREG is always implicitly killed
1646
1647 MI.eraseFromParent();
1648 return true;
1649}
1650
1651template <>
1652bool AVRExpandPseudo::expand<AVR::ROLBRdR1>(Block &MBB, BlockIt MBBI) {
1653 return expandROLBRd(MBB, MBBI);
1654}
1655
1656template <>
1657bool AVRExpandPseudo::expand<AVR::ROLBRdR17>(Block &MBB, BlockIt MBBI) {
1658 return expandROLBRd(MBB, MBBI);
1659}
1660
1661template <>
1662bool AVRExpandPseudo::expand<AVR::RORBRd>(Block &MBB, BlockIt MBBI) {
1663 // In AVR, the rotate instructions behave quite unintuitively. They rotate
1664 // bits through the carry bit in SREG, effectively rotating over 9 bits,
1665 // instead of 8. This is useful when we are dealing with numbers over
1666 // multiple registers, but when we actually need to rotate stuff, we have
1667 // to explicitly add the carry bit.
1668
1669 MachineInstr &MI = *MBBI;
1670 Register DstReg = MI.getOperand(0).getReg();
1671
1672 // bst r16, 0
1673 // ror r16
1674 // bld r16, 7
1675
1676 // Move the lowest bit from DstReg into the T bit
1677 buildMI(MBB, MBBI, AVR::BST).addReg(DstReg).addImm(0);
1678
1679 // Rotate to the right
1680 buildMI(MBB, MBBI, AVR::RORRd, DstReg).addReg(DstReg);
1681
1682 // Move the T bit into the highest bit of DstReg.
1683 buildMI(MBB, MBBI, AVR::BLD, DstReg).addReg(DstReg).addImm(7);
1684
1685 MI.eraseFromParent();
1686 return true;
1687}
1688
1689template <>
1690bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {
1691 MachineInstr &MI = *MBBI;
1692 Register DstLoReg, DstHiReg;
1693 Register DstReg = MI.getOperand(0).getReg();
1694 bool DstIsDead = MI.getOperand(0).isDead();
1695 bool DstIsKill = MI.getOperand(1).isKill();
1696 bool ImpIsDead = MI.getOperand(2).isDead();
1697 unsigned OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd
1698 unsigned OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd
1699 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1700
1701 // Low part
1702 buildMI(MBB, MBBI, OpLo)
1703 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1704 .addReg(DstLoReg, getKillRegState(DstIsKill))
1705 .addReg(DstLoReg, getKillRegState(DstIsKill));
1706
1707 auto MIBHI =
1708 buildMI(MBB, MBBI, OpHi)
1709 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1710 .addReg(DstHiReg, getKillRegState(DstIsKill))
1711 .addReg(DstHiReg, getKillRegState(DstIsKill));
1712
1713 if (ImpIsDead)
1714 MIBHI->getOperand(3).setIsDead();
1715
1716 // SREG is always implicitly killed
1717 MIBHI->getOperand(4).setIsKill();
1718
1719 MI.eraseFromParent();
1720 return true;
1721}
1722
1723template <>
1724bool AVRExpandPseudo::expand<AVR::LSLWHiRd>(Block &MBB, BlockIt MBBI) {
1725 MachineInstr &MI = *MBBI;
1726 Register DstLoReg, DstHiReg;
1727 Register DstReg = MI.getOperand(0).getReg();
1728 bool DstIsDead = MI.getOperand(0).isDead();
1729 bool DstIsKill = MI.getOperand(1).isKill();
1730 bool ImpIsDead = MI.getOperand(2).isDead();
1731 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1732
1733 // add hireg, hireg <==> lsl hireg
1734 auto MILSL =
1735 buildMI(MBB, MBBI, AVR::ADDRdRr)
1736 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1737 .addReg(DstHiReg, getKillRegState(DstIsKill))
1738 .addReg(DstHiReg, getKillRegState(DstIsKill));
1739
1740 if (ImpIsDead)
1741 MILSL->getOperand(3).setIsDead();
1742
1743 MI.eraseFromParent();
1744 return true;
1745}
1746
1747bool AVRExpandPseudo::expandLSLW4Rd(Block &MBB, BlockIt MBBI) {
1748 MachineInstr &MI = *MBBI;
1749 Register DstLoReg, DstHiReg;
1750 Register DstReg = MI.getOperand(0).getReg();
1751 bool DstIsDead = MI.getOperand(0).isDead();
1752 bool DstIsKill = MI.getOperand(1).isKill();
1753 bool ImpIsDead = MI.getOperand(3).isDead();
1754 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1755
1756 // swap Rh
1757 // swap Rl
1758 buildMI(MBB, MBBI, AVR::SWAPRd)
1759 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1760 .addReg(DstHiReg, RegState::Kill);
1761 buildMI(MBB, MBBI, AVR::SWAPRd)
1762 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1763 .addReg(DstLoReg, RegState::Kill);
1764
1765 // andi Rh, 0xf0
1766 auto MI0 =
1767 buildMI(MBB, MBBI, AVR::ANDIRdK)
1768 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1769 .addReg(DstHiReg, RegState::Kill)
1770 .addImm(0xf0);
1771 // SREG is implicitly dead.
1772 MI0->getOperand(3).setIsDead();
1773
1774 // eor Rh, Rl
1775 auto MI1 =
1776 buildMI(MBB, MBBI, AVR::EORRdRr)
1777 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1778 .addReg(DstHiReg, RegState::Kill)
1779 .addReg(DstLoReg);
1780 // SREG is implicitly dead.
1781 MI1->getOperand(3).setIsDead();
1782
1783 // andi Rl, 0xf0
1784 auto MI2 =
1785 buildMI(MBB, MBBI, AVR::ANDIRdK)
1786 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1787 .addReg(DstLoReg, getKillRegState(DstIsKill))
1788 .addImm(0xf0);
1789 // SREG is implicitly dead.
1790 MI2->getOperand(3).setIsDead();
1791
1792 // eor Rh, Rl
1793 auto MI3 =
1794 buildMI(MBB, MBBI, AVR::EORRdRr)
1795 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1796 .addReg(DstHiReg, getKillRegState(DstIsKill))
1797 .addReg(DstLoReg);
1798 if (ImpIsDead)
1799 MI3->getOperand(3).setIsDead();
1800
1801 MI.eraseFromParent();
1802 return true;
1803}
1804
1805bool AVRExpandPseudo::expandLSLW8Rd(Block &MBB, BlockIt MBBI) {
1806 MachineInstr &MI = *MBBI;
1807 Register DstLoReg, DstHiReg;
1808 Register DstReg = MI.getOperand(0).getReg();
1809 bool DstIsDead = MI.getOperand(0).isDead();
1810 bool DstIsKill = MI.getOperand(1).isKill();
1811 bool ImpIsDead = MI.getOperand(3).isDead();
1812 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1813
1814 // mov Rh, Rl
1815 buildMI(MBB, MBBI, AVR::MOVRdRr)
1816 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1817 .addReg(DstLoReg);
1818
1819 // clr Rl
1820 auto MIBLO =
1821 buildMI(MBB, MBBI, AVR::EORRdRr)
1822 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1823 .addReg(DstLoReg, getKillRegState(DstIsKill))
1824 .addReg(DstLoReg, getKillRegState(DstIsKill));
1825 if (ImpIsDead)
1826 MIBLO->getOperand(3).setIsDead();
1827
1828 MI.eraseFromParent();
1829 return true;
1830}
1831
1832bool AVRExpandPseudo::expandLSLW12Rd(Block &MBB, BlockIt MBBI) {
1833 MachineInstr &MI = *MBBI;
1834 Register DstLoReg, DstHiReg;
1835 Register DstReg = MI.getOperand(0).getReg();
1836 bool DstIsDead = MI.getOperand(0).isDead();
1837 bool DstIsKill = MI.getOperand(1).isKill();
1838 bool ImpIsDead = MI.getOperand(3).isDead();
1839 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1840
1841 // mov Rh, Rl
1842 buildMI(MBB, MBBI, AVR::MOVRdRr)
1843 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1844 .addReg(DstLoReg);
1845
1846 // swap Rh
1847 buildMI(MBB, MBBI, AVR::SWAPRd)
1848 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1849 .addReg(DstHiReg, RegState::Kill);
1850
1851 // andi Rh, 0xf0
1852 auto MI0 =
1853 buildMI(MBB, MBBI, AVR::ANDIRdK)
1854 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1855 .addReg(DstHiReg, getKillRegState(DstIsKill))
1856 .addImm(0xf0);
1857 // SREG is implicitly dead.
1858 MI0->getOperand(3).setIsDead();
1859
1860 // clr Rl
1861 auto MI1 =
1862 buildMI(MBB, MBBI, AVR::EORRdRr)
1863 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1864 .addReg(DstLoReg, getKillRegState(DstIsKill))
1865 .addReg(DstLoReg, getKillRegState(DstIsKill));
1866 if (ImpIsDead)
1867 MI1->getOperand(3).setIsDead();
1868
1869 MI.eraseFromParent();
1870 return true;
1871}
1872
1873template <>
1874bool AVRExpandPseudo::expand<AVR::LSLWNRd>(Block &MBB, BlockIt MBBI) {
1875 MachineInstr &MI = *MBBI;
1876 unsigned Imm = MI.getOperand(2).getImm();
1877 switch (Imm) {
1878 case 4:
1879 return expandLSLW4Rd(MBB, MBBI);
1880 case 8:
1881 return expandLSLW8Rd(MBB, MBBI);
1882 case 12:
1883 return expandLSLW12Rd(MBB, MBBI);
1884 default:
1885 llvm_unreachable("unimplemented lslwn");
1886 return false;
1887 }
1888}
1889
1890template <>
1891bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
1892 MachineInstr &MI = *MBBI;
1893 Register DstLoReg, DstHiReg;
1894 Register DstReg = MI.getOperand(0).getReg();
1895 bool DstIsDead = MI.getOperand(0).isDead();
1896 bool DstIsKill = MI.getOperand(1).isKill();
1897 bool ImpIsDead = MI.getOperand(2).isDead();
1898 unsigned OpLo = AVR::RORRd;
1899 unsigned OpHi = AVR::LSRRd;
1900 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1901
1902 // High part
1903 buildMI(MBB, MBBI, OpHi)
1904 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1905 .addReg(DstHiReg, getKillRegState(DstIsKill));
1906
1907 auto MIBLO =
1908 buildMI(MBB, MBBI, OpLo)
1909 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1910 .addReg(DstLoReg, getKillRegState(DstIsKill));
1911
1912 if (ImpIsDead)
1913 MIBLO->getOperand(2).setIsDead();
1914
1915 // SREG is always implicitly killed
1916 MIBLO->getOperand(3).setIsKill();
1917
1918 MI.eraseFromParent();
1919 return true;
1920}
1921
1922template <>
1923bool AVRExpandPseudo::expand<AVR::LSRWLoRd>(Block &MBB, BlockIt MBBI) {
1924 MachineInstr &MI = *MBBI;
1925 Register DstLoReg, DstHiReg;
1926 Register DstReg = MI.getOperand(0).getReg();
1927 bool DstIsDead = MI.getOperand(0).isDead();
1928 bool DstIsKill = MI.getOperand(1).isKill();
1929 bool ImpIsDead = MI.getOperand(2).isDead();
1930 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1931
1932 // lsr loreg
1933 auto MILSR =
1934 buildMI(MBB, MBBI, AVR::LSRRd)
1935 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1936 .addReg(DstLoReg, getKillRegState(DstIsKill));
1937
1938 if (ImpIsDead)
1939 MILSR->getOperand(2).setIsDead();
1940
1941 MI.eraseFromParent();
1942 return true;
1943}
1944
1945bool AVRExpandPseudo::expandLSRW4Rd(Block &MBB, BlockIt MBBI) {
1946 MachineInstr &MI = *MBBI;
1947 Register DstLoReg, DstHiReg;
1948 Register DstReg = MI.getOperand(0).getReg();
1949 bool DstIsDead = MI.getOperand(0).isDead();
1950 bool DstIsKill = MI.getOperand(1).isKill();
1951 bool ImpIsDead = MI.getOperand(3).isDead();
1952 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1953
1954 // swap Rh
1955 // swap Rl
1956 buildMI(MBB, MBBI, AVR::SWAPRd)
1957 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1958 .addReg(DstHiReg, RegState::Kill);
1959 buildMI(MBB, MBBI, AVR::SWAPRd)
1960 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1961 .addReg(DstLoReg, RegState::Kill);
1962
1963 // andi Rl, 0xf
1964 auto MI0 =
1965 buildMI(MBB, MBBI, AVR::ANDIRdK)
1966 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1967 .addReg(DstLoReg, RegState::Kill)
1968 .addImm(0xf);
1969 // SREG is implicitly dead.
1970 MI0->getOperand(3).setIsDead();
1971
1972 // eor Rl, Rh
1973 auto MI1 =
1974 buildMI(MBB, MBBI, AVR::EORRdRr)
1975 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1976 .addReg(DstLoReg, RegState::Kill)
1977 .addReg(DstHiReg);
1978 // SREG is implicitly dead.
1979 MI1->getOperand(3).setIsDead();
1980
1981 // andi Rh, 0xf
1982 auto MI2 =
1983 buildMI(MBB, MBBI, AVR::ANDIRdK)
1984 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1985 .addReg(DstHiReg, getKillRegState(DstIsKill))
1986 .addImm(0xf);
1987 // SREG is implicitly dead.
1988 MI2->getOperand(3).setIsDead();
1989
1990 // eor Rl, Rh
1991 auto MI3 =
1992 buildMI(MBB, MBBI, AVR::EORRdRr)
1993 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1994 .addReg(DstLoReg, getKillRegState(DstIsKill))
1995 .addReg(DstHiReg);
1996 if (ImpIsDead)
1997 MI3->getOperand(3).setIsDead();
1998
1999 MI.eraseFromParent();
2000 return true;
2001}
2002
2003bool AVRExpandPseudo::expandLSRW8Rd(Block &MBB, BlockIt MBBI) {
2004 MachineInstr &MI = *MBBI;
2005 Register DstLoReg, DstHiReg;
2006 Register DstReg = MI.getOperand(0).getReg();
2007 bool DstIsDead = MI.getOperand(0).isDead();
2008 bool DstIsKill = MI.getOperand(1).isKill();
2009 bool ImpIsDead = MI.getOperand(3).isDead();
2010 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2011
2012 // Move upper byte to lower byte.
2013 buildMI(MBB, MBBI, AVR::MOVRdRr)
2014 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2015 .addReg(DstHiReg);
2016
2017 // Clear upper byte.
2018 auto MIBHI =
2019 buildMI(MBB, MBBI, AVR::EORRdRr)
2020 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2021 .addReg(DstHiReg, getKillRegState(DstIsKill))
2022 .addReg(DstHiReg, getKillRegState(DstIsKill));
2023 if (ImpIsDead)
2024 MIBHI->getOperand(3).setIsDead();
2025
2026 MI.eraseFromParent();
2027 return true;
2028}
2029
2030bool AVRExpandPseudo::expandLSRW12Rd(Block &MBB, BlockIt MBBI) {
2031 MachineInstr &MI = *MBBI;
2032 Register DstLoReg, DstHiReg;
2033 Register DstReg = MI.getOperand(0).getReg();
2034 bool DstIsDead = MI.getOperand(0).isDead();
2035 bool DstIsKill = MI.getOperand(1).isKill();
2036 bool ImpIsDead = MI.getOperand(3).isDead();
2037 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2038
2039 // Move upper byte to lower byte.
2040 buildMI(MBB, MBBI, AVR::MOVRdRr)
2041 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2042 .addReg(DstHiReg);
2043
2044 // swap Rl
2045 buildMI(MBB, MBBI, AVR::SWAPRd)
2046 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2047 .addReg(DstLoReg, RegState::Kill);
2048
2049 // andi Rl, 0xf
2050 auto MI0 =
2051 buildMI(MBB, MBBI, AVR::ANDIRdK)
2052 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2053 .addReg(DstLoReg, getKillRegState(DstIsKill))
2054 .addImm(0xf);
2055 // SREG is implicitly dead.
2056 MI0->getOperand(3).setIsDead();
2057
2058 // Clear upper byte.
2059 auto MIBHI =
2060 buildMI(MBB, MBBI, AVR::EORRdRr)
2061 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2062 .addReg(DstHiReg, getKillRegState(DstIsKill))
2063 .addReg(DstHiReg, getKillRegState(DstIsKill));
2064 if (ImpIsDead)
2065 MIBHI->getOperand(3).setIsDead();
2066
2067 MI.eraseFromParent();
2068 return true;
2069}
2070
2071template <>
2072bool AVRExpandPseudo::expand<AVR::LSRWNRd>(Block &MBB, BlockIt MBBI) {
2073 MachineInstr &MI = *MBBI;
2074 unsigned Imm = MI.getOperand(2).getImm();
2075 switch (Imm) {
2076 case 4:
2077 return expandLSRW4Rd(MBB, MBBI);
2078 case 8:
2079 return expandLSRW8Rd(MBB, MBBI);
2080 case 12:
2081 return expandLSRW12Rd(MBB, MBBI);
2082 default:
2083 llvm_unreachable("unimplemented lsrwn");
2084 return false;
2085 }
2086}
2087
2088template <>
2089bool AVRExpandPseudo::expand<AVR::RORWRd>(Block &MBB, BlockIt MBBI) {
2090 llvm_unreachable("RORW unimplemented");
2091 return false;
2092}
2093
2094template <>
2095bool AVRExpandPseudo::expand<AVR::ROLWRd>(Block &MBB, BlockIt MBBI) {
2096 llvm_unreachable("ROLW unimplemented");
2097 return false;
2098}
2099
2100template <>
2101bool AVRExpandPseudo::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) {
2102 MachineInstr &MI = *MBBI;
2103 Register DstLoReg, DstHiReg;
2104 Register DstReg = MI.getOperand(0).getReg();
2105 bool DstIsDead = MI.getOperand(0).isDead();
2106 bool DstIsKill = MI.getOperand(1).isKill();
2107 bool ImpIsDead = MI.getOperand(2).isDead();
2108 unsigned OpLo = AVR::RORRd;
2109 unsigned OpHi = AVR::ASRRd;
2110 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2111
2112 // High part
2113 buildMI(MBB, MBBI, OpHi)
2114 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2115 .addReg(DstHiReg, getKillRegState(DstIsKill));
2116
2117 auto MIBLO =
2118 buildMI(MBB, MBBI, OpLo)
2119 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2120 .addReg(DstLoReg, getKillRegState(DstIsKill));
2121
2122 if (ImpIsDead)
2123 MIBLO->getOperand(2).setIsDead();
2124
2125 // SREG is always implicitly killed
2126 MIBLO->getOperand(3).setIsKill();
2127
2128 MI.eraseFromParent();
2129 return true;
2130}
2131
2132template <>
2133bool AVRExpandPseudo::expand<AVR::ASRWLoRd>(Block &MBB, BlockIt MBBI) {
2134 MachineInstr &MI = *MBBI;
2135 Register DstLoReg, DstHiReg;
2136 Register DstReg = MI.getOperand(0).getReg();
2137 bool DstIsDead = MI.getOperand(0).isDead();
2138 bool DstIsKill = MI.getOperand(1).isKill();
2139 bool ImpIsDead = MI.getOperand(2).isDead();
2140 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2141
2142 // asr loreg
2143 auto MIASR =
2144 buildMI(MBB, MBBI, AVR::ASRRd)
2145 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2146 .addReg(DstLoReg, getKillRegState(DstIsKill));
2147
2148 if (ImpIsDead)
2149 MIASR->getOperand(2).setIsDead();
2150
2151 MI.eraseFromParent();
2152 return true;
2153}
2154
2155bool AVRExpandPseudo::expandASRW7Rd(Block &MBB, BlockIt MBBI) {
2156 MachineInstr &MI = *MBBI;
2157 Register DstLoReg, DstHiReg;
2158 Register DstReg = MI.getOperand(0).getReg();
2159 bool DstIsDead = MI.getOperand(0).isDead();
2160 bool DstIsKill = MI.getOperand(1).isKill();
2161 bool ImpIsDead = MI.getOperand(3).isDead();
2162 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2163
2164 // lsl r24
2165 // mov r24,r25
2166 // rol r24
2167 // sbc r25,r25
2168
2169 // lsl r24 <=> add r24, r24
2170 buildMI(MBB, MBBI, AVR::ADDRdRr)
2171 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2172 .addReg(DstLoReg, RegState::Kill)
2173 .addReg(DstLoReg, RegState::Kill);
2174
2175 // mov r24, r25
2176 buildMI(MBB, MBBI, AVR::MOVRdRr)
2177 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2178 .addReg(DstHiReg);
2179
2180 // rol r24 <=> adc r24, r24
2181 buildMI(MBB, MBBI, AVR::ADCRdRr)
2182 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2183 .addReg(DstLoReg, getKillRegState(DstIsKill))
2184 .addReg(DstLoReg, getKillRegState(DstIsKill));
2185
2186 // sbc r25, r25
2187 auto MISBC =
2188 buildMI(MBB, MBBI, AVR::SBCRdRr)
2189 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2190 .addReg(DstHiReg, getKillRegState(DstIsKill))
2191 .addReg(DstHiReg, getKillRegState(DstIsKill));
2192
2193 if (ImpIsDead)
2194 MISBC->getOperand(3).setIsDead();
2195 // SREG is always implicitly killed
2196 MISBC->getOperand(4).setIsKill();
2197
2198 MI.eraseFromParent();
2199 return true;
2200}
2201
2202bool AVRExpandPseudo::expandASRW8Rd(Block &MBB, BlockIt MBBI) {
2203 MachineInstr &MI = *MBBI;
2204 Register DstLoReg, DstHiReg;
2205 Register DstReg = MI.getOperand(0).getReg();
2206 bool DstIsDead = MI.getOperand(0).isDead();
2207 bool DstIsKill = MI.getOperand(1).isKill();
2208 bool ImpIsDead = MI.getOperand(3).isDead();
2209 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2210
2211 // Move upper byte to lower byte.
2212 buildMI(MBB, MBBI, AVR::MOVRdRr)
2213 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2214 .addReg(DstHiReg);
2215
2216 // Move the sign bit to the C flag.
2217 buildMI(MBB, MBBI, AVR::ADDRdRr)
2218 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2219 .addReg(DstHiReg, RegState::Kill)
2220 .addReg(DstHiReg, RegState::Kill);
2221
2222 // Set upper byte to 0 or -1.
2223 auto MIBHI =
2224 buildMI(MBB, MBBI, AVR::SBCRdRr)
2225 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2226 .addReg(DstHiReg, getKillRegState(DstIsKill))
2227 .addReg(DstHiReg, getKillRegState(DstIsKill));
2228
2229 if (ImpIsDead)
2230 MIBHI->getOperand(3).setIsDead();
2231 // SREG is always implicitly killed
2232 MIBHI->getOperand(4).setIsKill();
2233
2234 MI.eraseFromParent();
2235 return true;
2236}
2237bool AVRExpandPseudo::expandASRW14Rd(Block &MBB, BlockIt MBBI) {
2238 MachineInstr &MI = *MBBI;
2239 Register DstLoReg, DstHiReg;
2240 Register DstReg = MI.getOperand(0).getReg();
2241 bool DstIsDead = MI.getOperand(0).isDead();
2242 bool DstIsKill = MI.getOperand(1).isKill();
2243 bool ImpIsDead = MI.getOperand(3).isDead();
2244 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2245
2246 // lsl r25
2247 // sbc r24, r24
2248 // lsl r25
2249 // mov r25, r24
2250 // rol r24
2251
2252 // lsl r25 <=> add r25, r25
2253 buildMI(MBB, MBBI, AVR::ADDRdRr)
2254 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2255 .addReg(DstHiReg, RegState::Kill)
2256 .addReg(DstHiReg, RegState::Kill);
2257
2258 // sbc r24, r24
2259 buildMI(MBB, MBBI, AVR::SBCRdRr)
2260 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2261 .addReg(DstLoReg, RegState::Kill)
2262 .addReg(DstLoReg, RegState::Kill);
2263
2264 // lsl r25 <=> add r25, r25
2265 buildMI(MBB, MBBI, AVR::ADDRdRr)
2266 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2267 .addReg(DstHiReg, RegState::Kill)
2268 .addReg(DstHiReg, RegState::Kill);
2269
2270 // mov r25, r24
2271 buildMI(MBB, MBBI, AVR::MOVRdRr)
2272 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2273 .addReg(DstLoReg);
2274
2275 // rol r24 <=> adc r24, r24
2276 auto MIROL =
2277 buildMI(MBB, MBBI, AVR::ADCRdRr)
2278 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2279 .addReg(DstLoReg, getKillRegState(DstIsKill))
2280 .addReg(DstLoReg, getKillRegState(DstIsKill));
2281
2282 if (ImpIsDead)
2283 MIROL->getOperand(3).setIsDead();
2284 // SREG is always implicitly killed
2285 MIROL->getOperand(4).setIsKill();
2286
2287 MI.eraseFromParent();
2288 return false;
2289}
2290
2291bool AVRExpandPseudo::expandASRW15Rd(Block &MBB, BlockIt MBBI) {
2292 MachineInstr &MI = *MBBI;
2293 Register DstLoReg, DstHiReg;
2294 Register DstReg = MI.getOperand(0).getReg();
2295 bool DstIsDead = MI.getOperand(0).isDead();
2296 bool ImpIsDead = MI.getOperand(3).isDead();
2297 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2298
2299 // lsl r25
2300 // sbc r25, r25
2301 // mov r24, r25
2302
2303 // lsl r25 <=> add r25, r25
2304 buildMI(MBB, MBBI, AVR::ADDRdRr)
2305 .addReg(DstHiReg, RegState::Define)
2306 .addReg(DstHiReg, RegState::Kill)
2307 .addReg(DstHiReg, RegState::Kill);
2308
2309 // sbc r25, r25
2310 auto MISBC =
2311 buildMI(MBB, MBBI, AVR::SBCRdRr)
2312 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2313 .addReg(DstHiReg, RegState::Kill)
2314 .addReg(DstHiReg, RegState::Kill);
2315 if (ImpIsDead)
2316 MISBC->getOperand(3).setIsDead();
2317 // SREG is always implicitly killed
2318 MISBC->getOperand(4).setIsKill();
2319
2320 // mov r24, r25
2321 buildMI(MBB, MBBI, AVR::MOVRdRr)
2322 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2323 .addReg(DstHiReg);
2324
2325 MI.eraseFromParent();
2326 return true;
2327}
2328
2329template <>
2330bool AVRExpandPseudo::expand<AVR::ASRWNRd>(Block &MBB, BlockIt MBBI) {
2331 MachineInstr &MI = *MBBI;
2332 unsigned Imm = MI.getOperand(2).getImm();
2333 switch (Imm) {
2334 case 7:
2335 return expandASRW7Rd(MBB, MBBI);
2336 case 8:
2337 return expandASRW8Rd(MBB, MBBI);
2338 case 14:
2339 return expandASRW14Rd(MBB, MBBI);
2340 case 15:
2341 return expandASRW15Rd(MBB, MBBI);
2342 default:
2343 llvm_unreachable("unimplemented asrwn");
2344 return false;
2345 }
2346}
2347
2348bool AVRExpandPseudo::expandLSLB7Rd(Block &MBB, BlockIt MBBI) {
2349 MachineInstr &MI = *MBBI;
2350 Register DstReg = MI.getOperand(0).getReg();
2351 bool DstIsDead = MI.getOperand(0).isDead();
2352 bool DstIsKill = MI.getOperand(1).isKill();
2353 bool ImpIsDead = MI.getOperand(3).isDead();
2354
2355 // ror r24
2356 // clr r24
2357 // ror r24
2358
2359 buildMI(MBB, MBBI, AVR::RORRd)
2360 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2361 .addReg(DstReg, RegState::Kill)
2362 ->getOperand(3)
2363 .setIsUndef(true);
2364
2365 buildMI(MBB, MBBI, AVR::EORRdRr)
2366 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2367 .addReg(DstReg, RegState::Kill)
2368 .addReg(DstReg, RegState::Kill);
2369
2370 auto MIRRC =
2371 buildMI(MBB, MBBI, AVR::RORRd)
2372 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2373 .addReg(DstReg, getKillRegState(DstIsKill));
2374
2375 if (ImpIsDead)
2376 MIRRC->getOperand(2).setIsDead();
2377
2378 // SREG is always implicitly killed
2379 MIRRC->getOperand(3).setIsKill();
2380
2381 MI.eraseFromParent();
2382 return true;
2383}
2384
2385template <>
2386bool AVRExpandPseudo::expand<AVR::LSLBNRd>(Block &MBB, BlockIt MBBI) {
2387 MachineInstr &MI = *MBBI;
2388 unsigned Imm = MI.getOperand(2).getImm();
2389 switch (Imm) {
2390 case 7:
2391 return expandLSLB7Rd(MBB, MBBI);
2392 default:
2393 llvm_unreachable("unimplemented lslbn");
2394 return false;
2395 }
2396}
2397
2398bool AVRExpandPseudo::expandLSRB7Rd(Block &MBB, BlockIt MBBI) {
2399 MachineInstr &MI = *MBBI;
2400 Register DstReg = MI.getOperand(0).getReg();
2401 bool DstIsDead = MI.getOperand(0).isDead();
2402 bool DstIsKill = MI.getOperand(1).isKill();
2403 bool ImpIsDead = MI.getOperand(3).isDead();
2404
2405 // rol r24
2406 // clr r24
2407 // rol r24
2408
2409 buildMI(MBB, MBBI, AVR::ADCRdRr)
2410 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2411 .addReg(DstReg, RegState::Kill)
2412 .addReg(DstReg, RegState::Kill)
2413 ->getOperand(4)
2414 .setIsUndef(true);
2415
2416 buildMI(MBB, MBBI, AVR::EORRdRr)
2417 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2418 .addReg(DstReg, RegState::Kill)
2419 .addReg(DstReg, RegState::Kill);
2420
2421 auto MIRRC =
2422 buildMI(MBB, MBBI, AVR::ADCRdRr)
2423 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2424 .addReg(DstReg, getKillRegState(DstIsKill))
2425 .addReg(DstReg, getKillRegState(DstIsKill));
2426
2427 if (ImpIsDead)
2428 MIRRC->getOperand(3).setIsDead();
2429
2430 // SREG is always implicitly killed
2431 MIRRC->getOperand(4).setIsKill();
2432
2433 MI.eraseFromParent();
2434 return true;
2435}
2436
2437template <>
2438bool AVRExpandPseudo::expand<AVR::LSRBNRd>(Block &MBB, BlockIt MBBI) {
2439 MachineInstr &MI = *MBBI;
2440 unsigned Imm = MI.getOperand(2).getImm();
2441 switch (Imm) {
2442 case 7:
2443 return expandLSRB7Rd(MBB, MBBI);
2444 default:
2445 llvm_unreachable("unimplemented lsrbn");
2446 return false;
2447 }
2448}
2449
2450bool AVRExpandPseudo::expandASRB6Rd(Block &MBB, BlockIt MBBI) {
2451 MachineInstr &MI = *MBBI;
2452 Register DstReg = MI.getOperand(0).getReg();
2453 bool DstIsDead = MI.getOperand(0).isDead();
2454 bool DstIsKill = MI.getOperand(1).isKill();
2455
2456 // bst r24, 6
2457 // lsl r24
2458 // sbc r24, r24
2459 // bld r24, 0
2460
2461 buildMI(MBB, MBBI, AVR::BST)
2462 .addReg(DstReg)
2463 .addImm(6)
2464 ->getOperand(2)
2465 .setIsUndef(true);
2466
2467 buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rd
2468 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2469 .addReg(DstReg, RegState::Kill)
2470 .addReg(DstReg, RegState::Kill);
2471
2472 buildMI(MBB, MBBI, AVR::SBCRdRr)
2473 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2474 .addReg(DstReg, RegState::Kill)
2475 .addReg(DstReg, RegState::Kill);
2476
2477 buildMI(MBB, MBBI, AVR::BLD)
2478 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2479 .addReg(DstReg, getKillRegState(DstIsKill))
2480 .addImm(0)
2481 ->getOperand(3)
2482 .setIsKill();
2483
2484 MI.eraseFromParent();
2485 return true;
2486}
2487
2488bool AVRExpandPseudo::expandASRB7Rd(Block &MBB, BlockIt MBBI) {
2489 MachineInstr &MI = *MBBI;
2490 Register DstReg = MI.getOperand(0).getReg();
2491 bool DstIsDead = MI.getOperand(0).isDead();
2492 bool DstIsKill = MI.getOperand(1).isKill();
2493 bool ImpIsDead = MI.getOperand(3).isDead();
2494
2495 // lsl r24
2496 // sbc r24, r24
2497
2498 buildMI(MBB, MBBI, AVR::ADDRdRr)
2499 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2500 .addReg(DstReg, RegState::Kill)
2501 .addReg(DstReg, RegState::Kill);
2502
2503 auto MIRRC =
2504 buildMI(MBB, MBBI, AVR::SBCRdRr)
2505 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2506 .addReg(DstReg, getKillRegState(DstIsKill))
2507 .addReg(DstReg, getKillRegState(DstIsKill));
2508
2509 if (ImpIsDead)
2510 MIRRC->getOperand(3).setIsDead();
2511
2512 // SREG is always implicitly killed
2513 MIRRC->getOperand(4).setIsKill();
2514
2515 MI.eraseFromParent();
2516 return true;
2517}
2518
2519template <>
2520bool AVRExpandPseudo::expand<AVR::ASRBNRd>(Block &MBB, BlockIt MBBI) {
2521 MachineInstr &MI = *MBBI;
2522 unsigned Imm = MI.getOperand(2).getImm();
2523 switch (Imm) {
2524 case 6:
2525 return expandASRB6Rd(MBB, MBBI);
2526 case 7:
2527 return expandASRB7Rd(MBB, MBBI);
2528 default:
2529 llvm_unreachable("unimplemented asrbn");
2530 return false;
2531 }
2532}
2533
2534template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
2535 MachineInstr &MI = *MBBI;
2536 Register DstLoReg, DstHiReg;
2537 // sext R17:R16, R17
2538 // mov r16, r17
2539 // lsl r17
2540 // sbc r17, r17
2541 // sext R17:R16, R13
2542 // mov r16, r13
2543 // mov r17, r13
2544 // lsl r17
2545 // sbc r17, r17
2546 // sext R17:R16, R16
2547 // mov r17, r16
2548 // lsl r17
2549 // sbc r17, r17
2550 Register DstReg = MI.getOperand(0).getReg();
2551 Register SrcReg = MI.getOperand(1).getReg();
2552 bool DstIsDead = MI.getOperand(0).isDead();
2553 bool SrcIsKill = MI.getOperand(1).isKill();
2554 bool ImpIsDead = MI.getOperand(2).isDead();
2555 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2556
2557 if (SrcReg != DstLoReg)
2558 buildMI(MBB, MBBI, AVR::MOVRdRr)
2559 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2560 .addReg(SrcReg);
2561
2562 if (SrcReg != DstHiReg) {
2563 auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr)
2564 .addReg(DstHiReg, RegState::Define)
2565 .addReg(SrcReg);
2566 if (SrcReg != DstLoReg && SrcIsKill)
2567 MOV->getOperand(1).setIsKill();
2568 }
2569
2570 buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
2571 .addReg(DstHiReg, RegState::Define)
2572 .addReg(DstHiReg, RegState::Kill)
2573 .addReg(DstHiReg, RegState::Kill);
2574
2575 auto SBC =
2576 buildMI(MBB, MBBI, AVR::SBCRdRr)
2577 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2578 .addReg(DstHiReg, RegState::Kill)
2579 .addReg(DstHiReg, RegState::Kill);
2580
2581 if (ImpIsDead)
2582 SBC->getOperand(3).setIsDead();
2583
2584 // SREG is always implicitly killed
2585 SBC->getOperand(4).setIsKill();
2586
2587 MI.eraseFromParent();
2588 return true;
2589}
2590
2591template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) {
2592 MachineInstr &MI = *MBBI;
2593 Register DstLoReg, DstHiReg;
2594 // zext R25:R24, R20
2595 // mov R24, R20
2596 // eor R25, R25
2597 // zext R25:R24, R24
2598 // eor R25, R25
2599 // zext R25:R24, R25
2600 // mov R24, R25
2601 // eor R25, R25
2602 Register DstReg = MI.getOperand(0).getReg();
2603 Register SrcReg = MI.getOperand(1).getReg();
2604 bool DstIsDead = MI.getOperand(0).isDead();
2605 bool SrcIsKill = MI.getOperand(1).isKill();
2606 bool ImpIsDead = MI.getOperand(2).isDead();
2607 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2608
2609 if (SrcReg != DstLoReg) {
2610 buildMI(MBB, MBBI, AVR::MOVRdRr)
2611 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2612 .addReg(SrcReg, getKillRegState(SrcIsKill));
2613 }
2614
2615 auto EOR =
2616 buildMI(MBB, MBBI, AVR::EORRdRr)
2617 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2618 .addReg(DstHiReg, RegState::Kill | RegState::Undef)
2619 .addReg(DstHiReg, RegState::Kill | RegState::Undef);
2620
2621 if (ImpIsDead)
2622 EOR->getOperand(3).setIsDead();
2623
2624 MI.eraseFromParent();
2625 return true;
2626}
2627
2628template <>
2629bool AVRExpandPseudo::expand<AVR::SPREAD>(Block &MBB, BlockIt MBBI) {
2630 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
2631 MachineInstr &MI = *MBBI;
2632 Register DstLoReg, DstHiReg;
2633 Register DstReg = MI.getOperand(0).getReg();
2634 bool DstIsDead = MI.getOperand(0).isDead();
2635 unsigned Flags = MI.getFlags();
2636 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2637
2638 // Low part
2639 buildMI(MBB, MBBI, AVR::INRdA)
2640 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2641 .addImm(STI.getIORegSPL())
2642 .setMIFlags(Flags);
2643
2644 // High part
2645 if (STI.getIORegSPH() != -1) {
2646 buildMI(MBB, MBBI, AVR::INRdA)
2647 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2648 .addImm(STI.getIORegSPH())
2649 .setMIFlags(Flags);
2650 } else {
2651 // Clear the upper byte if there is no SPH.
2652 auto MI0 =
2653 buildMI(MBB, MBBI, AVR::EORRdRr)
2654 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2655 .addReg(DstHiReg, RegState::Kill | RegState::Undef)
2656 .addReg(DstHiReg, RegState::Kill | RegState::Undef);
2657
2658 // SREG is implicitly dead.
2659 MI0->getOperand(3).setIsDead();
2660 }
2661
2662 MI.eraseFromParent();
2663 return true;
2664}
2665
2666template <>
2667bool AVRExpandPseudo::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {
2668 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
2669 MachineInstr &MI = *MBBI;
2670 Register SrcLoReg, SrcHiReg;
2671 Register SrcReg = MI.getOperand(1).getReg();
2672 bool SrcIsKill = MI.getOperand(1).isKill();
2673 unsigned Flags = MI.getFlags();
2674 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
2675
2676 // From the XMEGA series manual:
2677 // To prevent corruption when updating the stack pointer from software,
2678 // a write to SPL will automatically disable interrupts
2679 // for up to four instructions or until the next I/O memory write.
2680 if (STI.getELFArch() >= 102) { // An XMEGA device
2681 buildMI(MBB, MBBI, AVR::OUTARr)
2682 .addImm(STI.getIORegSPL())
2683 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
2684 .setMIFlags(Flags);
2685
2686 buildMI(MBB, MBBI, AVR::OUTARr)
2687 .addImm(STI.getIORegSPH())
2688 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
2689 .setMIFlags(Flags);
2690 } else { // Disable interrupts for older devices with SPH (3 extra
2691 // instructions)
2692 if (STI.getIORegSPH() != -1) {
2693 buildMI(MBB, MBBI, AVR::INRdA)
2694 .addReg(STI.getTmpRegister(), RegState::Define)
2695 .addImm(STI.getIORegSREG())
2696 .setMIFlags(Flags);
2697
2698 buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
2699
2700 buildMI(MBB, MBBI, AVR::OUTARr)
2701 .addImm(STI.getIORegSPH())
2702 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
2703 .setMIFlags(Flags);
2704
2705 buildMI(MBB, MBBI, AVR::OUTARr)
2706 .addImm(STI.getIORegSREG())
2707 .addReg(STI.getTmpRegister(), RegState::Kill)
2708 .setMIFlags(Flags);
2709 }
2710
2711 buildMI(MBB, MBBI, AVR::OUTARr)
2712 .addImm(STI.getIORegSPL())
2713 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
2714 .setMIFlags(Flags);
2715 }
2716
2717 MI.eraseFromParent();
2718 return true;
2719}
2720
2721template <> bool AVRExpandPseudo::expand<AVR::FRMSP>(Block &MBB, BlockIt MBBI) {
2722 MachineInstr &MI = *MBBI;
2723 MachineFunction &MF = *MI.getMF();
2724 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
2725 DebugLoc DL;
2726 Register ASOPointer = MI.getOperand(0).getReg();
2727 int64_t ASOAlignment = MI.getOperand(1).getImm();
2728
2729 // Note: `FrameReg` is an out-param here - passing `ASOPointer` instead would
2730 // overwrite the register we are supposed to write the aligned stack address
2731 // into.
2732 Register FrameReg;
2733
2734 StackOffset ASOOffset =
2735 MF.getSubtarget<AVRSubtarget>()
2736 .getFrameLowering()
2737 ->getFrameIndexReference(MF, AFI->AlignedStackObjectIdx, FrameReg);
2738
2739 TII->copyPhysReg(MBB, MI, DL, ASOPointer, AVR::R29R28, false, false, false);
2740
2741 buildMI(MBB, MI, AVR::ADIWRdKP)
2742 .addReg(ASOPointer, RegState::Define)
2743 .addReg(ASOPointer, RegState::Kill)
2744 .addImm(ASOOffset.getFixed() + ASOAlignment - 1)
2745 .setOperandDead(3); // implicit-def $sreg
2746
2747 buildMI(MBB, MI, AVR::ANDIWRdK)
2748 .addReg(ASOPointer, RegState::Define)
2749 .addReg(ASOPointer, RegState::Kill)
2750 .addImm(-ASOAlignment)
2751 .setOperandDead(3); // implicit-def $sreg
2752
2753 MI.eraseFromParent();
2754 return true;
2755}
2756
2757bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
2758 MachineInstr &MI = *MBBI;
2759 int Opcode = MBBI->getOpcode();
2760
2761#define EXPAND(Op) \
2762 case Op: \
2763 return expand<Op>(MBB, MI)
2764
2765 switch (Opcode) {
2766 EXPAND(AVR::ADDWRdRr);
2767 EXPAND(AVR::ADCWRdRr);
2768 EXPAND(AVR::ADIWRdKP);
2769 EXPAND(AVR::SUBWRdRr);
2770 EXPAND(AVR::SUBIWRdK);
2771 EXPAND(AVR::SBCWRdRr);
2772 EXPAND(AVR::SBCIWRdK);
2773 EXPAND(AVR::ANDWRdRr);
2774 EXPAND(AVR::ANDIWRdK);
2775 EXPAND(AVR::ORWRdRr);
2776 EXPAND(AVR::ORIWRdK);
2777 EXPAND(AVR::EORWRdRr);
2778 EXPAND(AVR::COMWRd);
2779 EXPAND(AVR::NEGWRd);
2780 EXPAND(AVR::CPWRdRr);
2781 EXPAND(AVR::CPCWRdRr);
2782 EXPAND(AVR::LDIWRdK);
2783 EXPAND(AVR::LDSWRdK);
2784 EXPAND(AVR::LDWRdPtr);
2785 EXPAND(AVR::LDWRdPtrPi);
2786 EXPAND(AVR::LDWRdPtrPd);
2787 EXPAND(AVR::LDDRdPtrQ);
2788 case AVR::LDDWRdYQ: // FIXME: Remove this once PR13375 gets fixed.
2789 EXPAND(AVR::LDDWRdPtrQ);
2790 EXPAND(AVR::LPMBRdZ);
2791 EXPAND(AVR::LPMWRdZ);
2792 EXPAND(AVR::LPMWRdZPi);
2793 EXPAND(AVR::ELPMBRdZ);
2794 EXPAND(AVR::ELPMWRdZ);
2795 EXPAND(AVR::ELPMBRdZPi);
2796 EXPAND(AVR::ELPMWRdZPi);
2797 EXPAND(AVR::AtomicLoad8);
2798 EXPAND(AVR::AtomicLoad16);
2799 EXPAND(AVR::AtomicStore8);
2800 EXPAND(AVR::AtomicStore16);
2801 EXPAND(AVR::AtomicFence);
2802 EXPAND(AVR::STSWKRr);
2803 EXPAND(AVR::STWPtrRr);
2804 EXPAND(AVR::STWPtrPiRr);
2805 EXPAND(AVR::STWPtrPdRr);
2806 EXPAND(AVR::STDPtrQRr);
2807 EXPAND(AVR::STDWPtrQRr);
2808 EXPAND(AVR::STDSPQRr);
2809 EXPAND(AVR::STDWSPQRr);
2810 EXPAND(AVR::INWRdA);
2811 EXPAND(AVR::OUTWARr);
2812 EXPAND(AVR::PUSHWRr);
2813 EXPAND(AVR::POPWRd);
2814 EXPAND(AVR::ROLBRdR1);
2815 EXPAND(AVR::ROLBRdR17);
2816 EXPAND(AVR::RORBRd);
2817 EXPAND(AVR::LSLWRd);
2818 EXPAND(AVR::LSRWRd);
2819 EXPAND(AVR::RORWRd);
2820 EXPAND(AVR::ROLWRd);
2821 EXPAND(AVR::ASRWRd);
2822 EXPAND(AVR::LSLWHiRd);
2823 EXPAND(AVR::LSRWLoRd);
2824 EXPAND(AVR::ASRWLoRd);
2825 EXPAND(AVR::LSLWNRd);
2826 EXPAND(AVR::LSRWNRd);
2827 EXPAND(AVR::ASRWNRd);
2828 EXPAND(AVR::LSLBNRd);
2829 EXPAND(AVR::LSRBNRd);
2830 EXPAND(AVR::ASRBNRd);
2831 EXPAND(AVR::SEXT);
2832 EXPAND(AVR::ZEXT);
2833 EXPAND(AVR::SPREAD);
2834 EXPAND(AVR::SPWRITE);
2835 EXPAND(AVR::FRMSP);
2836 }
2837#undef EXPAND
2838 return false;
2839}
2840
2841} // end of anonymous namespace
2842
2843INITIALIZE_PASS(AVRExpandPseudo, "avr-expand-pseudo", AVR_EXPAND_PSEUDO_NAME,
2844 false, false)
2845
2846FunctionPass *llvm::createAVRExpandPseudoPass() {
2847 return new AVRExpandPseudo();
2848}
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Imm
uint64_t Imm
Definition AMDGPUDisassembler.cpp:552
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
EXPAND
#define EXPAND(Op)
AVR_EXPAND_PSEUDO_NAME
#define AVR_EXPAND_PSEUDO_NAME
Definition AVRExpandPseudoInsts.cpp:28
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
expand
static Expected< BitVector > expand(StringRef S, StringRef Original)
Definition GlobPattern.cpp:26
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:870
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2128
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
llvm::AVRMachineFunctionInfo
Contains AVR-specific information for each MachineFunction.
Definition AVRMachineFunctionInfo.h:22
llvm::AVRRegisterInfo
Utilities relating to AVR registers.
Definition AVRRegisterInfo.h:24
llvm::AVRSubtarget
A specific AVR target MCU.
Definition AVRSubtarget.h:32
llvm::AVRSubtarget::getTmpRegister
Register getTmpRegister() const
Definition AVRSubtarget.h:91
llvm::AVRSubtarget::getELFArch
unsigned getELFArch() const
Gets the ELF architecture for the e_flags field of an ELF object file.
Definition AVRSubtarget.h:74
llvm::AVRSubtarget::getFrameLowering
const TargetFrameLowering * getFrameLowering() const override
Definition AVRSubtarget.h:43
llvm::AVRSubtarget::getIORegRAMPZ
int getIORegRAMPZ() const
Get I/O register addresses.
Definition AVRSubtarget.h:81
llvm::AVRSubtarget::getIORegSPL
int getIORegSPL() const
Definition AVRSubtarget.h:83
llvm::AVRSubtarget::getInstrInfo
const AVRInstrInfo * getInstrInfo() const override
Definition AVRSubtarget.h:42
llvm::AVRSubtarget::getIORegSREG
int getIORegSREG() const
Definition AVRSubtarget.h:85
llvm::AVRSubtarget::getIORegSPH
int getIORegSPH() const
Definition AVRSubtarget.h:84
llvm::AVRSubtarget::getRegisterInfo
const AVRRegisterInfo * getRegisterInfo() const override
Definition AVRSubtarget.h:52
llvm::BlockAddress
The address of a basic block.
Definition Constants.h:1088
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:126
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:312
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:340
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:778
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition MachineFunction.h:890
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:74
llvm::MachineOperand::CreateBA
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
Definition MachineOperand.h:929
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition MachineOperand.h:53
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition MachineOperand.h:62
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition MachineOperand.h:63
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition MachineRegisterInfo.h:55
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::StackOffset
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:31
llvm::StackOffset::getFixed
static StackOffset getFixed(int64_t Fixed)
Definition TypeSize.h:40
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::TargetFrameLowering::hasReservedCallFrame
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition TargetFrameLowering.h:315
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition TargetInstrInfo.h:115
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::AVRII::MO_HI
@ MO_HI
On a symbol operand, this represents the hi part.
Definition AVRInstrInfo.h:57
llvm::AVRII::MO_NEG
@ MO_NEG
On a symbol operand, this represents it has to be negated.
Definition AVRInstrInfo.h:60
llvm::AVRII::MO_LO
@ MO_LO
On a symbol operand, this represents the lo part.
Definition AVRInstrInfo.h:54
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition DefaultTargetInfo.h:21
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition MachineInstrBuilder.h:61
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition MachineInstrBuilder.h:65
llvm::RegState::Define
@ Define
Register definition.
Definition MachineInstrBuilder.h:57
llvm::getKillRegState
constexpr RegState getKillRegState(bool B)
Definition MachineInstrBuilder.h:90
llvm::getDeadRegState
constexpr RegState getDeadRegState(bool B)
Definition MachineInstrBuilder.h:93
llvm::createAVRExpandPseudoPass
FunctionPass * createAVRExpandPseudoPass()
llvm::isUInt
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:190
llvm::Op
DWARFExpression::Operation Op
Definition DWARFExpressionPrinter.cpp:25
llvm::getUndefRegState
constexpr RegState getUndefRegState(bool B)
Definition MachineInstrBuilder.h:96
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