LLVM 24.0.0git
AVRExpandPseudoInsts.cpp
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1//===-- AVRExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AVR.h"
16#include "AVRInstrInfo.h"
17#include "AVRMachineFunctionInfo.h"
18#include "AVRTargetMachine.h"
19#include "MCTargetDesc/AVRMCTargetDesc.h"
20
21#include "llvm/CodeGen/MachineFunctionPass.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/TargetRegisterInfo.h"
25
26using namespace llvm;
27
28#define AVR_EXPAND_PSEUDO_NAME "AVR pseudo instruction expansion pass"
29
30namespace {
31
32/// Expands "placeholder" instructions marked as pseudo into
33/// actual AVR instructions.
34class AVRExpandPseudo : public MachineFunctionPass {
35public:
36 static char ID;
37
38 AVRExpandPseudo() : MachineFunctionPass(ID) {}
39
40 bool runOnMachineFunction(MachineFunction &MF) override;
41
42 StringRef getPassName() const override { return AVR_EXPAND_PSEUDO_NAME; }
43
44private:
45 typedef MachineBasicBlock Block;
46 typedef Block::iterator BlockIt;
47
48 const AVRRegisterInfo *TRI;
49 const TargetInstrInfo *TII;
50
51 bool expandMBB(Block &MBB);
52 bool expandMI(Block &MBB, BlockIt MBBI);
53 template <unsigned OP> bool expand(Block &MBB, BlockIt MBBI);
54
55 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
56 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
57 }
58
59 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode,
60 Register DstReg) {
61 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
62 }
63
64 MachineRegisterInfo &getRegInfo(Block &MBB) {
65 return MBB.getParent()->getRegInfo();
66 }
67
68 bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
69 bool expandLogic(unsigned Op, Block &MBB, BlockIt MBBI);
70 bool expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI);
71 bool isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const;
72 bool isLogicRegOpUndef(unsigned Op, unsigned ImmVal) const;
73
74 template <typename Func> bool expandAtomic(Block &MBB, BlockIt MBBI, Func f);
75
76 template <typename Func>
77 bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI, Func f);
78
79 bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI);
80
81 /// Specific shift implementation for int8.
82 bool expandLSLB7Rd(Block &MBB, BlockIt MBBI);
83 bool expandLSRB7Rd(Block &MBB, BlockIt MBBI);
84 bool expandASRB6Rd(Block &MBB, BlockIt MBBI);
85 bool expandASRB7Rd(Block &MBB, BlockIt MBBI);
86
87 /// Specific shift implementation for int16.
88 bool expandLSLW4Rd(Block &MBB, BlockIt MBBI);
89 bool expandLSRW4Rd(Block &MBB, BlockIt MBBI);
90 bool expandASRW7Rd(Block &MBB, BlockIt MBBI);
91 bool expandLSLW8Rd(Block &MBB, BlockIt MBBI);
92 bool expandLSRW8Rd(Block &MBB, BlockIt MBBI);
93 bool expandASRW8Rd(Block &MBB, BlockIt MBBI);
94 bool expandLSLW12Rd(Block &MBB, BlockIt MBBI);
95 bool expandLSRW12Rd(Block &MBB, BlockIt MBBI);
96 bool expandASRW14Rd(Block &MBB, BlockIt MBBI);
97 bool expandASRW15Rd(Block &MBB, BlockIt MBBI);
98
99 // Common implementation of LPMWRdZ and ELPMWRdZ.
100 bool expandLPMWELPMW(Block &MBB, BlockIt MBBI, bool IsELPM);
101 // Common implementation of LPMBRdZ and ELPMBRdZ.
102 bool expandLPMBELPMB(Block &MBB, BlockIt MBBI, bool IsELPM);
103 // Common implementation of ROLBRdR1 and ROLBRdR17.
104 bool expandROLBRd(Block &MBB, BlockIt MBBI);
105};
106
107char AVRExpandPseudo::ID = 0;
108
109bool AVRExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
110 bool Modified = false;
111
112 BlockIt MBBI = MBB.begin(), E = MBB.end();
113 while (MBBI != E) {
114 BlockIt NMBBI = std::next(MBBI);
115 Modified |= expandMI(MBB, MBBI);
116 MBBI = NMBBI;
117 }
118
119 return Modified;
120}
121
122bool AVRExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
123 bool Modified = false;
124
125 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
126 TRI = STI.getRegisterInfo();
127 TII = STI.getInstrInfo();
128
129 for (Block &MBB : MF) {
130 bool ContinueExpanding = true;
131 unsigned ExpandCount = 0;
132
133 // Continue expanding the block until all pseudos are expanded.
134 do {
135 assert(ExpandCount < 10 && "pseudo expand limit reached");
136 (void)ExpandCount;
137
138 bool BlockModified = expandMBB(MBB);
139 Modified |= BlockModified;
140 ExpandCount++;
141
142 ContinueExpanding = BlockModified;
143 } while (ContinueExpanding);
144 }
145
146 return Modified;
147}
148
149bool AVRExpandPseudo::expandArith(unsigned OpLo, unsigned OpHi, Block &MBB,
150 BlockIt MBBI) {
151 MachineInstr &MI = *MBBI;
152 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
153 Register DstReg = MI.getOperand(0).getReg();
154 Register SrcReg = MI.getOperand(2).getReg();
155 bool DstIsDead = MI.getOperand(0).isDead();
156 bool DstIsKill = MI.getOperand(1).isKill();
157 bool SrcIsKill = MI.getOperand(2).isKill();
158 bool ImpIsDead = MI.getOperand(3).isDead();
159 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
160 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
161
162 buildMI(MBB, MBBI, OpLo)
163 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
164 .addReg(DstLoReg, getKillRegState(DstIsKill))
165 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
166
167 auto MIBHI =
168 buildMI(MBB, MBBI, OpHi)
169 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
170 .addReg(DstHiReg, getKillRegState(DstIsKill))
171 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
172
173 if (ImpIsDead)
174 MIBHI->getOperand(3).setIsDead();
175
176 // SREG is always implicitly killed
177 MIBHI->getOperand(4).setIsKill();
178
179 MI.eraseFromParent();
180 return true;
181}
182
183bool AVRExpandPseudo::expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
184 MachineInstr &MI = *MBBI;
185 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
186 Register DstReg = MI.getOperand(0).getReg();
187 Register SrcReg = MI.getOperand(2).getReg();
188 bool DstIsDead = MI.getOperand(0).isDead();
189 bool DstIsKill = MI.getOperand(1).isKill();
190 bool SrcIsKill = MI.getOperand(2).isKill();
191 bool ImpIsDead = MI.getOperand(3).isDead();
192 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
193 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
194
195 auto MIBLO =
196 buildMI(MBB, MBBI, Op)
197 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
198 .addReg(DstLoReg, getKillRegState(DstIsKill))
199 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
200
201 // SREG is always implicitly dead
202 MIBLO->getOperand(3).setIsDead();
203
204 auto MIBHI =
205 buildMI(MBB, MBBI, Op)
206 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
207 .addReg(DstHiReg, getKillRegState(DstIsKill))
208 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
209
210 if (ImpIsDead)
211 MIBHI->getOperand(3).setIsDead();
212
213 MI.eraseFromParent();
214 return true;
215}
216
217bool AVRExpandPseudo::isLogicImmOpRedundant(unsigned Op,
218 unsigned ImmVal) const {
219
220 // ANDI Rd, 0xff is redundant.
221 if (Op == AVR::ANDIRdK && ImmVal == 0xff)
222 return true;
223
224 // ORI Rd, 0x0 is redundant.
225 if (Op == AVR::ORIRdK && ImmVal == 0x0)
226 return true;
227
228 return false;
229}
230
231bool AVRExpandPseudo::isLogicRegOpUndef(unsigned Op, unsigned ImmVal) const {
232 // ANDI Rd, 0x00 clears all input bits.
233 if (Op == AVR::ANDIRdK && ImmVal == 0x00)
234 return true;
235
236 // ORI Rd, 0xff sets all input bits.
237 if (Op == AVR::ORIRdK && ImmVal == 0xff)
238 return true;
239
240 return false;
241}
242
243bool AVRExpandPseudo::expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI) {
244 MachineInstr &MI = *MBBI;
245 Register DstLoReg, DstHiReg;
246 Register DstReg = MI.getOperand(0).getReg();
247 bool DstIsDead = MI.getOperand(0).isDead();
248 bool SrcIsKill = MI.getOperand(1).isKill();
249 bool ImpIsDead = MI.getOperand(3).isDead();
250 unsigned Imm = MI.getOperand(2).getImm();
251 unsigned Lo8 = Imm & 0xff;
252 unsigned Hi8 = (Imm >> 8) & 0xff;
253 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
254
255 if (!isLogicImmOpRedundant(Op, Lo8)) {
256 auto MIBLO =
257 buildMI(MBB, MBBI, Op)
258 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
259 .addReg(DstLoReg, getKillRegState(SrcIsKill))
260 .addImm(Lo8);
261
262 // SREG is always implicitly dead
263 MIBLO->getOperand(3).setIsDead();
264
265 if (isLogicRegOpUndef(Op, Lo8))
266 MIBLO->getOperand(1).setIsUndef(true);
267 }
268
269 if (!isLogicImmOpRedundant(Op, Hi8)) {
270 auto MIBHI =
271 buildMI(MBB, MBBI, Op)
272 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
273 .addReg(DstHiReg, getKillRegState(SrcIsKill))
274 .addImm(Hi8);
275
276 if (ImpIsDead)
277 MIBHI->getOperand(3).setIsDead();
278
279 if (isLogicRegOpUndef(Op, Hi8))
280 MIBHI->getOperand(1).setIsUndef(true);
281 }
282
283 MI.eraseFromParent();
284 return true;
285}
286
287template <>
288bool AVRExpandPseudo::expand<AVR::ADDWRdRr>(Block &MBB, BlockIt MBBI) {
289 return expandArith(AVR::ADDRdRr, AVR::ADCRdRr, MBB, MBBI);
290}
291
292template <>
293bool AVRExpandPseudo::expand<AVR::ADCWRdRr>(Block &MBB, BlockIt MBBI) {
294 return expandArith(AVR::ADCRdRr, AVR::ADCRdRr, MBB, MBBI);
295}
296
297template <>
298bool AVRExpandPseudo::expand<AVR::ADIWRdKP>(Block &MBB, BlockIt MBBI) {
299 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
300 MachineInstr &MI = *MBBI;
301 Register DstReg = MI.getOperand(0).getReg();
302 Register SrcReg = MI.getOperand(1).getReg();
303 int64_t Imm = MI.getOperand(2).getImm();
304 unsigned Opcode;
305
306 if (SrcReg != DstReg) {
307 TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DstReg, SrcReg, false, false,
308 false);
309 }
310
311 if (isUInt<6>(Imm) && STI.hasADDSUBIW() &&
312 AVR::IWREGSRegClass.contains(DstReg)) {
313 Opcode = AVR::ADIWRdK;
314 } else {
315 Opcode = AVR::SUBIWRdK;
316 Imm = -Imm;
317 }
318
319 buildMI(MBB, MI, Opcode)
320 .addReg(DstReg, RegState::Define)
321 .addReg(DstReg, RegState::Kill)
322 .addImm(Imm)
323 .setOperandDead(3); // implicit-def $sreg
324
325 MI.eraseFromParent();
326 return true;
327}
328
329template <>
330bool AVRExpandPseudo::expand<AVR::SUBWRdRr>(Block &MBB, BlockIt MBBI) {
331 return expandArith(AVR::SUBRdRr, AVR::SBCRdRr, MBB, MBBI);
332}
333
334template <>
335bool AVRExpandPseudo::expand<AVR::SUBIWRdK>(Block &MBB, BlockIt MBBI) {
336 MachineInstr &MI = *MBBI;
337 Register DstLoReg, DstHiReg;
338 Register DstReg = MI.getOperand(0).getReg();
339 bool DstIsDead = MI.getOperand(0).isDead();
340 bool SrcIsKill = MI.getOperand(1).isKill();
341 bool ImpIsDead = MI.getOperand(3).isDead();
342 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
343
344 auto MIBLO =
345 buildMI(MBB, MBBI, AVR::SUBIRdK)
346 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
347 .addReg(DstLoReg, getKillRegState(SrcIsKill));
348
349 auto MIBHI =
350 buildMI(MBB, MBBI, AVR::SBCIRdK)
351 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
352 .addReg(DstHiReg, getKillRegState(SrcIsKill));
353
354 switch (MI.getOperand(2).getType()) {
355 case MachineOperand::MO_GlobalAddress: {
356 const GlobalValue *GV = MI.getOperand(2).getGlobal();
357 int64_t Offs = MI.getOperand(2).getOffset();
358 unsigned TF = MI.getOperand(2).getTargetFlags();
359 MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_LO);
360 MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_HI);
361 break;
362 }
363 case MachineOperand::MO_Immediate: {
364 unsigned Imm = MI.getOperand(2).getImm();
365 MIBLO.addImm(Imm & 0xff);
366 MIBHI.addImm((Imm >> 8) & 0xff);
367 break;
368 }
369 default:
370 llvm_unreachable("Unknown operand type!");
371 }
372
373 if (ImpIsDead)
374 MIBHI->getOperand(3).setIsDead();
375
376 // SREG is always implicitly killed
377 MIBHI->getOperand(4).setIsKill();
378
379 MI.eraseFromParent();
380 return true;
381}
382
383template <>
384bool AVRExpandPseudo::expand<AVR::SBCWRdRr>(Block &MBB, BlockIt MBBI) {
385 return expandArith(AVR::SBCRdRr, AVR::SBCRdRr, MBB, MBBI);
386}
387
388template <>
389bool AVRExpandPseudo::expand<AVR::SBCIWRdK>(Block &MBB, BlockIt MBBI) {
390 MachineInstr &MI = *MBBI;
391 Register DstLoReg, DstHiReg;
392 Register DstReg = MI.getOperand(0).getReg();
393 bool DstIsDead = MI.getOperand(0).isDead();
394 bool SrcIsKill = MI.getOperand(1).isKill();
395 bool ImpIsDead = MI.getOperand(3).isDead();
396 unsigned Imm = MI.getOperand(2).getImm();
397 unsigned Lo8 = Imm & 0xff;
398 unsigned Hi8 = (Imm >> 8) & 0xff;
399 unsigned OpLo = AVR::SBCIRdK;
400 unsigned OpHi = AVR::SBCIRdK;
401 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
402
403 auto MIBLO =
404 buildMI(MBB, MBBI, OpLo)
405 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
406 .addReg(DstLoReg, getKillRegState(SrcIsKill))
407 .addImm(Lo8);
408
409 // SREG is always implicitly killed
410 MIBLO->getOperand(4).setIsKill();
411
412 auto MIBHI =
413 buildMI(MBB, MBBI, OpHi)
414 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
415 .addReg(DstHiReg, getKillRegState(SrcIsKill))
416 .addImm(Hi8);
417
418 if (ImpIsDead)
419 MIBHI->getOperand(3).setIsDead();
420
421 // SREG is always implicitly killed
422 MIBHI->getOperand(4).setIsKill();
423
424 MI.eraseFromParent();
425 return true;
426}
427
428template <>
429bool AVRExpandPseudo::expand<AVR::ANDWRdRr>(Block &MBB, BlockIt MBBI) {
430 return expandLogic(AVR::ANDRdRr, MBB, MBBI);
431}
432
433template <>
434bool AVRExpandPseudo::expand<AVR::ANDIWRdK>(Block &MBB, BlockIt MBBI) {
435 return expandLogicImm(AVR::ANDIRdK, MBB, MBBI);
436}
437
438template <>
439bool AVRExpandPseudo::expand<AVR::ORWRdRr>(Block &MBB, BlockIt MBBI) {
440 return expandLogic(AVR::ORRdRr, MBB, MBBI);
441}
442
443template <>
444bool AVRExpandPseudo::expand<AVR::ORIWRdK>(Block &MBB, BlockIt MBBI) {
445 return expandLogicImm(AVR::ORIRdK, MBB, MBBI);
446}
447
448template <>
449bool AVRExpandPseudo::expand<AVR::EORWRdRr>(Block &MBB, BlockIt MBBI) {
450 return expandLogic(AVR::EORRdRr, MBB, MBBI);
451}
452
453template <>
454bool AVRExpandPseudo::expand<AVR::COMWRd>(Block &MBB, BlockIt MBBI) {
455 MachineInstr &MI = *MBBI;
456 Register DstLoReg, DstHiReg;
457 Register DstReg = MI.getOperand(0).getReg();
458 bool DstIsDead = MI.getOperand(0).isDead();
459 bool DstIsKill = MI.getOperand(1).isKill();
460 bool ImpIsDead = MI.getOperand(2).isDead();
461 unsigned OpLo = AVR::COMRd;
462 unsigned OpHi = AVR::COMRd;
463 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
464
465 auto MIBLO =
466 buildMI(MBB, MBBI, OpLo)
467 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
468 .addReg(DstLoReg, getKillRegState(DstIsKill));
469
470 // SREG is always implicitly dead
471 MIBLO->getOperand(2).setIsDead();
472
473 auto MIBHI =
474 buildMI(MBB, MBBI, OpHi)
475 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
476 .addReg(DstHiReg, getKillRegState(DstIsKill));
477
478 if (ImpIsDead)
479 MIBHI->getOperand(2).setIsDead();
480
481 MI.eraseFromParent();
482 return true;
483}
484
485template <>
486bool AVRExpandPseudo::expand<AVR::NEGWRd>(Block &MBB, BlockIt MBBI) {
487 MachineInstr &MI = *MBBI;
488 Register DstLoReg, DstHiReg;
489 Register DstReg = MI.getOperand(0).getReg();
490 Register ZeroReg = MI.getOperand(2).getReg();
491 bool DstIsDead = MI.getOperand(0).isDead();
492 bool DstIsKill = MI.getOperand(1).isKill();
493 bool ImpIsDead = MI.getOperand(2).isDead();
494 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
495
496 // Do NEG on the upper byte.
497 auto MIBHI =
498 buildMI(MBB, MBBI, AVR::NEGRd)
499 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
500 .addReg(DstHiReg, RegState::Kill);
501 // SREG is always implicitly dead
502 MIBHI->getOperand(2).setIsDead();
503
504 // Do NEG on the lower byte.
505 buildMI(MBB, MBBI, AVR::NEGRd)
506 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
507 .addReg(DstLoReg, getKillRegState(DstIsKill));
508
509 // Do an extra SBC.
510 auto MISBCI =
511 buildMI(MBB, MBBI, AVR::SBCRdRr)
512 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
513 .addReg(DstHiReg, getKillRegState(DstIsKill))
514 .addReg(ZeroReg);
515 if (ImpIsDead)
516 MISBCI->getOperand(3).setIsDead();
517 // SREG is always implicitly killed
518 MISBCI->getOperand(4).setIsKill();
519
520 MI.eraseFromParent();
521 return true;
522}
523
524template <>
525bool AVRExpandPseudo::expand<AVR::CPWRdRr>(Block &MBB, BlockIt MBBI) {
526 MachineInstr &MI = *MBBI;
527 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
528 Register DstReg = MI.getOperand(0).getReg();
529 Register SrcReg = MI.getOperand(1).getReg();
530 bool DstIsKill = MI.getOperand(0).isKill();
531 bool SrcIsKill = MI.getOperand(1).isKill();
532 bool ImpIsDead = MI.getOperand(2).isDead();
533 unsigned OpLo = AVR::CPRdRr;
534 unsigned OpHi = AVR::CPCRdRr;
535 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
536 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
537
538 // Low part
539 buildMI(MBB, MBBI, OpLo)
540 .addReg(DstLoReg, getKillRegState(DstIsKill))
541 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
542
543 auto MIBHI = buildMI(MBB, MBBI, OpHi)
544 .addReg(DstHiReg, getKillRegState(DstIsKill))
545 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
546
547 if (ImpIsDead)
548 MIBHI->getOperand(2).setIsDead();
549
550 // SREG is always implicitly killed
551 MIBHI->getOperand(3).setIsKill();
552
553 MI.eraseFromParent();
554 return true;
555}
556
557template <>
558bool AVRExpandPseudo::expand<AVR::CPCWRdRr>(Block &MBB, BlockIt MBBI) {
559 MachineInstr &MI = *MBBI;
560 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
561 Register DstReg = MI.getOperand(0).getReg();
562 Register SrcReg = MI.getOperand(1).getReg();
563 bool DstIsKill = MI.getOperand(0).isKill();
564 bool SrcIsKill = MI.getOperand(1).isKill();
565 bool ImpIsDead = MI.getOperand(2).isDead();
566 unsigned OpLo = AVR::CPCRdRr;
567 unsigned OpHi = AVR::CPCRdRr;
568 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
569 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
570
571 auto MIBLO = buildMI(MBB, MBBI, OpLo)
572 .addReg(DstLoReg, getKillRegState(DstIsKill))
573 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
574
575 // SREG is always implicitly killed
576 MIBLO->getOperand(3).setIsKill();
577
578 auto MIBHI = buildMI(MBB, MBBI, OpHi)
579 .addReg(DstHiReg, getKillRegState(DstIsKill))
580 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
581
582 if (ImpIsDead)
583 MIBHI->getOperand(2).setIsDead();
584
585 // SREG is always implicitly killed
586 MIBHI->getOperand(3).setIsKill();
587
588 MI.eraseFromParent();
589 return true;
590}
591
592template <>
593bool AVRExpandPseudo::expand<AVR::LDIWRdK>(Block &MBB, BlockIt MBBI) {
594 MachineInstr &MI = *MBBI;
595 Register DstLoReg, DstHiReg;
596 Register DstReg = MI.getOperand(0).getReg();
597 bool DstIsDead = MI.getOperand(0).isDead();
598 unsigned OpLo = AVR::LDIRdK;
599 unsigned OpHi = AVR::LDIRdK;
600 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
601
602 auto MIBLO =
603 buildMI(MBB, MBBI, OpLo)
604 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
605
606 auto MIBHI =
607 buildMI(MBB, MBBI, OpHi)
608 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
609
610 switch (MI.getOperand(1).getType()) {
611 case MachineOperand::MO_GlobalAddress: {
612 const GlobalValue *GV = MI.getOperand(1).getGlobal();
613 int64_t Offs = MI.getOperand(1).getOffset();
614 unsigned TF = MI.getOperand(1).getTargetFlags();
615
616 MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_LO);
617 MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_HI);
618 break;
619 }
620 case MachineOperand::MO_BlockAddress: {
621 const BlockAddress *BA = MI.getOperand(1).getBlockAddress();
622 unsigned TF = MI.getOperand(1).getTargetFlags();
623
624 MIBLO.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_LO));
625 MIBHI.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_HI));
626 break;
627 }
628 case MachineOperand::MO_Immediate: {
629 unsigned Imm = MI.getOperand(1).getImm();
630
631 MIBLO.addImm(Imm & 0xff);
632 MIBHI.addImm((Imm >> 8) & 0xff);
633 break;
634 }
635 default:
636 llvm_unreachable("Unknown operand type!");
637 }
638
639 MI.eraseFromParent();
640 return true;
641}
642
643template <>
644bool AVRExpandPseudo::expand<AVR::LDSWRdK>(Block &MBB, BlockIt MBBI) {
645 MachineInstr &MI = *MBBI;
646 Register DstLoReg, DstHiReg;
647 Register DstReg = MI.getOperand(0).getReg();
648 bool DstIsDead = MI.getOperand(0).isDead();
649 unsigned OpLo = AVR::LDSRdK;
650 unsigned OpHi = AVR::LDSRdK;
651 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
652
653 auto MIBLO =
654 buildMI(MBB, MBBI, OpLo)
655 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
656
657 auto MIBHI =
658 buildMI(MBB, MBBI, OpHi)
659 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
660
661 switch (MI.getOperand(1).getType()) {
662 case MachineOperand::MO_GlobalAddress: {
663 const GlobalValue *GV = MI.getOperand(1).getGlobal();
664 int64_t Offs = MI.getOperand(1).getOffset();
665 unsigned TF = MI.getOperand(1).getTargetFlags();
666
667 MIBLO.addGlobalAddress(GV, Offs, TF);
668 MIBHI.addGlobalAddress(GV, Offs + 1, TF);
669 break;
670 }
671 case MachineOperand::MO_Immediate: {
672 unsigned Imm = MI.getOperand(1).getImm();
673
674 MIBLO.addImm(Imm);
675 MIBHI.addImm(Imm + 1);
676 break;
677 }
678 default:
679 llvm_unreachable("Unknown operand type!");
680 }
681
682 MIBLO.setMemRefs(MI.memoperands());
683 MIBHI.setMemRefs(MI.memoperands());
684
685 MI.eraseFromParent();
686 return true;
687}
688
689template <>
690bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
691 MachineInstr &MI = *MBBI;
692 Register DstReg = MI.getOperand(0).getReg();
693 Register SrcReg = MI.getOperand(1).getReg();
694 bool DstIsKill = MI.getOperand(0).isKill();
695 bool SrcIsKill = MI.getOperand(1).isKill();
696 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
697
698 // DstReg has an earlyclobber so the register allocator will allocate them in
699 // separate registers.
700 assert(DstReg != SrcReg && "Dst and Src registers are the same!");
701
702 if (STI.hasTinyEncoding()) {
703 // Handle this case in the expansion of LDDWRdPtrQ because it is very
704 // similar.
705 buildMI(MBB, MBBI, AVR::LDDWRdPtrQ)
706 .addDef(DstReg, getKillRegState(DstIsKill))
707 .addReg(SrcReg, getKillRegState(SrcIsKill))
708 .addImm(0)
709 .setMemRefs(MI.memoperands());
710
711 } else {
712 Register DstLoReg, DstHiReg;
713 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
714
715 // Load low byte.
716 buildMI(MBB, MBBI, AVR::LDRdPtr)
717 .addReg(DstLoReg, RegState::Define)
718 .addReg(SrcReg)
719 .setMemRefs(MI.memoperands());
720
721 // Load high byte.
722 buildMI(MBB, MBBI, AVR::LDDRdPtrQ)
723 .addReg(DstHiReg, RegState::Define)
724 .addReg(SrcReg, getKillRegState(SrcIsKill))
725 .addImm(1)
726 .setMemRefs(MI.memoperands());
727 }
728
729 MI.eraseFromParent();
730 return true;
731}
732
733template <>
734bool AVRExpandPseudo::expand<AVR::LDWRdPtrPi>(Block &MBB, BlockIt MBBI) {
735 MachineInstr &MI = *MBBI;
736 Register DstLoReg, DstHiReg;
737 Register DstReg = MI.getOperand(0).getReg();
738 Register SrcReg = MI.getOperand(1).getReg();
739 bool DstIsDead = MI.getOperand(0).isDead();
740 bool SrcIsDead = MI.getOperand(1).isKill();
741 unsigned OpLo = AVR::LDRdPtrPi;
742 unsigned OpHi = AVR::LDRdPtrPi;
743 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
744
745 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
746
747 auto MIBLO =
748 buildMI(MBB, MBBI, OpLo)
749 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
750 .addReg(SrcReg, RegState::Define)
751 .addReg(SrcReg, RegState::Kill);
752
753 auto MIBHI =
754 buildMI(MBB, MBBI, OpHi)
755 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
756 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
757 .addReg(SrcReg, RegState::Kill);
758
759 MIBLO.setMemRefs(MI.memoperands());
760 MIBHI.setMemRefs(MI.memoperands());
761
762 MI.eraseFromParent();
763 return true;
764}
765
766template <>
767bool AVRExpandPseudo::expand<AVR::LDWRdPtrPd>(Block &MBB, BlockIt MBBI) {
768 MachineInstr &MI = *MBBI;
769 Register DstLoReg, DstHiReg;
770 Register DstReg = MI.getOperand(0).getReg();
771 Register SrcReg = MI.getOperand(1).getReg();
772 bool DstIsDead = MI.getOperand(0).isDead();
773 bool SrcIsDead = MI.getOperand(1).isKill();
774 unsigned OpLo = AVR::LDRdPtrPd;
775 unsigned OpHi = AVR::LDRdPtrPd;
776 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
777
778 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
779
780 auto MIBHI =
781 buildMI(MBB, MBBI, OpHi)
782 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
783 .addReg(SrcReg, RegState::Define)
784 .addReg(SrcReg, RegState::Kill);
785
786 auto MIBLO =
787 buildMI(MBB, MBBI, OpLo)
788 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
789 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
790 .addReg(SrcReg, RegState::Kill);
791
792 MIBLO.setMemRefs(MI.memoperands());
793 MIBHI.setMemRefs(MI.memoperands());
794
795 MI.eraseFromParent();
796 return true;
797}
798
799template <>
800bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
801 MachineInstr &MI = *MBBI;
802 Register DstReg = MI.getOperand(0).getReg();
803 Register SrcReg = MI.getOperand(1).getReg();
804 unsigned Imm = MI.getOperand(2).getImm();
805 bool DstIsKill = MI.getOperand(0).isKill();
806 bool SrcIsKill = MI.getOperand(1).isKill();
807 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
808
809 // Since we add 1 to the Imm value for the high byte below, and 63 is the
810 // highest Imm value allowed for the instruction, 62 is the limit here.
811 assert(Imm <= 62 && "Offset is out of range");
812
813 // DstReg has an earlyclobber so the register allocator will allocate them in
814 // separate registers.
815 assert(DstReg != SrcReg && "Dst and Src registers are the same!");
816
817 if (STI.hasTinyEncoding()) {
818 // Reduced tiny cores don't support load/store with displacement. However,
819 // they do support postincrement. So we'll simply adjust the pointer before
820 // and after and use postincrement to load multiple registers.
821
822 // Add offset. The offset can be 0 when expanding this instruction from the
823 // more specific LDWRdPtr instruction.
824 if (Imm != 0) {
825 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg)
826 .addReg(SrcReg)
827 .addImm(0x10000 - Imm);
828 }
829
830 // Do a word load with postincrement. This will be lowered to a two byte
831 // load.
832 buildMI(MBB, MBBI, AVR::LDWRdPtrPi)
833 .addDef(DstReg, getKillRegState(DstIsKill))
834 .addReg(SrcReg, getKillRegState(SrcIsKill))
835 .addImm(0)
836 .setMemRefs(MI.memoperands());
837
838 // If the pointer is used after the store instruction, subtract the new
839 // offset (with 2 added after the postincrement instructions) so it is the
840 // same as before.
841 if (!SrcIsKill) {
842 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg).addReg(SrcReg).addImm(Imm + 2);
843 }
844 } else {
845 Register DstLoReg, DstHiReg;
846 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
847
848 // Load low byte.
849 buildMI(MBB, MBBI, AVR::LDDRdPtrQ)
850 .addReg(DstLoReg, RegState::Define)
851 .addReg(SrcReg)
852 .addImm(Imm)
853 .setMemRefs(MI.memoperands());
854
855 // Load high byte.
856 buildMI(MBB, MBBI, AVR::LDDRdPtrQ)
857 .addReg(DstHiReg, RegState::Define)
858 .addReg(SrcReg, getKillRegState(SrcIsKill))
859 .addImm(Imm + 1)
860 .setMemRefs(MI.memoperands());
861 }
862
863 MI.eraseFromParent();
864 return true;
865}
866
867bool AVRExpandPseudo::expandLPMWELPMW(Block &MBB, BlockIt MBBI, bool IsELPM) {
868 MachineInstr &MI = *MBBI;
869 Register DstLoReg, DstHiReg;
870 Register DstReg = MI.getOperand(0).getReg();
871 Register SrcReg = MI.getOperand(1).getReg();
872 Register SrcLoReg, SrcHiReg;
873 bool SrcIsKill = MI.getOperand(1).isKill();
874 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
875 bool IsLPMRn = IsELPM ? STI.hasELPMX() : STI.hasLPMX();
876
877 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
878 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
879
880 // Set the I/O register RAMPZ for ELPM.
881 if (IsELPM) {
882 Register Bank = MI.getOperand(2).getReg();
883 // out RAMPZ, rtmp
884 buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(Bank);
885 }
886
887 // This is enforced by the @earlyclobber constraint.
888 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
889
890 if (IsLPMRn) {
891 unsigned OpLo = IsELPM ? AVR::ELPMRdZPi : AVR::LPMRdZPi;
892 unsigned OpHi = IsELPM ? AVR::ELPMRdZ : AVR::LPMRdZ;
893 // Load low byte.
894 auto MIBLO = buildMI(MBB, MBBI, OpLo)
895 .addReg(DstLoReg, RegState::Define)
896 .addReg(SrcReg);
897 // Load high byte.
898 auto MIBHI = buildMI(MBB, MBBI, OpHi)
899 .addReg(DstHiReg, RegState::Define)
900 .addReg(SrcReg, getKillRegState(SrcIsKill));
901 MIBLO.setMemRefs(MI.memoperands());
902 MIBHI.setMemRefs(MI.memoperands());
903 } else {
904 unsigned Opc = IsELPM ? AVR::ELPM : AVR::LPM;
905 // Load low byte, and copy to the low destination register.
906 auto MIBLO = buildMI(MBB, MBBI, Opc);
907 buildMI(MBB, MBBI, AVR::MOVRdRr)
908 .addReg(DstLoReg, RegState::Define)
909 .addReg(STI.getTmpRegister(), RegState::Kill);
910 MIBLO.setMemRefs(MI.memoperands());
911 // Increase the Z register by 1.
912 if (STI.hasADDSUBIW()) {
913 // adiw r31:r30, 1
914 auto MIINC = buildMI(MBB, MBBI, AVR::ADIWRdK)
915 .addReg(SrcReg, RegState::Define)
916 .addReg(SrcReg, getKillRegState(SrcIsKill))
917 .addImm(1);
918 MIINC->getOperand(3).setIsDead();
919 } else {
920 // subi r30, 255
921 // sbci r31, 255
922 buildMI(MBB, MBBI, AVR::SUBIRdK)
923 .addReg(SrcLoReg, RegState::Define)
924 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
925 .addImm(255);
926 auto MIZHI = buildMI(MBB, MBBI, AVR::SBCIRdK)
927 .addReg(SrcHiReg, RegState::Define)
928 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
929 .addImm(255);
930 MIZHI->getOperand(3).setIsDead();
931 MIZHI->getOperand(4).setIsKill();
932 }
933 // Load high byte, and copy to the high destination register.
934 auto MIBHI = buildMI(MBB, MBBI, Opc);
935 buildMI(MBB, MBBI, AVR::MOVRdRr)
936 .addReg(DstHiReg, RegState::Define)
937 .addReg(STI.getTmpRegister(), RegState::Kill);
938 MIBHI.setMemRefs(MI.memoperands());
939 }
940
941 // Restore the Z register if it is not killed.
942 if (!SrcIsKill) {
943 if (STI.hasADDSUBIW()) {
944 // sbiw r31:r30, 1
945 auto MIDEC = buildMI(MBB, MBBI, AVR::SBIWRdK)
946 .addReg(SrcReg, RegState::Define)
947 .addReg(SrcReg, getKillRegState(SrcIsKill))
948 .addImm(1);
949 MIDEC->getOperand(3).setIsDead();
950 } else {
951 // subi r30, 1
952 // sbci r31, 0
953 buildMI(MBB, MBBI, AVR::SUBIRdK)
954 .addReg(SrcLoReg, RegState::Define)
955 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
956 .addImm(1);
957 auto MIZHI = buildMI(MBB, MBBI, AVR::SBCIRdK)
958 .addReg(SrcHiReg, RegState::Define)
959 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
960 .addImm(0);
961 MIZHI->getOperand(3).setIsDead();
962 MIZHI->getOperand(4).setIsKill();
963 }
964 }
965
966 MI.eraseFromParent();
967 return true;
968}
969
970template <>
971bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
972 return expandLPMWELPMW(MBB, MBBI, false);
973}
974
975template <>
976bool AVRExpandPseudo::expand<AVR::ELPMWRdZ>(Block &MBB, BlockIt MBBI) {
977 return expandLPMWELPMW(MBB, MBBI, true);
978}
979
980bool AVRExpandPseudo::expandLPMBELPMB(Block &MBB, BlockIt MBBI, bool IsELPM) {
981 MachineInstr &MI = *MBBI;
982 Register DstReg = MI.getOperand(0).getReg();
983 Register SrcReg = MI.getOperand(1).getReg();
984 bool SrcIsKill = MI.getOperand(1).isKill();
985 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
986 bool IsLPMRn = IsELPM ? STI.hasELPMX() : STI.hasLPMX();
987
988 // Set the I/O register RAMPZ for ELPM (out RAMPZ, rtmp).
989 if (IsELPM) {
990 Register BankReg = MI.getOperand(2).getReg();
991 buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(BankReg);
992 }
993
994 // Load byte.
995 if (IsLPMRn) {
996 unsigned Opc = IsELPM ? AVR::ELPMRdZ : AVR::LPMRdZ;
997 auto MILB = buildMI(MBB, MBBI, Opc)
998 .addReg(DstReg, RegState::Define)
999 .addReg(SrcReg, getKillRegState(SrcIsKill));
1000 MILB.setMemRefs(MI.memoperands());
1001 } else {
1002 // For the basic ELPM/LPM instruction, its operand[0] is the implicit
1003 // 'Z' register, and its operand[1] is the implicit 'R0' register.
1004 unsigned Opc = IsELPM ? AVR::ELPM : AVR::LPM;
1005 auto MILB = buildMI(MBB, MBBI, Opc);
1006 buildMI(MBB, MBBI, AVR::MOVRdRr)
1007 .addReg(DstReg, RegState::Define)
1008 .addReg(STI.getTmpRegister(), RegState::Kill);
1009 MILB.setMemRefs(MI.memoperands());
1010 }
1011
1012 MI.eraseFromParent();
1013 return true;
1014}
1015
1016template <>
1017bool AVRExpandPseudo::expand<AVR::ELPMBRdZ>(Block &MBB, BlockIt MBBI) {
1018 return expandLPMBELPMB(MBB, MBBI, true);
1019}
1020
1021template <>
1022bool AVRExpandPseudo::expand<AVR::LPMBRdZ>(Block &MBB, BlockIt MBBI) {
1023 return expandLPMBELPMB(MBB, MBBI, false);
1024}
1025
1026template <>
1027bool AVRExpandPseudo::expand<AVR::LPMWRdZPi>(Block &MBB, BlockIt MBBI) {
1028 llvm_unreachable("16-bit LPMPi is unimplemented");
1029}
1030
1031template <>
1032bool AVRExpandPseudo::expand<AVR::ELPMBRdZPi>(Block &MBB, BlockIt MBBI) {
1033 llvm_unreachable("8-bit ELPMPi is unimplemented");
1034}
1035
1036template <>
1037bool AVRExpandPseudo::expand<AVR::ELPMWRdZPi>(Block &MBB, BlockIt MBBI) {
1038 llvm_unreachable("16-bit ELPMPi is unimplemented");
1039}
1040
1041template <typename Func>
1042bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
1043 MachineInstr &MI = *MBBI;
1044 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1045
1046 // Store the SREG.
1047 buildMI(MBB, MBBI, AVR::INRdA)
1048 .addReg(STI.getTmpRegister(), RegState::Define)
1049 .addImm(STI.getIORegSREG());
1050
1051 // Disable exceptions.
1052 buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
1053
1054 f(MI);
1055
1056 // Restore the status reg.
1057 buildMI(MBB, MBBI, AVR::OUTARr)
1058 .addImm(STI.getIORegSREG())
1059 .addReg(STI.getTmpRegister());
1060
1061 MI.eraseFromParent();
1062 return true;
1063}
1064
1065template <typename Func>
1066bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
1067 BlockIt MBBI, Func f) {
1068 return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
1069 auto Op1 = MI.getOperand(0);
1070 auto Op2 = MI.getOperand(1);
1071
1072 MachineInstr &NewInst =
1073 *buildMI(MBB, MBBI, Opcode).add(Op1).add(Op2).getInstr();
1074 f(NewInst);
1075 });
1076}
1077
1078bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
1079 BlockIt MBBI) {
1080 return expandAtomicBinaryOp(Opcode, MBB, MBBI, [](MachineInstr &MI) {});
1081}
1082
1083template <>
1084bool AVRExpandPseudo::expand<AVR::AtomicLoad8>(Block &MBB, BlockIt MBBI) {
1085 return expandAtomicBinaryOp(AVR::LDRdPtr, MBB, MBBI);
1086}
1087
1088template <>
1089bool AVRExpandPseudo::expand<AVR::AtomicLoad16>(Block &MBB, BlockIt MBBI) {
1090 return expandAtomicBinaryOp(AVR::LDWRdPtr, MBB, MBBI);
1091}
1092
1093template <>
1094bool AVRExpandPseudo::expand<AVR::AtomicStore8>(Block &MBB, BlockIt MBBI) {
1095 return expandAtomicBinaryOp(AVR::STPtrRr, MBB, MBBI);
1096}
1097
1098template <>
1099bool AVRExpandPseudo::expand<AVR::AtomicStore16>(Block &MBB, BlockIt MBBI) {
1100 return expandAtomicBinaryOp(AVR::STWPtrRr, MBB, MBBI);
1101}
1102
1103template <>
1104bool AVRExpandPseudo::expand<AVR::AtomicFence>(Block &MBB, BlockIt MBBI) {
1105 // On AVR, there is only one core and so atomic fences do nothing.
1106 MBBI->eraseFromParent();
1107 return true;
1108}
1109
1110template <>
1111bool AVRExpandPseudo::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) {
1112 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1113 MachineInstr &MI = *MBBI;
1114 Register SrcLoReg, SrcHiReg;
1115 Register SrcReg = MI.getOperand(1).getReg();
1116 bool SrcIsKill = MI.getOperand(1).isKill();
1117 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1118
1119 auto MIB0 = buildMI(MBB, MBBI, AVR::STSKRr);
1120 auto MIB1 = buildMI(MBB, MBBI, AVR::STSKRr);
1121
1122 switch (MI.getOperand(0).getType()) {
1123 case MachineOperand::MO_GlobalAddress: {
1124 const GlobalValue *GV = MI.getOperand(0).getGlobal();
1125 int64_t Offs = MI.getOperand(0).getOffset();
1126 unsigned TF = MI.getOperand(0).getTargetFlags();
1127
1128 if (STI.hasLowByteFirst()) {
1129 // Write the low byte first for XMEGA devices.
1130 MIB0.addGlobalAddress(GV, Offs, TF);
1131 MIB1.addGlobalAddress(GV, Offs + 1, TF);
1132 } else {
1133 // Write the high byte first for traditional devices.
1134 MIB0.addGlobalAddress(GV, Offs + 1, TF);
1135 MIB1.addGlobalAddress(GV, Offs, TF);
1136 }
1137
1138 break;
1139 }
1140 case MachineOperand::MO_Immediate: {
1141 unsigned Imm = MI.getOperand(0).getImm();
1142
1143 if (STI.hasLowByteFirst()) {
1144 // Write the low byte first for XMEGA devices.
1145 MIB0.addImm(Imm);
1146 MIB1.addImm(Imm + 1);
1147 } else {
1148 // Write the high byte first for traditional devices.
1149 MIB0.addImm(Imm + 1);
1150 MIB1.addImm(Imm);
1151 }
1152
1153 break;
1154 }
1155 default:
1156 llvm_unreachable("Unknown operand type!");
1157 }
1158
1159 if (STI.hasLowByteFirst()) {
1160 // Write the low byte first for XMEGA devices.
1161 MIB0.addReg(SrcLoReg, getKillRegState(SrcIsKill))
1162 .setMemRefs(MI.memoperands());
1163 MIB1.addReg(SrcHiReg, getKillRegState(SrcIsKill))
1164 .setMemRefs(MI.memoperands());
1165 } else {
1166 // Write the high byte first for traditional devices.
1167 MIB0.addReg(SrcHiReg, getKillRegState(SrcIsKill))
1168 .setMemRefs(MI.memoperands());
1169 MIB1.addReg(SrcLoReg, getKillRegState(SrcIsKill))
1170 .setMemRefs(MI.memoperands());
1171 }
1172
1173 MI.eraseFromParent();
1174 return true;
1175}
1176
1177template <>
1178bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
1179 MachineInstr &MI = *MBBI;
1180 Register DstReg = MI.getOperand(0).getReg();
1181 Register SrcReg = MI.getOperand(1).getReg();
1182 bool DstIsKill = MI.getOperand(0).isKill();
1183 bool DstIsUndef = MI.getOperand(0).isUndef();
1184 bool SrcIsKill = MI.getOperand(1).isKill();
1185 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1186
1187 //: TODO: need to reverse this order like inw and stsw?
1188
1189 if (STI.hasTinyEncoding()) {
1190 // Handle this case in the expansion of STDWPtrQRr because it is very
1191 // similar.
1192 buildMI(MBB, MBBI, AVR::STDWPtrQRr)
1193 .addReg(DstReg,
1194 getKillRegState(DstIsKill) | getUndefRegState(DstIsUndef))
1195 .addImm(0)
1196 .addReg(SrcReg, getKillRegState(SrcIsKill))
1197 .setMemRefs(MI.memoperands());
1198
1199 } else {
1200 Register SrcLoReg, SrcHiReg;
1201 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1202 if (STI.hasLowByteFirst()) {
1203 buildMI(MBB, MBBI, AVR::STPtrRr)
1204 .addReg(DstReg, getUndefRegState(DstIsUndef))
1205 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1206 .setMemRefs(MI.memoperands());
1207 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1208 .addReg(DstReg, getUndefRegState(DstIsUndef))
1209 .addImm(1)
1210 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1211 .setMemRefs(MI.memoperands());
1212 } else {
1213 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1214 .addReg(DstReg, getUndefRegState(DstIsUndef))
1215 .addImm(1)
1216 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1217 .setMemRefs(MI.memoperands());
1218 buildMI(MBB, MBBI, AVR::STPtrRr)
1219 .addReg(DstReg, getUndefRegState(DstIsUndef))
1220 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1221 .setMemRefs(MI.memoperands());
1222 }
1223 }
1224
1225 MI.eraseFromParent();
1226 return true;
1227}
1228
1229template <>
1230bool AVRExpandPseudo::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) {
1231 MachineInstr &MI = *MBBI;
1232 Register SrcLoReg, SrcHiReg;
1233 Register DstReg = MI.getOperand(0).getReg();
1234 Register SrcReg = MI.getOperand(2).getReg();
1235 unsigned Imm = MI.getOperand(3).getImm();
1236 bool DstIsDead = MI.getOperand(0).isDead();
1237 bool SrcIsKill = MI.getOperand(2).isKill();
1238 unsigned OpLo = AVR::STPtrPiRr;
1239 unsigned OpHi = AVR::STPtrPiRr;
1240 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1241
1242 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1243
1244 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1245 .addReg(DstReg, RegState::Define)
1246 .addReg(DstReg, RegState::Kill)
1247 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1248 .addImm(Imm);
1249
1250 auto MIBHI =
1251 buildMI(MBB, MBBI, OpHi)
1252 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1253 .addReg(DstReg, RegState::Kill)
1254 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1255 .addImm(Imm);
1256
1257 MIBLO.setMemRefs(MI.memoperands());
1258 MIBHI.setMemRefs(MI.memoperands());
1259
1260 MI.eraseFromParent();
1261 return true;
1262}
1263
1264template <>
1265bool AVRExpandPseudo::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) {
1266 MachineInstr &MI = *MBBI;
1267 Register SrcLoReg, SrcHiReg;
1268 Register DstReg = MI.getOperand(0).getReg();
1269 Register SrcReg = MI.getOperand(2).getReg();
1270 unsigned Imm = MI.getOperand(3).getImm();
1271 bool DstIsDead = MI.getOperand(0).isDead();
1272 bool SrcIsKill = MI.getOperand(2).isKill();
1273 unsigned OpLo = AVR::STPtrPdRr;
1274 unsigned OpHi = AVR::STPtrPdRr;
1275 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1276
1277 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1278
1279 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1280 .addReg(DstReg, RegState::Define)
1281 .addReg(DstReg, RegState::Kill)
1282 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1283 .addImm(Imm);
1284
1285 auto MIBLO =
1286 buildMI(MBB, MBBI, OpLo)
1287 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1288 .addReg(DstReg, RegState::Kill)
1289 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1290 .addImm(Imm);
1291
1292 MIBLO.setMemRefs(MI.memoperands());
1293 MIBHI.setMemRefs(MI.memoperands());
1294
1295 MI.eraseFromParent();
1296 return true;
1297}
1298
1299template <>
1300bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
1301 MachineInstr &MI = *MBBI;
1302 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1303
1304 Register DstReg = MI.getOperand(0).getReg();
1305 bool DstIsKill = MI.getOperand(0).isKill();
1306 unsigned Imm = MI.getOperand(1).getImm();
1307 Register SrcReg = MI.getOperand(2).getReg();
1308 bool SrcIsKill = MI.getOperand(2).isKill();
1309
1310 // STD's maximum displacement is 63, so larger stores have to be split into a
1311 // set of operations.
1312 // For avrtiny chips, STD is not available at all so we always have to fall
1313 // back to manual pointer adjustments.
1314 if (Imm >= 63 || STI.hasTinyEncoding()) {
1315 // Add offset. The offset can be 0 when expanding this instruction from the
1316 // more specific STWPtrRr instruction.
1317 if (Imm != 0) {
1318 buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
1319 .addReg(DstReg, RegState::Kill)
1320 .addImm(0x10000 - Imm);
1321 }
1322
1323 // Do the store. This is a word store, that will be expanded further.
1324 buildMI(MBB, MBBI, AVR::STWPtrPiRr, DstReg)
1325 .addReg(DstReg, getKillRegState(DstIsKill))
1326 .addReg(SrcReg, getKillRegState(SrcIsKill))
1327 .addImm(0)
1328 .setMemRefs(MI.memoperands());
1329
1330 // If the pointer is used after the store instruction, subtract the new
1331 // offset (with 2 added after the postincrement instructions) so it is the
1332 // same as before.
1333 if (!DstIsKill) {
1334 buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
1335 .addReg(DstReg, RegState::Kill)
1336 .addImm(Imm + 2);
1337 }
1338 } else {
1339 Register SrcLoReg, SrcHiReg;
1340 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1341
1342 if (STI.hasLowByteFirst()) {
1343 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1344 .addReg(DstReg)
1345 .addImm(Imm)
1346 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1347 .setMemRefs(MI.memoperands());
1348 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1349 .addReg(DstReg, getKillRegState(DstIsKill))
1350 .addImm(Imm + 1)
1351 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1352 .setMemRefs(MI.memoperands());
1353 } else {
1354 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1355 .addReg(DstReg)
1356 .addImm(Imm + 1)
1357 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1358 .setMemRefs(MI.memoperands());
1359 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1360 .addReg(DstReg, getKillRegState(DstIsKill))
1361 .addImm(Imm)
1362 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1363 .setMemRefs(MI.memoperands());
1364 }
1365 }
1366
1367 MI.eraseFromParent();
1368 return true;
1369}
1370
1371template <>
1372bool AVRExpandPseudo::expand<AVR::STDSPQRr>(Block &MBB, BlockIt MBBI) {
1373 MachineInstr &MI = *MBBI;
1374 const MachineFunction &MF = *MBB.getParent();
1375 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
1376
1377 assert(MI.getOperand(0).getReg() == AVR::SP &&
1378 "SP is expected as base pointer");
1379
1380 assert(STI.getFrameLowering()->hasReservedCallFrame(MF) &&
1381 "unexpected STDSPQRr pseudo instruction");
1382 (void)STI;
1383
1384 MI.setDesc(TII->get(AVR::STDPtrQRr));
1385 MI.getOperand(0).setReg(AVR::R29R28);
1386
1387 return true;
1388}
1389
1390template <>
1391bool AVRExpandPseudo::expand<AVR::STDWSPQRr>(Block &MBB, BlockIt MBBI) {
1392 MachineInstr &MI = *MBBI;
1393 const MachineFunction &MF = *MBB.getParent();
1394 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
1395
1396 assert(MI.getOperand(0).getReg() == AVR::SP &&
1397 "SP is expected as base pointer");
1398
1399 assert(STI.getFrameLowering()->hasReservedCallFrame(MF) &&
1400 "unexpected STDWSPQRr pseudo instruction");
1401 (void)STI;
1402
1403 MI.setDesc(TII->get(AVR::STDWPtrQRr));
1404 MI.getOperand(0).setReg(AVR::R29R28);
1405
1406 return true;
1407}
1408
1409template <>
1410bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {
1411 MachineInstr &MI = *MBBI;
1412 Register DstLoReg, DstHiReg;
1413 unsigned Imm = MI.getOperand(1).getImm();
1414 Register DstReg = MI.getOperand(0).getReg();
1415 bool DstIsDead = MI.getOperand(0).isDead();
1416 unsigned OpLo = AVR::INRdA;
1417 unsigned OpHi = AVR::INRdA;
1418 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1419
1420 // Since we add 1 to the Imm value for the high byte below, and 63 is the
1421 // highest Imm value allowed for the instruction, 62 is the limit here.
1422 assert(Imm <= 62 && "Address is out of range");
1423
1424 auto MIBLO =
1425 buildMI(MBB, MBBI, OpLo)
1426 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1427 .addImm(Imm);
1428
1429 auto MIBHI =
1430 buildMI(MBB, MBBI, OpHi)
1431 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1432 .addImm(Imm + 1);
1433
1434 MIBLO.setMemRefs(MI.memoperands());
1435 MIBHI.setMemRefs(MI.memoperands());
1436
1437 MI.eraseFromParent();
1438 return true;
1439}
1440
1441template <>
1442bool AVRExpandPseudo::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) {
1443 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1444 MachineInstr &MI = *MBBI;
1445 Register SrcLoReg, SrcHiReg;
1446 unsigned Imm = MI.getOperand(0).getImm();
1447 Register SrcReg = MI.getOperand(1).getReg();
1448 bool SrcIsKill = MI.getOperand(1).isKill();
1449 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1450
1451 // Since we add 1 to the Imm value for the high byte below, and 63 is the
1452 // highest Imm value allowed for the instruction, 62 is the limit here.
1453 assert(Imm <= 62 && "Address is out of range");
1454
1455 // 16 bit I/O writes need the high byte first on normal AVR devices,
1456 // and in reverse order for the XMEGA/XMEGA3/XMEGAU families.
1457 auto MIBHI = buildMI(MBB, MBBI, AVR::OUTARr)
1458 .addImm(STI.hasLowByteFirst() ? Imm : Imm + 1)
1459 .addReg(STI.hasLowByteFirst() ? SrcLoReg : SrcHiReg,
1460 getKillRegState(SrcIsKill));
1461 auto MIBLO = buildMI(MBB, MBBI, AVR::OUTARr)
1462 .addImm(STI.hasLowByteFirst() ? Imm + 1 : Imm)
1463 .addReg(STI.hasLowByteFirst() ? SrcHiReg : SrcLoReg,
1464 getKillRegState(SrcIsKill));
1465
1466 MIBLO.setMemRefs(MI.memoperands());
1467 MIBHI.setMemRefs(MI.memoperands());
1468
1469 MI.eraseFromParent();
1470 return true;
1471}
1472
1473template <>
1474bool AVRExpandPseudo::expand<AVR::PUSHWRr>(Block &MBB, BlockIt MBBI) {
1475 MachineInstr &MI = *MBBI;
1476 Register SrcLoReg, SrcHiReg;
1477 Register SrcReg = MI.getOperand(0).getReg();
1478 bool SrcIsKill = MI.getOperand(0).isKill();
1479 unsigned Flags = MI.getFlags();
1480 unsigned OpLo = AVR::PUSHRr;
1481 unsigned OpHi = AVR::PUSHRr;
1482 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1483
1484 // Low part
1485 buildMI(MBB, MBBI, OpLo)
1486 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1487 .setMIFlags(Flags);
1488
1489 // High part
1490 buildMI(MBB, MBBI, OpHi)
1491 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1492 .setMIFlags(Flags);
1493
1494 MI.eraseFromParent();
1495 return true;
1496}
1497
1498template <>
1499bool AVRExpandPseudo::expand<AVR::POPWRd>(Block &MBB, BlockIt MBBI) {
1500 MachineInstr &MI = *MBBI;
1501 Register DstLoReg, DstHiReg;
1502 Register DstReg = MI.getOperand(0).getReg();
1503 unsigned Flags = MI.getFlags();
1504 unsigned OpLo = AVR::POPRd;
1505 unsigned OpHi = AVR::POPRd;
1506 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1507
1508 buildMI(MBB, MBBI, OpHi, DstHiReg).setMIFlags(Flags); // High
1509 buildMI(MBB, MBBI, OpLo, DstLoReg).setMIFlags(Flags); // Low
1510
1511 MI.eraseFromParent();
1512 return true;
1513}
1514
1515bool AVRExpandPseudo::expandROLBRd(Block &MBB, BlockIt MBBI) {
1516 // In AVR, the rotate instructions behave quite unintuitively. They rotate
1517 // bits through the carry bit in SREG, effectively rotating over 9 bits,
1518 // instead of 8. This is useful when we are dealing with numbers over
1519 // multiple registers, but when we actually need to rotate stuff, we have
1520 // to explicitly add the carry bit.
1521
1522 MachineInstr &MI = *MBBI;
1523 unsigned OpShift, OpCarry;
1524 Register DstReg = MI.getOperand(0).getReg();
1525 Register ZeroReg = MI.getOperand(3).getReg();
1526 bool DstIsDead = MI.getOperand(0).isDead();
1527 bool DstIsKill = MI.getOperand(1).isKill();
1528 OpShift = AVR::ADDRdRr;
1529 OpCarry = AVR::ADCRdRr;
1530
1531 // add r16, r16
1532 // adc r16, r1
1533
1534 // Shift part
1535 buildMI(MBB, MBBI, OpShift)
1536 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1537 .addReg(DstReg, RegState::Kill)
1538 .addReg(DstReg, RegState::Kill);
1539
1540 // Add the carry bit
1541 auto MIB = buildMI(MBB, MBBI, OpCarry)
1542 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1543 .addReg(DstReg, getKillRegState(DstIsKill))
1544 .addReg(ZeroReg);
1545
1546 MIB->getOperand(3).setIsDead(); // SREG is always dead
1547 MIB->getOperand(4).setIsKill(); // SREG is always implicitly killed
1548
1549 MI.eraseFromParent();
1550 return true;
1551}
1552
1553template <>
1554bool AVRExpandPseudo::expand<AVR::ROLBRdR1>(Block &MBB, BlockIt MBBI) {
1555 return expandROLBRd(MBB, MBBI);
1556}
1557
1558template <>
1559bool AVRExpandPseudo::expand<AVR::ROLBRdR17>(Block &MBB, BlockIt MBBI) {
1560 return expandROLBRd(MBB, MBBI);
1561}
1562
1563template <>
1564bool AVRExpandPseudo::expand<AVR::RORBRd>(Block &MBB, BlockIt MBBI) {
1565 // In AVR, the rotate instructions behave quite unintuitively. They rotate
1566 // bits through the carry bit in SREG, effectively rotating over 9 bits,
1567 // instead of 8. This is useful when we are dealing with numbers over
1568 // multiple registers, but when we actually need to rotate stuff, we have
1569 // to explicitly add the carry bit.
1570
1571 MachineInstr &MI = *MBBI;
1572 Register DstReg = MI.getOperand(0).getReg();
1573
1574 // bst r16, 0
1575 // ror r16
1576 // bld r16, 7
1577
1578 // Move the lowest bit from DstReg into the T bit
1579 buildMI(MBB, MBBI, AVR::BST).addReg(DstReg).addImm(0);
1580
1581 // Rotate to the right
1582 buildMI(MBB, MBBI, AVR::RORRd, DstReg).addReg(DstReg);
1583
1584 // Move the T bit into the highest bit of DstReg.
1585 buildMI(MBB, MBBI, AVR::BLD, DstReg).addReg(DstReg).addImm(7);
1586
1587 MI.eraseFromParent();
1588 return true;
1589}
1590
1591template <>
1592bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {
1593 MachineInstr &MI = *MBBI;
1594 Register DstLoReg, DstHiReg;
1595 Register DstReg = MI.getOperand(0).getReg();
1596 bool DstIsDead = MI.getOperand(0).isDead();
1597 bool DstIsKill = MI.getOperand(1).isKill();
1598 bool ImpIsDead = MI.getOperand(2).isDead();
1599 unsigned OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd
1600 unsigned OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd
1601 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1602
1603 // Low part
1604 buildMI(MBB, MBBI, OpLo)
1605 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1606 .addReg(DstLoReg, getKillRegState(DstIsKill))
1607 .addReg(DstLoReg, getKillRegState(DstIsKill));
1608
1609 auto MIBHI =
1610 buildMI(MBB, MBBI, OpHi)
1611 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1612 .addReg(DstHiReg, getKillRegState(DstIsKill))
1613 .addReg(DstHiReg, getKillRegState(DstIsKill));
1614
1615 if (ImpIsDead)
1616 MIBHI->getOperand(3).setIsDead();
1617
1618 // SREG is always implicitly killed
1619 MIBHI->getOperand(4).setIsKill();
1620
1621 MI.eraseFromParent();
1622 return true;
1623}
1624
1625template <>
1626bool AVRExpandPseudo::expand<AVR::LSLWHiRd>(Block &MBB, BlockIt MBBI) {
1627 MachineInstr &MI = *MBBI;
1628 Register DstLoReg, DstHiReg;
1629 Register DstReg = MI.getOperand(0).getReg();
1630 bool DstIsDead = MI.getOperand(0).isDead();
1631 bool DstIsKill = MI.getOperand(1).isKill();
1632 bool ImpIsDead = MI.getOperand(2).isDead();
1633 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1634
1635 // add hireg, hireg <==> lsl hireg
1636 auto MILSL =
1637 buildMI(MBB, MBBI, AVR::ADDRdRr)
1638 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1639 .addReg(DstHiReg, getKillRegState(DstIsKill))
1640 .addReg(DstHiReg, getKillRegState(DstIsKill));
1641
1642 if (ImpIsDead)
1643 MILSL->getOperand(3).setIsDead();
1644
1645 MI.eraseFromParent();
1646 return true;
1647}
1648
1649bool AVRExpandPseudo::expandLSLW4Rd(Block &MBB, BlockIt MBBI) {
1650 MachineInstr &MI = *MBBI;
1651 Register DstLoReg, DstHiReg;
1652 Register DstReg = MI.getOperand(0).getReg();
1653 bool DstIsDead = MI.getOperand(0).isDead();
1654 bool DstIsKill = MI.getOperand(1).isKill();
1655 bool ImpIsDead = MI.getOperand(3).isDead();
1656 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1657
1658 // swap Rh
1659 // swap Rl
1660 buildMI(MBB, MBBI, AVR::SWAPRd)
1661 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1662 .addReg(DstHiReg, RegState::Kill);
1663 buildMI(MBB, MBBI, AVR::SWAPRd)
1664 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1665 .addReg(DstLoReg, RegState::Kill);
1666
1667 // andi Rh, 0xf0
1668 auto MI0 =
1669 buildMI(MBB, MBBI, AVR::ANDIRdK)
1670 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1671 .addReg(DstHiReg, RegState::Kill)
1672 .addImm(0xf0);
1673 // SREG is implicitly dead.
1674 MI0->getOperand(3).setIsDead();
1675
1676 // eor Rh, Rl
1677 auto MI1 =
1678 buildMI(MBB, MBBI, AVR::EORRdRr)
1679 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1680 .addReg(DstHiReg, RegState::Kill)
1681 .addReg(DstLoReg);
1682 // SREG is implicitly dead.
1683 MI1->getOperand(3).setIsDead();
1684
1685 // andi Rl, 0xf0
1686 auto MI2 =
1687 buildMI(MBB, MBBI, AVR::ANDIRdK)
1688 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1689 .addReg(DstLoReg, getKillRegState(DstIsKill))
1690 .addImm(0xf0);
1691 // SREG is implicitly dead.
1692 MI2->getOperand(3).setIsDead();
1693
1694 // eor Rh, Rl
1695 auto MI3 =
1696 buildMI(MBB, MBBI, AVR::EORRdRr)
1697 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1698 .addReg(DstHiReg, getKillRegState(DstIsKill))
1699 .addReg(DstLoReg);
1700 if (ImpIsDead)
1701 MI3->getOperand(3).setIsDead();
1702
1703 MI.eraseFromParent();
1704 return true;
1705}
1706
1707bool AVRExpandPseudo::expandLSLW8Rd(Block &MBB, BlockIt MBBI) {
1708 MachineInstr &MI = *MBBI;
1709 Register DstLoReg, DstHiReg;
1710 Register DstReg = MI.getOperand(0).getReg();
1711 bool DstIsDead = MI.getOperand(0).isDead();
1712 bool DstIsKill = MI.getOperand(1).isKill();
1713 bool ImpIsDead = MI.getOperand(3).isDead();
1714 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1715
1716 // mov Rh, Rl
1717 buildMI(MBB, MBBI, AVR::MOVRdRr)
1718 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1719 .addReg(DstLoReg);
1720
1721 // clr Rl
1722 auto MIBLO =
1723 buildMI(MBB, MBBI, AVR::EORRdRr)
1724 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1725 .addReg(DstLoReg, getKillRegState(DstIsKill))
1726 .addReg(DstLoReg, getKillRegState(DstIsKill));
1727 if (ImpIsDead)
1728 MIBLO->getOperand(3).setIsDead();
1729
1730 MI.eraseFromParent();
1731 return true;
1732}
1733
1734bool AVRExpandPseudo::expandLSLW12Rd(Block &MBB, BlockIt MBBI) {
1735 MachineInstr &MI = *MBBI;
1736 Register DstLoReg, DstHiReg;
1737 Register DstReg = MI.getOperand(0).getReg();
1738 bool DstIsDead = MI.getOperand(0).isDead();
1739 bool DstIsKill = MI.getOperand(1).isKill();
1740 bool ImpIsDead = MI.getOperand(3).isDead();
1741 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1742
1743 // mov Rh, Rl
1744 buildMI(MBB, MBBI, AVR::MOVRdRr)
1745 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1746 .addReg(DstLoReg);
1747
1748 // swap Rh
1749 buildMI(MBB, MBBI, AVR::SWAPRd)
1750 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1751 .addReg(DstHiReg, RegState::Kill);
1752
1753 // andi Rh, 0xf0
1754 auto MI0 =
1755 buildMI(MBB, MBBI, AVR::ANDIRdK)
1756 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1757 .addReg(DstHiReg, getKillRegState(DstIsKill))
1758 .addImm(0xf0);
1759 // SREG is implicitly dead.
1760 MI0->getOperand(3).setIsDead();
1761
1762 // clr Rl
1763 auto MI1 =
1764 buildMI(MBB, MBBI, AVR::EORRdRr)
1765 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1766 .addReg(DstLoReg, getKillRegState(DstIsKill))
1767 .addReg(DstLoReg, getKillRegState(DstIsKill));
1768 if (ImpIsDead)
1769 MI1->getOperand(3).setIsDead();
1770
1771 MI.eraseFromParent();
1772 return true;
1773}
1774
1775template <>
1776bool AVRExpandPseudo::expand<AVR::LSLWNRd>(Block &MBB, BlockIt MBBI) {
1777 MachineInstr &MI = *MBBI;
1778 unsigned Imm = MI.getOperand(2).getImm();
1779 switch (Imm) {
1780 case 4:
1781 return expandLSLW4Rd(MBB, MBBI);
1782 case 8:
1783 return expandLSLW8Rd(MBB, MBBI);
1784 case 12:
1785 return expandLSLW12Rd(MBB, MBBI);
1786 default:
1787 llvm_unreachable("unimplemented lslwn");
1788 return false;
1789 }
1790}
1791
1792template <>
1793bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
1794 MachineInstr &MI = *MBBI;
1795 Register DstLoReg, DstHiReg;
1796 Register DstReg = MI.getOperand(0).getReg();
1797 bool DstIsDead = MI.getOperand(0).isDead();
1798 bool DstIsKill = MI.getOperand(1).isKill();
1799 bool ImpIsDead = MI.getOperand(2).isDead();
1800 unsigned OpLo = AVR::RORRd;
1801 unsigned OpHi = AVR::LSRRd;
1802 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1803
1804 // High part
1805 buildMI(MBB, MBBI, OpHi)
1806 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1807 .addReg(DstHiReg, getKillRegState(DstIsKill));
1808
1809 auto MIBLO =
1810 buildMI(MBB, MBBI, OpLo)
1811 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1812 .addReg(DstLoReg, getKillRegState(DstIsKill));
1813
1814 if (ImpIsDead)
1815 MIBLO->getOperand(2).setIsDead();
1816
1817 // SREG is always implicitly killed
1818 MIBLO->getOperand(3).setIsKill();
1819
1820 MI.eraseFromParent();
1821 return true;
1822}
1823
1824template <>
1825bool AVRExpandPseudo::expand<AVR::LSRWLoRd>(Block &MBB, BlockIt MBBI) {
1826 MachineInstr &MI = *MBBI;
1827 Register DstLoReg, DstHiReg;
1828 Register DstReg = MI.getOperand(0).getReg();
1829 bool DstIsDead = MI.getOperand(0).isDead();
1830 bool DstIsKill = MI.getOperand(1).isKill();
1831 bool ImpIsDead = MI.getOperand(2).isDead();
1832 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1833
1834 // lsr loreg
1835 auto MILSR =
1836 buildMI(MBB, MBBI, AVR::LSRRd)
1837 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1838 .addReg(DstLoReg, getKillRegState(DstIsKill));
1839
1840 if (ImpIsDead)
1841 MILSR->getOperand(2).setIsDead();
1842
1843 MI.eraseFromParent();
1844 return true;
1845}
1846
1847bool AVRExpandPseudo::expandLSRW4Rd(Block &MBB, BlockIt MBBI) {
1848 MachineInstr &MI = *MBBI;
1849 Register DstLoReg, DstHiReg;
1850 Register DstReg = MI.getOperand(0).getReg();
1851 bool DstIsDead = MI.getOperand(0).isDead();
1852 bool DstIsKill = MI.getOperand(1).isKill();
1853 bool ImpIsDead = MI.getOperand(3).isDead();
1854 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1855
1856 // swap Rh
1857 // swap Rl
1858 buildMI(MBB, MBBI, AVR::SWAPRd)
1859 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1860 .addReg(DstHiReg, RegState::Kill);
1861 buildMI(MBB, MBBI, AVR::SWAPRd)
1862 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1863 .addReg(DstLoReg, RegState::Kill);
1864
1865 // andi Rl, 0xf
1866 auto MI0 =
1867 buildMI(MBB, MBBI, AVR::ANDIRdK)
1868 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1869 .addReg(DstLoReg, RegState::Kill)
1870 .addImm(0xf);
1871 // SREG is implicitly dead.
1872 MI0->getOperand(3).setIsDead();
1873
1874 // eor Rl, Rh
1875 auto MI1 =
1876 buildMI(MBB, MBBI, AVR::EORRdRr)
1877 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1878 .addReg(DstLoReg, RegState::Kill)
1879 .addReg(DstHiReg);
1880 // SREG is implicitly dead.
1881 MI1->getOperand(3).setIsDead();
1882
1883 // andi Rh, 0xf
1884 auto MI2 =
1885 buildMI(MBB, MBBI, AVR::ANDIRdK)
1886 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1887 .addReg(DstHiReg, getKillRegState(DstIsKill))
1888 .addImm(0xf);
1889 // SREG is implicitly dead.
1890 MI2->getOperand(3).setIsDead();
1891
1892 // eor Rl, Rh
1893 auto MI3 =
1894 buildMI(MBB, MBBI, AVR::EORRdRr)
1895 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1896 .addReg(DstLoReg, getKillRegState(DstIsKill))
1897 .addReg(DstHiReg);
1898 if (ImpIsDead)
1899 MI3->getOperand(3).setIsDead();
1900
1901 MI.eraseFromParent();
1902 return true;
1903}
1904
1905bool AVRExpandPseudo::expandLSRW8Rd(Block &MBB, BlockIt MBBI) {
1906 MachineInstr &MI = *MBBI;
1907 Register DstLoReg, DstHiReg;
1908 Register DstReg = MI.getOperand(0).getReg();
1909 bool DstIsDead = MI.getOperand(0).isDead();
1910 bool DstIsKill = MI.getOperand(1).isKill();
1911 bool ImpIsDead = MI.getOperand(3).isDead();
1912 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1913
1914 // Move upper byte to lower byte.
1915 buildMI(MBB, MBBI, AVR::MOVRdRr)
1916 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1917 .addReg(DstHiReg);
1918
1919 // Clear upper byte.
1920 auto MIBHI =
1921 buildMI(MBB, MBBI, AVR::EORRdRr)
1922 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1923 .addReg(DstHiReg, getKillRegState(DstIsKill))
1924 .addReg(DstHiReg, getKillRegState(DstIsKill));
1925 if (ImpIsDead)
1926 MIBHI->getOperand(3).setIsDead();
1927
1928 MI.eraseFromParent();
1929 return true;
1930}
1931
1932bool AVRExpandPseudo::expandLSRW12Rd(Block &MBB, BlockIt MBBI) {
1933 MachineInstr &MI = *MBBI;
1934 Register DstLoReg, DstHiReg;
1935 Register DstReg = MI.getOperand(0).getReg();
1936 bool DstIsDead = MI.getOperand(0).isDead();
1937 bool DstIsKill = MI.getOperand(1).isKill();
1938 bool ImpIsDead = MI.getOperand(3).isDead();
1939 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1940
1941 // Move upper byte to lower byte.
1942 buildMI(MBB, MBBI, AVR::MOVRdRr)
1943 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1944 .addReg(DstHiReg);
1945
1946 // swap Rl
1947 buildMI(MBB, MBBI, AVR::SWAPRd)
1948 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1949 .addReg(DstLoReg, RegState::Kill);
1950
1951 // andi Rl, 0xf
1952 auto MI0 =
1953 buildMI(MBB, MBBI, AVR::ANDIRdK)
1954 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1955 .addReg(DstLoReg, getKillRegState(DstIsKill))
1956 .addImm(0xf);
1957 // SREG is implicitly dead.
1958 MI0->getOperand(3).setIsDead();
1959
1960 // Clear upper byte.
1961 auto MIBHI =
1962 buildMI(MBB, MBBI, AVR::EORRdRr)
1963 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1964 .addReg(DstHiReg, getKillRegState(DstIsKill))
1965 .addReg(DstHiReg, getKillRegState(DstIsKill));
1966 if (ImpIsDead)
1967 MIBHI->getOperand(3).setIsDead();
1968
1969 MI.eraseFromParent();
1970 return true;
1971}
1972
1973template <>
1974bool AVRExpandPseudo::expand<AVR::LSRWNRd>(Block &MBB, BlockIt MBBI) {
1975 MachineInstr &MI = *MBBI;
1976 unsigned Imm = MI.getOperand(2).getImm();
1977 switch (Imm) {
1978 case 4:
1979 return expandLSRW4Rd(MBB, MBBI);
1980 case 8:
1981 return expandLSRW8Rd(MBB, MBBI);
1982 case 12:
1983 return expandLSRW12Rd(MBB, MBBI);
1984 default:
1985 llvm_unreachable("unimplemented lsrwn");
1986 return false;
1987 }
1988}
1989
1990template <>
1991bool AVRExpandPseudo::expand<AVR::RORWRd>(Block &MBB, BlockIt MBBI) {
1992 llvm_unreachable("RORW unimplemented");
1993 return false;
1994}
1995
1996template <>
1997bool AVRExpandPseudo::expand<AVR::ROLWRd>(Block &MBB, BlockIt MBBI) {
1998 llvm_unreachable("ROLW unimplemented");
1999 return false;
2000}
2001
2002template <>
2003bool AVRExpandPseudo::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) {
2004 MachineInstr &MI = *MBBI;
2005 Register DstLoReg, DstHiReg;
2006 Register DstReg = MI.getOperand(0).getReg();
2007 bool DstIsDead = MI.getOperand(0).isDead();
2008 bool DstIsKill = MI.getOperand(1).isKill();
2009 bool ImpIsDead = MI.getOperand(2).isDead();
2010 unsigned OpLo = AVR::RORRd;
2011 unsigned OpHi = AVR::ASRRd;
2012 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2013
2014 // High part
2015 buildMI(MBB, MBBI, OpHi)
2016 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2017 .addReg(DstHiReg, getKillRegState(DstIsKill));
2018
2019 auto MIBLO =
2020 buildMI(MBB, MBBI, OpLo)
2021 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2022 .addReg(DstLoReg, getKillRegState(DstIsKill));
2023
2024 if (ImpIsDead)
2025 MIBLO->getOperand(2).setIsDead();
2026
2027 // SREG is always implicitly killed
2028 MIBLO->getOperand(3).setIsKill();
2029
2030 MI.eraseFromParent();
2031 return true;
2032}
2033
2034template <>
2035bool AVRExpandPseudo::expand<AVR::ASRWLoRd>(Block &MBB, BlockIt MBBI) {
2036 MachineInstr &MI = *MBBI;
2037 Register DstLoReg, DstHiReg;
2038 Register DstReg = MI.getOperand(0).getReg();
2039 bool DstIsDead = MI.getOperand(0).isDead();
2040 bool DstIsKill = MI.getOperand(1).isKill();
2041 bool ImpIsDead = MI.getOperand(2).isDead();
2042 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2043
2044 // asr loreg
2045 auto MIASR =
2046 buildMI(MBB, MBBI, AVR::ASRRd)
2047 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2048 .addReg(DstLoReg, getKillRegState(DstIsKill));
2049
2050 if (ImpIsDead)
2051 MIASR->getOperand(2).setIsDead();
2052
2053 MI.eraseFromParent();
2054 return true;
2055}
2056
2057bool AVRExpandPseudo::expandASRW7Rd(Block &MBB, BlockIt MBBI) {
2058 MachineInstr &MI = *MBBI;
2059 Register DstLoReg, DstHiReg;
2060 Register DstReg = MI.getOperand(0).getReg();
2061 bool DstIsDead = MI.getOperand(0).isDead();
2062 bool DstIsKill = MI.getOperand(1).isKill();
2063 bool ImpIsDead = MI.getOperand(3).isDead();
2064 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2065
2066 // lsl r24
2067 // mov r24,r25
2068 // rol r24
2069 // sbc r25,r25
2070
2071 // lsl r24 <=> add r24, r24
2072 buildMI(MBB, MBBI, AVR::ADDRdRr)
2073 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2074 .addReg(DstLoReg, RegState::Kill)
2075 .addReg(DstLoReg, RegState::Kill);
2076
2077 // mov r24, r25
2078 buildMI(MBB, MBBI, AVR::MOVRdRr)
2079 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2080 .addReg(DstHiReg);
2081
2082 // rol r24 <=> adc r24, r24
2083 buildMI(MBB, MBBI, AVR::ADCRdRr)
2084 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2085 .addReg(DstLoReg, getKillRegState(DstIsKill))
2086 .addReg(DstLoReg, getKillRegState(DstIsKill));
2087
2088 // sbc r25, r25
2089 auto MISBC =
2090 buildMI(MBB, MBBI, AVR::SBCRdRr)
2091 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2092 .addReg(DstHiReg, getKillRegState(DstIsKill))
2093 .addReg(DstHiReg, getKillRegState(DstIsKill));
2094
2095 if (ImpIsDead)
2096 MISBC->getOperand(3).setIsDead();
2097 // SREG is always implicitly killed
2098 MISBC->getOperand(4).setIsKill();
2099
2100 MI.eraseFromParent();
2101 return true;
2102}
2103
2104bool AVRExpandPseudo::expandASRW8Rd(Block &MBB, BlockIt MBBI) {
2105 MachineInstr &MI = *MBBI;
2106 Register DstLoReg, DstHiReg;
2107 Register DstReg = MI.getOperand(0).getReg();
2108 bool DstIsDead = MI.getOperand(0).isDead();
2109 bool DstIsKill = MI.getOperand(1).isKill();
2110 bool ImpIsDead = MI.getOperand(3).isDead();
2111 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2112
2113 // Move upper byte to lower byte.
2114 buildMI(MBB, MBBI, AVR::MOVRdRr)
2115 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2116 .addReg(DstHiReg);
2117
2118 // Move the sign bit to the C flag.
2119 buildMI(MBB, MBBI, AVR::ADDRdRr)
2120 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2121 .addReg(DstHiReg, RegState::Kill)
2122 .addReg(DstHiReg, RegState::Kill);
2123
2124 // Set upper byte to 0 or -1.
2125 auto MIBHI =
2126 buildMI(MBB, MBBI, AVR::SBCRdRr)
2127 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2128 .addReg(DstHiReg, getKillRegState(DstIsKill))
2129 .addReg(DstHiReg, getKillRegState(DstIsKill));
2130
2131 if (ImpIsDead)
2132 MIBHI->getOperand(3).setIsDead();
2133 // SREG is always implicitly killed
2134 MIBHI->getOperand(4).setIsKill();
2135
2136 MI.eraseFromParent();
2137 return true;
2138}
2139bool AVRExpandPseudo::expandASRW14Rd(Block &MBB, BlockIt MBBI) {
2140 MachineInstr &MI = *MBBI;
2141 Register DstLoReg, DstHiReg;
2142 Register DstReg = MI.getOperand(0).getReg();
2143 bool DstIsDead = MI.getOperand(0).isDead();
2144 bool DstIsKill = MI.getOperand(1).isKill();
2145 bool ImpIsDead = MI.getOperand(3).isDead();
2146 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2147
2148 // lsl r25
2149 // sbc r24, r24
2150 // lsl r25
2151 // mov r25, r24
2152 // rol r24
2153
2154 // lsl r25 <=> add r25, r25
2155 buildMI(MBB, MBBI, AVR::ADDRdRr)
2156 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2157 .addReg(DstHiReg, RegState::Kill)
2158 .addReg(DstHiReg, RegState::Kill);
2159
2160 // sbc r24, r24
2161 buildMI(MBB, MBBI, AVR::SBCRdRr)
2162 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2163 .addReg(DstLoReg, RegState::Kill)
2164 .addReg(DstLoReg, RegState::Kill);
2165
2166 // lsl r25 <=> add r25, r25
2167 buildMI(MBB, MBBI, AVR::ADDRdRr)
2168 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2169 .addReg(DstHiReg, RegState::Kill)
2170 .addReg(DstHiReg, RegState::Kill);
2171
2172 // mov r25, r24
2173 buildMI(MBB, MBBI, AVR::MOVRdRr)
2174 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2175 .addReg(DstLoReg);
2176
2177 // rol r24 <=> adc r24, r24
2178 auto MIROL =
2179 buildMI(MBB, MBBI, AVR::ADCRdRr)
2180 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2181 .addReg(DstLoReg, getKillRegState(DstIsKill))
2182 .addReg(DstLoReg, getKillRegState(DstIsKill));
2183
2184 if (ImpIsDead)
2185 MIROL->getOperand(3).setIsDead();
2186 // SREG is always implicitly killed
2187 MIROL->getOperand(4).setIsKill();
2188
2189 MI.eraseFromParent();
2190 return false;
2191}
2192
2193bool AVRExpandPseudo::expandASRW15Rd(Block &MBB, BlockIt MBBI) {
2194 MachineInstr &MI = *MBBI;
2195 Register DstLoReg, DstHiReg;
2196 Register DstReg = MI.getOperand(0).getReg();
2197 bool DstIsDead = MI.getOperand(0).isDead();
2198 bool ImpIsDead = MI.getOperand(3).isDead();
2199 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2200
2201 // lsl r25
2202 // sbc r25, r25
2203 // mov r24, r25
2204
2205 // lsl r25 <=> add r25, r25
2206 buildMI(MBB, MBBI, AVR::ADDRdRr)
2207 .addReg(DstHiReg, RegState::Define)
2208 .addReg(DstHiReg, RegState::Kill)
2209 .addReg(DstHiReg, RegState::Kill);
2210
2211 // sbc r25, r25
2212 auto MISBC =
2213 buildMI(MBB, MBBI, AVR::SBCRdRr)
2214 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2215 .addReg(DstHiReg, RegState::Kill)
2216 .addReg(DstHiReg, RegState::Kill);
2217 if (ImpIsDead)
2218 MISBC->getOperand(3).setIsDead();
2219 // SREG is always implicitly killed
2220 MISBC->getOperand(4).setIsKill();
2221
2222 // mov r24, r25
2223 buildMI(MBB, MBBI, AVR::MOVRdRr)
2224 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2225 .addReg(DstHiReg);
2226
2227 MI.eraseFromParent();
2228 return true;
2229}
2230
2231template <>
2232bool AVRExpandPseudo::expand<AVR::ASRWNRd>(Block &MBB, BlockIt MBBI) {
2233 MachineInstr &MI = *MBBI;
2234 unsigned Imm = MI.getOperand(2).getImm();
2235 switch (Imm) {
2236 case 7:
2237 return expandASRW7Rd(MBB, MBBI);
2238 case 8:
2239 return expandASRW8Rd(MBB, MBBI);
2240 case 14:
2241 return expandASRW14Rd(MBB, MBBI);
2242 case 15:
2243 return expandASRW15Rd(MBB, MBBI);
2244 default:
2245 llvm_unreachable("unimplemented asrwn");
2246 return false;
2247 }
2248}
2249
2250bool AVRExpandPseudo::expandLSLB7Rd(Block &MBB, BlockIt MBBI) {
2251 MachineInstr &MI = *MBBI;
2252 Register DstReg = MI.getOperand(0).getReg();
2253 bool DstIsDead = MI.getOperand(0).isDead();
2254 bool DstIsKill = MI.getOperand(1).isKill();
2255 bool ImpIsDead = MI.getOperand(3).isDead();
2256
2257 // ror r24
2258 // clr r24
2259 // ror r24
2260
2261 buildMI(MBB, MBBI, AVR::RORRd)
2262 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2263 .addReg(DstReg, RegState::Kill)
2264 ->getOperand(3)
2265 .setIsUndef(true);
2266
2267 buildMI(MBB, MBBI, AVR::EORRdRr)
2268 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2269 .addReg(DstReg, RegState::Kill)
2270 .addReg(DstReg, RegState::Kill);
2271
2272 auto MIRRC =
2273 buildMI(MBB, MBBI, AVR::RORRd)
2274 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2275 .addReg(DstReg, getKillRegState(DstIsKill));
2276
2277 if (ImpIsDead)
2278 MIRRC->getOperand(2).setIsDead();
2279
2280 // SREG is always implicitly killed
2281 MIRRC->getOperand(3).setIsKill();
2282
2283 MI.eraseFromParent();
2284 return true;
2285}
2286
2287template <>
2288bool AVRExpandPseudo::expand<AVR::LSLBNRd>(Block &MBB, BlockIt MBBI) {
2289 MachineInstr &MI = *MBBI;
2290 unsigned Imm = MI.getOperand(2).getImm();
2291 switch (Imm) {
2292 case 7:
2293 return expandLSLB7Rd(MBB, MBBI);
2294 default:
2295 llvm_unreachable("unimplemented lslbn");
2296 return false;
2297 }
2298}
2299
2300bool AVRExpandPseudo::expandLSRB7Rd(Block &MBB, BlockIt MBBI) {
2301 MachineInstr &MI = *MBBI;
2302 Register DstReg = MI.getOperand(0).getReg();
2303 bool DstIsDead = MI.getOperand(0).isDead();
2304 bool DstIsKill = MI.getOperand(1).isKill();
2305 bool ImpIsDead = MI.getOperand(3).isDead();
2306
2307 // rol r24
2308 // clr r24
2309 // rol r24
2310
2311 buildMI(MBB, MBBI, AVR::ADCRdRr)
2312 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2313 .addReg(DstReg, RegState::Kill)
2314 .addReg(DstReg, RegState::Kill)
2315 ->getOperand(4)
2316 .setIsUndef(true);
2317
2318 buildMI(MBB, MBBI, AVR::EORRdRr)
2319 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2320 .addReg(DstReg, RegState::Kill)
2321 .addReg(DstReg, RegState::Kill);
2322
2323 auto MIRRC =
2324 buildMI(MBB, MBBI, AVR::ADCRdRr)
2325 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2326 .addReg(DstReg, getKillRegState(DstIsKill))
2327 .addReg(DstReg, getKillRegState(DstIsKill));
2328
2329 if (ImpIsDead)
2330 MIRRC->getOperand(3).setIsDead();
2331
2332 // SREG is always implicitly killed
2333 MIRRC->getOperand(4).setIsKill();
2334
2335 MI.eraseFromParent();
2336 return true;
2337}
2338
2339template <>
2340bool AVRExpandPseudo::expand<AVR::LSRBNRd>(Block &MBB, BlockIt MBBI) {
2341 MachineInstr &MI = *MBBI;
2342 unsigned Imm = MI.getOperand(2).getImm();
2343 switch (Imm) {
2344 case 7:
2345 return expandLSRB7Rd(MBB, MBBI);
2346 default:
2347 llvm_unreachable("unimplemented lsrbn");
2348 return false;
2349 }
2350}
2351
2352bool AVRExpandPseudo::expandASRB6Rd(Block &MBB, BlockIt MBBI) {
2353 MachineInstr &MI = *MBBI;
2354 Register DstReg = MI.getOperand(0).getReg();
2355 bool DstIsDead = MI.getOperand(0).isDead();
2356 bool DstIsKill = MI.getOperand(1).isKill();
2357
2358 // bst r24, 6
2359 // lsl r24
2360 // sbc r24, r24
2361 // bld r24, 0
2362
2363 buildMI(MBB, MBBI, AVR::BST)
2364 .addReg(DstReg)
2365 .addImm(6)
2366 ->getOperand(2)
2367 .setIsUndef(true);
2368
2369 buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rd
2370 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2371 .addReg(DstReg, RegState::Kill)
2372 .addReg(DstReg, RegState::Kill);
2373
2374 buildMI(MBB, MBBI, AVR::SBCRdRr)
2375 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2376 .addReg(DstReg, RegState::Kill)
2377 .addReg(DstReg, RegState::Kill);
2378
2379 buildMI(MBB, MBBI, AVR::BLD)
2380 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2381 .addReg(DstReg, getKillRegState(DstIsKill))
2382 .addImm(0)
2383 ->getOperand(3)
2384 .setIsKill();
2385
2386 MI.eraseFromParent();
2387 return true;
2388}
2389
2390bool AVRExpandPseudo::expandASRB7Rd(Block &MBB, BlockIt MBBI) {
2391 MachineInstr &MI = *MBBI;
2392 Register DstReg = MI.getOperand(0).getReg();
2393 bool DstIsDead = MI.getOperand(0).isDead();
2394 bool DstIsKill = MI.getOperand(1).isKill();
2395 bool ImpIsDead = MI.getOperand(3).isDead();
2396
2397 // lsl r24
2398 // sbc r24, r24
2399
2400 buildMI(MBB, MBBI, AVR::ADDRdRr)
2401 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2402 .addReg(DstReg, RegState::Kill)
2403 .addReg(DstReg, RegState::Kill);
2404
2405 auto MIRRC =
2406 buildMI(MBB, MBBI, AVR::SBCRdRr)
2407 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2408 .addReg(DstReg, getKillRegState(DstIsKill))
2409 .addReg(DstReg, getKillRegState(DstIsKill));
2410
2411 if (ImpIsDead)
2412 MIRRC->getOperand(3).setIsDead();
2413
2414 // SREG is always implicitly killed
2415 MIRRC->getOperand(4).setIsKill();
2416
2417 MI.eraseFromParent();
2418 return true;
2419}
2420
2421template <>
2422bool AVRExpandPseudo::expand<AVR::ASRBNRd>(Block &MBB, BlockIt MBBI) {
2423 MachineInstr &MI = *MBBI;
2424 unsigned Imm = MI.getOperand(2).getImm();
2425 switch (Imm) {
2426 case 6:
2427 return expandASRB6Rd(MBB, MBBI);
2428 case 7:
2429 return expandASRB7Rd(MBB, MBBI);
2430 default:
2431 llvm_unreachable("unimplemented asrbn");
2432 return false;
2433 }
2434}
2435
2436template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
2437 MachineInstr &MI = *MBBI;
2438 Register DstLoReg, DstHiReg;
2439 // sext R17:R16, R17
2440 // mov r16, r17
2441 // lsl r17
2442 // sbc r17, r17
2443 // sext R17:R16, R13
2444 // mov r16, r13
2445 // mov r17, r13
2446 // lsl r17
2447 // sbc r17, r17
2448 // sext R17:R16, R16
2449 // mov r17, r16
2450 // lsl r17
2451 // sbc r17, r17
2452 Register DstReg = MI.getOperand(0).getReg();
2453 Register SrcReg = MI.getOperand(1).getReg();
2454 bool DstIsDead = MI.getOperand(0).isDead();
2455 bool SrcIsKill = MI.getOperand(1).isKill();
2456 bool ImpIsDead = MI.getOperand(2).isDead();
2457 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2458
2459 if (SrcReg != DstLoReg)
2460 buildMI(MBB, MBBI, AVR::MOVRdRr)
2461 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2462 .addReg(SrcReg);
2463
2464 if (SrcReg != DstHiReg) {
2465 auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr)
2466 .addReg(DstHiReg, RegState::Define)
2467 .addReg(SrcReg);
2468 if (SrcReg != DstLoReg && SrcIsKill)
2469 MOV->getOperand(1).setIsKill();
2470 }
2471
2472 buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
2473 .addReg(DstHiReg, RegState::Define)
2474 .addReg(DstHiReg, RegState::Kill)
2475 .addReg(DstHiReg, RegState::Kill);
2476
2477 auto SBC =
2478 buildMI(MBB, MBBI, AVR::SBCRdRr)
2479 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2480 .addReg(DstHiReg, RegState::Kill)
2481 .addReg(DstHiReg, RegState::Kill);
2482
2483 if (ImpIsDead)
2484 SBC->getOperand(3).setIsDead();
2485
2486 // SREG is always implicitly killed
2487 SBC->getOperand(4).setIsKill();
2488
2489 MI.eraseFromParent();
2490 return true;
2491}
2492
2493template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) {
2494 MachineInstr &MI = *MBBI;
2495 Register DstLoReg, DstHiReg;
2496 // zext R25:R24, R20
2497 // mov R24, R20
2498 // eor R25, R25
2499 // zext R25:R24, R24
2500 // eor R25, R25
2501 // zext R25:R24, R25
2502 // mov R24, R25
2503 // eor R25, R25
2504 Register DstReg = MI.getOperand(0).getReg();
2505 Register SrcReg = MI.getOperand(1).getReg();
2506 bool DstIsDead = MI.getOperand(0).isDead();
2507 bool SrcIsKill = MI.getOperand(1).isKill();
2508 bool ImpIsDead = MI.getOperand(2).isDead();
2509 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2510
2511 if (SrcReg != DstLoReg) {
2512 buildMI(MBB, MBBI, AVR::MOVRdRr)
2513 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2514 .addReg(SrcReg, getKillRegState(SrcIsKill));
2515 }
2516
2517 auto EOR =
2518 buildMI(MBB, MBBI, AVR::EORRdRr)
2519 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2520 .addReg(DstHiReg, RegState::Kill | RegState::Undef)
2521 .addReg(DstHiReg, RegState::Kill | RegState::Undef);
2522
2523 if (ImpIsDead)
2524 EOR->getOperand(3).setIsDead();
2525
2526 MI.eraseFromParent();
2527 return true;
2528}
2529
2530template <>
2531bool AVRExpandPseudo::expand<AVR::SPREAD>(Block &MBB, BlockIt MBBI) {
2532 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
2533 MachineInstr &MI = *MBBI;
2534 Register DstLoReg, DstHiReg;
2535 Register DstReg = MI.getOperand(0).getReg();
2536 bool DstIsDead = MI.getOperand(0).isDead();
2537 unsigned Flags = MI.getFlags();
2538 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2539
2540 // Low part
2541 buildMI(MBB, MBBI, AVR::INRdA)
2542 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2543 .addImm(STI.getIORegSPL())
2544 .setMIFlags(Flags);
2545
2546 // High part
2547 if (STI.getIORegSPH() != -1) {
2548 buildMI(MBB, MBBI, AVR::INRdA)
2549 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2550 .addImm(STI.getIORegSPH())
2551 .setMIFlags(Flags);
2552 } else {
2553 // Clear the upper byte if there is no SPH.
2554 auto MI0 =
2555 buildMI(MBB, MBBI, AVR::EORRdRr)
2556 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2557 .addReg(DstHiReg, RegState::Kill)
2558 .addReg(DstHiReg);
2559 // SREG is implicitly dead.
2560 MI0->getOperand(3).setIsDead();
2561 }
2562
2563 MI.eraseFromParent();
2564 return true;
2565}
2566
2567template <>
2568bool AVRExpandPseudo::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {
2569 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
2570 MachineInstr &MI = *MBBI;
2571 Register SrcLoReg, SrcHiReg;
2572 Register SrcReg = MI.getOperand(1).getReg();
2573 bool SrcIsKill = MI.getOperand(1).isKill();
2574 unsigned Flags = MI.getFlags();
2575 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
2576
2577 // From the XMEGA series manual:
2578 // To prevent corruption when updating the stack pointer from software,
2579 // a write to SPL will automatically disable interrupts
2580 // for up to four instructions or until the next I/O memory write.
2581 if (STI.getELFArch() >= 102) { // An XMEGA device
2582 buildMI(MBB, MBBI, AVR::OUTARr)
2583 .addImm(STI.getIORegSPL())
2584 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
2585 .setMIFlags(Flags);
2586
2587 buildMI(MBB, MBBI, AVR::OUTARr)
2588 .addImm(STI.getIORegSPH())
2589 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
2590 .setMIFlags(Flags);
2591 } else { // Disable interrupts for older devices with SPH (3 extra
2592 // instructions)
2593 if (STI.getIORegSPH() != -1) {
2594 buildMI(MBB, MBBI, AVR::INRdA)
2595 .addReg(STI.getTmpRegister(), RegState::Define)
2596 .addImm(STI.getIORegSREG())
2597 .setMIFlags(Flags);
2598
2599 buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
2600
2601 buildMI(MBB, MBBI, AVR::OUTARr)
2602 .addImm(STI.getIORegSPH())
2603 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
2604 .setMIFlags(Flags);
2605
2606 buildMI(MBB, MBBI, AVR::OUTARr)
2607 .addImm(STI.getIORegSREG())
2608 .addReg(STI.getTmpRegister(), RegState::Kill)
2609 .setMIFlags(Flags);
2610 }
2611
2612 buildMI(MBB, MBBI, AVR::OUTARr)
2613 .addImm(STI.getIORegSPL())
2614 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
2615 .setMIFlags(Flags);
2616 }
2617
2618 MI.eraseFromParent();
2619 return true;
2620}
2621
2622template <> bool AVRExpandPseudo::expand<AVR::FRMSP>(Block &MBB, BlockIt MBBI) {
2623 MachineInstr &MI = *MBBI;
2624 MachineFunction &MF = *MI.getMF();
2625 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
2626 DebugLoc DL;
2627 Register ASOPointer = MI.getOperand(0).getReg();
2628 int64_t ASOAlignment = MI.getOperand(1).getImm();
2629
2630 StackOffset ASOOffset =
2631 MF.getSubtarget<AVRSubtarget>()
2632 .getFrameLowering()
2633 ->getFrameIndexReference(MF, AFI->AlignedStackObjectIdx, ASOPointer);
2634
2635 TII->copyPhysReg(MBB, MI, DL, ASOPointer, AVR::R29R28, false, false, false);
2636
2637 buildMI(MBB, MI, AVR::ADIWRdKP)
2638 .addReg(ASOPointer, RegState::Define)
2639 .addReg(ASOPointer, RegState::Kill)
2640 .addImm(ASOOffset.getFixed() + ASOAlignment - 1)
2641 .setOperandDead(3); // implicit-def $sreg
2642
2643 buildMI(MBB, MI, AVR::ANDIWRdK)
2644 .addReg(ASOPointer, RegState::Define)
2645 .addReg(ASOPointer, RegState::Kill)
2646 .addImm(-ASOAlignment)
2647 .setOperandDead(3); // implicit-def $sreg
2648
2649 MI.eraseFromParent();
2650 return true;
2651}
2652
2653bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
2654 MachineInstr &MI = *MBBI;
2655 int Opcode = MBBI->getOpcode();
2656
2657#define EXPAND(Op) \
2658 case Op: \
2659 return expand<Op>(MBB, MI)
2660
2661 switch (Opcode) {
2662 EXPAND(AVR::ADDWRdRr);
2663 EXPAND(AVR::ADCWRdRr);
2664 EXPAND(AVR::ADIWRdKP);
2665 EXPAND(AVR::SUBWRdRr);
2666 EXPAND(AVR::SUBIWRdK);
2667 EXPAND(AVR::SBCWRdRr);
2668 EXPAND(AVR::SBCIWRdK);
2669 EXPAND(AVR::ANDWRdRr);
2670 EXPAND(AVR::ANDIWRdK);
2671 EXPAND(AVR::ORWRdRr);
2672 EXPAND(AVR::ORIWRdK);
2673 EXPAND(AVR::EORWRdRr);
2674 EXPAND(AVR::COMWRd);
2675 EXPAND(AVR::NEGWRd);
2676 EXPAND(AVR::CPWRdRr);
2677 EXPAND(AVR::CPCWRdRr);
2678 EXPAND(AVR::LDIWRdK);
2679 EXPAND(AVR::LDSWRdK);
2680 EXPAND(AVR::LDWRdPtr);
2681 EXPAND(AVR::LDWRdPtrPi);
2682 EXPAND(AVR::LDWRdPtrPd);
2683 case AVR::LDDWRdYQ: //: FIXME: remove this once PR13375 gets fixed
2684 EXPAND(AVR::LDDWRdPtrQ);
2685 EXPAND(AVR::LPMBRdZ);
2686 EXPAND(AVR::LPMWRdZ);
2687 EXPAND(AVR::LPMWRdZPi);
2688 EXPAND(AVR::ELPMBRdZ);
2689 EXPAND(AVR::ELPMWRdZ);
2690 EXPAND(AVR::ELPMBRdZPi);
2691 EXPAND(AVR::ELPMWRdZPi);
2692 EXPAND(AVR::AtomicLoad8);
2693 EXPAND(AVR::AtomicLoad16);
2694 EXPAND(AVR::AtomicStore8);
2695 EXPAND(AVR::AtomicStore16);
2696 EXPAND(AVR::AtomicFence);
2697 EXPAND(AVR::STSWKRr);
2698 EXPAND(AVR::STWPtrRr);
2699 EXPAND(AVR::STWPtrPiRr);
2700 EXPAND(AVR::STWPtrPdRr);
2701 EXPAND(AVR::STDWPtrQRr);
2702 EXPAND(AVR::STDSPQRr);
2703 EXPAND(AVR::STDWSPQRr);
2704 EXPAND(AVR::INWRdA);
2705 EXPAND(AVR::OUTWARr);
2706 EXPAND(AVR::PUSHWRr);
2707 EXPAND(AVR::POPWRd);
2708 EXPAND(AVR::ROLBRdR1);
2709 EXPAND(AVR::ROLBRdR17);
2710 EXPAND(AVR::RORBRd);
2711 EXPAND(AVR::LSLWRd);
2712 EXPAND(AVR::LSRWRd);
2713 EXPAND(AVR::RORWRd);
2714 EXPAND(AVR::ROLWRd);
2715 EXPAND(AVR::ASRWRd);
2716 EXPAND(AVR::LSLWHiRd);
2717 EXPAND(AVR::LSRWLoRd);
2718 EXPAND(AVR::ASRWLoRd);
2719 EXPAND(AVR::LSLWNRd);
2720 EXPAND(AVR::LSRWNRd);
2721 EXPAND(AVR::ASRWNRd);
2722 EXPAND(AVR::LSLBNRd);
2723 EXPAND(AVR::LSRBNRd);
2724 EXPAND(AVR::ASRBNRd);
2725 EXPAND(AVR::SEXT);
2726 EXPAND(AVR::ZEXT);
2727 EXPAND(AVR::SPREAD);
2728 EXPAND(AVR::SPWRITE);
2729 EXPAND(AVR::FRMSP);
2730 }
2731#undef EXPAND
2732 return false;
2733}
2734
2735} // end of anonymous namespace
2736
2737INITIALIZE_PASS(AVRExpandPseudo, "avr-expand-pseudo", AVR_EXPAND_PSEUDO_NAME,
2738 false, false)
2739
2740FunctionPass *llvm::createAVRExpandPseudoPass() {
2741 return new AVRExpandPseudo();
2742}
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Imm
unsigned Imm
Definition AMDGPUDisassembler.cpp:482
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
EXPAND
#define EXPAND(Op)
AVR_EXPAND_PSEUDO_NAME
#define AVR_EXPAND_PSEUDO_NAME
Definition AVRExpandPseudoInsts.cpp:28
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
expand
static Expected< BitVector > expand(StringRef S, StringRef Original)
Definition GlobPattern.cpp:26
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:866
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2131
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
llvm::AVRMachineFunctionInfo
Contains AVR-specific information for each MachineFunction.
Definition AVRMachineFunctionInfo.h:22
llvm::AVRRegisterInfo
Utilities relating to AVR registers.
Definition AVRRegisterInfo.h:24
llvm::AVRSubtarget
A specific AVR target MCU.
Definition AVRSubtarget.h:32
llvm::AVRSubtarget::getTmpRegister
Register getTmpRegister() const
Definition AVRSubtarget.h:91
llvm::AVRSubtarget::getELFArch
unsigned getELFArch() const
Gets the ELF architecture for the e_flags field of an ELF object file.
Definition AVRSubtarget.h:74
llvm::AVRSubtarget::getFrameLowering
const TargetFrameLowering * getFrameLowering() const override
Definition AVRSubtarget.h:43
llvm::AVRSubtarget::getIORegRAMPZ
int getIORegRAMPZ() const
Get I/O register addresses.
Definition AVRSubtarget.h:81
llvm::AVRSubtarget::getIORegSPL
int getIORegSPL() const
Definition AVRSubtarget.h:83
llvm::AVRSubtarget::getInstrInfo
const AVRInstrInfo * getInstrInfo() const override
Definition AVRSubtarget.h:42
llvm::AVRSubtarget::getIORegSREG
int getIORegSREG() const
Definition AVRSubtarget.h:85
llvm::AVRSubtarget::getIORegSPH
int getIORegSPH() const
Definition AVRSubtarget.h:84
llvm::AVRSubtarget::getRegisterInfo
const AVRRegisterInfo * getRegisterInfo() const override
Definition AVRSubtarget.h:52
llvm::BlockAddress
The address of a basic block.
Definition Constants.h:1088
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:126
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:343
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:789
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition MachineFunction.h:885
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:74
llvm::MachineOperand::CreateBA
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
Definition MachineOperand.h:926
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition MachineOperand.h:53
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition MachineOperand.h:62
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition MachineOperand.h:63
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition MachineRegisterInfo.h:53
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::StackOffset
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:30
llvm::StackOffset::getFixed
static StackOffset getFixed(int64_t Fixed)
Definition TypeSize.h:39
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::TargetFrameLowering::hasReservedCallFrame
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition TargetFrameLowering.h:315
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition TargetInstrInfo.h:116
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::AVRII::MO_HI
@ MO_HI
On a symbol operand, this represents the hi part.
Definition AVRInstrInfo.h:57
llvm::AVRII::MO_NEG
@ MO_NEG
On a symbol operand, this represents it has to be negated.
Definition AVRInstrInfo.h:60
llvm::AVRII::MO_LO
@ MO_LO
On a symbol operand, this represents the lo part.
Definition AVRInstrInfo.h:54
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition MachineInstrBuilder.h:61
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition MachineInstrBuilder.h:65
llvm::RegState::Define
@ Define
Register definition.
Definition MachineInstrBuilder.h:57
llvm::getKillRegState
constexpr RegState getKillRegState(bool B)
Definition MachineInstrBuilder.h:90
llvm::getDeadRegState
constexpr RegState getDeadRegState(bool B)
Definition MachineInstrBuilder.h:93
llvm::createAVRExpandPseudoPass
FunctionPass * createAVRExpandPseudoPass()
llvm::isUInt
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:190
llvm::Op
DWARFExpression::Operation Op
Definition DWARFExpressionPrinter.cpp:25
llvm::getUndefRegState
constexpr RegState getUndefRegState(bool B)
Definition MachineInstrBuilder.h:96
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