30#define DEBUG_TYPE "mccodeemitter"
41 :
MRI(mri), IsLittleEndian(IsLittleEndian) { }
42 BPFMCCodeEmitter(
const BPFMCCodeEmitter &) =
delete;
43 void operator=(
const BPFMCCodeEmitter &) =
delete;
44 ~BPFMCCodeEmitter()
override =
default;
79unsigned BPFMCCodeEmitter::getMachineOpValue(
const MCInst &
MI,
86 return static_cast<unsigned>(MO.
getImm());
94 if (
MI.getOpcode() == BPF::JAL)
97 else if (
MI.getOpcode() == BPF::LD_imm64)
99 else if (
MI.getOpcode() == BPF::JMPL)
110 return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
113void BPFMCCodeEmitter::encodeInstruction(
const MCInst &
MI,
117 unsigned Opcode =
MI.getOpcode();
122 if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
134 OSE.write<uint8_t>(0);
135 OSE.write<uint8_t>(0);
157 int MemOpStartIndex = 1, Opcode =
MI.getOpcode();
158 if (Opcode == BPF::CMPXCHGW32 || Opcode == BPF::CMPXCHGD)
162 const MCOperand Op1 =
MI.getOperand(MemOpStartIndex);
163 assert(Op1.
isReg() &&
"First operand is not register.");
164 Encoding =
MRI.getEncodingValue(Op1.
getReg());
166 MCOperand Op2 =
MI.getOperand(MemOpStartIndex + 1);
167 assert(Op2.
isImm() &&
"Second operand is not immediate.");
168 Encoding |= Op2.
getImm() & 0xffff;
172#include "BPFGenMCCodeEmitter.inc"
unsigned const MachineRegisterInfo * MRI
static uint8_t SwapBits(uint8_t Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This class represents an Operation in the Expression.
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
Base class for the full range of assembler expressions which are needed for parsing.
@ SymbolRef
References to labels and assigned expressions.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Instances of this class represent a single low-level machine instruction.
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
LLVM Value Representation.
A raw_ostream that writes to an SmallVector or SmallString.
This is an optimization pass for GlobalISel generic memory operations.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
@ FK_PCRel_2
A two-byte pc relative fixup.
@ FK_SecRel_8
A eight-byte section relative fixup.
MCCodeEmitter * createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCCodeEmitter * createBPFMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Adapter to write values to a stream in a particular byte order.